2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/config.h>
17 #include <linux/linkage.h>
18 #include <asm/hazards.h>
21 * The following macros are especially useful for __asm__
28 #define STR(x) __STR(x)
37 #define _ULCAST_ (unsigned long)
41 * Coprocessor 0 register names
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
52 #define CP0_BADVADDR $8
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
69 #define CP0_PERFORMANCE $25
71 #define CP0_CACHEERR $27
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
92 * Coprocessor 0 Set 1 register names
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
101 #define CP0_TX39_CACHE $7
104 * Coprocessor 1 (FPU) register names
106 #define CP1_REVISION $0
107 #define CP1_STATUS $31
110 * FPU Status Register Values
113 * Status Register Values
116 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
117 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
118 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
119 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
120 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
121 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
122 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
123 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
124 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
125 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
128 * X the exception cause indicator
129 * E the exception enable
130 * S the sticky/flag bit
132 #define FPU_CSR_ALL_X 0x0003f000
133 #define FPU_CSR_UNI_X 0x00020000
134 #define FPU_CSR_INV_X 0x00010000
135 #define FPU_CSR_DIV_X 0x00008000
136 #define FPU_CSR_OVF_X 0x00004000
137 #define FPU_CSR_UDF_X 0x00002000
138 #define FPU_CSR_INE_X 0x00001000
140 #define FPU_CSR_ALL_E 0x00000f80
141 #define FPU_CSR_INV_E 0x00000800
142 #define FPU_CSR_DIV_E 0x00000400
143 #define FPU_CSR_OVF_E 0x00000200
144 #define FPU_CSR_UDF_E 0x00000100
145 #define FPU_CSR_INE_E 0x00000080
147 #define FPU_CSR_ALL_S 0x0000007c
148 #define FPU_CSR_INV_S 0x00000040
149 #define FPU_CSR_DIV_S 0x00000020
150 #define FPU_CSR_OVF_S 0x00000010
151 #define FPU_CSR_UDF_S 0x00000008
152 #define FPU_CSR_INE_S 0x00000004
155 #define FPU_CSR_RN 0x0 /* nearest */
156 #define FPU_CSR_RZ 0x1 /* towards zero */
157 #define FPU_CSR_RU 0x2 /* towards +Infinity */
158 #define FPU_CSR_RD 0x3 /* towards -Infinity */
162 * Values for PageMask register
164 #ifdef CONFIG_CPU_VR41XX
166 /* Why doesn't stupidity hurt ... */
168 #define PM_1K 0x00000000
169 #define PM_4K 0x00001800
170 #define PM_16K 0x00007800
171 #define PM_64K 0x0001f800
172 #define PM_256K 0x0007f800
176 #define PM_4K 0x00000000
177 #define PM_16K 0x00006000
178 #define PM_64K 0x0001e000
179 #define PM_256K 0x0007e000
180 #define PM_1M 0x001fe000
181 #define PM_4M 0x007fe000
182 #define PM_16M 0x01ffe000
183 #define PM_64M 0x07ffe000
184 #define PM_256M 0x1fffe000
189 * Default page size for a given kernel configuration
191 #ifdef CONFIG_PAGE_SIZE_4KB
192 #define PM_DEFAULT_MASK PM_4K
193 #elif defined(CONFIG_PAGE_SIZE_16KB)
194 #define PM_DEFAULT_MASK PM_16K
195 #elif defined(CONFIG_PAGE_SIZE_64KB)
196 #define PM_DEFAULT_MASK PM_64K
198 #error Bad page size configuration!
203 * Values used for computation of new tlb entries
216 * R4x00 interrupt enable / cause bits
218 #define IE_SW0 (_ULCAST_(1) << 8)
219 #define IE_SW1 (_ULCAST_(1) << 9)
220 #define IE_IRQ0 (_ULCAST_(1) << 10)
221 #define IE_IRQ1 (_ULCAST_(1) << 11)
222 #define IE_IRQ2 (_ULCAST_(1) << 12)
223 #define IE_IRQ3 (_ULCAST_(1) << 13)
224 #define IE_IRQ4 (_ULCAST_(1) << 14)
225 #define IE_IRQ5 (_ULCAST_(1) << 15)
228 * R4x00 interrupt cause bits
230 #define C_SW0 (_ULCAST_(1) << 8)
231 #define C_SW1 (_ULCAST_(1) << 9)
232 #define C_IRQ0 (_ULCAST_(1) << 10)
233 #define C_IRQ1 (_ULCAST_(1) << 11)
234 #define C_IRQ2 (_ULCAST_(1) << 12)
235 #define C_IRQ3 (_ULCAST_(1) << 13)
236 #define C_IRQ4 (_ULCAST_(1) << 14)
237 #define C_IRQ5 (_ULCAST_(1) << 15)
240 * Bitfields in the R4xx0 cp0 status register
242 #define ST0_IE 0x00000001
243 #define ST0_EXL 0x00000002
244 #define ST0_ERL 0x00000004
245 #define ST0_KSU 0x00000018
246 # define KSU_USER 0x00000010
247 # define KSU_SUPERVISOR 0x00000008
248 # define KSU_KERNEL 0x00000000
249 #define ST0_UX 0x00000020
250 #define ST0_SX 0x00000040
251 #define ST0_KX 0x00000080
252 #define ST0_DE 0x00010000
253 #define ST0_CE 0x00020000
256 * Bitfields in the R[23]000 cp0 status register.
258 #define ST0_IEC 0x00000001
259 #define ST0_KUC 0x00000002
260 #define ST0_IEP 0x00000004
261 #define ST0_KUP 0x00000008
262 #define ST0_IEO 0x00000010
263 #define ST0_KUO 0x00000020
264 /* bits 6 & 7 are reserved on R[23]000 */
265 #define ST0_ISC 0x00010000
266 #define ST0_SWC 0x00020000
267 #define ST0_CM 0x00080000
270 * Bits specific to the R4640/R4650
272 #define ST0_UM (_ULCAST_(1) << 4)
273 #define ST0_IL (_ULCAST_(1) << 23)
274 #define ST0_DL (_ULCAST_(1) << 24)
277 * Bitfields in the TX39 family CP0 Configuration Register 3
279 #define TX39_CONF_ICS_SHIFT 19
280 #define TX39_CONF_ICS_MASK 0x00380000
281 #define TX39_CONF_ICS_1KB 0x00000000
282 #define TX39_CONF_ICS_2KB 0x00080000
283 #define TX39_CONF_ICS_4KB 0x00100000
284 #define TX39_CONF_ICS_8KB 0x00180000
285 #define TX39_CONF_ICS_16KB 0x00200000
287 #define TX39_CONF_DCS_SHIFT 16
288 #define TX39_CONF_DCS_MASK 0x00070000
289 #define TX39_CONF_DCS_1KB 0x00000000
290 #define TX39_CONF_DCS_2KB 0x00010000
291 #define TX39_CONF_DCS_4KB 0x00020000
292 #define TX39_CONF_DCS_8KB 0x00030000
293 #define TX39_CONF_DCS_16KB 0x00040000
295 #define TX39_CONF_CWFON 0x00004000
296 #define TX39_CONF_WBON 0x00002000
297 #define TX39_CONF_RF_SHIFT 10
298 #define TX39_CONF_RF_MASK 0x00000c00
299 #define TX39_CONF_DOZE 0x00000200
300 #define TX39_CONF_HALT 0x00000100
301 #define TX39_CONF_LOCK 0x00000080
302 #define TX39_CONF_ICE 0x00000020
303 #define TX39_CONF_DCE 0x00000010
304 #define TX39_CONF_IRSIZE_SHIFT 2
305 #define TX39_CONF_IRSIZE_MASK 0x0000000c
306 #define TX39_CONF_DRSIZE_SHIFT 0
307 #define TX39_CONF_DRSIZE_MASK 0x00000003
310 * Status register bits available in all MIPS CPUs.
312 #define ST0_IM 0x0000ff00
313 #define STATUSB_IP0 8
314 #define STATUSF_IP0 (_ULCAST_(1) << 8)
315 #define STATUSB_IP1 9
316 #define STATUSF_IP1 (_ULCAST_(1) << 9)
317 #define STATUSB_IP2 10
318 #define STATUSF_IP2 (_ULCAST_(1) << 10)
319 #define STATUSB_IP3 11
320 #define STATUSF_IP3 (_ULCAST_(1) << 11)
321 #define STATUSB_IP4 12
322 #define STATUSF_IP4 (_ULCAST_(1) << 12)
323 #define STATUSB_IP5 13
324 #define STATUSF_IP5 (_ULCAST_(1) << 13)
325 #define STATUSB_IP6 14
326 #define STATUSF_IP6 (_ULCAST_(1) << 14)
327 #define STATUSB_IP7 15
328 #define STATUSF_IP7 (_ULCAST_(1) << 15)
329 #define STATUSB_IP8 0
330 #define STATUSF_IP8 (_ULCAST_(1) << 0)
331 #define STATUSB_IP9 1
332 #define STATUSF_IP9 (_ULCAST_(1) << 1)
333 #define STATUSB_IP10 2
334 #define STATUSF_IP10 (_ULCAST_(1) << 2)
335 #define STATUSB_IP11 3
336 #define STATUSF_IP11 (_ULCAST_(1) << 3)
337 #define STATUSB_IP12 4
338 #define STATUSF_IP12 (_ULCAST_(1) << 4)
339 #define STATUSB_IP13 5
340 #define STATUSF_IP13 (_ULCAST_(1) << 5)
341 #define STATUSB_IP14 6
342 #define STATUSF_IP14 (_ULCAST_(1) << 6)
343 #define STATUSB_IP15 7
344 #define STATUSF_IP15 (_ULCAST_(1) << 7)
345 #define ST0_CH 0x00040000
346 #define ST0_SR 0x00100000
347 #define ST0_TS 0x00200000
348 #define ST0_BEV 0x00400000
349 #define ST0_RE 0x02000000
350 #define ST0_FR 0x04000000
351 #define ST0_CU 0xf0000000
352 #define ST0_CU0 0x10000000
353 #define ST0_CU1 0x20000000
354 #define ST0_CU2 0x40000000
355 #define ST0_CU3 0x80000000
356 #define ST0_XX 0x80000000 /* MIPS IV naming */
359 * Bitfields and bit numbers in the coprocessor 0 cause register.
361 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
363 #define CAUSEB_EXCCODE 2
364 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
366 #define CAUSEF_IP (_ULCAST_(255) << 8)
368 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
370 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
371 #define CAUSEB_IP2 10
372 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
373 #define CAUSEB_IP3 11
374 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
375 #define CAUSEB_IP4 12
376 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
377 #define CAUSEB_IP5 13
378 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
379 #define CAUSEB_IP6 14
380 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
381 #define CAUSEB_IP7 15
382 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
384 #define CAUSEF_IV (_ULCAST_(1) << 23)
386 #define CAUSEF_CE (_ULCAST_(3) << 28)
388 #define CAUSEF_BD (_ULCAST_(1) << 31)
391 * Bits in the coprocessor 0 config register.
394 #define CONF_CM_CACHABLE_NO_WA 0
395 #define CONF_CM_CACHABLE_WA 1
396 #define CONF_CM_UNCACHED 2
397 #define CONF_CM_CACHABLE_NONCOHERENT 3
398 #define CONF_CM_CACHABLE_CE 4
399 #define CONF_CM_CACHABLE_COW 5
400 #define CONF_CM_CACHABLE_CUW 6
401 #define CONF_CM_CACHABLE_ACCELERATED 7
402 #define CONF_CM_CMASK 7
403 #define CONF_BE (_ULCAST_(1) << 15)
405 /* Bits common to various processors. */
406 #define CONF_CU (_ULCAST_(1) << 3)
407 #define CONF_DB (_ULCAST_(1) << 4)
408 #define CONF_IB (_ULCAST_(1) << 5)
409 #define CONF_DC (_ULCAST_(7) << 6)
410 #define CONF_IC (_ULCAST_(7) << 9)
411 #define CONF_EB (_ULCAST_(1) << 13)
412 #define CONF_EM (_ULCAST_(1) << 14)
413 #define CONF_SM (_ULCAST_(1) << 16)
414 #define CONF_SC (_ULCAST_(1) << 17)
415 #define CONF_EW (_ULCAST_(3) << 18)
416 #define CONF_EP (_ULCAST_(15)<< 24)
417 #define CONF_EC (_ULCAST_(7) << 28)
418 #define CONF_CM (_ULCAST_(1) << 31)
420 /* Bits specific to the R4xx0. */
421 #define R4K_CONF_SW (_ULCAST_(1) << 20)
422 #define R4K_CONF_SS (_ULCAST_(1) << 21)
423 #define R4K_CONF_SB (_ULCAST_(3) << 22)
425 /* Bits specific to the R5000. */
426 #define R5K_CONF_SE (_ULCAST_(1) << 12)
427 #define R5K_CONF_SS (_ULCAST_(3) << 20)
429 /* Bits specific to the R10000. */
430 #define R10K_CONF_DN (_ULCAST_(3) << 3)
431 #define R10K_CONF_CT (_ULCAST_(1) << 5)
432 #define R10K_CONF_PE (_ULCAST_(1) << 6)
433 #define R10K_CONF_PM (_ULCAST_(3) << 7)
434 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
435 #define R10K_CONF_SB (_ULCAST_(1) << 13)
436 #define R10K_CONF_SK (_ULCAST_(1) << 14)
437 #define R10K_CONF_SS (_ULCAST_(7) << 16)
438 #define R10K_CONF_SC (_ULCAST_(7) << 19)
439 #define R10K_CONF_DC (_ULCAST_(7) << 26)
440 #define R10K_CONF_IC (_ULCAST_(7) << 29)
442 /* Bits specific to the VR41xx. */
443 #define VR41_CONF_CS (_ULCAST_(1) << 12)
444 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
445 #define VR41_CONF_AD (_ULCAST_(1) << 23)
447 /* Bits specific to the R30xx. */
448 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
449 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
450 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
451 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
452 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
453 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
454 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
455 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
456 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
458 /* Bits specific to the TX49. */
459 #define TX49_CONF_DC (_ULCAST_(1) << 16)
460 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
461 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
462 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
464 /* Bits specific to the MIPS32/64 PRA. */
465 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
466 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
467 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
468 #define MIPS_CONF_M (_ULCAST_(1) << 31)
471 * R10000 performance counter definitions.
473 * FIXME: The R10000 performance counter opens a nice way to implement CPU
474 * time accounting with a precission of one cycle. I don't have
475 * R10000 silicon but just a manual, so ...
479 * Events counted by counter #0
482 #define CE0_INSN_ISSUED 1
483 #define CE0_LPSC_ISSUED 2
484 #define CE0_S_ISSUED 3
485 #define CE0_SC_ISSUED 4
486 #define CE0_SC_FAILED 5
487 #define CE0_BRANCH_DECODED 6
488 #define CE0_QW_WB_SECONDARY 7
489 #define CE0_CORRECTED_ECC_ERRORS 8
490 #define CE0_ICACHE_MISSES 9
491 #define CE0_SCACHE_I_MISSES 10
492 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
493 #define CE0_EXT_INTERVENTIONS_REQ 12
494 #define CE0_EXT_INVALIDATE_REQ 13
495 #define CE0_VIRTUAL_COHERENCY_COND 14
496 #define CE0_INSN_GRADUATED 15
499 * Events counted by counter #1
502 #define CE1_INSN_GRADUATED 1
503 #define CE1_LPSC_GRADUATED 2
504 #define CE1_S_GRADUATED 3
505 #define CE1_SC_GRADUATED 4
506 #define CE1_FP_INSN_GRADUATED 5
507 #define CE1_QW_WB_PRIMARY 6
508 #define CE1_TLB_REFILL 7
509 #define CE1_BRANCH_MISSPREDICTED 8
510 #define CE1_DCACHE_MISS 9
511 #define CE1_SCACHE_D_MISSES 10
512 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
513 #define CE1_EXT_INTERVENTION_HITS 12
514 #define CE1_EXT_INVALIDATE_REQ 13
515 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
516 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
519 * These flags define in which privilege mode the counters count events
521 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
522 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
523 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
524 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
529 * Functions to access the r10k performance counter and control registers
531 #define read_r10k_perf_cntr(counter) \
532 ({ unsigned int __res; \
533 __asm__ __volatile__( \
534 "mfpc\t%0, "STR(counter) \
538 #define write_r10k_perf_cntr(counter,val) \
539 __asm__ __volatile__( \
540 "mtpc\t%0, "STR(counter) \
543 #define read_r10k_perf_cntl(counter) \
544 ({ unsigned int __res; \
545 __asm__ __volatile__( \
546 "mfps\t%0, "STR(counter) \
550 #define write_r10k_perf_cntl(counter,val) \
551 __asm__ __volatile__( \
552 "mtps\t%0, "STR(counter) \
556 * Macros to access the system control coprocessor
559 #define __read_32bit_c0_register(source, sel) \
562 __asm__ __volatile__( \
563 "mfc0\t%0, " #source "\n\t" \
566 __asm__ __volatile__( \
568 "mfc0\t%0, " #source ", " #sel "\n\t" \
574 #define __read_64bit_c0_register(source, sel) \
575 ({ unsigned long __res; \
577 __asm__ __volatile__( \
579 "dmfc0\t%0, " #source "\n\t" \
583 __asm__ __volatile__( \
585 "dmfc0\t%0, " #source ", " #sel "\n\t" \
591 #define __write_32bit_c0_register(register, sel, value) \
594 __asm__ __volatile__( \
595 "mtc0\t%z0, " #register "\n\t" \
596 : : "Jr" ((unsigned int)value)); \
598 __asm__ __volatile__( \
600 "mtc0\t%z0, " #register ", " #sel "\n\t" \
602 : : "Jr" ((unsigned int)value)); \
605 #define __write_64bit_c0_register(register, sel, value) \
608 __asm__ __volatile__( \
610 "dmtc0\t%z0, " #register "\n\t" \
614 __asm__ __volatile__( \
616 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
621 #define __read_ulong_c0_register(reg, sel) \
622 ((sizeof(unsigned long) == 4) ? \
623 __read_32bit_c0_register(reg, sel) : \
624 __read_64bit_c0_register(reg, sel))
626 #define __write_ulong_c0_register(reg, sel, val) \
628 if (sizeof(unsigned long) == 4) \
629 __write_32bit_c0_register(reg, sel, val); \
631 __write_64bit_c0_register(reg, sel, val); \
635 * On The RM7000 these are use to access cop0 set 1 registers
637 #define __read_32bit_c0_ctrl_register(source) \
639 __asm__ __volatile__( \
640 "cfc0\t%0, " #source "\n\t" \
645 #define __write_32bit_c0_ctrl_register(register, value) \
647 __asm__ __volatile__( \
648 "ctc0\t%z0, " #register "\n\t" \
649 : : "Jr" ((unsigned int)value)); \
653 * These versions are only needed for systems with more than 38 bits of
654 * physical address space running the 32-bit kernel. That's none atm :-)
656 #define __read_64bit_c0_split(source, sel) \
658 unsigned long long val; \
659 unsigned long flags; \
661 local_irq_save(flags); \
663 __asm__ __volatile__( \
665 "dmfc0\t%M0, " #source "\n\t" \
666 "dsll\t%L0, %M0, 32\n\t" \
667 "dsrl\t%M0, %M0, 32\n\t" \
668 "dsrl\t%L0, %L0, 32\n\t" \
672 __asm__ __volatile__( \
674 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
675 "dsll\t%L0, %M0, 32\n\t" \
676 "dsrl\t%M0, %M0, 32\n\t" \
677 "dsrl\t%L0, %L0, 32\n\t" \
680 local_irq_restore(flags); \
685 #define __write_64bit_c0_split(source, sel, val) \
687 unsigned long flags; \
689 local_irq_save(flags); \
691 __asm__ __volatile__( \
693 "dsll\t%L0, %L0, 32\n\t" \
694 "dsrl\t%L0, %L0, 32\n\t" \
695 "dsll\t%M0, %M0, 32\n\t" \
696 "or\t%L0, %L0, %M0\n\t" \
697 "dmtc0\t%L0, " #source "\n\t" \
701 __asm__ __volatile__( \
703 "dsll\t%L0, %L0, 32\n\t" \
704 "dsrl\t%L0, %L0, 32\n\t" \
705 "dsll\t%M0, %M0, 32\n\t" \
706 "or\t%L0, %L0, %M0\n\t" \
707 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
710 local_irq_restore(flags); \
713 #define read_c0_index() __read_32bit_c0_register($0, 0)
714 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
716 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
717 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
719 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
720 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
722 #define read_c0_conf() __read_32bit_c0_register($3, 0)
723 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
725 #define read_c0_context() __read_ulong_c0_register($4, 0)
726 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
728 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
729 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
731 #define read_c0_wired() __read_32bit_c0_register($6, 0)
732 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
734 #define read_c0_info() __read_32bit_c0_register($7, 0)
736 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
737 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
739 #define read_c0_count() __read_32bit_c0_register($9, 0)
740 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
742 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
743 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
745 #define read_c0_compare() __read_32bit_c0_register($11, 0)
746 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
748 #define read_c0_status() __read_32bit_c0_register($12, 0)
749 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
751 #define read_c0_cause() __read_32bit_c0_register($13, 0)
752 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
754 #define read_c0_epc() __read_ulong_c0_register($14, 0)
755 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
757 #define read_c0_prid() __read_32bit_c0_register($15, 0)
759 #define read_c0_config() __read_32bit_c0_register($16, 0)
760 #define read_c0_config1() __read_32bit_c0_register($16, 1)
761 #define read_c0_config2() __read_32bit_c0_register($16, 2)
762 #define read_c0_config3() __read_32bit_c0_register($16, 3)
763 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
764 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
765 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
766 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
769 * The WatchLo register. There may be upto 8 of them.
771 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
772 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
773 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
774 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
775 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
776 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
777 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
778 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
779 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
780 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
781 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
782 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
783 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
784 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
785 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
786 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
789 * The WatchHi register. There may be upto 8 of them.
791 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
792 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
793 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
794 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
795 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
796 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
797 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
798 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
800 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
801 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
802 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
803 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
804 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
805 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
806 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
807 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
809 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
810 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
812 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
813 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
815 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
816 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
818 #define read_c0_diag() __read_32bit_c0_register($22, 0)
819 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
821 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
822 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
824 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
825 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
827 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
828 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
830 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
831 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
833 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
834 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
836 #define read_c0_debug() __read_32bit_c0_register($23, 0)
837 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
839 #define read_c0_depc() __read_ulong_c0_register($24, 0)
840 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
842 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
843 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
845 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
846 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
848 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
850 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
851 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
853 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
854 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
856 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
857 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
859 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
860 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
863 * Macros to access the floating point coprocessor control registers
865 #define read_32bit_cp1_register(source) \
867 __asm__ __volatile__( \
869 ".set\treorder\n\t" \
870 "cfc1\t%0,"STR(source)"\n\t" \
878 * It is responsibility of the caller to take care of any TLB hazards.
880 static inline void tlb_probe(void)
882 __asm__ __volatile__(
888 static inline void tlb_read(void)
890 __asm__ __volatile__(
896 static inline void tlb_write_indexed(void)
898 __asm__ __volatile__(
904 static inline void tlb_write_random(void)
906 __asm__ __volatile__(
913 * Manipulate bits in a c0 register.
915 #define __BUILD_SET_C0(name) \
916 static inline unsigned int \
917 set_c0_##name(unsigned int set) \
921 res = read_c0_##name(); \
923 write_c0_##name(res); \
928 static inline unsigned int \
929 clear_c0_##name(unsigned int clear) \
933 res = read_c0_##name(); \
935 write_c0_##name(res); \
940 static inline unsigned int \
941 change_c0_##name(unsigned int change, unsigned int new) \
945 res = read_c0_##name(); \
947 res |= (new & change); \
948 write_c0_##name(res); \
953 __BUILD_SET_C0(status)
954 __BUILD_SET_C0(cause)
955 __BUILD_SET_C0(config)
956 __BUILD_SET_C0(intcontrol)
958 #endif /* !__ASSEMBLY__ */
960 #endif /* _ASM_MIPSREGS_H */