2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
9 #ifndef _ASM_PGTABLE_32_H
10 #define _ASM_PGTABLE_32_H
12 #include <linux/config.h>
13 #include <asm/addrspace.h>
16 #include <linux/linkage.h>
17 #include <asm/cachectl.h>
18 #include <asm/fixmap.h>
21 * - add_wired_entry() add a fixed TLB entry, and move wired register
23 extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
24 unsigned long entryhi, unsigned long pagemask);
27 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
28 * starting at the top and working down. This is for populating the
29 * TLB before trap_init() puts the TLB miss handler in place. It
30 * should be used only for entries matching the actual page tables,
31 * to prevent inconsistencies.
33 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
34 unsigned long entryhi, unsigned long pagemask);
37 /* Basically we have the same two-level (which is the logical three level
38 * Linux page table layout folded) page tables as the i386. Some day
39 * when we have proper page coloring support we can have a 1% quicker
40 * tlb refill handling mechanism, but for now it is a bit slower but
41 * works even with the cache aliasing problem the R4k and above have.
44 /* PMD_SHIFT determines the size of the area a second-level page table can map */
45 #ifdef CONFIG_64BIT_PHYS_ADDR
50 #define PMD_SIZE (1UL << PMD_SHIFT)
51 #define PMD_MASK (~(PMD_SIZE-1))
53 /* PGDIR_SHIFT determines what a third-level page table entry can map */
54 #define PGDIR_SHIFT PMD_SHIFT
55 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
56 #define PGDIR_MASK (~(PGDIR_SIZE-1))
59 * Entries per page directory level: we use two-level, so
60 * we don't really have any PMD directory physically.
62 #ifdef CONFIG_64BIT_PHYS_ADDR
72 #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
73 #define PTRS_PER_PMD 1
74 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
76 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
77 #define FIRST_USER_PGD_NR 0
79 #define VMALLOC_START KSEG2
82 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
84 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
87 #ifdef CONFIG_64BIT_PHYS_ADDR
88 #define pte_ERROR(e) \
89 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
91 #define pte_ERROR(e) \
92 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
94 #define pmd_ERROR(e) \
95 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
96 #define pgd_ERROR(e) \
97 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
99 extern void load_pgd(unsigned long pg_dir);
101 extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)];
104 * Empty pgd/pmd entries point to the invalid_pte_table.
106 static inline int pmd_none(pmd_t pmd)
108 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
111 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
113 static inline int pmd_present(pmd_t pmd)
115 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
118 static inline void pmd_clear(pmd_t *pmdp)
120 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
124 * The "pgd_xxx()" functions here are trivial for a folded two-level
125 * setup: the pgd is never bad, and a pmd always exists (as it's folded
126 * into the pgd entry)
128 static inline int pgd_none(pgd_t pgd) { return 0; }
129 static inline int pgd_bad(pgd_t pgd) { return 0; }
130 static inline int pgd_present(pgd_t pgd) { return 1; }
131 static inline void pgd_clear(pgd_t *pgdp) { }
133 #define pte_page(x) pfn_to_page(pte_pfn(x))
136 #ifdef CONFIG_CPU_VR41XX
137 #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
138 #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
140 #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
141 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
144 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
147 * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
150 #define pte_to_pgoff(_pte) \
151 ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
153 #define pgoff_to_pte(off) \
154 ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
159 * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
162 #define pte_to_pgoff(_pte) \
163 ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
165 #define pgoff_to_pte(off) \
166 ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
170 #define __pgd_offset(address) pgd_index(address)
171 #define __pmd_offset(address) \
172 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
174 /* to find an entry in a kernel page-table-directory */
175 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
177 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
179 /* to find an entry in a page-table-directory */
180 #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
182 /* Find an entry in the second-level page table.. */
183 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
185 return (pmd_t *) dir;
188 /* Find an entry in the third-level page table.. */
189 #define __pte_offset(address) \
190 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
191 #define pte_offset(dir, address) \
192 ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address))
193 #define pte_offset_kernel(dir, address) \
194 ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address))
196 #define pte_offset_map(dir, address) \
197 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
198 #define pte_offset_map_nested(dir, address) \
199 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
200 #define pte_unmap(pte) ((void)(pte))
201 #define pte_unmap_nested(pte) ((void)(pte))
203 /* Swap entries must have VALID and GLOBAL bits cleared. */
204 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
206 #define __swp_type(x) (((x).val >> 1) & 0x7f)
207 #define __swp_offset(x) ((x).val >> 10)
208 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) })
211 #define __swp_type(x) (((x).val >> 1) & 0x1f)
212 #define __swp_offset(x) ((x).val >> 8)
213 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
216 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
217 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
219 #ifdef CONFIG_64BIT_PHYS_ADDR
220 typedef u64 pte_addr_t;
222 typedef pte_t *pte_addr_t;
225 #endif /* _ASM_PGTABLE_32_H */