2 * include/asm-mips/vr41xx/vr41xx.h
4 * Include file for NEC VR4100 series.
6 * Copyright (C) 1999 Michael Klar
7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #ifndef __NEC_VR41XX_H
18 #define __NEC_VR41XX_H
20 #include <linux/interrupt.h>
25 /* VR4122 0x00000c70-0x00000c72 */
26 #define PRID_VR4122_REV1_0 0x00000c70
27 #define PRID_VR4122_REV2_0 0x00000c70
28 #define PRID_VR4122_REV2_1 0x00000c70
29 #define PRID_VR4122_REV3_0 0x00000c71
30 #define PRID_VR4122_REV3_1 0x00000c72
32 /* VR4181A 0x00000c73-0x00000c7f */
33 #define PRID_VR4181A_REV1_0 0x00000c73
34 #define PRID_VR4181A_REV1_1 0x00000c74
36 /* VR4131 0x00000c80-0x00000c83 */
37 #define PRID_VR4131_REV1_2 0x00000c80
38 #define PRID_VR4131_REV2_0 0x00000c81
39 #define PRID_VR4131_REV2_1 0x00000c82
40 #define PRID_VR4131_REV2_2 0x00000c83
42 /* VR4133 0x00000c84- */
43 #define PRID_VR4133 0x00000c84
48 #define IO_MEM_RESOURCE_START 0UL
49 #define IO_MEM_RESOURCE_END 0x1fffffffUL
54 extern unsigned long vr41xx_get_vtclock_frequency(void);
55 extern unsigned long vr41xx_get_tclock_frequency(void);
76 extern void vr41xx_supply_clock(vr41xx_clock_t clock);
77 extern void vr41xx_mask_clock(vr41xx_clock_t clock);
80 * Interrupt Control Unit
82 /* CPU core Interrupt Numbers */
83 #define MIPS_CPU_IRQ_BASE 0
84 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
85 #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
86 #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
87 #define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2)
88 #define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3)
89 #define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4)
90 #define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5)
91 #define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6)
92 #define MIPS_COUNTER_IRQ MIPS_CPU_IRQ(7)
94 /* SYINT1 Interrupt Numbers */
95 #define SYSINT1_IRQ_BASE 8
96 #define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
97 #define BATTRY_IRQ SYSINT1_IRQ(0)
98 #define POWER_IRQ SYSINT1_IRQ(1)
99 #define RTCLONG1_IRQ SYSINT1_IRQ(2)
100 #define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
102 #define PIU_IRQ SYSINT1_IRQ(5)
103 #define AIU_IRQ SYSINT1_IRQ(6)
104 #define KIU_IRQ SYSINT1_IRQ(7)
105 #define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8)
106 #define SIU_IRQ SYSINT1_IRQ(9)
107 #define BUSERR_IRQ SYSINT1_IRQ(10)
108 #define SOFTINT_IRQ SYSINT1_IRQ(11)
109 #define CLKRUN_IRQ SYSINT1_IRQ(12)
110 #define DOZEPIU_IRQ SYSINT1_IRQ(13)
111 #define SYSINT1_IRQ_LAST DOZEPIU_IRQ
113 /* SYSINT2 Interrupt Numbers */
114 #define SYSINT2_IRQ_BASE 24
115 #define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
116 #define RTCLONG2_IRQ SYSINT2_IRQ(0)
117 #define LED_IRQ SYSINT2_IRQ(1)
118 #define HSP_IRQ SYSINT2_IRQ(2)
119 #define TCLOCK_IRQ SYSINT2_IRQ(3)
120 #define FIR_IRQ SYSINT2_IRQ(4)
121 #define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
122 #define DSIU_IRQ SYSINT2_IRQ(5)
123 #define PCI_IRQ SYSINT2_IRQ(6)
124 #define SCU_IRQ SYSINT2_IRQ(7)
125 #define CSI_IRQ SYSINT2_IRQ(8)
126 #define BCU_IRQ SYSINT2_IRQ(9)
127 #define ETHERNET_IRQ SYSINT2_IRQ(10)
128 #define SYSINT2_IRQ_LAST ETHERNET_IRQ
130 /* GIU Interrupt Numbers */
131 #define GIU_IRQ_BASE 40
132 #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
133 #define GIU_IRQ_LAST GIU_IRQ(31)
134 #define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */
136 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
137 extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
139 extern void vr41xx_enable_dsiuint(void);
140 extern void vr41xx_disable_dsiuint(void);
143 * Power Management Unit
149 extern void vr41xx_set_rtclong1_cycle(uint32_t cycles);
150 extern uint32_t vr41xx_read_rtclong1_counter(void);
152 extern void vr41xx_set_rtclong2_cycle(uint32_t cycles);
153 extern uint32_t vr41xx_read_rtclong2_counter(void);
155 extern void vr41xx_set_tclock_cycle(uint32_t cycles);
156 extern uint32_t vr41xx_read_tclock_counter(void);
159 * General-Purpose I/O Unit
164 TRIGGER_EDGE_FALLING,
173 extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
180 extern void vr41xx_set_irq_level(int pin, int level);
193 * Serial Interface Unit
195 extern void vr41xx_siu_init(void);
196 extern int vr41xx_serial_ports;
204 /* IrDA interfaces */
212 extern void vr41xx_select_siu_interface(siu_interface_t interface,
213 irda_module_t module);
216 * Debug Serial Interface Unit
218 extern void vr41xx_dsiu_init(void);
223 struct vr41xx_pci_address_space {
229 struct vr41xx_pci_address_map {
230 struct vr41xx_pci_address_space *mem1;
231 struct vr41xx_pci_address_space *mem2;
232 struct vr41xx_pci_address_space *io;
235 extern void vr41xx_pciu_init(struct vr41xx_pci_address_map *map);
237 #endif /* __NEC_VR41XX_H */