1 #ifndef __ASM_PARISC_PCI_H
2 #define __ASM_PARISC_PCI_H
4 #include <linux/config.h>
5 #include <asm/scatterlist.h>
8 ** HP PCI platforms generally support multiple bus adapters.
9 ** (workstations 1-~4, servers 2-~32)
11 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
14 ** Under a PCI bus, most HP platforms support PPBs up to two or three
15 ** levels deep. See "Bit3" product line.
17 #define PCI_MAX_BUSSES 256
20 ** pci_hba_data (aka H2P_OBJECT in HP/UX)
22 ** This is the "common" or "base" data structure which HBA drivers
23 ** (eg Dino or LBA) are required to place at the top of their own
24 ** platform_data structure. I've heard this called "C inheritance" too.
26 ** Data needed by pcibios layer belongs here.
29 unsigned long base_addr; /* aka Host Physical Address */
30 const struct parisc_device *dev; /* device from PA bus walk */
31 struct pci_bus *hba_bus; /* primary PCI bus below HBA */
32 int hba_num; /* I/O port space access "key" */
33 struct resource bus_num; /* PCI bus numbers */
34 struct resource io_space; /* PIOP */
35 struct resource lmmio_space; /* bus addresses < 4Gb */
36 struct resource elmmio_space; /* additional bus addresses < 4Gb */
37 struct resource gmmio_space; /* bus addresses > 4Gb */
38 /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
39 * elmmio_space and gmmio_space as a contiguous array of
40 * resources. This #define represents the array size */
41 #define DINO_MAX_LMMIO_RESOURCES 3
43 unsigned long lmmio_space_offset; /* CPU view - PCI view */
44 void * iommu; /* IOMMU this device is under */
45 /* REVISIT - spinlock to protect resources? */
48 #define HBA_DATA(d) ((struct pci_hba_data *) (d))
51 ** We support 2^16 I/O ports per HBA. These are set up in the form
52 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
55 #define HBA_PORT_SPACE_BITS 16
57 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
58 #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
60 #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
61 #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
64 ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
65 ** Note that we currently support only LMMIO.
67 #define PCI_BUS_ADDR(hba,a) ((a) - hba->lmmio_space_offset)
68 #define PCI_HOST_ADDR(hba,a) ((a) + hba->lmmio_space_offset)
71 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
72 ** (This eliminates some of the warnings).
77 /* The PCI address space does equal the physical memory
78 * address space. The networking and block device layers use
79 * this boolean for bounce buffer decisions.
81 #define PCI_DMA_BUS_IS_PHYS (1)
84 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
85 ** to both MMIO and I/O port space. Due to poor performance of I/O Port
86 ** access under HP PCI bus adapters, strongly reccomend use of MMIO
89 ** While I'm at it more PA programming notes:
91 ** 1) MMIO stores (writes) are posted operations. This means the processor
92 ** gets an "ACK" before the write actually gets to the device. A read
93 ** to the same device (or typically the bus adapter above it) will
94 ** force in-flight write transaction(s) out to the targeted device
95 ** before the read can complete.
97 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
98 ** respect to DMA on all platforms. Ie PIO data can reach the processor
99 ** before in-flight DMA reaches memory. Since most SMP PA platforms
100 ** are I/O coherent, it generally doesn't matter...but sometimes
103 ** I've helped device driver writers debug both types of problems.
105 struct pci_port_ops {
106 u8 (*inb) (struct pci_hba_data *hba, u16 port);
107 u16 (*inw) (struct pci_hba_data *hba, u16 port);
108 u32 (*inl) (struct pci_hba_data *hba, u16 port);
109 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
110 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
111 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
115 struct pci_bios_ops {
117 void (*fixup_bus)(struct pci_bus *bus);
120 /* pci_unmap_{single,page} is not a nop, thus... */
121 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
122 dma_addr_t ADDR_NAME;
123 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
125 #define pci_unmap_addr(PTR, ADDR_NAME) \
127 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
128 (((PTR)->ADDR_NAME) = (VAL))
129 #define pci_unmap_len(PTR, LEN_NAME) \
131 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
132 (((PTR)->LEN_NAME) = (VAL))
135 ** Stuff declared in arch/parisc/kernel/pci.c
137 extern struct pci_port_ops *pci_port;
138 extern struct pci_bios_ops *pci_bios;
139 extern int pci_post_reset_delay; /* delay after de-asserting #RESET */
140 extern int pci_hba_count;
141 extern struct pci_hba_data *parisc_pci_hba[];
144 extern void pcibios_register_hba(struct pci_hba_data *);
145 extern void pcibios_set_master(struct pci_dev *);
147 extern inline void pcibios_register_hba(struct pci_hba_data *x)
153 ** used by drivers/pci/pci.c:pci_do_scan_bus()
154 ** 0 == check if bridge is numbered before re-numbering.
155 ** 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
158 ** To date, only alpha sets this to one. We'll need to set this
159 ** to zero for legacy platforms and one for PAT platforms.
161 #define pcibios_assign_all_busses() (pdc_type == PDC_TYPE_PAT)
162 #define pcibios_scan_all_fns(a, b) 0
164 #define PCIBIOS_MIN_IO 0x10
165 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
167 /* Don't support DAC yet. */
168 #define pci_dac_dma_supported(pci_dev, mask) (0)
170 /* export the pci_ DMA API in terms of the dma_ one */
171 #include <asm-generic/pci-dma-compat.h>
174 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
175 struct resource *res);
177 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
181 #endif /* __ASM_PARISC_PCI_H */