2 * include/asm-ppc/ibm44x.h
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2002-2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifndef __ASM_IBM44x_H__
18 #define __ASM_IBM44x_H__
20 #include <linux/config.h>
23 #define NR_BOARD_IRQS 0
26 #define _IO_BASE isa_io_base
27 #define _ISA_MEM_BASE isa_mem_base
28 #define PCI_DRAM_OFFSET pci_dram_offset
30 /* TLB entry offset/size used for pinning kernel lowmem */
31 #define PPC44x_PIN_SHIFT 28
32 #define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
34 /* Lowest TLB slot consumed by the default pinned TLBs */
35 #define PPC44x_LOW_SLOT 63
38 * Standard 4GB "page" definitions
40 #define PPC44x_IO_PAGE 0x0000000100000000ULL
41 #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
42 #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
43 #define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
48 #define PPC44x_IO_LO 0x40000000
49 #define PPC44x_IO_HI 0x40001000
50 #define PPC44x_PCICFG_LO 0x0ec00000
51 #define PPC44x_PCICFG_HI 0x0ec7ffff
52 #define PPC44x_PCIMEM_LO 0x80002000
53 #define PPC44x_PCIMEM_HI 0xffffffff
56 * The "residual" board information structure the boot loader passes
64 #define SPRN_CPC0_GPIO 0xe5/BEARLRL
72 #define DCRN_CPR_CONFIG_ADDR 0xc
73 #define DCRN_CPR_CONFIG_DATA 0xd
75 #define DCRN_CPR_CLKUPD 0x0020
76 #define DCRN_CPR_PLLC 0x0040
77 #define DCRN_CPR_PLLD 0x0060
78 #define DCRN_CPR_PRIMAD 0x0080
79 #define DCRN_CPR_PRIMBD 0x00a0
80 #define DCRN_CPR_OPBD 0x00c0
81 #define DCRN_CPR_PERD 0x00e0
82 #define DCRN_CPR_MALD 0x0100
84 /* CPRs read/write helper macros */
85 #define CPR_READ(offset) ({\
86 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
87 mfdcr(DCRN_CPR_CONFIG_DATA);})
88 #define CPR_WRITE(offset, data) ({\
89 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
90 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
93 #define DCRN_SDR_CONFIG_ADDR 0xe
94 #define DCRN_SDR_CONFIG_DATA 0xf
95 #define DCRN_SDR_PFC0 0x4100
96 #define DCRN_SDR_PFC1 0x4101
97 #define DCRN_SDR_PFC1_EPS 0x1c00000
98 #define DCRN_SDR_PFC1_EPS_SHIFT 22
99 #define DCRN_SDR_PFC1_RMII 0x02000000
100 #define DCRN_SDR_MFR 0x4300
101 #define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
102 #define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
103 #define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
104 #define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
105 #define DCRN_SDR_MFR_T0TXFL 0x00080000
106 #define DCRN_SDR_MFR_T0TXFH 0x00040000
107 #define DCRN_SDR_MFR_T1TXFL 0x00020000
108 #define DCRN_SDR_MFR_T1TXFH 0x00010000
109 #define DCRN_SDR_MFR_E0TXFL 0x00008000
110 #define DCRN_SDR_MFR_E0TXFH 0x00004000
111 #define DCRN_SDR_MFR_E0RXFL 0x00002000
112 #define DCRN_SDR_MFR_E0RXFH 0x00001000
113 #define DCRN_SDR_MFR_E1TXFL 0x00000800
114 #define DCRN_SDR_MFR_E1TXFH 0x00000400
115 #define DCRN_SDR_MFR_E1RXFL 0x00000200
116 #define DCRN_SDR_MFR_E1RXFH 0x00000100
117 #define DCRN_SDR_MFR_E2TXFL 0x00000080
118 #define DCRN_SDR_MFR_E2TXFH 0x00000040
119 #define DCRN_SDR_MFR_E2RXFL 0x00000020
120 #define DCRN_SDR_MFR_E2RXFH 0x00000010
121 #define DCRN_SDR_MFR_E3TXFL 0x00000008
122 #define DCRN_SDR_MFR_E3TXFH 0x00000004
123 #define DCRN_SDR_MFR_E3RXFL 0x00000002
124 #define DCRN_SDR_MFR_E3RXFH 0x00000001
125 #define DCRN_SDR_UART0 0x0120
126 #define DCRN_SDR_UART1 0x0121
128 /* SDR read/write helper macros */
129 #define SDR_READ(offset) ({\
130 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
131 mfdcr(DCRN_SDR_CONFIG_DATA);})
132 #define SDR_WRITE(offset, data) ({\
133 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
134 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
135 #endif /* CONFIG_440GX */
138 #define DCRN_DMA0_BASE 0x100
139 #define DCRN_DMA1_BASE 0x108
140 #define DCRN_DMA2_BASE 0x110
141 #define DCRN_DMA3_BASE 0x118
142 #define DCRN_DMASR_BASE 0x120
143 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
144 #define DCRN_MAL_BASE 0x180
147 #define DCRN_UIC0_BASE 0xc0
148 #define DCRN_UIC1_BASE 0xd0
149 #define DCRN_UIC2_BASE 0x210
150 #define DCRN_UICB_BASE 0x200
151 #define UIC0 DCRN_UIC0_BASE
152 #define UIC1 DCRN_UIC1_BASE
153 #define UIC2 DCRN_UIC2_BASE
154 #define UICB DCRN_UICB_BASE
156 #define DCRN_UIC_SR(base) (base + 0x0)
157 #define DCRN_UIC_ER(base) (base + 0x2)
158 #define DCRN_UIC_CR(base) (base + 0x3)
159 #define DCRN_UIC_PR(base) (base + 0x4)
160 #define DCRN_UIC_TR(base) (base + 0x5)
161 #define DCRN_UIC_MSR(base) (base + 0x6)
162 #define DCRN_UIC_VR(base) (base + 0x7)
163 #define DCRN_UIC_VCR(base) (base + 0x8)
165 #define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
166 #define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
168 #define UICB_UIC0NC 0x40000000
169 #define UICB_UIC1NC 0x10000000
170 #define UICB_UIC2NC 0x04000000
173 #define DCRN_MALCR(base) (base + 0x0) /* Configuration */
174 #define DCRN_MALESR(base) (base + 0x1) /* Error Status */
175 #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
176 #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
177 #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
178 #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
179 #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
180 #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
181 #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
182 #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
183 #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
184 #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
185 #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
186 #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
187 #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
188 #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
189 #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
190 #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
191 #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
193 /* Compatibility DCRN's */
194 #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
195 #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
196 #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
197 #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
198 #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
199 #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
200 #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
201 #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
204 #define MALCR_MMSR 0x80000000 /* MAL Software reset */
205 #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
206 #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
207 #define MALCR_PLBP_3 0x00C00000 /* highest */
208 #define MALCR_GA 0x00200000 /* Guarded Active Bit */
209 #define MALCR_OA 0x00100000 /* Ordered Active Bit */
210 #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
211 #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
212 #define MALCR_PLBLT_2 0x00020000
213 #define MALCR_PLBLT_3 0x00010000
214 #define MALCR_PLBLT_4 0x00008000
216 #define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
218 #define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
220 #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
221 #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
222 #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
223 #define MALCR_LEA 0x00000002 /* Locked Error Active */
224 #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
226 #define MALESR_EVB 0x80000000 /* Error Valid Bit */
227 #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
228 #define MALESR_DE 0x00100000 /* Descriptor Error */
229 #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
230 #define MALESR_OTE 0x00040000 /* OPB Timeout Error */
231 #define MALESR_OSE 0x00020000 /* OPB Slave Error */
232 #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
233 #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
234 #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
235 #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
236 #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
237 #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
239 #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
240 #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
241 #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
242 #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
243 #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
244 /* DCRN_MALTXEOBISR */
245 #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
246 #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
248 /* 440GP PLB Arbiter DCRs */
249 #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
250 #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
251 #define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
252 #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
253 #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
254 #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
256 /* 440GP Clock, PM, chip control */
257 #define DCRN_CPC0_SR 0x0b0
258 #define DCRN_CPC0_ER 0x0b1
259 #define DCRN_CPC0_FR 0x0b2
260 #define DCRN_CPC0_SYS0 0x0e0
261 #define DCRN_CPC0_SYS1 0x0e1
262 #define DCRN_CPC0_CUST0 0x0e2
263 #define DCRN_CPC0_CUST1 0x0e3
264 #define DCRN_CPC0_STRP0 0x0e4
265 #define DCRN_CPC0_STRP1 0x0e5
266 #define DCRN_CPC0_STRP2 0x0e6
267 #define DCRN_CPC0_STRP3 0x0e7
268 #define DCRN_CPC0_GPIO 0x0e8
269 #define DCRN_CPC0_PLB 0x0e9
270 #define DCRN_CPC0_CR1 0x0ea
271 #define DCRN_CPC0_CR0 0x0eb
272 #define DCRN_CPC0_MIRQ0 0x0ec
273 #define DCRN_CPC0_MIRQ1 0x0ed
274 #define DCRN_CPC0_JTAGID 0x0ef
276 /* 440GP DMA controller DCRs */
277 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
278 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
279 #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
280 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
281 #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
282 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
283 #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
284 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
286 #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
287 #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
288 #define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
289 #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
290 #define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
291 #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
292 #define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
293 #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
295 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
296 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
297 #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
298 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
299 #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
300 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
301 #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
302 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
304 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
305 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
306 #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
307 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
308 #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
309 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
310 #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
311 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
313 #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
314 #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
315 #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
316 #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
318 /* 440GP DRAM controller DCRs */
319 #define DCRN_SDRAM0_CFGADDR 0x010
320 #define DCRN_SDRAM0_CFGDATA 0x011
322 #define SDRAM0_B0CR 0x40
323 #define SDRAM0_B1CR 0x44
324 #define SDRAM0_B2CR 0x48
325 #define SDRAM0_B3CR 0x4c
327 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001
328 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000
329 #define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
330 #define SDRAM_CONFIG_SIZE_8M 0x00000001
331 #define SDRAM_CONFIG_SIZE_16M 0x00000002
332 #define SDRAM_CONFIG_SIZE_32M 0x00000003
333 #define SDRAM_CONFIG_SIZE_64M 0x00000004
334 #define SDRAM_CONFIG_SIZE_128M 0x00000005
335 #define SDRAM_CONFIG_SIZE_256M 0x00000006
336 #define SDRAM_CONFIG_SIZE_512M 0x00000007
337 #define PPC44x_MEM_SIZE_8M 0x00800000
338 #define PPC44x_MEM_SIZE_16M 0x01000000
339 #define PPC44x_MEM_SIZE_32M 0x02000000
340 #define PPC44x_MEM_SIZE_64M 0x04000000
341 #define PPC44x_MEM_SIZE_128M 0x08000000
342 #define PPC44x_MEM_SIZE_256M 0x10000000
343 #define PPC44x_MEM_SIZE_512M 0x20000000
346 /* Internal SRAM Controller */
347 #define DCRN_SRAM0_SB0CR 0x020
348 #define DCRN_SRAM0_SB1CR 0x021
349 #define DCRN_SRAM0_SB2CR 0x022
350 #define DCRN_SRAM0_SB3CR 0x023
351 #define SRAM_SBCR_BAS0 0x80000000
352 #define SRAM_SBCR_BAS1 0x80010000
353 #define SRAM_SBCR_BAS2 0x80020000
354 #define SRAM_SBCR_BAS3 0x80030000
355 #define SRAM_SBCR_BU_MASK 0x00000180
356 #define SRAM_SBCR_BS_64KB 0x00000800
357 #define SRAM_SBCR_BU_RO 0x00000080
358 #define SRAM_SBCR_BU_RW 0x00000180
359 #define DCRN_SRAM0_BEAR 0x024
360 #define DCRN_SRAM0_BESR0 0x025
361 #define DCRN_SRAM0_BESR1 0x026
362 #define DCRN_SRAM0_PMEG 0x027
363 #define DCRN_SRAM0_CID 0x028
364 #define DCRN_SRAM0_REVID 0x029
365 #define DCRN_SRAM0_DPC 0x02a
366 #define SRAM_DPC_ENABLE 0x80000000
368 /* L2 Cache Controller */
369 #define DCRN_L2C0_CFG 0x030
370 #define L2C_CFG_L2M 0x80000000
371 #define L2C_CFG_ICU 0x40000000
372 #define L2C_CFG_DCU 0x20000000
373 #define L2C_CFG_DCW_MASK 0x1e000000
374 #define L2C_CFG_TPC 0x01000000
375 #define L2C_CFG_CPC 0x00800000
376 #define L2C_CFG_FRAN 0x00200000
377 #define L2C_CFG_SS_MASK 0x00180000
378 #define L2C_CFG_SS_256 0x00000000
379 #define L2C_CFG_CPIM 0x00040000
380 #define L2C_CFG_TPIM 0x00020000
381 #define L2C_CFG_LIM 0x00010000
382 #define L2C_CFG_PMUX_MASK 0x00007000
383 #define L2C_CFG_PMUX_SNP 0x00000000
384 #define L2C_CFG_PMUX_IF 0x00001000
385 #define L2C_CFG_PMUX_DF 0x00002000
386 #define L2C_CFG_PMUX_DS 0x00003000
387 #define L2C_CFG_PMIM 0x00000800
388 #define L2C_CFG_TPEI 0x00000400
389 #define L2C_CFG_CPEI 0x00000200
390 #define L2C_CFG_NAM 0x00000100
391 #define L2C_CFG_SMCM 0x00000080
392 #define L2C_CFG_NBRM 0x00000040
393 #define DCRN_L2C0_CMD 0x031
394 #define L2C_CMD_CLR 0x80000000
395 #define L2C_CMD_DIAG 0x40000000
396 #define L2C_CMD_INV 0x20000000
397 #define L2C_CMD_CCP 0x10000000
398 #define L2C_CMD_CTE 0x08000000
399 #define L2C_CMD_STRC 0x04000000
400 #define L2C_CMD_STPC 0x02000000
401 #define L2C_CMD_RPMC 0x01000000
402 #define L2C_CMD_HCC 0x00800000
403 #define DCRN_L2C0_ADDR 0x032
404 #define DCRN_L2C0_DATA 0x033
405 #define DCRN_L2C0_SR 0x034
406 #define L2C_SR_CC 0x80000000
407 #define L2C_SR_CPE 0x40000000
408 #define L2C_SR_TPE 0x20000000
409 #define L2C_SR_LRU 0x10000000
410 #define L2C_SR_PCS 0x08000000
411 #define DCRN_L2C0_REVID 0x035
412 #define DCRN_L2C0_SNP0 0x036
413 #define DCRN_L2C0_SNP1 0x037
414 #define L2C_SNP_BA_MASK 0xffff0000
415 #define L2C_SNP_SSR_MASK 0x0000f000
416 #define L2C_SNP_SSR_32G 0x0000f000
417 #define L2C_SNP_ESR 0x00000800
418 #endif /* CONFIG_440GX */
423 #define PCIX0_REG_BASE 0x20ec80000ULL
424 #define PCIX0_REG_SIZE 0x200
426 #define PCIX0_VENDID 0x000
427 #define PCIX0_DEVID 0x002
428 #define PCIX0_COMMAND 0x004
429 #define PCIX0_STATUS 0x006
430 #define PCIX0_REVID 0x008
431 #define PCIX0_CLS 0x009
432 #define PCIX0_CACHELS 0x00c
433 #define PCIX0_LATTIM 0x00d
434 #define PCIX0_HDTYPE 0x00e
435 #define PCIX0_BIST 0x00f
436 #define PCIX0_BAR0L 0x010
437 #define PCIX0_BAR0H 0x014
438 #define PCIX0_BAR1 0x018
439 #define PCIX0_BAR2L 0x01c
440 #define PCIX0_BAR2H 0x020
441 #define PCIX0_BAR3 0x024
442 #define PCIX0_CISPTR 0x028
443 #define PCIX0_SBSYSVID 0x02c
444 #define PCIX0_SBSYSID 0x02e
445 #define PCIX0_EROMBA 0x030
446 #define PCIX0_CAP 0x034
447 #define PCIX0_RES0 0x035
448 #define PCIX0_RES1 0x036
449 #define PCIX0_RES2 0x038
450 #define PCIX0_INTLN 0x03c
451 #define PCIX0_INTPN 0x03d
452 #define PCIX0_MINGNT 0x03e
453 #define PCIX0_MAXLTNCY 0x03f
454 #define PCIX0_BRDGOPT1 0x040
455 #define PCIX0_BRDGOPT2 0x044
456 #define PCIX0_ERREN 0x050
457 #define PCIX0_ERRSTS 0x054
458 #define PCIX0_PLBBESR 0x058
459 #define PCIX0_PLBBEARL 0x05c
460 #define PCIX0_PLBBEARH 0x060
461 #define PCIX0_POM0LAL 0x068
462 #define PCIX0_POM0LAH 0x06c
463 #define PCIX0_POM0SA 0x070
464 #define PCIX0_POM0PCIAL 0x074
465 #define PCIX0_POM0PCIAH 0x078
466 #define PCIX0_POM1LAL 0x07c
467 #define PCIX0_POM1LAH 0x080
468 #define PCIX0_POM1SA 0x084
469 #define PCIX0_POM1PCIAL 0x088
470 #define PCIX0_POM1PCIAH 0x08c
471 #define PCIX0_POM2SA 0x090
472 #define PCIX0_PIM0SAL 0x098
473 #define PCIX0_PIM0SA PCIX0_PIM0SAL
474 #define PCIX0_PIM0LAL 0x09c
475 #define PCIX0_PIM0LAH 0x0a0
476 #define PCIX0_PIM1SA 0x0a4
477 #define PCIX0_PIM1LAL 0x0a8
478 #define PCIX0_PIM1LAH 0x0ac
479 #define PCIX0_PIM2SAL 0x0b0
480 #define PCIX0_PIM2SA PCIX0_PIM2SAL
481 #define PCIX0_PIM2LAL 0x0b4
482 #define PCIX0_PIM2LAH 0x0b8
483 #define PCIX0_OMCAPID 0x0c0
484 #define PCIX0_OMNIPTR 0x0c1
485 #define PCIX0_OMMC 0x0c2
486 #define PCIX0_OMMA 0x0c4
487 #define PCIX0_OMMUA 0x0c8
488 #define PCIX0_OMMDATA 0x0cc
489 #define PCIX0_OMMEOI 0x0ce
490 #define PCIX0_PMCAPID 0x0d0
491 #define PCIX0_PMNIPTR 0x0d1
492 #define PCIX0_PMC 0x0d2
493 #define PCIX0_PMCSR 0x0d4
494 #define PCIX0_PMCSRBSE 0x0d6
495 #define PCIX0_PMDATA 0x0d7
496 #define PCIX0_PMSCRR 0x0d8
497 #define PCIX0_CAPID 0x0dc
498 #define PCIX0_NIPTR 0x0dd
499 #define PCIX0_CMD 0x0de
500 #define PCIX0_STS 0x0e0
501 #define PCIX0_IDR 0x0e4
502 #define PCIX0_CID 0x0e8
503 #define PCIX0_RID 0x0ec
504 #define PCIX0_PIM0SAH 0x0f8
505 #define PCIX0_PIM2SAH 0x0fc
506 #define PCIX0_MSGIL 0x100
507 #define PCIX0_MSGIH 0x104
508 #define PCIX0_MSGOL 0x108
509 #define PCIX0_MSGOH 0x10c
510 #define PCIX0_IM 0x1f8
521 #define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
523 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
525 #include <asm/ibm4xx.h>
527 #endif /* __ASSEMBLY__ */
528 #endif /* __ASM_IBM44x_H__ */
529 #endif /* __KERNEL__ */