2 * include/asm-ppc/ibm44x.h
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2002-2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifndef __ASM_IBM44x_H__
18 #define __ASM_IBM44x_H__
20 #include <linux/config.h>
24 * Data structure defining board information maintained by the boot
25 * ROM on IBM's "Ebony" evaluation board. An effort has been made to
26 * keep the field names consistent with the 8xx 'bd_t' board info
29 * Ebony firmware stores MAC addresses in the F/W VPD area. The
30 * firmware must store the other dynamic values in NVRAM like on
31 * the previous 40x systems so they should be accessible if we
34 typedef struct board_info {
35 unsigned char bi_enetaddr[2][6]; /* EMAC addresses */
36 unsigned int bi_opb_busfreq; /* OPB clock in Hz */
37 int bi_iic_fast[2]; /* Use fast i2c mode */
39 #endif /* __ASSEMBLY__ */
42 #define NR_BOARD_IRQS 0
45 #define _IO_BASE isa_io_base
46 #define _ISA_MEM_BASE isa_mem_base
47 #define PCI_DRAM_OFFSET pci_dram_offset
49 /* TLB entry offset/size used for pinning kernel lowmem */
50 #define PPC44x_PIN_SHIFT 28
51 #define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
53 /* Lowest TLB slot consumed by the default pinned TLBs */
54 #define PPC44x_LOW_SLOT 63
57 * Standard 4GB "page" definitions
59 #define PPC44x_IO_PAGE 0x0000000100000000ULL
60 #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
61 #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
62 #define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
67 #define PPC44x_IO_LO 0x40000000
68 #define PPC44x_IO_HI 0x40001000
69 #define PPC44x_PCICFG_LO 0x0ec00000
70 #define PPC44x_PCICFG_HI 0x0ec7ffff
71 #define PPC44x_PCIMEM_LO 0x80002000
72 #define PPC44x_PCIMEM_HI 0xffffffff
75 * The "residual" board information structure the boot loader passes
83 #define SPRN_CPC0_GPIO 0xe5/BEARLRL
91 #define DCRN_SDR_CONFIG_ADDR 0xe
92 #define DCRN_SDR_CONFIG_DATA 0xf
93 #define DCRN_SDR_PFC0 0x4100
94 #define DCRN_SDR_PFC1 0x4101
95 #define DCRN_SDR_MFR 0x4300
96 #define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
97 #define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
98 #define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
99 #define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
100 #define DCRN_SDR_MFR_T0TXFL 0x00080000
101 #define DCRN_SDR_MFR_T0TXFH 0x00040000
102 #define DCRN_SDR_MFR_T1TXFL 0x00020000
103 #define DCRN_SDR_MFR_T1TXFH 0x00010000
104 #define DCRN_SDR_MFR_E0TXFL 0x00008000
105 #define DCRN_SDR_MFR_E0TXFH 0x00004000
106 #define DCRN_SDR_MFR_E0RXFL 0x00002000
107 #define DCRN_SDR_MFR_E0RXFH 0x00001000
108 #define DCRN_SDR_MFR_E1TXFL 0x00000800
109 #define DCRN_SDR_MFR_E1TXFH 0x00000400
110 #define DCRN_SDR_MFR_E1RXFL 0x00000200
111 #define DCRN_SDR_MFR_E1RXFH 0x00000100
112 #define DCRN_SDR_MFR_E2TXFL 0x00000080
113 #define DCRN_SDR_MFR_E2TXFH 0x00000040
114 #define DCRN_SDR_MFR_E2RXFL 0x00000020
115 #define DCRN_SDR_MFR_E2RXFH 0x00000010
116 #define DCRN_SDR_MFR_E3TXFL 0x00000008
117 #define DCRN_SDR_MFR_E3TXFH 0x00000004
118 #define DCRN_SDR_MFR_E3RXFL 0x00000002
119 #define DCRN_SDR_MFR_E3RXFH 0x00000001
121 /* SDR read/write helper macros */
122 #define SDR_READ(offset) ({\
123 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
124 mfdcr(DCRN_SDR_CONFIG_DATA);})
125 #define SDR_WRITE(offset, data) ({\
126 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
127 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
128 #endif /* CONFIG_440GX */
131 #define DCRN_DMA0_BASE 0x100
132 #define DCRN_DMA1_BASE 0x108
133 #define DCRN_DMA2_BASE 0x110
134 #define DCRN_DMA3_BASE 0x118
135 #define DCRN_DMASR_BASE 0x120
136 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
137 #define DCRN_MAL_BASE 0x180
140 #define DCRN_UIC0_BASE 0xc0
141 #define DCRN_UIC1_BASE 0xd0
142 #define UIC0 DCRN_UIC0_BASE
143 #define UIC1 DCRN_UIC1_BASE
145 #define DCRN_UIC_SR(base) (base + 0x0)
146 #define DCRN_UIC_ER(base) (base + 0x2)
147 #define DCRN_UIC_CR(base) (base + 0x3)
148 #define DCRN_UIC_PR(base) (base + 0x4)
149 #define DCRN_UIC_TR(base) (base + 0x5)
150 #define DCRN_UIC_MSR(base) (base + 0x6)
151 #define DCRN_UIC_VR(base) (base + 0x7)
152 #define DCRN_UIC_VCR(base) (base + 0x8)
154 #define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
155 #define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
158 #define DCRN_MALCR(base) (base + 0x0) /* Configuration */
159 #define DCRN_MALESR(base) (base + 0x1) /* Error Status */
160 #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
161 #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
162 #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
163 #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
164 #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
165 #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
166 #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
167 #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
168 #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
169 #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
170 #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
171 #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
172 #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
173 #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
174 #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
175 #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
176 #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
178 /* Compatibility DCRN's */
179 #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
180 #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
181 #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
182 #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
183 #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
184 #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
185 #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
186 #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
189 #define MALCR_MMSR 0x80000000 /* MAL Software reset */
190 #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
191 #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
192 #define MALCR_PLBP_3 0x00C00000 /* highest */
193 #define MALCR_GA 0x00200000 /* Guarded Active Bit */
194 #define MALCR_OA 0x00100000 /* Ordered Active Bit */
195 #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
196 #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
197 #define MALCR_PLBLT_2 0x00020000
198 #define MALCR_PLBLT_3 0x00010000
199 #define MALCR_PLBLT_4 0x00008000
201 #define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
203 #define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
205 #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
206 #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
207 #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
208 #define MALCR_LEA 0x00000002 /* Locked Error Active */
209 #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
211 #define MALESR_EVB 0x80000000 /* Error Valid Bit */
212 #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
213 #define MALESR_DE 0x00100000 /* Descriptor Error */
214 #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
215 #define MALESR_OTE 0x00040000 /* OPB Timeout Error */
216 #define MALESR_OSE 0x00020000 /* OPB Slave Error */
217 #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
218 #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
219 #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
220 #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
221 #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
222 #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
224 #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
225 #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
226 #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
227 #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
228 #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
229 /* DCRN_MALTXEOBISR */
230 #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
231 #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
233 /* 440GP PLB Arbiter DCRs */
234 #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
235 #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
236 #define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
237 #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
238 #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
239 #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
241 /* 440GP Clock, PM, chip control */
242 #define DCRN_CPC0_SR 0x0b0
243 #define DCRN_CPC0_ER 0x0b1
244 #define DCRN_CPC0_FR 0x0b2
245 #define DCRN_CPC0_SYS0 0x0e0
246 #define DCRN_CPC0_SYS1 0x0e1
247 #define DCRN_CPC0_CUST0 0x0e2
248 #define DCRN_CPC0_CUST1 0x0e3
249 #define DCRN_CPC0_STRP0 0x0e4
250 #define DCRN_CPC0_STRP1 0x0e5
251 #define DCRN_CPC0_STRP2 0x0e6
252 #define DCRN_CPC0_STRP3 0x0e7
253 #define DCRN_CPC0_GPIO 0x0e8
254 #define DCRN_CPC0_PLB 0x0e9
255 #define DCRN_CPC0_CR1 0x0ea
256 #define DCRN_CPC0_CR0 0x0eb
257 #define DCRN_CPC0_MIRQ0 0x0ec
258 #define DCRN_CPC0_MIRQ1 0x0ed
259 #define DCRN_CPC0_JTAGID 0x0ef
261 /* 440GP DMA controller DCRs */
262 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
263 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
264 #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
265 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
266 #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
267 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
268 #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
269 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
271 #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
272 #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
273 #define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
274 #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
275 #define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
276 #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
277 #define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
278 #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
280 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
281 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
282 #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
283 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
284 #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
285 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
286 #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
287 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
289 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
290 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
291 #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
292 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
293 #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
294 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
295 #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
296 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
298 #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
299 #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
300 #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
301 #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
303 /* 440GP DRAM controller DCRs */
304 #define DCRN_SDRAM0_CFGADDR 0x010
305 #define DCRN_SDRAM0_CFGDATA 0x011
307 #define SDRAM0_B0CR 0x40
308 #define SDRAM0_B1CR 0x44
309 #define SDRAM0_B2CR 0x48
310 #define SDRAM0_B3CR 0x4c
312 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001
313 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000
314 #define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
315 #define SDRAM_CONFIG_SIZE_8M 0x00000001
316 #define SDRAM_CONFIG_SIZE_16M 0x00000002
317 #define SDRAM_CONFIG_SIZE_32M 0x00000003
318 #define SDRAM_CONFIG_SIZE_64M 0x00000004
319 #define SDRAM_CONFIG_SIZE_128M 0x00000005
320 #define SDRAM_CONFIG_SIZE_256M 0x00000006
321 #define SDRAM_CONFIG_SIZE_512M 0x00000007
322 #define PPC44x_MEM_SIZE_8M 0x00800000
323 #define PPC44x_MEM_SIZE_16M 0x01000000
324 #define PPC44x_MEM_SIZE_32M 0x02000000
325 #define PPC44x_MEM_SIZE_64M 0x04000000
326 #define PPC44x_MEM_SIZE_128M 0x08000000
327 #define PPC44x_MEM_SIZE_256M 0x10000000
328 #define PPC44x_MEM_SIZE_512M 0x20000000
333 #define PCIX0_REG_BASE 0x20ec80000ULL
334 #define PCIX0_REG_SIZE 0x200
336 #define PCIX0_VENDID 0x000
337 #define PCIX0_DEVID 0x002
338 #define PCIX0_COMMAND 0x004
339 #define PCIX0_STATUS 0x006
340 #define PCIX0_REVID 0x008
341 #define PCIX0_CLS 0x009
342 #define PCIX0_CACHELS 0x00c
343 #define PCIX0_LATTIM 0x00d
344 #define PCIX0_HDTYPE 0x00e
345 #define PCIX0_BIST 0x00f
346 #define PCIX0_BAR0L 0x010
347 #define PCIX0_BAR0H 0x014
348 #define PCIX0_BAR1 0x018
349 #define PCIX0_BAR2L 0x01c
350 #define PCIX0_BAR2H 0x020
351 #define PCIX0_BAR3 0x024
352 #define PCIX0_CISPTR 0x028
353 #define PCIX0_SBSYSVID 0x02c
354 #define PCIX0_SBSYSID 0x02e
355 #define PCIX0_EROMBA 0x030
356 #define PCIX0_CAP 0x034
357 #define PCIX0_RES0 0x035
358 #define PCIX0_RES1 0x036
359 #define PCIX0_RES2 0x038
360 #define PCIX0_INTLN 0x03c
361 #define PCIX0_INTPN 0x03d
362 #define PCIX0_MINGNT 0x03e
363 #define PCIX0_MAXLTNCY 0x03f
364 #define PCIX0_BRDGOPT1 0x040
365 #define PCIX0_BRDGOPT2 0x044
366 #define PCIX0_ERREN 0x050
367 #define PCIX0_ERRSTS 0x054
368 #define PCIX0_PLBBESR 0x058
369 #define PCIX0_PLBBEARL 0x05c
370 #define PCIX0_PLBBEARH 0x060
371 #define PCIX0_POM0LAL 0x068
372 #define PCIX0_POM0LAH 0x06c
373 #define PCIX0_POM0SA 0x070
374 #define PCIX0_POM0PCIAL 0x074
375 #define PCIX0_POM0PCIAH 0x078
376 #define PCIX0_POM1LAL 0x07c
377 #define PCIX0_POM1LAH 0x080
378 #define PCIX0_POM1SA 0x084
379 #define PCIX0_POM1PCIAL 0x088
380 #define PCIX0_POM1PCIAH 0x08c
381 #define PCIX0_POM2SA 0x090
382 #define PCIX0_PIM0SAL 0x098
383 #define PCIX0_PIM0SA PCIX0_PIM0SAL
384 #define PCIX0_PIM0LAL 0x09c
385 #define PCIX0_PIM0LAH 0x0a0
386 #define PCIX0_PIM1SA 0x0a4
387 #define PCIX0_PIM1LAL 0x0a8
388 #define PCIX0_PIM1LAH 0x0ac
389 #define PCIX0_PIM2SAL 0x0b0
390 #define PCIX0_PIM2SA PCIX0_PIM2SAL
391 #define PCIX0_PIM2LAL 0x0b4
392 #define PCIX0_PIM2LAH 0x0b8
393 #define PCIX0_OMCAPID 0x0c0
394 #define PCIX0_OMNIPTR 0x0c1
395 #define PCIX0_OMMC 0x0c2
396 #define PCIX0_OMMA 0x0c4
397 #define PCIX0_OMMUA 0x0c8
398 #define PCIX0_OMMDATA 0x0cc
399 #define PCIX0_OMMEOI 0x0ce
400 #define PCIX0_PMCAPID 0x0d0
401 #define PCIX0_PMNIPTR 0x0d1
402 #define PCIX0_PMC 0x0d2
403 #define PCIX0_PMCSR 0x0d4
404 #define PCIX0_PMCSRBSE 0x0d6
405 #define PCIX0_PMDATA 0x0d7
406 #define PCIX0_PMSCRR 0x0d8
407 #define PCIX0_CAPID 0x0dc
408 #define PCIX0_NIPTR 0x0dd
409 #define PCIX0_CMD 0x0de
410 #define PCIX0_STS 0x0e0
411 #define PCIX0_IDR 0x0e4
412 #define PCIX0_CID 0x0e8
413 #define PCIX0_RID 0x0ec
414 #define PCIX0_PIM0SAH 0x0f8
415 #define PCIX0_PIM2SAH 0x0fc
416 #define PCIX0_MSGIL 0x100
417 #define PCIX0_MSGIH 0x104
418 #define PCIX0_MSGOL 0x108
419 #define PCIX0_MSGOH 0x10c
420 #define PCIX0_IM 0x1f8
427 #define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
429 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
431 #include <asm/ibm4xx.h>
433 #endif /* __ASSEMBLY__ */
434 #endif /* __ASM_IBM44x_H__ */
435 #endif /* __KERNEL__ */