5 #include <linux/config.h>
6 #include <linux/types.h>
10 #include <asm/byteorder.h>
13 #define SIO_CONFIG_RA 0x398
14 #define SIO_CONFIG_RD 0x399
18 #define PMAC_ISA_MEM_BASE 0
19 #define PMAC_PCI_DRAM_OFFSET 0
20 #define CHRP_ISA_IO_BASE 0xf8000000
21 #define CHRP_ISA_MEM_BASE 0xf7000000
22 #define CHRP_PCI_DRAM_OFFSET 0
23 #define PREP_ISA_IO_BASE 0x80000000
24 #define PREP_ISA_MEM_BASE 0xc0000000
25 #define PREP_PCI_DRAM_OFFSET 0x80000000
27 #if defined(CONFIG_4xx)
28 #include <asm/ibm4xx.h>
29 #elif defined(CONFIG_8xx)
30 #include <asm/mpc8xx.h>
31 #elif defined(CONFIG_8260)
32 #include <asm/mpc8260.h>
33 #elif defined(CONFIG_85xx)
34 #include <asm/mpc85xx.h>
35 #elif defined(CONFIG_APUS)
37 #define _ISA_MEM_BASE 0
38 #define PCI_DRAM_OFFSET 0
39 #else /* Everyone else */
40 #define _IO_BASE isa_io_base
41 #define _ISA_MEM_BASE isa_mem_base
42 #define PCI_DRAM_OFFSET pci_dram_offset
43 #endif /* Platform-dependent I/O */
45 extern unsigned long isa_io_base;
46 extern unsigned long isa_mem_base;
47 extern unsigned long pci_dram_offset;
49 #define readb(addr) in_8((volatile u8 *)(addr))
50 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
51 #if defined(CONFIG_APUS)
52 #define readw(addr) (*(volatile u16 *) (addr))
53 #define readl(addr) (*(volatile u32 *) (addr))
54 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
55 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
57 #define readw(addr) in_le16((volatile u16 *)(addr))
58 #define readl(addr) in_le32((volatile u32 *)(addr))
59 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
60 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
61 #endif /* CONFIG_APUS */
63 #define readb_relaxed(addr) readb(addr)
64 #define readw_relaxed(addr) readw(addr)
65 #define readl_relaxed(addr) readl(addr)
67 #define __raw_readb(addr) (*(volatile unsigned char *)(addr))
68 #define __raw_readw(addr) (*(volatile unsigned short *)(addr))
69 #define __raw_readl(addr) (*(volatile unsigned int *)(addr))
70 #define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v))
71 #define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v))
72 #define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v))
75 * The insw/outsw/insl/outsl macros don't do byte-swapping.
76 * They are only used in practice for transferring buffers which
77 * are arrays of bytes, and byte-swapping is not appropriate in
80 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
81 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
82 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
83 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
84 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
85 #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
88 * On powermacs, we will get a machine check exception if we
89 * try to read data from a non-existent I/O port. Because the
90 * machine check is an asynchronous exception, it isn't
91 * well-defined which instruction SRR0 will point to when the
93 * With the sequence below (twi; isync; nop), we have found that
94 * the machine check occurs on one of the three instructions on
95 * all PPC implementations tested so far. The twi and isync are
96 * needed on the 601 (in fact twi; sync works too), the isync and
97 * nop are needed on 604[e|r], and any of twi, sync or isync will
98 * work on 603[e], 750, 74xx.
99 * The twi creates an explicit data dependency on the returned
100 * value which seems to be needed to make the 601 wait for the
104 #define __do_in_asm(name, op) \
105 extern __inline__ unsigned int name(unsigned int port) \
108 __asm__ __volatile__( \
114 ".section .fixup,\"ax\"\n" \
118 ".section __ex_table,\"a\"\n" \
125 : "r" (port + _IO_BASE)); \
129 #define __do_out_asm(name, op) \
130 extern __inline__ void name(unsigned int val, unsigned int port) \
132 __asm__ __volatile__( \
136 ".section __ex_table,\"a\"\n" \
140 : : "r" (val), "r" (port + _IO_BASE)); \
143 __do_out_asm(outb, "stbx")
145 __do_in_asm(inb, "lbzx")
146 __do_in_asm(inw, "lhz%U1%X1")
147 __do_in_asm(inl, "lwz%U1%X1")
148 __do_out_asm(outl,"stw%U0%X0")
149 __do_out_asm(outw, "sth%U0%X0")
150 #elif defined (CONFIG_8260_PCI9)
151 /* in asm cannot be defined if PCI9 workaround is used */
152 #define inb(port) in_8((u8 *)((port)+_IO_BASE))
153 #define inw(port) in_le16((u16 *)((port)+_IO_BASE))
154 #define inl(port) in_le32((u32 *)((port)+_IO_BASE))
155 __do_out_asm(outw, "sthbrx")
156 __do_out_asm(outl, "stwbrx")
158 __do_in_asm(inb, "lbzx")
159 __do_in_asm(inw, "lhbrx")
160 __do_in_asm(inl, "lwbrx")
161 __do_out_asm(outw, "sthbrx")
162 __do_out_asm(outl, "stwbrx")
166 #define inb_p(port) inb((port))
167 #define outb_p(val, port) outb((val), (port))
168 #define inw_p(port) inw((port))
169 #define outw_p(val, port) outw((val), (port))
170 #define inl_p(port) inl((port))
171 #define outl_p(val, port) outl((val), (port))
173 extern void _insb(volatile u8 *port, void *buf, int ns);
174 extern void _outsb(volatile u8 *port, const void *buf, int ns);
175 extern void _insw(volatile u16 *port, void *buf, int ns);
176 extern void _outsw(volatile u16 *port, const void *buf, int ns);
177 extern void _insl(volatile u32 *port, void *buf, int nl);
178 extern void _outsl(volatile u32 *port, const void *buf, int nl);
179 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
180 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
181 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
182 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
185 * The *_ns versions below don't do byte-swapping.
186 * Neither do the standard versions now, these are just here
189 #define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
190 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
191 #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
192 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
195 #define IO_SPACE_LIMIT ~0
197 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
198 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
199 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
202 * Map in an area of physical address space, for accessing
205 extern void *__ioremap(phys_addr_t address, unsigned long size,
206 unsigned long flags);
207 extern void *ioremap(phys_addr_t address, unsigned long size);
209 extern void *ioremap64(unsigned long long address, unsigned long size);
211 #define ioremap_nocache(addr, size) ioremap((addr), (size))
212 extern void iounmap(void *addr);
213 extern unsigned long iopa(unsigned long addr);
214 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
215 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
216 unsigned int size, int flags);
219 * The PCI bus is inherently Little-Endian. The PowerPC is being
220 * run Big-Endian. Thus all values which cross the [PCI] barrier
221 * must be endian-adjusted. Also, the local DRAM has a different
222 * address from the PCI point of view, thus buffer addresses also
223 * have to be modified [mapped] appropriately.
225 extern inline unsigned long virt_to_bus(volatile void * address)
228 if (address == (void *)0)
230 return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
232 return iopa ((unsigned long) address);
236 extern inline void * bus_to_virt(unsigned long address)
241 return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
243 return (void*) mm_ptov (address);
248 * Change virtual addresses to physical addresses and vv, for
249 * addresses in the area where the kernel has the RAM mapped.
251 extern inline unsigned long virt_to_phys(volatile void * address)
254 return (unsigned long) address - KERNELBASE;
256 return iopa ((unsigned long) address);
260 extern inline void * phys_to_virt(unsigned long address)
263 return (void *) (address + KERNELBASE);
265 return (void*) mm_ptov (address);
270 * Change "struct page" to physical address.
272 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
273 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
276 * Enforce In-order Execution of I/O:
277 * Acts as a barrier to ensure all previous I/O accesses have
278 * completed before any further ones are issued.
280 extern inline void eieio(void)
282 __asm__ __volatile__ ("eieio" : : : "memory");
285 /* Enforce in-order execution of data I/O.
286 * No distinction between read/write on PPC; use eieio for all three.
288 #define iobarrier_rw() eieio()
289 #define iobarrier_r() eieio()
290 #define iobarrier_w() eieio()
293 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
295 * Read operations have additional twi & isync to make sure the read
296 * is actually performed (i.e. the data has come back) before we start
297 * executing any following instructions.
299 extern inline int in_8(volatile unsigned char *addr)
303 __asm__ __volatile__(
306 "isync" : "=r" (ret) : "m" (*addr));
310 extern inline void out_8(volatile unsigned char *addr, int val)
312 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
315 extern inline int in_le16(volatile unsigned short *addr)
319 __asm__ __volatile__("lhbrx %0,0,%1;\n"
321 "isync" : "=r" (ret) :
322 "r" (addr), "m" (*addr));
326 extern inline int in_be16(volatile unsigned short *addr)
330 __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
332 "isync" : "=r" (ret) : "m" (*addr));
336 extern inline void out_le16(volatile unsigned short *addr, int val)
338 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
339 "r" (val), "r" (addr));
342 extern inline void out_be16(volatile unsigned short *addr, int val)
344 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
347 extern inline unsigned in_le32(volatile unsigned *addr)
351 __asm__ __volatile__("lwbrx %0,0,%1;\n"
353 "isync" : "=r" (ret) :
354 "r" (addr), "m" (*addr));
358 extern inline unsigned in_be32(volatile unsigned *addr)
362 __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
364 "isync" : "=r" (ret) : "m" (*addr));
368 extern inline void out_le32(volatile unsigned *addr, int val)
370 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
371 "r" (val), "r" (addr));
374 extern inline void out_be32(volatile unsigned *addr, int val)
376 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
379 static inline int check_signature(unsigned long io_addr,
380 const unsigned char *signature, int length)
384 if (readb(io_addr) != *signature)
395 /* Make some pcmcia drivers happy */
396 static inline int isa_check_signature(unsigned long io_addr,
397 const unsigned char *signature, int length)
402 #endif /* _PPC_IO_H */
404 #ifdef CONFIG_8260_PCI9
405 #include <asm/mpc8260_pci9.h>
408 #endif /* __KERNEL__ */