5 #include <linux/config.h>
6 #include <asm/machdep.h> /* ppc_md */
7 #include <asm/atomic.h>
10 * These constants are used for passing information about interrupt
11 * signal polarity and level/edge sensing to the low-level PIC chip
14 #define IRQ_SENSE_MASK 0x1
15 #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
16 #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
18 #define IRQ_POLARITY_MASK 0x2
19 #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
20 #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
22 #if defined(CONFIG_40x)
23 #include <asm/ibm4xx.h>
26 #define NR_BOARD_IRQS 0
29 #ifndef UIC_WIDTH /* Number of interrupts per device */
33 #ifndef NR_UICS /* number of UIC devices */
37 #if defined (CONFIG_403)
39 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
40 * 32 possible interrupts, a majority of which are not implemented on
41 * all cores. There are six configurable, external interrupt pins and
42 * there are eight internal interrupts for the on-chip serial port
43 * (SPU), DMA controller, and JTAG controller.
47 #define NR_AIC_IRQS 32
48 #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
50 #elif !defined (CONFIG_403)
53 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
54 * possible interrupts as well. There are seven, configurable external
55 * interrupt pins and there are 17 internal interrupts for the on-chip
56 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
61 #define NR_UIC_IRQS UIC_WIDTH
62 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
65 irq_canonicalize(int irq)
70 #elif defined(CONFIG_44x)
71 #include <asm/ibm44x.h>
73 #define NR_UIC_IRQS 32
74 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
77 irq_canonicalize(int irq)
82 #elif defined(CONFIG_8xx)
84 /* Now include the board configuration specific associations.
86 #include <asm/mpc8xx.h>
88 /* The MPC8xx cores have 16 possible interrupts. There are eight
89 * possible level sensitive interrupts assigned and generated internally
90 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
91 * There are eight external interrupts (IRQs) that can be configured
92 * as either level or edge sensitive.
94 * On some implementations, there is also the possibility of an 8259
95 * through the PCI and PCI-ISA bridges.
97 * We are "flattening" the interrupt vectors of the cascaded CPM
98 * and 8259 interrupt controllers so that we can uniquely identify
99 * any interrupt source with a single integer.
101 #define NR_SIU_INTS 16
102 #define NR_CPM_INTS 32
104 #define NR_8259_INTS 0
107 #define SIU_IRQ_OFFSET 0
108 #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
109 #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
111 #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
113 /* These values must be zero-based and map 1:1 with the SIU configuration.
114 * They are used throughout the 8xx I/O subsystem to generate
115 * interrupt masks, flags, and other control patterns. This is why the
116 * current kernel assumption of the 8259 as the base controller is such
117 * a pain in the butt.
119 #define SIU_IRQ0 (0) /* Highest priority */
120 #define SIU_LEVEL0 (1)
122 #define SIU_LEVEL1 (3)
124 #define SIU_LEVEL2 (5)
126 #define SIU_LEVEL3 (7)
128 #define SIU_LEVEL4 (9)
129 #define SIU_IRQ5 (10)
130 #define SIU_LEVEL5 (11)
131 #define SIU_IRQ6 (12)
132 #define SIU_LEVEL6 (13)
133 #define SIU_IRQ7 (14)
134 #define SIU_LEVEL7 (15)
136 /* The internal interrupts we can configure as we see fit.
137 * My personal preference is CPM at level 2, which puts it above the
138 * MBX PCI/ISA/IDE interrupts.
140 #ifndef PIT_INTERRUPT
141 #define PIT_INTERRUPT SIU_LEVEL0
143 #ifndef CPM_INTERRUPT
144 #define CPM_INTERRUPT SIU_LEVEL2
146 #ifndef PCMCIA_INTERRUPT
147 #define PCMCIA_INTERRUPT SIU_LEVEL6
149 #ifndef DEC_INTERRUPT
150 #define DEC_INTERRUPT SIU_LEVEL7
153 /* Some internal interrupt registers use an 8-bit mask for the interrupt
154 * level instead of a number.
156 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
158 /* always the same on 8xx -- Cort */
159 static __inline__ int irq_canonicalize(int irq)
164 #elif defined(CONFIG_CPM2) && defined(CONFIG_85xx)
165 /* Now include the board configuration specific associations.
167 #include <asm/mpc85xx.h>
169 /* The MPC8560 openpic has 32 internal interrupts and 12 external
172 * We are "flattening" the interrupt vectors of the cascaded CPM
173 * so that we can uniquely identify any interrupt source with a
176 #define NR_CPM_INTS 64
177 #define NR_EPIC_INTS 44
179 #define NR_8259_INTS 0
181 #define NUM_8259_INTERRUPTS NR_8259_INTS
183 #ifndef CPM_IRQ_OFFSET
184 #define CPM_IRQ_OFFSET 0
187 #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
189 /* These values must be zero-based and map 1:1 with the EPIC configuration.
190 * They are used throughout the 8560 I/O subsystem to generate
191 * interrupt masks, flags, and other control patterns. This is why the
192 * current kernel assumption of the 8259 as the base controller is such
193 * a pain in the butt.
196 #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
197 #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
198 #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
199 #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
200 #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
201 #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
202 #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
203 #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
204 #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
205 #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
206 #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
207 #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
208 #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
209 #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
210 #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
211 #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
212 #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
213 #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
214 #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
215 #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
216 #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
217 #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
218 #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
219 #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
220 #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
221 #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
222 #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
223 #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
224 #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
225 #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
226 #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
227 #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
228 #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
229 #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
230 #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
232 static __inline__ int irq_canonicalize(int irq)
237 #else /* CONFIG_40x + CONFIG_8xx */
239 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
240 * so it is the max of them all
246 #define NUM_8259_INTERRUPTS 16
248 #else /* CONFIG_8260 */
250 /* The 8260 has an internal interrupt controller with a maximum of
251 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
252 * Don't be confused by the 8260 documentation where they list an
253 * "interrupt number" and "interrupt vector". We are only interested
254 * in the interrupt vector. There are "reserved" holes where the
255 * vector number increases, but the interrupt number in the table does not.
256 * (Document errata updates have fixed this...make sure you have up to
257 * date processor documentation -- Dan).
259 #define NR_SIU_INTS 64
261 #define SIU_INT_ERROR ((uint)0x00)
262 #define SIU_INT_I2C ((uint)0x01)
263 #define SIU_INT_SPI ((uint)0x02)
264 #define SIU_INT_RISC ((uint)0x03)
265 #define SIU_INT_SMC1 ((uint)0x04)
266 #define SIU_INT_SMC2 ((uint)0x05)
267 #define SIU_INT_IDMA1 ((uint)0x06)
268 #define SIU_INT_IDMA2 ((uint)0x07)
269 #define SIU_INT_IDMA3 ((uint)0x08)
270 #define SIU_INT_IDMA4 ((uint)0x09)
271 #define SIU_INT_SDMA ((uint)0x0a)
272 #define SIU_INT_TIMER1 ((uint)0x0c)
273 #define SIU_INT_TIMER2 ((uint)0x0d)
274 #define SIU_INT_TIMER3 ((uint)0x0e)
275 #define SIU_INT_TIMER4 ((uint)0x0f)
276 #define SIU_INT_TMCNT ((uint)0x10)
277 #define SIU_INT_PIT ((uint)0x11)
278 #define SIU_INT_IRQ1 ((uint)0x13)
279 #define SIU_INT_IRQ2 ((uint)0x14)
280 #define SIU_INT_IRQ3 ((uint)0x15)
281 #define SIU_INT_IRQ4 ((uint)0x16)
282 #define SIU_INT_IRQ5 ((uint)0x17)
283 #define SIU_INT_IRQ6 ((uint)0x18)
284 #define SIU_INT_IRQ7 ((uint)0x19)
285 #define SIU_INT_FCC1 ((uint)0x20)
286 #define SIU_INT_FCC2 ((uint)0x21)
287 #define SIU_INT_FCC3 ((uint)0x22)
288 #define SIU_INT_MCC1 ((uint)0x24)
289 #define SIU_INT_MCC2 ((uint)0x25)
290 #define SIU_INT_SCC1 ((uint)0x28)
291 #define SIU_INT_SCC2 ((uint)0x29)
292 #define SIU_INT_SCC3 ((uint)0x2a)
293 #define SIU_INT_SCC4 ((uint)0x2b)
294 #define SIU_INT_PC15 ((uint)0x30)
295 #define SIU_INT_PC14 ((uint)0x31)
296 #define SIU_INT_PC13 ((uint)0x32)
297 #define SIU_INT_PC12 ((uint)0x33)
298 #define SIU_INT_PC11 ((uint)0x34)
299 #define SIU_INT_PC10 ((uint)0x35)
300 #define SIU_INT_PC9 ((uint)0x36)
301 #define SIU_INT_PC8 ((uint)0x37)
302 #define SIU_INT_PC7 ((uint)0x38)
303 #define SIU_INT_PC6 ((uint)0x39)
304 #define SIU_INT_PC5 ((uint)0x3a)
305 #define SIU_INT_PC4 ((uint)0x3b)
306 #define SIU_INT_PC3 ((uint)0x3c)
307 #define SIU_INT_PC2 ((uint)0x3d)
308 #define SIU_INT_PC1 ((uint)0x3e)
309 #define SIU_INT_PC0 ((uint)0x3f)
311 #endif /* CONFIG_8260 */
314 * This gets called from serial.c, which is now used on
315 * powermacs as well as prep/chrp boxes.
316 * Prep and chrp both have cascaded 8259 PICs.
318 static __inline__ int irq_canonicalize(int irq)
320 if (ppc_md.irq_canonicalize)
321 return ppc_md.irq_canonicalize(irq);
327 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
328 /* pedantic: these are long because they are used with set_bit --RR */
329 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
330 extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
331 extern atomic_t ppc_n_lost_interrupts;
335 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
337 #endif /* _ASM_IRQ_H */
338 #endif /* __KERNEL__ */