2 * include/asm-ppc/gt64260_defs.h
4 * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
7 * Author: Mark A. Greer <mgreer@mvista.com>
9 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #ifndef __ASMPPC_MV64x60_DEFS_H
15 #define __ASMPPC_MV64x60_DEFS_H
18 * Define the Marvell bridges that are supported
20 #define MV64x60_TYPE_INVALID 0
21 #define MV64x60_TYPE_GT64260A 1
22 #define MV64x60_TYPE_GT64260B 2
23 #define MV64x60_TYPE_MV64360 3
24 #define MV64x60_TYPE_MV64361 4
25 #define MV64x60_TYPE_MV64362 5
26 #define MV64x60_TYPE_MV64460 6
29 /* Revisions of each supported chip */
30 #define GT64260_REV_A 0x10
31 #define GT64260_REV_B 0x20
35 /* Minimum window size supported by 64260 is 1MB */
36 #define GT64260_WINDOW_SIZE_MIN 0x00100000
37 #define MV64360_WINDOW_SIZE_MIN 0x00010000
39 /* IRQ's for embedded controllers */
40 #define MV64x60_IRQ_DEV 1
41 #define MV64x60_IRQ_CPU_ERR 3
42 #define MV64x60_IRQ_TIMER_0_1 8
43 #define MV64x60_IRQ_TIMER_2_3 9
44 #define MV64x60_IRQ_TIMER_4_5 10
45 #define MV64x60_IRQ_TIMER_6_7 11
46 #define MV64x60_IRQ_ETH_0 32
47 #define MV64x60_IRQ_ETH_1 33
48 #define MV64x60_IRQ_ETH_2 34
49 #define MV64x60_IRQ_SDMA_0 36
50 #define MV64x60_IRQ_I2C 37
51 #define MV64x60_IRQ_SDMA_1 38
52 #define MV64x60_IRQ_BRG 39
53 #define MV64x60_IRQ_MPSC_0 40
54 #define MV64x60_IRQ_MPSC_1 42
55 #define MV64x60_IRQ_COMM 43
57 #define MV64360_IRQ_PCI0 12
58 #define MV64360_IRQ_SRAM_PAR_ERR 13
59 #define MV64360_IRQ_PCI1 16
61 /* Offsets for register blocks */
62 #define MV64x60_MPSC_0_OFFSET 0x8000
63 #define MV64x60_MPSC_1_OFFSET 0x9000
64 #define MV64x60_MPSC_ROUTING_OFFSET 0xb400
65 #define MV64x60_SDMA_0_OFFSET 0x4000
66 #define MV64x60_SDMA_1_OFFSET 0x6000
67 #define MV64x60_SDMA_INTR_OFFSET 0xb800
68 #define MV64x60_BRG_0_OFFSET 0xb200
69 #define MV64x60_BRG_1_OFFSET 0xb208
72 *****************************************************************************
74 * CPU Interface Registers
76 *****************************************************************************
79 /* CPU physical address of 64260's registers */
80 #define MV64x60_INTERNAL_SPACE_DECODE 0x0068
81 #define MV64x60_INTERNAL_SPACE_SIZE 0x10000
82 #define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000
84 #define MV64360_CPU_BAR_ENABLE 0x0278
86 /* CPU Memory Controller Window Registers (4 windows) */
87 #define MV64x60_CPU2MEM_WINDOWS 4
89 #define MV64x60_CPU2MEM_0_BASE 0x0008
90 #define MV64x60_CPU2MEM_0_SIZE 0x0010
91 #define MV64x60_CPU2MEM_1_BASE 0x0208
92 #define MV64x60_CPU2MEM_1_SIZE 0x0210
93 #define MV64x60_CPU2MEM_2_BASE 0x0018
94 #define MV64x60_CPU2MEM_2_SIZE 0x0020
95 #define MV64x60_CPU2MEM_3_BASE 0x0218
96 #define MV64x60_CPU2MEM_3_SIZE 0x0220
98 /* CPU Device Controller Window Registers (4 windows) */
99 #define MV64x60_CPU2DEV_CS_WINDOWS 4
101 #define MV64x60_CPU2DEV_0_BASE 0x0028
102 #define MV64x60_CPU2DEV_0_SIZE 0x0030
103 #define MV64x60_CPU2DEV_1_BASE 0x0228
104 #define MV64x60_CPU2DEV_1_SIZE 0x0230
105 #define MV64x60_CPU2DEV_2_BASE 0x0248
106 #define MV64x60_CPU2DEV_2_SIZE 0x0250
107 #define MV64x60_CPU2DEV_3_BASE 0x0038
108 #define MV64x60_CPU2DEV_3_SIZE 0x0040
110 #define MV64x60_CPU2BOOT_0_BASE 0x0238
111 #define MV64x60_CPU2BOOT_0_SIZE 0x0240
113 /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
114 #define MV64x60_PCI_BUSES 2
115 #define MV64x60_PCI_IO_WINDOWS_PER_BUS 1
116 #define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4
118 #define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000
119 #define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
120 #define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000
121 #define MV64x60_CPU2PCI_SWAP_WORD 0x03000000
123 #define MV64x60_CPU2PCI_MEM_REQ64 (1<<27)
125 #define MV64x60_CPU2PCI0_IO_BASE 0x0048
126 #define MV64x60_CPU2PCI0_IO_SIZE 0x0050
127 #define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
128 #define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
129 #define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080
130 #define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088
131 #define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258
132 #define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260
133 #define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280
134 #define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288
136 #define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
137 #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
138 #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
139 #define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100
140 #define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328
141 #define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8
142 #define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330
143 #define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300
144 #define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338
146 #define MV64x60_CPU2PCI1_IO_BASE 0x0090
147 #define MV64x60_CPU2PCI1_IO_SIZE 0x0098
148 #define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
149 #define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
150 #define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0
151 #define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8
152 #define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0
153 #define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8
154 #define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0
155 #define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8
157 #define MV64360_CPU2SRAM_BASE 0x0268
159 #define MV64x60_CPU2PCI1_IO_REMAP 0x0108
160 #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
161 #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
162 #define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118
163 #define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348
164 #define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310
165 #define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350
166 #define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318
167 #define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358
169 /* CPU Control Registers */
170 #define MV64x60_CPU_CONFIG 0x0000
171 #define MV64x60_CPU_MODE 0x0120
172 #define MV64x60_CPU_MASTER_CNTL 0x0160
173 #define MV64x60_CPU_XBAR_CNTL_LO 0x0150
174 #define MV64x60_CPU_XBAR_CNTL_HI 0x0158
175 #define MV64x60_CPU_XBAR_TO 0x0168
177 #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170
178 #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178
180 #define MV64360_CPU_PADS_CALIBRATION 0x03b4
181 #define MV64360_CPU_RESET_SAMPLE_LO 0x03c4
182 #define MV64360_CPU_RESET_SAMPLE_HI 0x03d4
184 /* SMP Register Map */
185 #define MV64360_WHO_AM_I 0x0200
186 #define MV64360_CPU0_DOORBELL 0x0214
187 #define MV64360_CPU0_DOORBELL_CLR 0x021c
188 #define MV64360_CPU0_DOORBELL_MASK 0x0234
189 #define MV64360_CPU1_DOORBELL 0x0224
190 #define MV64360_CPU1_DOORBELL_CLR 0x022c
191 #define MV64360_CPU1_DOORBELL_MASK 0x023c
192 #define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10))
193 #define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10))
194 #define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08))
195 #define MV64360_SEMAPHORE_0 0x0244
196 #define MV64360_SEMAPHORE_1 0x024c
197 #define MV64360_SEMAPHORE_2 0x0254
198 #define MV64360_SEMAPHORE_3 0x025c
199 #define MV64360_SEMAPHORE_4 0x0264
200 #define MV64360_SEMAPHORE_5 0x026c
201 #define MV64360_SEMAPHORE_6 0x0274
202 #define MV64360_SEMAPHORE_7 0x027c
204 /* CPU Sync Barrier Registers */
205 #define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0
206 #define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8
208 #define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0
209 #define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8
210 #define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0
211 #define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8
213 /* CPU Deadlock and Ordering registers (Rev B part only) */
214 #define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
215 #define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
216 #define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
218 /* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
219 #define MV64x260_CPU_PROT_WINDOWS 4
221 #define GT64260_CPU_PROT_ACCPROTECT (1<<16)
222 #define GT64260_CPU_PROT_WRPROTECT (1<<17)
223 #define GT64260_CPU_PROT_CACHEPROTECT (1<<18)
225 #define MV64360_CPU_PROT_ACCPROTECT (1<<20)
226 #define MV64360_CPU_PROT_WRPROTECT (1<<21)
227 #define MV64360_CPU_PROT_CACHEPROTECT (1<<22)
228 #define MV64360_CPU_PROT_WIN_ENABLE (1<<31)
230 #define MV64x60_CPU_PROT_BASE_0 0x0180
231 #define MV64x60_CPU_PROT_SIZE_0 0x0188
232 #define MV64x60_CPU_PROT_BASE_1 0x0190
233 #define MV64x60_CPU_PROT_SIZE_1 0x0198
234 #define MV64x60_CPU_PROT_BASE_2 0x01a0
235 #define MV64x60_CPU_PROT_SIZE_2 0x01a8
236 #define MV64x60_CPU_PROT_BASE_3 0x01b0
237 #define MV64x60_CPU_PROT_SIZE_3 0x01b8
239 #define GT64260_CPU_PROT_BASE_4 0x01c0
240 #define GT64260_CPU_PROT_SIZE_4 0x01c8
241 #define GT64260_CPU_PROT_BASE_5 0x01d0
242 #define GT64260_CPU_PROT_SIZE_5 0x01d8
243 #define GT64260_CPU_PROT_BASE_6 0x01e0
244 #define GT64260_CPU_PROT_SIZE_6 0x01e8
245 #define GT64260_CPU_PROT_BASE_7 0x01f0
246 #define GT64260_CPU_PROT_SIZE_7 0x01f8
248 /* CPU Snoop Control Registers (64260 only) */
249 #define GT64260_CPU_SNOOP_WINDOWS 4
251 #define GT64260_CPU_SNOOP_NONE 0x00000000
252 #define GT64260_CPU_SNOOP_WT 0x00010000
253 #define GT64260_CPU_SNOOP_WB 0x00020000
254 #define GT64260_CPU_SNOOP_MASK 0x00030000
255 #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK
257 #define GT64260_CPU_SNOOP_BASE_0 0x0380
258 #define GT64260_CPU_SNOOP_SIZE_0 0x0388
259 #define GT64260_CPU_SNOOP_BASE_1 0x0390
260 #define GT64260_CPU_SNOOP_SIZE_1 0x0398
261 #define GT64260_CPU_SNOOP_BASE_2 0x03a0
262 #define GT64260_CPU_SNOOP_SIZE_2 0x03a8
263 #define GT64260_CPU_SNOOP_BASE_3 0x03b0
264 #define GT64260_CPU_SNOOP_SIZE_3 0x03b8
266 /* CPU Error Report Registers */
267 #define MV64x60_CPU_ERR_ADDR_LO 0x0070
268 #define MV64x60_CPU_ERR_ADDR_HI 0x0078
269 #define MV64x60_CPU_ERR_DATA_LO 0x0128
270 #define MV64x60_CPU_ERR_DATA_HI 0x0130
271 #define MV64x60_CPU_ERR_PARITY 0x0138
272 #define MV64x60_CPU_ERR_CAUSE 0x0140
273 #define MV64x60_CPU_ERR_MASK 0x0148
276 *****************************************************************************
278 * SRAM Cotnroller Registers
280 *****************************************************************************
283 #define MV64360_SRAM_CONFIG 0x0380
284 #define MV64360_SRAM_TEST_MODE 0x03f4
285 #define MV64360_SRAM_ERR_CAUSE 0x0388
286 #define MV64360_SRAM_ERR_ADDR_LO 0x0390
287 #define MV64360_SRAM_ERR_ADDR_HI 0x03f8
288 #define MV64360_SRAM_ERR_DATA_LO 0x0398
289 #define MV64360_SRAM_ERR_DATA_HI 0x03a0
290 #define MV64360_SRAM_ERR_PARITY 0x03a8
294 *****************************************************************************
296 * SDRAM Cotnroller Registers
298 *****************************************************************************
301 /* SDRAM Config Registers (64260) */
302 #define GT64260_SDRAM_CONFIG 0x0448
304 /* SDRAM Error Report Registers (64260) */
305 #define GT64260_SDRAM_ERR_DATA_LO 0x0484
306 #define GT64260_SDRAM_ERR_DATA_HI 0x0480
307 #define GT64260_SDRAM_ERR_ADDR 0x0490
308 #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488
309 #define GT64260_SDRAM_ERR_ECC_CALC 0x048c
310 #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494
311 #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498
313 /* SDRAM Config Registers (64360) */
314 #define MV64360_SDRAM_CONFIG 0x1400
316 /* SDRAM Error Report Registers (64360) */
317 #define MV64360_SDRAM_ERR_DATA_LO 0x1444
318 #define MV64360_SDRAM_ERR_DATA_HI 0x1440
319 #define MV64360_SDRAM_ERR_ADDR 0x1450
320 #define MV64360_SDRAM_ERR_ECC_RCVD 0x1448
321 #define MV64360_SDRAM_ERR_ECC_CALC 0x144c
322 #define MV64360_SDRAM_ERR_ECC_CNTL 0x1454
323 #define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458
327 *****************************************************************************
329 * Device/BOOT Cotnroller Registers
331 *****************************************************************************
334 /* Device Control Registers */
335 #define MV64x60_DEV_BANK_PARAMS_0 0x045c
336 #define MV64x60_DEV_BANK_PARAMS_1 0x0460
337 #define MV64x60_DEV_BANK_PARAMS_2 0x0464
338 #define MV64x60_DEV_BANK_PARAMS_3 0x0468
339 #define MV64x60_DEV_BOOT_PARAMS 0x046c
340 #define MV64x60_DEV_IF_CNTL 0x04c0
341 #define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8
342 #define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc
343 #define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4
345 /* Device Interrupt Registers */
346 #define MV64x60_DEV_INTR_CAUSE 0x04d0
347 #define MV64x60_DEV_INTR_MASK 0x04d4
348 #define MV64x60_DEV_INTR_ERR_ADDR 0x04d8
350 #define MV64360_DEV_INTR_ERR_DATA 0x04dc
351 #define MV64360_DEV_INTR_ERR_PAR 0x04e0
355 *****************************************************************************
357 * PCI Bridge Interface Registers
359 *****************************************************************************
362 /* PCI Configuration Access Registers */
363 #define MV64x60_PCI0_CONFIG_ADDR 0x0cf8
364 #define MV64x60_PCI0_CONFIG_DATA 0x0cfc
365 #define MV64x60_PCI0_IACK 0x0c34
367 #define MV64x60_PCI1_CONFIG_ADDR 0x0c78
368 #define MV64x60_PCI1_CONFIG_DATA 0x0c7c
369 #define MV64x60_PCI1_IACK 0x0cb4
371 /* PCI Control Registers */
372 #define MV64x60_PCI0_CMD 0x0c00
373 #define MV64x60_PCI0_MODE 0x0d00
374 #define MV64x60_PCI0_TO_RETRY 0x0c04
375 #define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04
376 #define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38
377 #define MV64x60_PCI0_ARBITER_CNTL 0x1d00
378 #define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08
379 #define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c
380 #define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04
381 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18
382 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c
383 #define MV64x60_PCI0_SYNC_BARRIER 0x1d10
384 #define MV64x60_PCI0_P2P_CONFIG 0x1d14
385 #define MV64x60_PCI0_INTR_MASK
387 #define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54
389 #define MV64x60_PCI1_CMD 0x0c80
390 #define MV64x60_PCI1_MODE 0x0d80
391 #define MV64x60_PCI1_TO_RETRY 0x0c84
392 #define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84
393 #define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8
394 #define MV64x60_PCI1_ARBITER_CNTL 0x1d80
395 #define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88
396 #define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c
397 #define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84
398 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98
399 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c
400 #define MV64x60_PCI1_SYNC_BARRIER 0x1d90
401 #define MV64x60_PCI1_P2P_CONFIG 0x1d94
403 #define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4
405 /* PCI Access Control Regions Registers */
406 #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12)
407 #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13)
408 #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16)
409 #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17)
410 #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18)
411 #define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000
412 #define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000
413 #define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000
414 #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000
415 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
416 #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000
417 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000
418 #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000
419 #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000
420 #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28)
421 #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29)
423 #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \
424 GT64260_PCI_ACC_CNTL_DREADEN | \
425 GT64260_PCI_ACC_CNTL_RDPREFETCH | \
426 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
427 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
428 GT64260_PCI_ACC_CNTL_MBURST_MASK | \
429 GT64260_PCI_ACC_CNTL_SWAP_MASK | \
430 GT64260_PCI_ACC_CNTL_ACCPROT| \
431 GT64260_PCI_ACC_CNTL_WRPROT)
433 #define MV64360_PCI_ACC_CNTL_ENABLE (1<<0)
434 #define MV64360_PCI_ACC_CNTL_REQ64 (1<<1)
435 #define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
436 #define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004
437 #define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008
438 #define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
439 #define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4)
440 #define MV64360_PCI_ACC_CNTL_WRPROT (1<<5)
441 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
442 #define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040
443 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
444 #define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
445 #define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
446 #define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
447 #define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
448 #define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
449 #define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300
450 #define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
451 #define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
452 #define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
453 #define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
454 #define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
456 #define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \
457 MV64360_PCI_ACC_CNTL_REQ64 | \
458 MV64360_PCI_ACC_CNTL_SNOOP_MASK | \
459 MV64360_PCI_ACC_CNTL_ACCPROT | \
460 MV64360_PCI_ACC_CNTL_WRPROT | \
461 MV64360_PCI_ACC_CNTL_SWAP_MASK | \
462 MV64360_PCI_ACC_CNTL_MBURST_MASK | \
463 MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
465 #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
466 #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
467 #define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
468 #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
469 #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
470 #define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
471 #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
472 #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
473 #define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
474 #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
475 #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
476 #define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
477 #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
478 #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
479 #define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
480 #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
481 #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
482 #define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
484 #define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60
485 #define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64
486 #define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68
487 #define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70
488 #define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74
489 #define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78
491 #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
492 #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
493 #define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
494 #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
495 #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
496 #define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
497 #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
498 #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
499 #define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
500 #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
501 #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
502 #define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
503 #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
504 #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
505 #define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
506 #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
507 #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
508 #define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
510 #define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0
511 #define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4
512 #define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8
513 #define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0
514 #define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4
515 #define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8
517 /* PCI Snoop Control Registers (64260 only) */
518 #define GT64260_PCI_SNOOP_NONE 0x00000000
519 #define GT64260_PCI_SNOOP_WT 0x00001000
520 #define GT64260_PCI_SNOOP_WB 0x00002000
522 #define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00
523 #define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04
524 #define GT64260_PCI0_SNOOP_0_SIZE 0x1f08
525 #define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10
526 #define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14
527 #define GT64260_PCI0_SNOOP_1_SIZE 0x1f18
528 #define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20
529 #define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24
530 #define GT64260_PCI0_SNOOP_2_SIZE 0x1f28
531 #define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30
532 #define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34
533 #define GT64260_PCI0_SNOOP_3_SIZE 0x1f38
535 #define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80
536 #define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84
537 #define GT64260_PCI1_SNOOP_0_SIZE 0x1f88
538 #define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90
539 #define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94
540 #define GT64260_PCI1_SNOOP_1_SIZE 0x1f98
541 #define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0
542 #define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4
543 #define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8
544 #define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0
545 #define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4
546 #define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8
548 /* PCI Error Report Registers */
549 #define MV64x60_PCI0_ERR_SERR_MASK 0x0c28
550 #define MV64x60_PCI0_ERR_ADDR_LO 0x1d40
551 #define MV64x60_PCI0_ERR_ADDR_HI 0x1d44
552 #define MV64x60_PCI0_ERR_DATA_LO 0x1d48
553 #define MV64x60_PCI0_ERR_DATA_HI 0x1d4c
554 #define MV64x60_PCI0_ERR_CMD 0x1d50
555 #define MV64x60_PCI0_ERR_CAUSE 0x1d58
556 #define MV64x60_PCI0_ERR_MASK 0x1d5c
558 #define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8
559 #define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0
560 #define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4
561 #define MV64x60_PCI1_ERR_DATA_LO 0x1dc8
562 #define MV64x60_PCI1_ERR_DATA_HI 0x1dcc
563 #define MV64x60_PCI1_ERR_CMD 0x1dd0
564 #define MV64x60_PCI1_ERR_CAUSE 0x1dd8
565 #define MV64x60_PCI1_ERR_MASK 0x1ddc
567 /* PCI Slave Address Decoding Registers */
568 #define MV64x60_PCI0_MEM_0_SIZE 0x0c08
569 #define MV64x60_PCI0_MEM_1_SIZE 0x0d08
570 #define MV64x60_PCI0_MEM_2_SIZE 0x0c0c
571 #define MV64x60_PCI0_MEM_3_SIZE 0x0d0c
572 #define MV64x60_PCI1_MEM_0_SIZE 0x0c88
573 #define MV64x60_PCI1_MEM_1_SIZE 0x0d88
574 #define MV64x60_PCI1_MEM_2_SIZE 0x0c8c
575 #define MV64x60_PCI1_MEM_3_SIZE 0x0d8c
577 #define MV64x60_PCI0_BAR_ENABLE 0x0c3c
578 #define MV64x60_PCI1_BAR_ENABLE 0x0cbc
580 #define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
586 #define MV64x60_PCI0_SLAVE_BAR_REG_ENABLES 0x0c3c
587 #define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48
588 #define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48
589 #define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c
590 #define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c
591 #define MV64x60_PCI0_SLAVE_CS_0_REMAP 0x0c50
592 #define MV64x60_PCI0_SLAVE_CS_1_REMAP 0x0d50
593 #define MV64x60_PCI0_SLAVE_CS_2_REMAP 0x0d58
594 #define MV64x60_PCI0_SLAVE_CS_3_REMAP 0x0c54
595 #define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54
596 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c
597 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60
598 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64
599 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68
600 #define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c
601 #define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70
603 #define GT64260_PCI0_SLAVE_DAC_SCS_0_REMAP 0x0f00
604 #define GT64260_PCI0_SLAVE_DAC_SCS_1_REMAP 0x0f04
605 #define GT64260_PCI0_SLAVE_DAC_SCS_2_REMAP 0x0f08
606 #define GT64260_PCI0_SLAVE_DAC_SCS_3_REMAP 0x0f0c
607 #define GT64260_PCI0_SLAVE_DAC_CS_0_REMAP 0x0f10
608 #define GT64260_PCI0_SLAVE_DAC_CS_1_REMAP 0x0f14
609 #define GT64260_PCI0_SLAVE_DAC_CS_2_REMAP 0x0f18
610 #define GT64260_PCI0_SLAVE_DAC_CS_3_REMAP 0x0f1c
611 #define GT64260_PCI0_SLAVE_DAC_BOOT_REMAP 0x0f20
612 #define GT64260_PCI0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24
613 #define GT64260_PCI0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28
614 #define GT64260_PCI0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c
615 #define GT64260_PCI0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30
616 #define GT64260_PCI0_SLAVE_DAC_CPU_REMAP 0x0f34
618 #define GT64260_PCI0_SLAVE_EXP_ROM_REMAP 0x0f38
619 #define GT64260_PCI0_SLAVE_PCI_DECODE_CNTL 0x0d3c
626 #define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
628 #define MV64x60_PCI1_SLAVE_MEM_0_SIZE 0x0c88
629 #define MV64x60_PCI1_SLAVE_MEM_1_SIZE 0x0d88
630 #define MV64x60_PCI1_SLAVE_MEM_2_SIZE 0x0c8c
631 #define MV64x60_PCI1_SLAVE_MEM_3_SIZE 0x0d8c
632 #define MV64x60_PCI1_SLAVE_CS_0_SIZE 0x0c90
633 #define MV64x60_PCI1_SLAVE_CS_1_SIZE 0x0d90
634 #define MV64x60_PCI1_SLAVE_CS_2_SIZE 0x0d98
635 #define MV64x60_PCI1_SLAVE_CS_3_SIZE 0x0c94
636 #define MV64x60_PCI1_SLAVE_BOOT_SIZE 0x0d94
637 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_SIZE 0x0d9c
638 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_SIZE 0x0da0
639 #define MV64x60_PCI1_SLAVE_P2P_IO_SIZE 0x0da4
640 #define MV64x60_PCI1_SLAVE_CPU_SIZE 0x0da8
646 #define GT64260_PCI1_SLAVE_DAC_SCS_0_SIZE 0x0e80
647 #define GT64260_PCI1_SLAVE_DAC_SCS_1_SIZE 0x0e84
648 #define GT64260_PCI1_SLAVE_DAC_SCS_2_SIZE 0x0e88
649 #define GT64260_PCI1_SLAVE_DAC_SCS_3_SIZE 0x0e8c
650 #define GT64260_PCI1_SLAVE_DAC_CS_0_SIZE 0x0e90
651 #define GT64260_PCI1_SLAVE_DAC_CS_1_SIZE 0x0e94
652 #define GT64260_PCI1_SLAVE_DAC_CS_2_SIZE 0x0e98
653 #define GT64260_PCI1_SLAVE_DAC_CS_3_SIZE 0x0e9c
654 #define GT64260_PCI1_SLAVE_DAC_BOOT_SIZE 0x0ea0
655 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4
656 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8
657 #define GT64260_PCI1_SLAVE_DAC_CPU_SIZE 0x0eac
659 #define GT64260_PCI1_SLAVE_EXP_ROM_SIZE 0x0dac
666 #define MV64x60_PCI1_SLAVE_BAR_REG_ENABLES 0x0cbc
667 #define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8
668 #define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8
669 #define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc
670 #define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc
671 #define MV64x60_PCI1_SLAVE_CS_0_REMAP 0x0cd0
672 #define MV64x60_PCI1_SLAVE_CS_1_REMAP 0x0dd0
673 #define MV64x60_PCI1_SLAVE_CS_2_REMAP 0x0dd8
674 #define MV64x60_PCI1_SLAVE_CS_3_REMAP 0x0cd4
675 #define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4
676 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc
677 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0
678 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4
679 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8
680 #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec
681 #define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0
687 #define GT64260_PCI1_SLAVE_DAC_SCS_0_REMAP 0x0f80
688 #define GT64260_PCI1_SLAVE_DAC_SCS_1_REMAP 0x0f84
689 #define GT64260_PCI1_SLAVE_DAC_SCS_2_REMAP 0x0f88
690 #define GT64260_PCI1_SLAVE_DAC_SCS_3_REMAP 0x0f8c
691 #define GT64260_PCI1_SLAVE_DAC_CS_0_REMAP 0x0f90
692 #define GT64260_PCI1_SLAVE_DAC_CS_1_REMAP 0x0f94
693 #define GT64260_PCI1_SLAVE_DAC_CS_2_REMAP 0x0f98
694 #define GT64260_PCI1_SLAVE_DAC_CS_3_REMAP 0x0f9c
695 #define GT64260_PCI1_SLAVE_DAC_BOOT_REMAP 0x0fa0
696 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4
697 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8
698 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac
699 #define GT64260_PCI1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0
700 #define GT64260_PCI1_SLAVE_DAC_CPU_REMAP 0x0fb4
702 #define GT64260_PCI1_SLAVE_EXP_ROM_REMAP 0x0fb8
703 #define GT64260_PCI1_SLAVE_PCI_DECODE_CNTL 0x0dbc
707 *****************************************************************************
709 * Timer/Counter Interface Registers
711 *****************************************************************************
714 #define MV64x60_TIMR_CNTR_0 0x0850
715 #define MV64x60_TIMR_CNTR_1 0x0854
716 #define MV64x60_TIMR_CNTR_2 0x0858
717 #define MV64x60_TIMR_CNTR_3 0x085c
718 #define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864
719 #define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868
720 #define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c
722 #define GT64260_TIMR_CNTR_4 0x0950
723 #define GT64260_TIMR_CNTR_5 0x0954
724 #define GT64260_TIMR_CNTR_6 0x0958
725 #define GT64260_TIMR_CNTR_7 0x095c
726 #define GT64260_TIMR_CNTR_4_7_CNTL 0x0964
727 #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968
728 #define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c
732 *****************************************************************************
734 * Communications Controller (Enet, Serial, etc.) Interface Registers
736 *****************************************************************************
739 #define GT64260_COMM_ENET_0_OFFSET 0xf200
740 #define GT64260_COMM_ENET_1_OFFSET 0xf220
741 #define GT64260_COMM_ENET_2_OFFSET 0xf240
743 #define GT64260_ENET_CNTL_LO \
744 (0xf200 - GT64260_COMM_ENET_0_BASE)
745 #define GT64260_ENET_CNTL_HI \
746 (0xf204 - GT64260_COMM_ENET_0_BASE)
747 #define GT64260_ENET_RX_BUF_PCI_ADDR_HI \
748 (0xf208 - GT64260_COMM_ENET_0_BASE)
749 #define GT64260_ENET_TX_BUF_PCI_ADDR_HI \
750 (0xf20c - GT64260_COMM_ENET_0_BASE)
751 #define GT64260_ENET_RX_DESC_ADDR_HI \
752 (0xf210 - GT64260_COMM_ENET_0_BASE)
753 #define GT64260_ENET_TX_DESC_ADDR_HI \
754 (0xf214 - GT64260_COMM_ENET_0_BASE)
755 #define GT64260_ENET_HASH_TAB_PCI_ADDR_HI \
756 (0xf218 - GT64260_COMM_ENET_0_BASE)
758 #define GT64260_COMM_MPSC_0_OFFSET 0xf280
759 #define GT64260_COMM_MPSC_1_OFFSET 0xf2c0
761 #define GT64260_MPSC_CNTL_LO \
762 (0xf280 - GT64260_COMM_MPSC_0_BASE)
763 #define GT64260_MPSC_CNTL_HI \
764 (0xf284 - GT64260_COMM_MPSC_0_BASE)
765 #define GT64260_MPSC_RX_BUF_PCI_ADDR_HI \
766 (0xf288 - GT64260_COMM_MPSC_0_BASE)
767 #define GT64260_MPSC_TX_BUF_PCI_ADDR_HI \
768 (0xf28c - GT64260_COMM_MPSC_0_BASE)
769 #define GT64260_MPSC_RX_DESC_ADDR_HI \
770 (0xf290 - GT64260_COMM_MPSC_0_BASE)
771 #define GT64260_MPSC_TX_DESC_ADDR_HI \
772 (0xf294 - GT64260_COMM_MPSC_0_BASE)
774 #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320
775 #define GT64260_SER_INIT_LAST_DATA 0xf324
776 #define GT64260_SER_INIT_CONTROL 0xf328
777 #define GT64260_SER_INIT_STATUS 0xf32c
779 #define GT64260_COMM_ARBITER_CNTL 0xf300
780 #define GT64260_COMM_CONFIG 0xb40c
781 #define GT64260_COMM_XBAR_TO 0xf304
782 #define GT64260_COMM_INTR_CAUSE 0xf310
783 #define GT64260_COMM_INTR_MASK 0xf314
784 #define GT64260_COMM_ERR_ADDR 0xf318
788 *****************************************************************************
790 * Fast Ethernet Controller Interface Registers
792 *****************************************************************************
795 #define GT64260_ENET_PHY_ADDR 0x2000
796 #define GT64260_ENET_ESMIR 0x2010
798 #define GT64260_ENET_0_OFFSET 0x2400
799 #define GT64260_ENET_1_OFFSET 0x2800
800 #define GT64260_ENET_2_OFFSET 0x2c00
802 #define GT64260_ENET_EPCR (0x2400 - GT64260_ENET_0_OFFSET)
803 #define GT64260_ENET_EPCXR (0x2408 - GT64260_ENET_0_OFFSET)
804 #define GT64260_ENET_EPCMR (0x2410 - GT64260_ENET_0_OFFSET)
805 #define GT64260_ENET_EPSR (0x2418 - GT64260_ENET_0_OFFSET)
806 #define GT64260_ENET_ESPR (0x2420 - GT64260_ENET_0_OFFSET)
807 #define GT64260_ENET_EHTPR (0x2428 - GT64260_ENET_0_OFFSET)
808 #define GT64260_ENET_EFCSAL (0x2430 - GT64260_ENET_0_OFFSET)
809 #define GT64260_ENET_EFCSAH (0x2438 - GT64260_ENET_0_OFFSET)
810 #define GT64260_ENET_ESDCR (0x2440 - GT64260_ENET_0_OFFSET)
811 #define GT64260_ENET_ESDCMR (0x2448 - GT64260_ENET_0_OFFSET)
812 #define GT64260_ENET_EICR (0x2450 - GT64260_ENET_0_OFFSET)
813 #define GT64260_ENET_EIMR (0x2458 - GT64260_ENET_0_OFFSET)
814 #define GT64260_ENET_EFRDP0 (0x2480 - GT64260_ENET_0_OFFSET)
815 #define GT64260_ENET_EFRDP1 (0x2484 - GT64260_ENET_0_OFFSET)
816 #define GT64260_ENET_EFRDP2 (0x2488 - GT64260_ENET_0_OFFSET)
817 #define GT64260_ENET_EFRDP3 (0x248c - GT64260_ENET_0_OFFSET)
818 #define GT64260_ENET_ECRDP0 (0x24a0 - GT64260_ENET_0_OFFSET)
819 #define GT64260_ENET_ECRDP1 (0x24a4 - GT64260_ENET_0_OFFSET)
820 #define GT64260_ENET_ECRDP2 (0x24a8 - GT64260_ENET_0_OFFSET)
821 #define GT64260_ENET_ECRDP3 (0x24ac - GT64260_ENET_0_OFFSET)
822 #define GT64260_ENET_ECTDP0 (0x24e0 - GT64260_ENET_0_OFFSET)
823 #define GT64260_ENET_ECTDP1 (0x24e4 - GT64260_ENET_0_OFFSET)
824 #define GT64260_ENET_DSCP2P0L (0x2460 - GT64260_ENET_0_OFFSET)
825 #define GT64260_ENET_DSCP2P0H (0x2464 - GT64260_ENET_0_OFFSET)
826 #define GT64260_ENET_DSCP2P1L (0x2468 - GT64260_ENET_0_OFFSET)
827 #define GT64260_ENET_DSCP2P1H (0x246c - GT64260_ENET_0_OFFSET)
828 #define GT64260_ENET_VPT2P (0x2470 - GT64260_ENET_0_OFFSET)
829 #define GT64260_ENET_MIB_CTRS (0x2500 - GT64260_ENET_0_OFFSET)
832 *****************************************************************************
834 * IDMA Controller Interface Registers
836 *****************************************************************************
839 #define GT64260_IDMA_0_OFFSET 0x0800
840 #define GT64260_IDMA_1_OFFSET 0x0804
841 #define GT64260_IDMA_2_OFFSET 0x0808
842 #define GT64260_IDMA_3_OFFSET 0x080c
843 #define GT64260_IDMA_4_OFFSET 0x0900
844 #define GT64260_IDMA_5_OFFSET 0x0904
845 #define GT64260_IDMA_6_OFFSET 0x0908
846 #define GT64260_IDMA_7_OFFSET 0x090c
848 #define GT64260_IDMA_BYTE_COUNT (0x0800 - GT64260_IDMA_0_OFFSET)
849 #define GT64260_IDMA_SRC_ADDR (0x0810 - GT64260_IDMA_0_OFFSET)
850 #define GT64260_IDMA_DST_ADDR (0x0820 - GT64260_IDMA_0_OFFSET)
851 #define GT64260_IDMA_NEXT_DESC (0x0830 - GT64260_IDMA_0_OFFSET)
852 #define GT64260_IDMA_CUR_DESC (0x0870 - GT64260_IDMA_0_OFFSET)
853 #define GT64260_IDMA_SRC_PCI_ADDR_HI (0x0890 - GT64260_IDMA_0_OFFSET)
854 #define GT64260_IDMA_DST_PCI_ADDR_HI (0x08a0 - GT64260_IDMA_0_OFFSET)
855 #define GT64260_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - GT64260_IDMA_0_OFFSET)
856 #define GT64260_IDMA_CONTROL_LO (0x0840 - GT64260_IDMA_0_OFFSET)
857 #define GT64260_IDMA_CONTROL_HI (0x0880 - GT64260_IDMA_0_OFFSET)
859 #define GT64260_IDMA_0_3_ARBITER_CNTL 0x0860
860 #define GT64260_IDMA_4_7_ARBITER_CNTL 0x0960
862 #define GT64260_IDMA_0_3_XBAR_TO 0x08d0
863 #define GT64260_IDMA_4_7_XBAR_TO 0x09d0
865 #define GT64260_IDMA_0_3_INTR_CAUSE 0x08c0
866 #define GT64260_IDMA_0_3_INTR_MASK 0x08c4
867 #define GT64260_IDMA_0_3_ERROR_ADDR 0x08c8
868 #define GT64260_IDMA_0_3_ERROR_SELECT 0x08cc
869 #define GT64260_IDMA_4_7_INTR_CAUSE 0x09c0
870 #define GT64260_IDMA_4_7_INTR_MASK 0x09c4
871 #define GT64260_IDMA_4_7_ERROR_ADDR 0x09c8
872 #define GT64260_IDMA_4_7_ERROR_SELECT 0x09cc
875 *****************************************************************************
877 * Watchdog Timer Interface Registers
879 *****************************************************************************
882 #define GT64260_WDT_WDC 0xb410
883 #define GT64260_WDT_WDV 0xb414
887 *****************************************************************************
889 * General Purpose Pins Controller Interface Registers
891 *****************************************************************************
894 #define MV64x60_GPP_IO_CNTL 0xf100
895 #define MV64x60_GPP_LEVEL_CNTL 0xf110
896 #define MV64x60_GPP_VALUE 0xf104
897 #define MV64x60_GPP_INTR_CAUSE 0xf108
898 #define MV64x60_GPP_INTR_MASK 0xf10c
902 *****************************************************************************
904 * Multi-Purpose Pins Controller Interface Registers
906 *****************************************************************************
909 #define MV64x60_MPP_CNTL_0 0xf000
910 #define MV64x60_MPP_CNTL_1 0xf004
911 #define MV64x60_MPP_CNTL_2 0xf008
912 #define MV64x60_MPP_CNTL_3 0xf00c
913 #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010
917 *****************************************************************************
919 * I2C Controller Interface Registers
921 *****************************************************************************
924 #define GT64260_I2C_OFFSET 0xc000
926 #define GT64260_I2C_ADDR (0xc000 - GT64260_I2C_OFFSET)
927 #define GT64260_I2C_EX_ADDR (0xc010 - GT64260_I2C_OFFSET)
928 #define GT64260_I2C_DATA (0xc004 - GT64260_I2C_OFFSET)
929 #define GT64260_I2C_CONTROL (0xc008 - GT64260_I2C_OFFSET)
930 #define GT64260_I2C_STATUS (0xc00c - GT64260_I2C_OFFSET)
931 #define GT64260_I2C_BAUD_RATE (0xc00c - GT64260_I2C_OFFSET)
932 #define GT64260_I2C_RESET (0xc01c - GT64260_I2C_OFFSET)
934 #define GT64260_I2C_ACK_BIT (1<<2)
935 #define GT64260_I2C_IFLG_BIT (1<<3)
936 #define GT64260_I2C_STOP_BIT (1<<4)
937 #define GT64260_I2C_START_BIT (1<<5)
938 #define GT64260_I2C_ENABLE_BIT (1<<6)
939 #define GT64260_I2C_INT_ENABLE_BIT (1<<7)
941 #define GT64260_I2C_DATA_READ_BIT 0x01
943 #define GT64260_I2C_STATUS_SENT_START 0x08
944 #define GT64260_I2C_STATUS_RESENT_START 0x10
945 #define GT64260_I2C_STATUS_WRITE_ADDR_ACK 0x18
946 #define GT64260_I2C_STATUS_WRITE_ACK 0x28
947 #define GT64260_I2C_STATUS_READ_ADDR_ACK 0x40
948 #define GT64260_I2C_STATUS_READ_ACK 0x50
949 #define GT64260_I2C_STATUS_READ_NO_ACK 0x58
950 #define GT64260_I2C_STATUS_IDLE 0xf8
954 *****************************************************************************
956 * Interrupt Controller Interface Registers
958 *****************************************************************************
961 #define GT64260_IC_OFFSET 0x0c18
963 #define GT64260_IC_MAIN_CAUSE_LO (0x0c18 - GT64260_IC_OFFSET)
964 #define GT64260_IC_MAIN_CAUSE_HI (0x0c68 - GT64260_IC_OFFSET)
965 #define GT64260_IC_CPU_INTR_MASK_LO (0x0c1c - GT64260_IC_OFFSET)
966 #define GT64260_IC_CPU_INTR_MASK_HI (0x0c6c - GT64260_IC_OFFSET)
967 #define GT64260_IC_CPU_SELECT_CAUSE (0x0c70 - GT64260_IC_OFFSET)
968 #define GT64260_IC_PCI0_INTR_MASK_LO (0x0c24 - GT64260_IC_OFFSET)
969 #define GT64260_IC_PCI0_INTR_MASK_HI (0x0c64 - GT64260_IC_OFFSET)
970 #define GT64260_IC_PCI0_SELECT_CAUSE (0x0c74 - GT64260_IC_OFFSET)
971 #define GT64260_IC_PCI1_INTR_MASK_LO (0x0ca4 - GT64260_IC_OFFSET)
972 #define GT64260_IC_PCI1_INTR_MASK_HI (0x0ce4 - GT64260_IC_OFFSET)
973 #define GT64260_IC_PCI1_SELECT_CAUSE (0x0cf4 - GT64260_IC_OFFSET)
974 #define GT64260_IC_CPU_INT_0_MASK (0x0e60 - GT64260_IC_OFFSET)
975 #define GT64260_IC_CPU_INT_1_MASK (0x0e64 - GT64260_IC_OFFSET)
976 #define GT64260_IC_CPU_INT_2_MASK (0x0e68 - GT64260_IC_OFFSET)
977 #define GT64260_IC_CPU_INT_3_MASK (0x0e6c - GT64260_IC_OFFSET)
979 #define MV64360_IC_OFFSET 0x0000
981 #define MV64360_IC_MAIN_CAUSE_LO (0x0004 - MV64360_IC_OFFSET)
982 #define MV64360_IC_MAIN_CAUSE_HI (0x000c - MV64360_IC_OFFSET)
983 #define MV64360_IC_CPU0_INTR_MASK_LO (0x0014 - MV64360_IC_OFFSET)
984 #define MV64360_IC_CPU0_INTR_MASK_HI (0x001c - MV64360_IC_OFFSET)
985 #define MV64360_IC_CPU0_SELECT_CAUSE (0x0024 - MV64360_IC_OFFSET)
986 #define MV64360_IC_CPU1_INTR_MASK_LO (0x0034 - MV64360_IC_OFFSET)
987 #define MV64360_IC_CPU1_INTR_MASK_HI (0x003c - MV64360_IC_OFFSET)
988 #define MV64360_IC_CPU1_SELECT_CAUSE (0x0044 - MV64360_IC_OFFSET)
989 #define MV64360_IC_INT0_MASK_LO (0x0054 - MV64360_IC_OFFSET)
990 #define MV64360_IC_INT0_MASK_HI (0x005c - MV64360_IC_OFFSET)
991 #define MV64360_IC_INT0_SELECT_CAUSE (0x0064 - MV64360_IC_OFFSET)
992 #define MV64360_IC_INT1_MASK_LO (0x0074 - MV64360_IC_OFFSET)
993 #define MV64360_IC_INT1_MASK_HI (0x007c - MV64360_IC_OFFSET)
994 #define MV64360_IC_INT1_SELECT_CAUSE (0x0084 - MV64360_IC_OFFSET)
996 #endif /* __ASMPPC_MV64x60_DEFS_H */