5 #include <linux/config.h>
8 #include <linux/sched.h>
9 #include <linux/threads.h>
10 #include <asm/processor.h> /* For TASK_SIZE */
14 extern unsigned long va_to_phys(unsigned long address);
15 extern pte_t *va_to_pte(unsigned long address);
16 extern unsigned long ioremap_bot, ioremap_base;
17 #endif /* __ASSEMBLY__ */
20 * The PowerPC MMU uses a hash table containing PTEs, together with
21 * a set of 16 segment registers (on 32-bit implementations), to define
22 * the virtual to physical address mapping.
24 * We use the hash table as an extended TLB, i.e. a cache of currently
25 * active mappings. We maintain a two-level page table tree, much
26 * like that used by the i386, for the sake of the Linux memory
27 * management code. Low-level assembler code in hashtable.S
28 * (procedure hash_page) is responsible for extracting ptes from the
29 * tree and putting them into the hash table when necessary, and
30 * updating the accessed and modified bits in the page table tree.
34 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
35 * We also use the two level tables, but we can put the real bits in them
36 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
37 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
38 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
39 * based upon user/super access. The TLB does not have accessed nor write
40 * protect. We assume that if the TLB get loaded with an entry it is
41 * accessed, and overload the changed bit for write protect. We use
42 * two bits in the software pte that are supposed to be set to zero in
43 * the TLB entry (24 and 25) for these indicators. Although the level 1
44 * descriptor contains the guarded and writethrough/copyback bits, we can
45 * set these at the page level since they get copied from the Mx_TWC
46 * register when the TLB entry is loaded. We will use bit 27 for guard, since
47 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
48 * These will get masked from the level 2 descriptor at TLB load time, and
49 * copied to the MD_TWC before it gets loaded.
50 * Large page sizes added. We currently support two sizes, 4K and 8M.
51 * This also allows a TLB hander optimization because we can directly
52 * load the PMD into MD_TWC. The 8M pages are only used for kernel
53 * mapping of well known areas. The PMD (PGD) entries contain control
54 * flags in addition to the address, so care must be taken that the
55 * software no longer assumes these are only pointers.
59 * At present, all PowerPC 400-class processors share a similar TLB
60 * architecture. The instruction and data sides share a unified,
61 * 64-entry, fully-associative TLB which is maintained totally under
62 * software control. In addition, the instruction side has a
63 * hardware-managed, 4-entry, fully-associative TLB which serves as a
64 * first level to the shared TLB. These two TLBs are known as the UTLB
65 * and ITLB, respectively (see "mmu.h" for definitions).
69 * The normal case is that PTEs are 32-bits and we have a 1-page
70 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
72 * For any >32-bit physical address platform, we can use the following
73 * two level page table layout where the pgdir is 8KB and the MS 13 bits
74 * are an index to the second level table. The combined pgdir/pmd first
75 * level has 2048 entries and the second level has 512 64-bit PTE entries.
78 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
79 #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
80 #define PMD_SIZE (1UL << PMD_SHIFT)
81 #define PMD_MASK (~(PMD_SIZE-1))
83 /* PGDIR_SHIFT determines what a top-level page table entry can map */
84 #define PGDIR_SHIFT PMD_SHIFT
85 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
86 #define PGDIR_MASK (~(PGDIR_SIZE-1))
89 * entries per page directory level: our page-table tree is two-level, so
90 * we don't really have any PMD directory.
92 #define PTRS_PER_PTE (1 << PTE_SHIFT)
93 #define PTRS_PER_PMD 1
94 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
96 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
97 #define FIRST_USER_PGD_NR 0
99 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
100 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
102 #define pte_ERROR(e) \
103 printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
104 #define pmd_ERROR(e) \
105 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
106 #define pgd_ERROR(e) \
107 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
110 * Just any arbitrary offset to the start of the vmalloc VM area: the
111 * current 64MB value just means that there will be a 64MB "hole" after the
112 * physical memory until the kernel virtual memory starts. That means that
113 * any out-of-bounds memory accesses will hopefully be caught.
114 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
115 * area for the same reason. ;)
117 * We no longer map larger than phys RAM with the BATs so we don't have
118 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
119 * about clashes between our early calls to ioremap() that start growing down
120 * from ioremap_base being run into the VM area allocations (growing upwards
121 * from VMALLOC_START). For this reason we have ioremap_bot to check when
122 * we actually run into our mappings setup in the early boot with the VM
123 * system. This really does become a problem for machines with good amounts
126 #define VMALLOC_OFFSET (0x1000000) /* 16M */
128 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC44x_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
130 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
132 #define VMALLOC_END ioremap_bot
135 * Bits in a linux-style PTE. These match the bits in the
136 * (hardware-defined) PowerPC PTE as closely as possible.
139 #if defined(CONFIG_40x)
141 /* There are several potential gotchas here. The 40x hardware TLBLO
142 field looks like this:
144 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
145 RPN..................... 0 0 EX WR ZSEL....... W I M G
147 Where possible we make the Linux PTE bits match up with this
149 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
150 support down to 1k pages), this is done in the TLBMiss exception
152 - We use only zones 0 (for kernel pages) and 1 (for user pages)
153 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
154 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
156 - PRESENT *must* be in the bottom two bits because swap cache
157 entries use the top 30 bits. Because 40x doesn't support SMP
158 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
159 is cleared in the TLB miss handler before the TLB entry is loaded.
160 - All other bits of the PTE are loaded into TLBLO without
161 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
162 software PTE bits. We actually use use bits 21, 24, 25, and
163 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
167 /* Definitions for 40x embedded chips. */
168 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
169 #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
170 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
171 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
172 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
173 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
174 #define _PAGE_RW 0x040 /* software: Writes permitted */
175 #define _PAGE_DIRTY 0x080 /* software: dirty page */
176 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
177 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
178 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
180 #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
181 #define _PMD_BAD 0x802
182 #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
183 #define _PMD_SIZE_4M 0x0c0
184 #define _PMD_SIZE_16M 0x0e0
185 #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
187 #elif defined(CONFIG_44x)
189 * Definitions for PPC440
191 * Because of the 3 word TLB entries to support 36-bit addressing,
192 * the attribute are difficult to map in such a fashion that they
193 * are easily loaded during exception processing. I decided to
194 * organize the entry so the ERPN is the only portion in the
195 * upper word of the PTE and the attribute bits below are packed
196 * in as sensibly as they can be in the area below a 4KB page size
197 * oriented RPN. This at least makes it easy to load the RPN and
198 * ERPN fields in the TLB. -Matt
200 * Note that these bits preclude future use of a page size
203 #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
204 #define _PAGE_RW 0x00000002 /* S: Write permission */
205 #define _PAGE_DIRTY 0x00000004 /* S: Page dirty */
206 #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
207 #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
208 #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
209 #define _PAGE_USER 0x00000040 /* S: User page */
210 #define _PAGE_ENDIAN 0x00000080 /* H: E bit */
211 #define _PAGE_GUARDED 0x00000100 /* H: G bit */
212 #define _PAGE_COHERENT 0x00000200 /* H: M bit */
213 #define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */
214 #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
215 #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
217 /* TODO: Add large page lowmem mapping support */
218 #define _PMD_PRESENT 0
219 #define _PMD_PRESENT_MASK (PAGE_MASK)
220 #define _PMD_BAD (~PAGE_MASK)
222 /* ERPN in a PTE never gets cleared, ignore it */
223 #define _PTE_NONE_MASK 0xffffffff00000000ULL
225 #elif defined(CONFIG_E500)
228 MMU Assist Register 3:
230 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
231 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
233 - PRESENT *must* be in the bottom three bits because swap cache
234 entries use the top 29 bits.
236 - FILE *must* be in the bottom three bits because swap cache
237 entries use the top 29 bits.
240 /* Definitions for e500 core */
241 #define _PAGE_PRESENT 0x001 /* S: PTE contains a translation */
242 #define _PAGE_USER 0x002 /* S: User page (maps to UR) */
243 #define _PAGE_FILE 0x002 /* S: when !present: nonlinear file mapping */
244 #define _PAGE_ACCESSED 0x004 /* S: Page referenced */
245 #define _PAGE_HWWRITE 0x008 /* H: Dirty & RW, set in exception */
246 #define _PAGE_RW 0x010 /* S: Write permission */
247 #define _PAGE_HWEXEC 0x020 /* H: UX permission */
249 #define _PAGE_ENDIAN 0x040 /* H: E bit */
250 #define _PAGE_GUARDED 0x080 /* H: G bit */
251 #define _PAGE_COHERENT 0x100 /* H: M bit */
252 #define _PAGE_NO_CACHE 0x200 /* H: I bit */
253 #define _PAGE_WRITETHRU 0x400 /* H: W bit */
254 #define _PAGE_DIRTY 0x800 /* S: Page dirty */
256 #define _PMD_PRESENT 0
257 #define _PMD_PRESENT_MASK (PAGE_MASK)
258 #define _PMD_BAD (~PAGE_MASK)
260 #define NUM_TLBCAMS (16)
262 #elif defined(CONFIG_8xx)
263 /* Definitions for 8xx embedded chips. */
264 #define _PAGE_PRESENT 0x0001 /* Page is valid */
265 #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
266 #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
267 #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
269 /* These five software bits must be masked out when the entry is loaded
272 #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
273 #define _PAGE_GUARDED 0x0010 /* software: guarded access */
274 #define _PAGE_DIRTY 0x0020 /* software: page changed */
275 #define _PAGE_RW 0x0040 /* software: user write access allowed */
276 #define _PAGE_ACCESSED 0x0080 /* software: page referenced */
278 /* Setting any bits in the nibble with the follow two controls will
279 * require a TLB exception handler change. It is assumed unused bits
282 #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
283 #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
285 #define _PMD_PRESENT 0x0001
286 #define _PMD_BAD 0x0ff0
287 #define _PMD_PAGE_MASK 0x000c
288 #define _PMD_PAGE_8M 0x000c
291 * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
292 * for an address even if _PAGE_PRESENT is not set, as a performance
293 * optimization. This is a bug if you ever want to use swap unless
294 * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
295 * definitions for __swp_entry etc. below, which would be gross.
298 #define _PTE_NONE_MASK _PAGE_ACCESSED
300 #else /* CONFIG_6xx */
301 /* Definitions for 60x, 740/750, etc. */
302 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
303 #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
304 #define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
305 #define _PAGE_USER 0x004 /* usermode access allowed */
306 #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
307 #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
308 #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
309 #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
310 #define _PAGE_DIRTY 0x080 /* C: page changed */
311 #define _PAGE_ACCESSED 0x100 /* R: page referenced */
312 #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
313 #define _PAGE_RW 0x400 /* software: user write access allowed */
315 #define _PTE_NONE_MASK _PAGE_HASHPTE
317 #define _PMD_PRESENT 0
318 #define _PMD_PRESENT_MASK (PAGE_MASK)
319 #define _PMD_BAD (~PAGE_MASK)
323 * Some bits are only used on some cpu families...
325 #ifndef _PAGE_HASHPTE
326 #define _PAGE_HASHPTE 0
328 #ifndef _PTE_NONE_MASK
329 #define _PTE_NONE_MASK 0
332 #define _PAGE_SHARED 0
334 #ifndef _PAGE_HWWRITE
335 #define _PAGE_HWWRITE 0
338 #define _PAGE_HWEXEC 0
343 #ifndef _PMD_PRESENT_MASK
344 #define _PMD_PRESENT_MASK _PMD_PRESENT
348 #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
351 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
354 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
355 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
356 * to have it in the Linux PTE, and in fact the bit could be reused for
357 * another purpose. -- paulus.
361 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
363 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
365 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
366 #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
368 #ifdef CONFIG_PPC_STD_MMU
369 /* On standard PPC MMU, no user access implies kernel read/write access,
370 * so to write-protect kernel memory we must turn on user access */
371 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
373 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
376 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
377 #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
379 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
380 /* We want the debuggers to be able to set breakpoints anywhere, so
381 * don't write protect the kernel text */
382 #define _PAGE_RAM_TEXT _PAGE_RAM
384 #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
387 #define PAGE_NONE __pgprot(_PAGE_BASE)
388 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
389 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
390 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
391 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
392 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
393 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
395 #define PAGE_KERNEL __pgprot(_PAGE_RAM)
396 #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
399 * The PowerPC can only do execute protection on a segment (256MB) basis,
400 * not on a page basis. So we consider execute permission the same as read.
401 * Also, write permissions imply read permissions.
402 * This is the closest we can get..
404 #define __P000 PAGE_NONE
405 #define __P001 PAGE_READONLY_X
406 #define __P010 PAGE_COPY
407 #define __P011 PAGE_COPY_X
408 #define __P100 PAGE_READONLY
409 #define __P101 PAGE_READONLY_X
410 #define __P110 PAGE_COPY
411 #define __P111 PAGE_COPY_X
413 #define __S000 PAGE_NONE
414 #define __S001 PAGE_READONLY_X
415 #define __S010 PAGE_SHARED
416 #define __S011 PAGE_SHARED_X
417 #define __S100 PAGE_READONLY
418 #define __S101 PAGE_READONLY_X
419 #define __S110 PAGE_SHARED
420 #define __S111 PAGE_SHARED_X
423 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
424 * kernel without large page PMD support */
425 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
428 * Conversions between PTE values and page frame numbers.
431 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
432 #define pte_page(x) pfn_to_page(pte_pfn(x))
434 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
435 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
438 * ZERO_PAGE is a global shared page that is always zero: used
439 * for zero-mapped memory areas etc..
441 extern unsigned long empty_zero_page[1024];
442 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
444 #endif /* __ASSEMBLY__ */
446 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
447 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
448 #define pte_clear(ptep) do { set_pte((ptep), __pte(0)); } while (0)
450 #define pmd_none(pmd) (!pmd_val(pmd))
451 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
452 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
453 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
457 * The "pgd_xxx()" functions here are trivial for a folded two-level
458 * setup: the pgd is never bad, and a pmd always exists (as it's folded
459 * into the pgd entry)
461 static inline int pgd_none(pgd_t pgd) { return 0; }
462 static inline int pgd_bad(pgd_t pgd) { return 0; }
463 static inline int pgd_present(pgd_t pgd) { return 1; }
464 #define pgd_clear(xp) do { } while (0)
466 #define pgd_page(pgd) \
467 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
470 * The following only work if pte_present() is true.
471 * Undefined behaviour if not..
473 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
474 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
475 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
476 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
477 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
478 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
480 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
481 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
483 static inline pte_t pte_rdprotect(pte_t pte) {
484 pte_val(pte) &= ~_PAGE_USER; return pte; }
485 static inline pte_t pte_wrprotect(pte_t pte) {
486 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
487 static inline pte_t pte_exprotect(pte_t pte) {
488 pte_val(pte) &= ~_PAGE_EXEC; return pte; }
489 static inline pte_t pte_mkclean(pte_t pte) {
490 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
491 static inline pte_t pte_mkold(pte_t pte) {
492 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
494 static inline pte_t pte_mkread(pte_t pte) {
495 pte_val(pte) |= _PAGE_USER; return pte; }
496 static inline pte_t pte_mkexec(pte_t pte) {
497 pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
498 static inline pte_t pte_mkwrite(pte_t pte) {
499 pte_val(pte) |= _PAGE_RW; return pte; }
500 static inline pte_t pte_mkdirty(pte_t pte) {
501 pte_val(pte) |= _PAGE_DIRTY; return pte; }
502 static inline pte_t pte_mkyoung(pte_t pte) {
503 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
505 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
507 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
512 * Atomic PTE updates.
514 * pte_update clears and sets bit atomically, and returns
516 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
517 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
519 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
522 unsigned long old, tmp;
524 __asm__ __volatile__("\
531 : "=&r" (old), "=&r" (tmp), "=m" (*p)
532 : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p)
538 * set_pte stores a linux PTE into the linux page table.
539 * On machines which use an MMU hash table we avoid changing the
542 static inline void set_pte(pte_t *ptep, pte_t pte)
544 #if _PAGE_HASHPTE != 0
545 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
551 extern void flush_hash_one_pte(pte_t *ptep);
554 * 2.6 calles this without flushing the TLB entry, this is wrong
555 * for our hash-based implementation, we fix that up here
557 static inline int ptep_test_and_clear_young(pte_t *ptep)
560 old = (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED);
561 #if _PAGE_HASHPTE != 0
562 if (old & _PAGE_HASHPTE)
563 flush_hash_one_pte(ptep);
568 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
570 return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
573 static inline pte_t ptep_get_and_clear(pte_t *ptep)
575 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
578 static inline void ptep_set_wrprotect(pte_t *ptep)
580 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
583 static inline void ptep_mkdirty(pte_t *ptep)
585 pte_update(ptep, 0, _PAGE_DIRTY);
588 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
589 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
591 unsigned long bits = pte_val(entry) &
592 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
593 pte_update(ptep, 0, bits);
596 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
598 __ptep_set_access_flags(__ptep, __entry, __dirty); \
599 flush_tlb_page_nohash(__vma, __address); \
603 * Macro to mark a page protection value as "uncacheable".
605 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
607 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
610 * Note that on Book E processors, the pmd contains the kernel virtual
611 * (lowmem) address of the pte page. The physical address is less useful
612 * because everything runs with translation enabled (even the TLB miss
613 * handler). On everything else the pmd contains the physical address
614 * of the pte page. -- paulus
617 #define pmd_page_kernel(pmd) \
618 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
619 #define pmd_page(pmd) \
620 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
622 #define pmd_page_kernel(pmd) \
623 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
624 #define pmd_page(pmd) \
625 (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
628 /* to find an entry in a kernel page-table-directory */
629 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
631 /* to find an entry in a page-table-directory */
632 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
633 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
635 /* Find an entry in the second-level page table.. */
636 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
638 return (pmd_t *) dir;
641 /* Find an entry in the third-level page table.. */
642 #define pte_index(address) \
643 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
644 #define pte_offset_kernel(dir, addr) \
645 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
646 #define pte_offset_map(dir, addr) \
647 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
648 #define pte_offset_map_nested(dir, addr) \
649 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
651 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
652 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
654 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
656 extern void paging_init(void);
659 * When flushing the tlb entry for a page, we also need to flush the hash
660 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
662 extern int flush_hash_pages(unsigned context, unsigned long va,
663 unsigned long pmdval, int count);
665 /* Add an HPTE to the hash table */
666 extern void add_hash_page(unsigned context, unsigned long va,
667 unsigned long pmdval);
670 * Encode and decode a swap entry.
671 * Note that the bits we use in a PTE for representing a swap entry
672 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
673 *_PAGE_HASHPTE bit (if used). -- paulus
675 #define __swp_type(entry) ((entry).val & 0x1f)
676 #define __swp_offset(entry) ((entry).val >> 5)
677 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
678 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
679 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
681 /* Encode and decode a nonlinear file mapping entry */
682 #define PTE_FILE_MAX_BITS 29
683 #define pte_to_pgoff(pte) (pte_val(pte) >> 3)
684 #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
687 /* For virtual address to physical address conversion */
688 extern void cache_clear(__u32 addr, int length);
689 extern void cache_push(__u32 addr, int length);
690 extern int mm_end_of_chunk (unsigned long addr, int len);
691 extern unsigned long iopa(unsigned long addr);
692 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
694 /* Values for nocacheflag and cmode */
695 /* These are not used by the APUS kernel_map, but prevents
696 compilation errors. */
697 #define KERNELMAP_FULL_CACHING 0
698 #define KERNELMAP_NOCACHE_SER 1
699 #define KERNELMAP_NOCACHE_NONSER 2
700 #define KERNELMAP_NO_COPYBACK 3
703 * Map some physical address range into the kernel address space.
705 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
706 int nocacheflag, unsigned long *memavailp );
709 * Set cache mode of (kernel space) address range.
711 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
714 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
715 #define kern_addr_valid(addr) (1)
717 #define io_remap_page_range remap_page_range
720 * No page table caches to initialise
722 #define pgtable_cache_init() do { } while (0)
724 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
726 #endif /* !__ASSEMBLY__ */
728 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
729 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
730 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
731 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
732 #define __HAVE_ARCH_PTEP_MKDIRTY
733 #define __HAVE_ARCH_PTE_SAME
734 #include <asm-generic/pgtable.h>
736 #endif /* _PPC_PGTABLE_H */
737 #endif /* __KERNEL__ */