2 * Contains register definitions common to the Book E PowerPC
3 * specification. Notice that while the IBM-40x series of CPUs
4 * are not true Book E PowerPCs, they borrowed a number of features
5 * before Book E was finalized, and are included here as well. Unfortunatly,
6 * they sometimes used different locations than true Book E CPUs did.
9 #ifndef __ASM_PPC_REG_BOOKE_H__
10 #define __ASM_PPC_REG_BOOKE_H__
13 /* Device Control Registers */
14 #define mfdcr(rn) mfdcr_or_dflt(rn, 0)
15 #define mfdcr_or_dflt(rn,default_rval) \
16 ({unsigned int rval; \
18 rval = default_rval; \
20 asm volatile("mfdcr %0," __stringify(rn) : "=r" (rval)); \
23 #define mtdcr(rn, v) \
26 asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (v)); \
29 /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
30 #define mfdcri(base, reg) \
32 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
33 mfdcr(base ## _CFGDATA); \
36 #define mtdcri(base, reg, data) \
38 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
39 mtdcr(base ## _CFGDATA, data); \
41 #endif /* __ASSEMBLY__ */
44 /* Machine State Register (MSR) Fields */
45 #define MSR_DWE (1<<10) /* Debug Wait Enable */
46 #define MSR_IS MSR_IR /* Instruction Space */
47 #define MSR_DS MSR_DR /* Data Space */
49 /* Default MSR for kernel mode. */
50 #if defined (CONFIG_40x)
51 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE|MSR_DE)
52 #elif defined(CONFIG_BOOKE)
53 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE)
56 /* Special Purpose Registers (SPRNs)*/
57 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
58 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
59 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
60 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
61 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
62 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
63 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
64 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
65 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
66 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
67 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
68 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
69 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
70 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
71 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
72 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
73 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
74 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
75 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
76 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
77 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
78 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
79 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
80 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
81 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
82 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
83 #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
84 #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
85 #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
86 #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
87 #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
88 #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
89 #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
90 #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
91 #define SPRN_MCSR 0x23C /* Machine Check Status Register */
93 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
94 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
95 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
96 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
97 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
98 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
99 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
100 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
101 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
103 #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
104 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */
105 #define SPRN_CCR0 0x3B3 /* Core Configuration Register */
106 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
107 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
108 #define SPRN_SLER 0x3BB /* Little-endian real mode */
109 #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
110 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
111 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
112 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
113 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
114 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
115 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
118 * SPRs which have conflicting definitions on true Book E versus classic,
122 #define SPRN_PID 0x030 /* Process ID */
123 #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
124 #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
125 #define SPRN_DEAR 0x03D /* Data Error Address Register */
126 #define SPRN_ESR 0x03E /* Exception Syndrome Register */
127 #define SPRN_PIR 0x11E /* Processor Identification Register */
128 #define SPRN_DBSR 0x130 /* Debug Status Register */
129 #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
130 #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
131 #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
132 #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
133 #define SPRN_DAC1 0x13C /* Data Address Compare 1 */
134 #define SPRN_DAC2 0x13D /* Data Address Compare 2 */
135 #define SPRN_TSR 0x150 /* Timer Status Register */
136 #define SPRN_TCR 0x154 /* Timer Control Register */
139 #define SPRN_PID 0x3B1 /* Process ID */
140 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
141 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
142 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
143 #define SPRN_TSR 0x3D8 /* Timer Status Register */
144 #define SPRN_TCR 0x3DA /* Timer Control Register */
145 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
146 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
147 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
148 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
149 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
150 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
151 #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
152 #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
155 /* Bit definitions for the DBSR. */
157 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
160 #define DBSR_IC 0x08000000 /* Instruction Completion */
161 #define DBSR_BT 0x04000000 /* Branch Taken */
162 #define DBSR_TIE 0x01000000 /* Trap Instruction Event */
165 #define DBSR_IC 0x80000000 /* Instruction Completion */
166 #define DBSR_BT 0x40000000 /* Branch taken */
167 #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
170 /* Bit definitions related to the ESR. */
171 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
172 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
173 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
174 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
175 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
176 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
177 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
178 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
179 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
180 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
181 #define ESR_ST 0x00800000 /* Store Operation */
183 /* Bit definitions related to the DBCR0. */
184 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
185 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
186 #define DBCR0_RST 0x30000000 /* all the bits in the RST field */
187 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
188 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
189 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */
190 #define DBCR0_RST_NONE 0x00000000 /* No Reset */
191 #define DBCR0_IC 0x08000000 /* Instruction Completion */
192 #define DBCR0_BT 0x04000000 /* Branch Taken */
193 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */
194 #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
195 #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
196 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
197 #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
198 #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
199 #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
200 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
201 #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
202 #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
203 #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
204 #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
205 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
207 /* Bit definitions related to the TCR. */
208 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
209 #define TCR_WP_MASK TCR_WP(3)
210 #define WP_2_17 0 /* 2^17 clocks */
211 #define WP_2_21 1 /* 2^21 clocks */
212 #define WP_2_25 2 /* 2^25 clocks */
213 #define WP_2_29 3 /* 2^29 clocks */
214 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
215 #define TCR_WRC_MASK TCR_WRC(3)
216 #define WRC_NONE 0 /* No reset will occur */
217 #define WRC_CORE 1 /* Core reset will occur */
218 #define WRC_CHIP 2 /* Chip reset will occur */
219 #define WRC_SYSTEM 3 /* System reset will occur */
220 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
221 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
222 #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
223 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
224 #define TCR_FP_MASK TCR_FP(3)
225 #define FP_2_9 0 /* 2^9 clocks */
226 #define FP_2_13 1 /* 2^13 clocks */
227 #define FP_2_17 2 /* 2^17 clocks */
228 #define FP_2_21 3 /* 2^21 clocks */
229 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
230 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
232 /* Bit definitions for the TSR. */
233 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
234 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
235 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
236 #define WRS_NONE 0 /* No WDT reset occurred */
237 #define WRS_CORE 1 /* WDT forced core reset */
238 #define WRS_CHIP 2 /* WDT forced chip reset */
239 #define WRS_SYSTEM 3 /* WDT forced system reset */
240 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
241 #define TSR_DIS TSR_PIS /* DEC Interrupt Status */
242 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
244 /* Bit definitions for the DCCR. */
245 #define DCCR_NOCACHE 0 /* Noncacheable */
246 #define DCCR_CACHE 1 /* Cacheable */
248 /* Bit definitions for DCWR. */
249 #define DCWR_COPY 0 /* Copy-back */
250 #define DCWR_WRITE 1 /* Write-through */
252 /* Bit definitions for ICCR. */
253 #define ICCR_NOCACHE 0 /* Noncacheable */
254 #define ICCR_CACHE 1 /* Cacheable */
256 /* Bit definitions for SGR. */
257 #define SGR_NORMAL 0 /* Speculative fetching allowed. */
258 #define SGR_GUARDED 1 /* Speculative fetching disallowed. */
260 /* Short-hand for various SPRs. */
262 #define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */
263 #define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */
265 #define CSRR0 SPRN_SRR2 /* Logically and functionally equivalent. */
266 #define CSRR1 SPRN_SRR3 /* Logically and functionally equivalent. */
268 #define MCSRR0 SPRN_MCSRR0 /* Machine Check Save and Restore Register 0 */
269 #define MCSRR1 SPRN_MCSRR1 /* Machine Check Save and Restore Register 1 */
270 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
271 #define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */
272 #define SPRG5R SPRN_SPRG5R
273 #define SPRG6R SPRN_SPRG6R
274 #define SPRG7R SPRN_SPRG7R
275 #define SPRG4W SPRN_SPRG4W
276 #define SPRG5W SPRN_SPRG5W
277 #define SPRG6W SPRN_SPRG6W
278 #define SPRG7W SPRN_SPRG7W
281 * The IBM-403 is an even more odd special case, as it is much
282 * older than the IBM-405 series. We put these down here incase someone
283 * wishes to support these machines again.
286 /* Special Purpose Registers (SPRNs)*/
287 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
288 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
289 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
290 #define SPRN_TBHI 0x3DC /* Time Base High */
291 #define SPRN_TBLO 0x3DD /* Time Base Low */
292 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
293 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
294 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
295 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
296 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
299 /* Bit definitions for the DBCR. */
300 #define DBCR_EDM DBCR0_EDM
301 #define DBCR_IDM DBCR0_IDM
302 #define DBCR_RST(x) (((x) & 0x3) << 28)
303 #define DBCR_RST_NONE 0
304 #define DBCR_RST_CORE 1
305 #define DBCR_RST_CHIP 2
306 #define DBCR_RST_SYSTEM 3
307 #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
308 #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
309 #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
310 #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
311 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
312 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
313 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
314 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
315 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
316 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
317 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
322 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
323 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
324 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
325 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
326 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
327 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
328 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
329 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
330 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
331 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
333 #endif /* __ASM_PPC_REG_BOOKE_H__ */
334 #endif /* __KERNEL__ */