2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
9 #ifndef __ASM_UNINORTH_H__
10 #define __ASM_UNINORTH_H__
13 * Uni-N and U3 config space reg. definitions
18 /* Address ranges selection. This one should work with Bandit too */
20 #define UNI_N_ADDR_SELECT 0x48
21 #define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22 #define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
26 #define UNI_N_CFG_GART_BASE 0x8c
27 #define UNI_N_CFG_AGP_BASE 0x90
28 #define UNI_N_CFG_GART_CTRL 0x94
29 #define UNI_N_CFG_INTERNAL_STATUS 0x98
31 /* UNI_N_CFG_GART_CTRL bits definitions */
33 #define UNI_N_CFG_GART_INVAL 0x00000001
34 #define UNI_N_CFG_GART_ENABLE 0x00000100
35 #define UNI_N_CFG_GART_2xRESET 0x00010000
36 #define UNI_N_CFG_GART_DISSBADET 0x00020000
38 /* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
39 * revision 1.5 (x4 AGP) may need further changes.
41 * AGP_BASE register contains the base address of the AGP aperture on
42 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
43 * even if decoding of this address range is enabled in the address select
44 * register. Apparently, the only supported bases are 256Mb multiples
45 * (high 4 bits of that register).
47 * GART_BASE register appear to contain the physical address of the GART
48 * in system memory in the high address bits (page aligned), and the
49 * GART size in the low order bits (number of GART pages)
51 * The GART format itself is one 32bits word per physical memory page.
52 * This word contains, in little-endian format (!!!), the physical address
53 * of the page in the high bits, and what appears to be an "enable" bit
54 * in the LSB bit (0) that must be set to 1 when the entry is valid.
56 * Obviously, the GART is not cache coherent and so any change to it
57 * must be flushed to memory (or maybe just make the GART space non
58 * cachable). AGP memory itself doens't seem to be cache coherent neither.
60 * In order to invalidate the GART (which is probably necessary to inval
61 * the bridge internal TLBs), the following sequence has to be written,
62 * in order, to the GART_CTRL register:
64 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
65 * UNI_N_CFG_GART_ENABLE
66 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
67 * UNI_N_CFG_GART_ENABLE
69 * As far as AGP "features" are concerned, it looks like fast write may
70 * not be supported but this has to be confirmed.
72 * Turning on AGP seem to require a double invalidate operation, one before
73 * setting the AGP command register, on after.
75 * Turning off AGP seems to require the following sequence: first wait
76 * for the AGP to be idle by reading the internal status register, then
77 * write in that order to the GART_CTRL register:
79 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
81 * UNI_N_CFG_GART_2xRESET
86 * Uni-N memory mapped reg. definitions
88 * Those registers are Big-Endian !!
90 * Their meaning come from either Darwin and/or from experiments I made with
91 * the bootrom, I'm not sure about their exact meaning yet
95 /* Version of the UniNorth chip */
96 #define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
98 #define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
99 #define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
100 #define UNI_N_VERSION_150 0x0011 /* 1.5 */
101 #define UNI_N_VERSION_200 0x0024 /* 2.0 */
102 #define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
103 #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
104 #define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
106 /* This register is used to enable/disable various clocks */
107 #define UNI_N_CLOCK_CNTL 0x0020
108 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
109 #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
110 #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
111 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
113 /* Power Management control */
114 #define UNI_N_POWER_MGT 0x0030
115 #define UNI_N_POWER_MGT_NORMAL 0x00
116 #define UNI_N_POWER_MGT_IDLE2 0x01
117 #define UNI_N_POWER_MGT_SLEEP 0x02
119 /* This register is configured by Darwin depending on the UniN
122 #define UNI_N_ARB_CTRL 0x0040
123 #define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
124 #define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
125 #define UNI_N_ARB_CTRL_QACK_DELAY 0x30
126 #define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
128 /* This one _might_ return the CPU number of the CPU reading it;
129 * the bootROM decides whether to boot or to sleep/spinloop depending
130 * on this register beeing 0 or not
132 #define UNI_N_CPU_NUMBER 0x0050
134 /* This register appear to be read by the bootROM to decide what
135 * to do on a non-recoverable reset (powerup or wakeup)
137 #define UNI_N_HWINIT_STATE 0x0070
138 #define UNI_N_HWINIT_STATE_SLEEPING 0x01
139 #define UNI_N_HWINIT_STATE_RUNNING 0x02
140 /* This last bit appear to be used by the bootROM to know the second
141 * CPU has started and will enter it's sleep loop with IP=0
143 #define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
145 /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
149 * U3 specific registers
154 #define U3_TOGGLE_REG 0x00e0
155 #define U3_PMC_START_STOP 0x0001
156 #define U3_MPIC_RESET 0x0002
157 #define U3_MPIC_OUTPUT_ENABLE 0x0004
159 /* U3 API PHY Config 1 */
160 #define U3_API_PHY_CONFIG_1 0x23030
162 /* U3 HyperTransport registers */
163 #define U3_HT_CONFIG_BASE 0x70000
164 #define U3_HT_LINK_COMMAND 0x100
165 #define U3_HT_LINK_CONFIG 0x110
166 #define U3_HT_LINK_FREQ 0x120
168 #endif /* __ASM_UNINORTH_H__ */
169 #endif /* __KERNEL__ */