1 #ifndef _PPC64_CACHEFLUSH_H
2 #define _PPC64_CACHEFLUSH_H
5 #include <asm/cputable.h>
8 * No cache flushing is required when address mappings are
9 * changed, because the caches on PowerPCs are physically
12 #define flush_cache_all() do { } while (0)
13 #define flush_cache_mm(mm) do { } while (0)
14 #define flush_cache_range(vma, start, end) do { } while (0)
15 #define flush_cache_page(vma, vmaddr) do { } while (0)
16 #define flush_icache_page(vma, page) do { } while (0)
17 #define flush_cache_vmap(start, end) do { } while (0)
18 #define flush_cache_vunmap(start, end) do { } while (0)
20 extern void flush_dcache_page(struct page *page);
21 extern void __flush_icache_range(unsigned long, unsigned long);
22 extern void flush_icache_user_range(struct vm_area_struct *vma,
23 struct page *page, unsigned long addr,
26 extern void flush_dcache_range(unsigned long start, unsigned long stop);
27 extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
29 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
30 do { memcpy(dst, src, len); \
31 flush_icache_user_range(vma, page, vaddr, len); \
33 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
36 extern void __flush_dcache_icache(void *page_va);
38 static inline void flush_icache_range(unsigned long start, unsigned long stop)
40 if (!(cur_cpu_spec->cpu_features & CPU_FTR_COHERENT_ICACHE))
41 __flush_icache_range(start, stop);
44 #endif /* _PPC64_CACHEFLUSH_H */