3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 //=============================================================================
24 // This control block contains the data that is shared between the
25 // hypervisor (PLIC) and the OS.
28 //----------------------------------------------------------------------------
29 #include <asm/types.h>
33 //=============================================================================
34 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
35 // NOTE: The xDynXyz fields are fields that will be dynamically changed by
36 // PLIC when preparing to bring a processor online or when dispatching a
38 //=============================================================================
39 u32 xDesc; // Eye catcher 0xD397D781 x00-x03
40 u16 xSize; // Size of this struct x04-x05
41 u16 xRsvd1_0; // Reserved x06-x07
42 u16 xRsvd1_1:14; // Reserved x08-x09
43 u8 xSharedProc:1; // Shared processor indicator ...
44 u8 xSecondaryThread:1; // Secondary thread indicator ...
45 volatile u8 xDynProcStatus:8; // Dynamic Status of this proc x0A-x0A
46 u8 xSecondaryThreadCnt; // Secondary thread count x0B-x0B
47 volatile u16 xDynHvPhysicalProcIndex;// Dynamic HV Physical Proc Index0C-x0D
48 volatile u16 xDynHvLogicalProcIndex;// Dynamic HV Logical Proc Indexx0E-x0F
49 u32 xDecrVal; // Value for Decr programming x10-x13
50 u32 xPMCVal; // Value for PMC regs x14-x17
51 volatile u32 xDynHwNodeId; // Dynamic Hardware Node id x18-x1B
52 volatile u32 xDynHwProcId; // Dynamic Hardware Proc Id x1C-x1F
53 volatile u32 xDynPIR; // Dynamic ProcIdReg value x20-x23
54 u32 xDseiData; // DSEI data x24-x27
55 u64 xSPRG3; // SPRG3 value x28-x2F
56 u8 xRsvd1_3[80]; // Reserved x30-x7F
58 //=============================================================================
59 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
60 //=============================================================================
61 // This Dword contains a byte for each type of interrupt that can occur.
62 // The IPI is a count while the others are just a binary 1 or 0.
66 u16 xRsvd; // Reserved - cleared by #mpasmbl
67 u8 xXirrInt; // Indicates xXirrValue is valid or Immed IO
68 u8 xIpiCnt; // IPI Count
69 u8 xDecrInt; // DECR interrupt occurred
70 u8 xPdcInt; // PDC interrupt occurred
71 u8 xQuantumInt; // Interrupt quantum reached
72 u8 xOldPlicDeferredExtInt; // Old PLIC has a deferred XIRR pending
76 // Whenever any fields in this Dword are set then PLIC will defer the
77 // processing of external interrupts. Note that PLIC will store the
78 // XIRR directly into the xXirrValue field so that another XIRR will
79 // not be presented until this one clears. The layout of the low
80 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
81 // entire Dword is zero or not. A non-zero value in the low order
82 // 2-bytes will result in SLIC being granted the highest thread
83 // priority upon return. A 0 will return to SLIC as medium priority.
84 u64 xPlicDeferIntsArea; // Entire Dword
86 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
87 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
88 u64 xSavedSrr0; // Saved SRR0 x10-x17
89 u64 xSavedSrr1; // Saved SRR1 x18-x1F
91 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
92 u64 xSavedGpr3; // Saved GPR3 x20-x27
93 u64 xSavedGpr4; // Saved GPR4 x28-x2F
94 u64 xSavedGpr5; // Saved GPR5 x30-x37
96 u8 xRsvd2_1; // Reserved x38-x38
97 u8 xCpuCtlsTaskAttributes; // Task attributes for cpuctls x39-x39
98 u8 xFPRegsInUse; // FP regs in use x3A-x3A
99 u8 xPMCRegsInUse; // PMC regs in use x3B-x3B
100 volatile u32 xSavedDecr; // Saved Decr Value x3C-x3F
101 volatile u64 xEmulatedTimeBase;// Emulated TB for this thread x40-x47
102 volatile u64 xCurPLICLatency; // Unaccounted PLIC latency x48-x4F
103 u64 xTotPLICLatency; // Accumulated PLIC latency x50-x57
104 u64 xWaitStateCycles; // Wait cycles for this proc x58-x5F
105 u64 xEndOfQuantum; // TB at end of quantum x60-x67
106 u64 xPDCSavedSPRG1; // Saved SPRG1 for PMC int x68-x6F
107 u64 xPDCSavedSRR0; // Saved SRR0 for PMC int x70-x77
108 volatile u32 xVirtualDecr; // Virtual DECR for shared procsx78-x7B
109 u16 xSLBCount; // # of SLBs to maintain x7C-x7D
110 u8 xIdle; // Indicate OS is idle x7E
111 u8 xRsvd2_2; // Reserved x7F
114 //=============================================================================
115 // CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
116 //=============================================================================
117 // This is the xYieldCount. An "odd" value (low bit on) means that
118 // the processor is yielded (either because of an OS yield or a PLIC
119 // preempt). An even value implies that the processor is currently
121 // NOTE: This value will ALWAYS be zero for dedicated processors and
122 // will NEVER be zero for shared processors (ie, initialized to a 1).
123 volatile u32 xYieldCount; // PLIC increments each dispatchx00-x03
124 u8 xRsvd3_0[124]; // Reserved x04-x7F
126 //=============================================================================
127 // CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
128 //=============================================================================
129 u8 xPmcSaveArea[256]; // PMC interrupt Area x00-xFF
134 #endif /* _ITLPPACA_H */