2 * PowerPC memory management structures
4 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
18 #include <linux/stringify.h>
22 /* Time to allow for more things here */
23 typedef unsigned long mm_context_id_t;
26 #ifdef CONFIG_HUGETLB_PAGE
28 u16 htlb_segs; /* bitmask */
32 #define STE_ESID_V 0x80
33 #define STE_ESID_KS 0x20
34 #define STE_ESID_KP 0x10
35 #define STE_ESID_N 0x08
37 #define STE_VSID_SHIFT 12
40 unsigned long esid_data;
41 unsigned long vsid_data;
44 /* Hardware Page Table Entry */
46 #define HPTES_PER_GROUP 8
49 unsigned long avpn:57; /* vsid | api == avpn */
50 unsigned long : 2; /* Software use */
51 unsigned long bolted: 1; /* HPTE is "bolted" */
52 unsigned long lock: 1; /* lock on pSeries SMP */
53 unsigned long l: 1; /* Virtual page is large (L=1) or 4 KB (L=0) */
54 unsigned long h: 1; /* Hash function identifier */
55 unsigned long v: 1; /* Valid (v=1) or invalid (v=0) */
59 unsigned long pp0: 1; /* Page protection bit 0 */
60 unsigned long ts: 1; /* Tag set bit */
61 unsigned long rpn: 50; /* Real page number */
62 unsigned long : 2; /* Reserved */
63 unsigned long ac: 1; /* Address compare */
64 unsigned long r: 1; /* Referenced */
65 unsigned long c: 1; /* Changed */
66 unsigned long w: 1; /* Write-thru cache mode */
67 unsigned long i: 1; /* Cache inhibited */
68 unsigned long m: 1; /* Memory coherence required */
69 unsigned long g: 1; /* Guarded */
70 unsigned long n: 1; /* No-execute */
71 unsigned long pp: 2; /* Page protection bits 1:2 */
75 char padding[6]; /* padding */
76 unsigned long : 6; /* padding */
77 unsigned long flags: 10; /* HPTE flags */
89 Hpte_dword1_flags flags;
93 /* Values for PP (assumes Ks=0, Kp=1) */
94 /* pp0 will always be 0 for linux */
95 #define PP_RWXX 0 /* Supervisor read/write, User none */
96 #define PP_RWRX 1 /* Supervisor read/write, User read */
97 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
98 #define PP_RXRX 3 /* Supervisor read, User read */
101 extern HPTE * htab_address;
102 extern unsigned long htab_hash_mask;
104 static inline unsigned long hpt_hash(unsigned long vpn, int large)
117 return (vsid & 0x7fffffffffUL) ^ page;
120 static inline void __tlbie(unsigned long va, int large)
122 /* clear top 16 bits, non SLS segment */
123 va &= ~(0xffffULL << 48);
127 asm volatile("tlbie %0,1" : : "r"(va) : "memory");
130 asm volatile("tlbie %0,0" : : "r"(va) : "memory");
134 static inline void tlbie(unsigned long va, int large)
136 asm volatile("ptesync": : :"memory");
138 asm volatile("eieio; tlbsync; ptesync": : :"memory");
141 static inline void __tlbiel(unsigned long va)
143 /* clear top 16 bits, non SLS segment */
144 va &= ~(0xffffULL << 48);
148 * Thanks to Alan Modra we are now able to use machine specific
149 * assembly instructions (like tlbiel) by using the gas -many flag.
150 * However we have to support older toolchains so for the moment
154 asm volatile("tlbiel %0" : : "r"(va) : "memory");
156 asm volatile(".long 0x7c000224 | (%0 << 11)" : : "r"(va) : "memory");
160 static inline void tlbiel(unsigned long va)
162 asm volatile("ptesync": : :"memory");
164 asm volatile("ptesync": : :"memory");
168 * Handle a fault by adding an HPTE. If the address can't be determined
169 * to be valid via Linux page tables, return 1. If handled return 0
171 extern int __hash_page(unsigned long ea, unsigned long access,
172 unsigned long vsid, pte_t *ptep, unsigned long trap,
175 extern void htab_finish_init(void);
177 #endif /* __ASSEMBLY__ */
180 * Location of cpu0's segment table
182 #define STAB0_PAGE 0x9
183 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
184 #define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
186 #define SLB_NUM_BOLTED 3
187 #define SLB_CACHE_ENTRIES 8
189 /* Bits in the SLB ESID word */
190 #define SLB_ESID_V 0x0000000008000000 /* entry is valid */
192 /* Bits in the SLB VSID word */
193 #define SLB_VSID_SHIFT 12
194 #define SLB_VSID_KS 0x0000000000000800
195 #define SLB_VSID_KP 0x0000000000000400
196 #define SLB_VSID_N 0x0000000000000200 /* no-execute */
197 #define SLB_VSID_L 0x0000000000000100 /* largepage (4M) */
198 #define SLB_VSID_C 0x0000000000000080 /* class */
200 #define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C)
201 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS)
203 #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
205 #define VSID_MODULUS ((1UL<<VSID_BITS)-1)
207 #define CONTEXT_BITS 20
208 #define USER_ESID_BITS 15
211 * This macro generates asm code to compute the VSID scramble
212 * function. Used in slb_allocate() and do_stab_bolted. The function
213 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
215 * rt = register continaing the proto-VSID and into which the
216 * VSID will be stored
217 * rx = scratch register (clobbered)
219 * - rt and rx must be different registers
220 * - The answer will end up in the low 36 bits of rt. The higher
221 * bits may contain other garbage, so you may need to mask the
224 #define ASM_VSID_SCRAMBLE(rt, rx) \
225 lis rx,VSID_MULTIPLIER@h; \
226 ori rx,rx,VSID_MULTIPLIER@l; \
227 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
229 srdi rx,rt,VSID_BITS; \
230 clrldi rt,rt,(64-VSID_BITS); \
231 add rt,rt,rx; /* add high and low bits */ \
232 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
233 * 2^36-1+2^28-1. That in particular means that if r3 >= \
234 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
235 * the bit clear, r3 already has the answer we want, if it \
236 * doesn't, the answer is the low 36 bits of r3+1. So in all \
237 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
239 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
242 #endif /* _PPC64_MMU_H_ */