6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/dma-mapping.h>
16 #include <asm/machdep.h>
17 #include <asm/scatterlist.h>
21 #define PCIBIOS_MIN_IO 0x1000
22 #define PCIBIOS_MIN_MEM 0x10000000
26 #ifdef CONFIG_PPC_ISERIES
27 #define pcibios_scan_all_fns(a, b) 0
29 extern int pcibios_scan_all_fns(struct pci_bus *bus, int devfn);
32 static inline void pcibios_set_master(struct pci_dev *dev)
34 /* No special bus mastering setup handling */
37 static inline void pcibios_penalize_isa_irq(int irq)
39 /* We don't do dynamic PCI IRQ allocation */
42 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
43 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
45 if (ppc_md.pci_get_legacy_ide_irq)
46 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
47 return channel ? 15 : 14;
50 #define HAVE_ARCH_PCI_MWI 1
51 static inline int pcibios_prep_mwi(struct pci_dev *dev)
54 * We would like to avoid touching the cacheline size or MWI bit
55 * but we cant do that with the current pcibios_prep_mwi
56 * interface. pSeries firmware sets the cacheline size (which is not
57 * the cpu cacheline size in all cases) and hardware treats MWI
58 * the same as memory write. So we dont touch the cacheline size
59 * here and allow the generic code to set the MWI bit.
64 extern unsigned int pcibios_assign_all_busses(void);
67 * PCI DMA operations are abstracted for G5 vs. i/pSeries
70 void * (*pci_alloc_consistent)(struct pci_dev *hwdev, size_t size,
71 dma_addr_t *dma_handle);
72 void (*pci_free_consistent)(struct pci_dev *hwdev, size_t size,
73 void *vaddr, dma_addr_t dma_handle);
75 dma_addr_t (*pci_map_single)(struct pci_dev *hwdev, void *ptr,
76 size_t size, enum dma_data_direction direction);
77 void (*pci_unmap_single)(struct pci_dev *hwdev, dma_addr_t dma_addr,
78 size_t size, enum dma_data_direction direction);
79 int (*pci_map_sg)(struct pci_dev *hwdev, struct scatterlist *sg,
80 int nents, enum dma_data_direction direction);
81 void (*pci_unmap_sg)(struct pci_dev *hwdev, struct scatterlist *sg,
82 int nents, enum dma_data_direction direction);
83 int (*pci_dma_supported)(struct pci_dev *hwdev, u64 mask);
84 int (*pci_dac_dma_supported)(struct pci_dev *hwdev, u64 mask);
87 extern struct pci_dma_ops pci_dma_ops;
89 static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
90 dma_addr_t *dma_handle)
92 return pci_dma_ops.pci_alloc_consistent(hwdev, size, dma_handle);
95 static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
96 void *vaddr, dma_addr_t dma_handle)
98 pci_dma_ops.pci_free_consistent(hwdev, size, vaddr, dma_handle);
101 static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
102 size_t size, int direction)
104 return pci_dma_ops.pci_map_single(hwdev, ptr, size,
105 (enum dma_data_direction)direction);
108 static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
109 size_t size, int direction)
111 pci_dma_ops.pci_unmap_single(hwdev, dma_addr, size,
112 (enum dma_data_direction)direction);
115 static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
116 int nents, int direction)
118 return pci_dma_ops.pci_map_sg(hwdev, sg, nents,
119 (enum dma_data_direction)direction);
122 static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
123 int nents, int direction)
125 pci_dma_ops.pci_unmap_sg(hwdev, sg, nents,
126 (enum dma_data_direction)direction);
129 static inline void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev,
130 dma_addr_t dma_handle,
131 size_t size, int direction)
133 BUG_ON(direction == PCI_DMA_NONE);
137 static inline void pci_dma_sync_single_for_device(struct pci_dev *hwdev,
138 dma_addr_t dma_handle,
139 size_t size, int direction)
141 BUG_ON(direction == PCI_DMA_NONE);
145 static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev,
146 struct scatterlist *sg,
147 int nelems, int direction)
149 BUG_ON(direction == PCI_DMA_NONE);
153 static inline void pci_dma_sync_sg_for_device(struct pci_dev *hwdev,
154 struct scatterlist *sg,
155 int nelems, int direction)
157 BUG_ON(direction == PCI_DMA_NONE);
161 /* Return whether the given PCI device DMA address mask can
162 * be supported properly. For example, if your device can
163 * only drive the low 24-bits during PCI bus mastering, then
164 * you would pass 0x00ffffff as the mask to this function.
165 * We default to supporting only 32 bits DMA unless we have
166 * an explicit override of this function in pci_dma_ops for
169 static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
171 if (pci_dma_ops.pci_dma_supported)
172 return pci_dma_ops.pci_dma_supported(hwdev, mask);
173 return (mask < 0x100000000ull);
176 /* For DAC DMA, we currently don't support it by default, but
177 * we let the platform override this
179 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
181 if (pci_dma_ops.pci_dac_dma_supported)
182 return pci_dma_ops.pci_dac_dma_supported(hwdev, mask);
186 static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
188 return dma_mapping_error(dma_addr);
191 extern int pci_domain_nr(struct pci_bus *bus);
193 /* Set the name of the bus as it appears in /proc/bus/pci */
194 extern int pci_name_bus(char *name, struct pci_bus *bus);
196 struct vm_area_struct;
197 /* Map a range of PCI memory or I/O space for a device into user space */
198 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
199 enum pci_mmap_state mmap_state, int write_combine);
201 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
202 #define HAVE_PCI_MMAP 1
204 #define pci_map_page(dev, page, off, size, dir) \
205 pci_map_single(dev, (page_address(page) + (off)), size, dir)
206 #define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
208 /* pci_unmap_{single,page} is not a nop, thus... */
209 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
210 dma_addr_t ADDR_NAME;
211 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
213 #define pci_unmap_addr(PTR, ADDR_NAME) \
215 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
216 (((PTR)->ADDR_NAME) = (VAL))
217 #define pci_unmap_len(PTR, LEN_NAME) \
219 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
220 (((PTR)->LEN_NAME) = (VAL))
222 /* The PCI address space does equal the physical memory
223 * address space. The networking and block device layers use
224 * this boolean for bounce buffer decisions.
226 #define PCI_DMA_BUS_IS_PHYS (0)
229 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
230 struct resource *res);
233 unmap_bus_range(struct pci_bus *bus);
236 remap_bus_range(struct pci_bus *bus);
239 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus);
241 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
243 extern int pci_read_irq_line(struct pci_dev *dev);
245 extern void pcibios_add_platform_entries(struct pci_dev *dev);
247 #endif /* __KERNEL__ */
249 #endif /* __PPC64_PCI_H */