2 * arch/ppc64/kernel/ppc_asm.h
4 * Definitions used by various bits of low-level assembly code on PowerPC.
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #ifndef _PPC64_PPC_ASM_H
15 #define _PPC64_PPC_ASM_H
17 * Macros for storing registers into and loading registers from
20 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
21 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
26 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
31 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
32 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
33 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
34 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
35 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
36 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
37 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
38 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
39 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
40 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
41 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
42 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
44 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
45 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
46 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
47 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
48 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
49 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
50 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
51 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
52 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
53 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
54 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
55 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
57 #define CHECKANYINT(ra,rb) \
58 mfspr rb,SPRG3; /* Get Paca address */\
59 ld ra,PACALPPACA+LPPACAANYINT(rb); /* Get pending interrupt flags */\
62 /* Macros to adjust thread priority for Iseries hardware multithreading */
63 #define HMT_LOW or 1,1,1
64 #define HMT_MEDIUM or 2,2,2
65 #define HMT_HIGH or 3,3,3
67 /* Insert the high 32 bits of the MSR into what will be the new
68 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
71 #define FIX_SRR1(ra, rb) \
76 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
79 * LOADADDR( rn, name )
80 * loads the address of 'name' into 'rn'
82 * LOADBASE( rn, name )
83 * loads the address (less the low 16 bits) of 'name' into 'rn'
84 * suitable for base+disp addressing
86 #define LOADADDR(rn,name) \
87 lis rn,name##@highest; \
88 ori rn,rn,name##@higher; \
90 oris rn,rn,name##@h; \
93 #define LOADBASE(rn,name) \
94 lis rn,name@highest; \
95 ori rn,rn,name@higher; \
100 #define SET_REG_TO_CONST(reg, value) \
101 lis reg,(((value)>>48)&0xFFFF); \
102 ori reg,reg,(((value)>>32)&0xFFFF); \
103 rldicr reg,reg,32,31; \
104 oris reg,reg,(((value)>>16)&0xFFFF); \
105 ori reg,reg,((value)&0xFFFF);
107 #define SET_REG_TO_LABEL(reg, label) \
108 lis reg,(label)@highest; \
109 ori reg,reg,(label)@higher; \
110 rldicr reg,reg,32,31; \
111 oris reg,reg,(label)@h; \
112 ori reg,reg,(label)@l;
115 /* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
116 * Then we can easily do this with one asm insn. -Peter
118 #define tophys(rd,rs) \
119 lis rd,((KERNELBASE>>48)&0xFFFF); \
120 rldicr rd,rd,32,31; \
123 #define tovirt(rd,rs) \
124 lis rd,((KERNELBASE>>48)&0xFFFF); \
125 rldicr rd,rd,32,31; \
128 /* Condition Register Bit Fields */
140 /* General Purpose Registers (GPRs) */
176 /* Floating Point Registers (FPRs) */
244 #endif /* _PPC64_PPC_ASM_H */