2 * include/asm-s390/spinlock.h
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Derived from "include/asm-i386/spinlock.h"
11 #ifndef __ASM_SPINLOCK_H
12 #define __ASM_SPINLOCK_H
16 * Grmph, take care of %&#! user space programs that include
17 * asm/spinlock.h. The diagnose is only available in kernel
21 #include <asm/lowcore.h>
22 #define __DIAG44_INSN "ex"
23 #define __DIAG44_OPERAND __LC_DIAG44_OPCODE
25 #define __DIAG44_INSN "#"
26 #define __DIAG44_OPERAND 0
28 #endif /* __s390x__ */
31 * Simple spin lock operations. There are two variants, one clears IRQ's
32 * on the local processor, one does not.
34 * We make no fairness assumptions. They have a cost.
38 volatile unsigned int lock;
39 } __attribute__ ((aligned (4))) spinlock_t;
41 #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
42 #define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
43 #define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
44 #define spin_is_locked(x) ((x)->lock != 0)
46 extern inline void _raw_spin_lock(spinlock_t *lp)
49 unsigned int reg1, reg2;
50 __asm__ __volatile(" bras %0,1f\n"
55 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
56 : "a" (&lp->lock), "m" (lp->lock)
59 unsigned long reg1, reg2;
60 __asm__ __volatile(" bras %1,1f\n"
61 "0: " __DIAG44_INSN " 0,%4\n"
65 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
66 : "a" (&lp->lock), "i" (__DIAG44_OPERAND),
67 "m" (lp->lock) : "cc", "memory" );
68 #endif /* __s390x__ */
71 extern inline int _raw_spin_trylock(spinlock_t *lp)
76 __asm__ __volatile(" basr %1,0\n"
78 : "=d" (result), "=&d" (reg), "=m" (lp->lock)
79 : "a" (&lp->lock), "m" (lp->lock), "0" (0)
84 extern inline void _raw_spin_unlock(spinlock_t *lp)
88 __asm__ __volatile("cs %0,%3,0(%4)"
89 : "=d" (old), "=m" (lp->lock)
90 : "0" (lp->lock), "d" (0), "a" (lp)
95 * Read-write spinlocks, allowing multiple readers
96 * but only one writer.
98 * NOTE! it is quite common to have readers in interrupts
99 * but no interrupt writers. For those circumstances we
100 * can "mix" irq-safe locks - any writer needs to get a
101 * irq-safe write-lock, but readers can get non-irqsafe
105 volatile unsigned long lock;
106 volatile unsigned long owner_pc;
109 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
111 #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
113 #define rwlock_is_locked(x) ((x)->lock != 0)
116 #define _raw_read_lock(rw) \
117 asm volatile(" l 2,0(%1)\n" \
120 "1: la 2,0(2)\n" /* clear high (=write) bit */ \
121 " la 3,1(2)\n" /* one more reader */ \
122 " cs 2,3,0(%1)\n" /* try to write new value */ \
124 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
125 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
126 #else /* __s390x__ */
127 #define _raw_read_lock(rw) \
128 asm volatile(" lg 2,0(%1)\n" \
130 "0: " __DIAG44_INSN " 0,%2\n" \
131 "1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \
132 " la 3,1(2)\n" /* one more reader */ \
133 " csg 2,3,0(%1)\n" /* try to write new value */ \
135 : "=m" ((rw)->lock) \
136 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
137 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
138 #endif /* __s390x__ */
141 #define _raw_read_unlock(rw) \
142 asm volatile(" l 2,0(%1)\n" \
146 " ahi 3,-1\n" /* one less reader */ \
149 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
150 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
151 #else /* __s390x__ */
152 #define _raw_read_unlock(rw) \
153 asm volatile(" lg 2,0(%1)\n" \
155 "0: " __DIAG44_INSN " 0,%2\n" \
157 " bctgr 3,0\n" /* one less reader */ \
160 : "=m" ((rw)->lock) \
161 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
162 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
163 #endif /* __s390x__ */
166 #define _raw_write_lock(rw) \
167 asm volatile(" lhi 3,1\n" \
168 " sll 3,31\n" /* new lock value = 0x80000000 */ \
171 "1: slr 2,2\n" /* old lock value must be 0 */ \
174 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
175 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
176 #else /* __s390x__ */
177 #define _raw_write_lock(rw) \
178 asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
180 "0: " __DIAG44_INSN " 0,%2\n" \
181 "1: slgr 2,2\n" /* old lock value must be 0 */ \
184 : "=m" ((rw)->lock) \
185 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
186 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
187 #endif /* __s390x__ */
190 #define _raw_write_unlock(rw) \
191 asm volatile(" slr 3,3\n" /* new lock value = 0 */ \
195 " sll 2,31\n" /* old lock value must be 0x80000000 */ \
198 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
199 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
200 #else /* __s390x__ */
201 #define _raw_write_unlock(rw) \
202 asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \
204 "0: " __DIAG44_INSN " 0,%2\n" \
205 "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
208 : "=m" ((rw)->lock) \
209 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
210 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
211 #endif /* __s390x__ */
213 extern inline int _raw_write_trylock(rwlock_t *rw)
215 unsigned long result, reg;
217 __asm__ __volatile__(
222 #else /* __s390x__ */
224 "0: csg %0,%1,0(%3)\n"
225 #endif /* __s390x__ */
226 : "=d" (result), "=&d" (reg), "=m" (rw->lock)
227 : "a" (&rw->lock), "m" (rw->lock), "0" (0UL)
232 #endif /* __ASM_SPINLOCK_H */