2 * include/asm-s390/system.h
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Derived from "include/asm-i386/system.h"
11 #ifndef __ASM_SYSTEM_H
12 #define __ASM_SYSTEM_H
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <asm/types.h>
17 #include <asm/ptrace.h>
18 #include <asm/setup.h>
24 extern struct task_struct *__switch_to(void *, void *);
27 #define __FLAG_SHIFT 56
28 #else /* ! __s390x__ */
29 #define __FLAG_SHIFT 24
30 #endif /* ! __s390x__ */
32 static inline void save_fp_regs(s390_fp_regs *fpregs)
39 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
40 if (!MACHINE_HAS_IEEE)
56 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
59 static inline void restore_fp_regs(s390_fp_regs *fpregs)
66 : : "a" (fpregs), "m" (*fpregs) );
67 if (!MACHINE_HAS_IEEE)
83 : : "a" (fpregs), "m" (*fpregs) );
86 static inline void save_access_regs(unsigned int *acrs)
88 asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
91 static inline void restore_access_regs(unsigned int *acrs)
93 asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
96 #define switch_to(prev,next,last) do { \
99 save_fp_regs(&prev->thread.fp_regs); \
100 restore_fp_regs(&next->thread.fp_regs); \
101 save_access_regs(&prev->thread.acrs[0]); \
102 restore_access_regs(&next->thread.acrs[0]); \
103 prev = __switch_to(prev,next); \
106 #define prepare_arch_switch(rq, next) do { } while(0)
107 #define task_running(rq, p) ((rq)->curr == (p))
108 #define finish_arch_switch(rq, prev) do { \
109 set_fs(current->thread.mm_segment); \
110 spin_unlock_irq(&(rq)->lock); \
113 #define nop() __asm__ __volatile__ ("nop")
115 #define xchg(ptr,x) \
116 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
118 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
120 unsigned long addr, old;
125 addr = (unsigned long) ptr;
126 shift = (3 ^ (addr & 3)) << 3;
135 : "=&d" (old), "=m" (*(int *) addr)
136 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
137 "m" (*(int *) addr) : "memory", "cc", "0" );
141 addr = (unsigned long) ptr;
142 shift = (2 ^ (addr & 2)) << 3;
151 : "=&d" (old), "=m" (*(int *) addr)
152 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
153 "m" (*(int *) addr) : "memory", "cc", "0" );
159 "0: cs %0,%2,0(%3)\n"
161 : "=&d" (old), "=m" (*(int *) ptr)
162 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
170 "0: csg %0,%2,0(%3)\n"
172 : "=&d" (old), "=m" (*(long *) ptr)
173 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
177 #endif /* __s390x__ */
183 * Atomic compare and exchange. Compare OLD with MEM, if identical,
184 * store NEW in MEM. Return the initial value in MEM. Success is
185 * indicated by comparing RETURN with OLD.
188 #define __HAVE_ARCH_CMPXCHG 1
190 #define cmpxchg(ptr,o,n)\
191 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
192 (unsigned long)(n),sizeof(*(ptr))))
194 static inline unsigned long
195 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
197 unsigned long addr, prev, tmp;
202 addr = (unsigned long) ptr;
203 shift = (3 ^ (addr & 3)) << 3;
217 : "=&d" (prev), "=&d" (tmp)
218 : "d" (old << shift), "d" (new << shift), "a" (ptr),
219 "d" (~(255 << shift))
221 return prev >> shift;
223 addr = (unsigned long) ptr;
224 shift = (2 ^ (addr & 2)) << 3;
238 : "=&d" (prev), "=&d" (tmp)
239 : "d" (old << shift), "d" (new << shift), "a" (ptr),
240 "d" (~(65535 << shift))
242 return prev >> shift;
246 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
253 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
256 #endif /* __s390x__ */
262 * Force strict CPU ordering.
263 * And yes, this is required on UP too when we're talking
266 * This is very similar to the ppc eieio/sync instruction in that is
267 * does a checkpoint syncronisation & makes sure that
268 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
271 #define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
272 # define SYNC_OTHER_CORES(x) eieio()
274 #define rmb() eieio()
275 #define wmb() eieio()
276 #define read_barrier_depends() do { } while(0)
277 #define smp_mb() mb()
278 #define smp_rmb() rmb()
279 #define smp_wmb() wmb()
280 #define smp_read_barrier_depends() read_barrier_depends()
281 #define smp_mb__before_clear_bit() smp_mb()
282 #define smp_mb__after_clear_bit() smp_mb()
285 #define set_mb(var, value) do { var = value; mb(); } while (0)
286 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
288 /* interrupt control.. */
289 #define local_irq_enable() ({ \
290 unsigned long __dummy; \
291 __asm__ __volatile__ ( \
293 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
296 #define local_irq_disable() ({ \
297 unsigned long __flags; \
298 __asm__ __volatile__ ( \
299 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
303 #define local_save_flags(x) \
304 __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
306 #define local_irq_restore(x) \
307 __asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory")
309 #define irqs_disabled() \
311 unsigned long flags; \
312 local_save_flags(flags); \
313 !((flags >> __FLAG_SHIFT) & 3); \
318 #define __load_psw(psw) \
319 __asm__ __volatile__("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
321 #define __ctl_load(array, low, high) ({ \
322 __asm__ __volatile__ ( \
324 " lctlg 0,0,0(%0)\n" \
326 : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
329 #define __ctl_store(array, low, high) ({ \
330 __asm__ __volatile__ ( \
332 " stctg 0,0,0(%1)\n" \
334 : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
337 #define __ctl_set_bit(cr, bit) ({ \
339 __asm__ __volatile__ ( \
340 " bras 1,0f\n" /* skip indirect insns */ \
341 " stctg 0,0,0(%1)\n" \
342 " lctlg 0,0,0(%1)\n" \
343 "0: ex %2,0(1)\n" /* execute stctl */ \
345 " ogr 0,%3\n" /* set the bit */ \
347 "1: ex %2,6(1)" /* execute lctl */ \
349 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
350 "a" (cr*17), "a" (1L<<(bit)) \
351 : "cc", "0", "1" ); \
354 #define __ctl_clear_bit(cr, bit) ({ \
356 __asm__ __volatile__ ( \
357 " bras 1,0f\n" /* skip indirect insns */ \
358 " stctg 0,0,0(%1)\n" \
359 " lctlg 0,0,0(%1)\n" \
360 "0: ex %2,0(1)\n" /* execute stctl */ \
362 " ngr 0,%3\n" /* set the bit */ \
364 "1: ex %2,6(1)" /* execute lctl */ \
366 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
367 "a" (cr*17), "a" (~(1L<<(bit))) \
368 : "cc", "0", "1" ); \
371 #else /* __s390x__ */
373 #define __load_psw(psw) \
374 __asm__ __volatile__("lpsw 0(%0)" : : "a" (&psw) : "cc" );
376 #define __ctl_load(array, low, high) ({ \
377 __asm__ __volatile__ ( \
379 " lctl 0,0,0(%0)\n" \
381 : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
384 #define __ctl_store(array, low, high) ({ \
385 __asm__ __volatile__ ( \
387 " stctl 0,0,0(%1)\n" \
389 : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
392 #define __ctl_set_bit(cr, bit) ({ \
394 __asm__ __volatile__ ( \
395 " bras 1,0f\n" /* skip indirect insns */ \
396 " stctl 0,0,0(%1)\n" \
397 " lctl 0,0,0(%1)\n" \
398 "0: ex %2,0(1)\n" /* execute stctl */ \
400 " or 0,%3\n" /* set the bit */ \
402 "1: ex %2,4(1)" /* execute lctl */ \
404 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
405 "a" (cr*17), "a" (1<<(bit)) \
406 : "cc", "0", "1" ); \
409 #define __ctl_clear_bit(cr, bit) ({ \
411 __asm__ __volatile__ ( \
412 " bras 1,0f\n" /* skip indirect insns */ \
413 " stctl 0,0,0(%1)\n" \
414 " lctl 0,0,0(%1)\n" \
415 "0: ex %2,0(1)\n" /* execute stctl */ \
417 " nr 0,%3\n" /* set the bit */ \
419 "1: ex %2,4(1)" /* execute lctl */ \
421 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
422 "a" (cr*17), "a" (~(1<<(bit))) \
423 : "cc", "0", "1" ); \
425 #endif /* __s390x__ */
427 /* For spinlocks etc */
428 #define local_irq_save(x) ((x) = local_irq_disable())
432 extern void smp_ctl_set_bit(int cr, int bit);
433 extern void smp_ctl_clear_bit(int cr, int bit);
434 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
435 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
439 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
440 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
442 #endif /* CONFIG_SMP */
444 extern void (*_machine_restart)(char *command);
445 extern void (*_machine_halt)(void);
446 extern void (*_machine_power_off)(void);
448 #endif /* __KERNEL__ */