6 * linux/include/asm-sh/irq.h
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
14 #include <linux/config.h>
15 #include <asm/machvec.h>
16 #include <asm/ptrace.h> /* for pt_regs */
18 #if defined(CONFIG_CPU_SH3)
19 #define INTC_IPRA 0xfffffee2UL
20 #define INTC_IPRB 0xfffffee4UL
21 #elif defined(CONFIG_CPU_SH4)
22 #define INTC_IPRA 0xffd00004UL
23 #define INTC_IPRB 0xffd00008UL
24 #define INTC_IPRC 0xffd0000cUL
25 #define INTC_IPRD 0xffd00010UL
29 #define TIMER_IPR_ADDR INTC_IPRA
30 #define TIMER_IPR_POS 3
31 #define TIMER_PRIORITY 2
34 #define TIMER1_IPR_ADDR INTC_IPRA
35 #define TIMER1_IPR_POS 2
36 #define TIMER1_PRIORITY 4
39 #define RTC_IPR_ADDR INTC_IPRA
41 #define RTC_PRIORITY TIMER_PRIORITY
43 #if defined(CONFIG_CPU_SH3)
48 #define DMA_IPR_ADDR INTC_IPRE
50 #define DMA_PRIORITY 7
51 #elif defined(CONFIG_CPU_SH4)
56 #define DMTE4_IRQ 44 /* 7751R only */
57 #define DMTE5_IRQ 45 /* 7751R only */
58 #define DMTE6_IRQ 46 /* 7751R only */
59 #define DMTE7_IRQ 47 /* 7751R only */
61 #define DMA_IPR_ADDR INTC_IPRC
63 #define DMA_PRIORITY 7
66 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
67 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
68 defined (CONFIG_CPU_SUBTYPE_SH7751)
69 #define SCI_ERI_IRQ 23
70 #define SCI_RXI_IRQ 24
71 #define SCI_TXI_IRQ 25
72 #define SCI_IPR_ADDR INTC_IPRB
74 #define SCI_PRIORITY 3
77 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
78 #define SCIF_ERI_IRQ 56
79 #define SCIF_RXI_IRQ 57
80 #define SCIF_BRI_IRQ 58
81 #define SCIF_TXI_IRQ 59
82 #define SCIF_IPR_ADDR INTC_IPRE
83 #define SCIF_IPR_POS 1
84 #define SCIF_PRIORITY 3
86 #define IRDA_ERI_IRQ 52
87 #define IRDA_RXI_IRQ 53
88 #define IRDA_BRI_IRQ 54
89 #define IRDA_TXI_IRQ 55
90 #define IRDA_IPR_ADDR INTC_IPRE
91 #define IRDA_IPR_POS 2
92 #define IRDA_PRIORITY 3
93 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
94 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
95 #define SCIF_ERI_IRQ 40
96 #define SCIF_RXI_IRQ 41
97 #define SCIF_BRI_IRQ 42
98 #define SCIF_TXI_IRQ 43
99 #define SCIF_IPR_ADDR INTC_IPRC
100 #define SCIF_IPR_POS 1
101 #define SCIF_PRIORITY 3
102 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
103 #define SCIF1_ERI_IRQ 23
104 #define SCIF1_RXI_IRQ 24
105 #define SCIF1_BRI_IRQ 25
106 #define SCIF1_TXI_IRQ 26
107 #define SCIF1_IPR_ADDR INTC_IPRB
108 #define SCIF1_IPR_POS 1
109 #define SCIF1_PRIORITY 3
113 /* NR_IRQS is made from three components:
114 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
115 * 2. PINT_NR_IRQS - number of PINT interrupts
116 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
119 /* 1. ONCHIP_NR_IRQS */
120 #ifdef CONFIG_SH_GENERIC
121 # define ONCHIP_NR_IRQS 144
123 # if defined(CONFIG_CPU_SUBTYPE_SH7604)
124 # define ONCHIP_NR_IRQS 24 // Actually 21
125 # elif defined(CONFIG_CPU_SUBTYPE_SH7707)
126 # define ONCHIP_NR_IRQS 64
127 # define PINT_NR_IRQS 16
128 # elif defined(CONFIG_CPU_SUBTYPE_SH7708)
129 # define ONCHIP_NR_IRQS 32
130 # elif defined(CONFIG_CPU_SUBTYPE_SH7709)
131 # define ONCHIP_NR_IRQS 64 // Actually 61
132 # define PINT_NR_IRQS 16
133 # elif defined(CONFIG_CPU_SUBTYPE_SH7750)
134 # define ONCHIP_NR_IRQS 48 // Actually 44
135 # elif defined(CONFIG_CPU_SUBTYPE_SH7751)
136 # define ONCHIP_NR_IRQS 72
137 # elif defined(CONFIG_CPU_SUBTYPE_SH7760)
138 # define ONCHIP_NR_IRQS 110
139 # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
140 # define ONCHIP_NR_IRQS 144
144 /* 2. PINT_NR_IRQS */
145 #ifdef CONFIG_SH_GENERIC
146 # define PINT_NR_IRQS 16
148 # ifndef PINT_NR_IRQS
149 # define PINT_NR_IRQS 0
154 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
157 /* 3. OFFCHIP_NR_IRQS */
158 #ifdef CONFIG_SH_GENERIC
159 # define OFFCHIP_NR_IRQS 16
161 # if defined(CONFIG_HD64461)
162 # define OFFCHIP_NR_IRQS 18
163 # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
164 # define OFFCHIP_NR_IRQS 48
165 # elif defined(CONFIG_HD64465)
166 # define OFFCHIP_NR_IRQS 16
167 # elif defined (CONFIG_SH_EC3104)
168 # define OFFCHIP_NR_IRQS 16
169 # elif defined (CONFIG_SH_DREAMCAST)
170 # define OFFCHIP_NR_IRQS 96
172 # define OFFCHIP_NR_IRQS 0
176 #if OFFCHIP_NR_IRQS > 0
177 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
181 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
183 /* In a generic kernel, NR_IRQS is an upper bound, and we should use
184 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
186 #ifdef CONFIG_SH_GENERIC
187 # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
189 # define ACTUAL_NR_IRQS NR_IRQS
193 extern void disable_irq(unsigned int);
194 extern void disable_irq_nosync(unsigned int);
195 extern void enable_irq(unsigned int);
198 * Simple Mask Register Support
200 extern void make_maskreg_irq(unsigned int irq);
201 extern unsigned short *irq_mask_register;
204 * Function for "on chip support modules".
206 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
207 int pos, int priority);
208 extern void make_imask_irq(unsigned int irq);
210 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
211 #define INTC_IPRA 0xfffffee2UL
212 #define INTC_IPRB 0xfffffe60UL
214 #define INTC_VCRA 0xfffffe62UL
215 #define INTC_VCRB 0xfffffe64UL
216 #define INTC_VCRC 0xfffffe66UL
217 #define INTC_VCRD 0xfffffe68UL
219 #define INTC_VCRWDT 0xfffffee4UL
220 #define INTC_VCRDIV 0xffffff0cUL
221 #define INTC_VCRDMA0 0xffffffa0UL
222 #define INTC_VCRDMA1 0xffffffa8UL
224 #define INTC_ICR 0xfffffee0UL
225 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
226 #define INTC_IRR0 0xa4000004UL
227 #define INTC_IRR1 0xa4000006UL
228 #define INTC_IRR2 0xa4000008UL
230 #define INTC_ICR0 0xfffffee0UL
231 #define INTC_ICR1 0xa4000010UL
232 #define INTC_ICR2 0xa4000012UL
233 #define INTC_INTER 0xa4000014UL
235 #define INTC_IPRC 0xa4000016UL
236 #define INTC_IPRD 0xa4000018UL
237 #define INTC_IPRE 0xa400001aUL
238 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
239 #define INTC_IPRF 0xa400001cUL
242 #define PORT_PACR 0xa4000100UL
243 #define PORT_PBCR 0xa4000102UL
244 #define PORT_PCCR 0xa4000104UL
245 #define PORT_PFCR 0xa400010aUL
246 #define PORT_PADR 0xa4000120UL
247 #define PORT_PBDR 0xa4000122UL
248 #define PORT_PCDR 0xa4000124UL
249 #define PORT_PFDR 0xa400012aUL
258 #define IRQ0_IPR_ADDR INTC_IPRC
259 #define IRQ1_IPR_ADDR INTC_IPRC
260 #define IRQ2_IPR_ADDR INTC_IPRC
261 #define IRQ3_IPR_ADDR INTC_IPRC
262 #define IRQ4_IPR_ADDR INTC_IPRD
263 #define IRQ5_IPR_ADDR INTC_IPRD
265 #define IRQ0_IPR_POS 0
266 #define IRQ1_IPR_POS 1
267 #define IRQ2_IPR_POS 2
268 #define IRQ3_IPR_POS 3
269 #define IRQ4_IPR_POS 0
270 #define IRQ5_IPR_POS 1
272 #define IRQ0_PRIORITY 1
273 #define IRQ1_PRIORITY 1
274 #define IRQ2_PRIORITY 1
275 #define IRQ3_PRIORITY 1
276 #define IRQ4_PRIORITY 1
277 #define IRQ5_PRIORITY 1
282 #define PINT0_IPR_ADDR INTC_IPRD
283 #define PINT8_IPR_ADDR INTC_IPRD
285 #define PINT0_IPR_POS 3
286 #define PINT8_IPR_POS 2
287 #define PINT0_PRIORITY 2
288 #define PINT8_PRIORITY 2
290 extern int ipr_irq_demux(int irq);
291 #define __irq_demux(irq) ipr_irq_demux(irq)
294 #define __irq_demux(irq) irq
295 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
297 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
298 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
299 #define INTC_ICR 0xffd00000
300 #define INTC_ICR_NMIL (1<<15)
301 #define INTC_ICR_MAI (1<<14)
302 #define INTC_ICR_NMIB (1<<9)
303 #define INTC_ICR_NMIE (1<<8)
304 #define INTC_ICR_IRLM (1<<7)
307 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
308 #define INTC2_FIRST_IRQ 64
309 #define NR_INTC2_IRQS 25
311 #define INTC2_BASE0 0xfe080000
312 #define INTC2_INTC2MODE (INTC2_BASE0+0x80)
314 #define INTC2_INTPRI_OFFSET 0x00
315 #define INTC2_INTREQ_OFFSET 0x20
316 #define INTC2_INTMSK_OFFSET 0x40
317 #define INTC2_INTMSKCLR_OFFSET 0x60
319 extern void make_intc2_irq(unsigned int irq,unsigned int addr,
320 unsigned int group,int pos,int priority);
324 static inline int generic_irq_demux(int irq)
329 #define irq_canonicalize(irq) (irq)
330 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
334 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
336 #endif /* __ASM_SH_IRQ_H */