include/asm-x86_64/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define                 APIC_ID_MASK            (0xFFu<<24)
  15 #define                 GET_APIC_ID(x)          (((x)>>24)&0xFFu)
  16 #define                 SET_APIC_ID(x)          (((x)<<24))
  17 #define         APIC_LVR        0x30
  18 #define                 APIC_LVR_MASK           0xFF00FF
  19 #define                 GET_APIC_VERSION(x)     ((x)&0xFFu)
  20 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFFu)
  21 #define                 APIC_INTEGRATED(x)      ((x)&0xF0u)
  22 #define         APIC_TASKPRI    0x80
  23 #define                 APIC_TPRI_MASK          0xFFu
  24 #define         APIC_ARBPRI     0x90
  25 #define                 APIC_ARBPRI_MASK        0xFFu
  26 #define         APIC_PROCPRI    0xA0
  27 #define         APIC_EOI        0xB0
  28 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  29 #define         APIC_RRR        0xC0
  30 #define         APIC_LDR        0xD0
  31 #define                 APIC_LDR_MASK           (0xFFu<<24)
  32 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFFu)
  33 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  34 #define                 APIC_ALL_CPUS           0xFFu
  35 #define         APIC_DFR        0xE0
  36 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  37 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  38 #define         APIC_SPIV       0xF0
  39 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  40 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  41 #define         APIC_ISR        0x100
  42 #define         APIC_TMR        0x180
  43 #define         APIC_IRR        0x200
  44 #define         APIC_ESR        0x280
  45 #define                 APIC_ESR_SEND_CS        0x00001
  46 #define                 APIC_ESR_RECV_CS        0x00002
  47 #define                 APIC_ESR_SEND_ACC       0x00004
  48 #define                 APIC_ESR_RECV_ACC       0x00008
  49 #define                 APIC_ESR_SENDILL        0x00020
  50 #define                 APIC_ESR_RECVILL        0x00040
  51 #define                 APIC_ESR_ILLREGA        0x00080
  52 #define         APIC_ICR        0x300
  53 #define                 APIC_DEST_SELF          0x40000
  54 #define                 APIC_DEST_ALLINC        0x80000
  55 #define                 APIC_DEST_ALLBUT        0xC0000
  56 #define                 APIC_ICR_RR_MASK        0x30000
  57 #define                 APIC_ICR_RR_INVALID     0x00000
  58 #define                 APIC_ICR_RR_INPROG      0x10000
  59 #define                 APIC_ICR_RR_VALID       0x20000
  60 #define                 APIC_INT_LEVELTRIG      0x08000
  61 #define                 APIC_INT_ASSERT         0x04000
  62 #define                 APIC_ICR_BUSY           0x01000
  63 #define                 APIC_DEST_LOGICAL       0x00800
  64 #define                 APIC_DEST_PHYSICAL      0x00000
  65 #define                 APIC_DM_FIXED           0x00000
  66 #define                 APIC_DM_LOWEST          0x00100
  67 #define                 APIC_DM_SMI             0x00200
  68 #define                 APIC_DM_REMRD           0x00300
  69 #define                 APIC_DM_NMI             0x00400
  70 #define                 APIC_DM_INIT            0x00500
  71 #define                 APIC_DM_STARTUP         0x00600
  72 #define                 APIC_DM_EXTINT          0x00700
  73 #define                 APIC_VECTOR_MASK        0x000FF
  74 #define         APIC_ICR2       0x310
  75 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  76 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  77 #define         APIC_LVTT       0x320
  78 #define         APIC_LVTTHMR    0x330
  79 #define         APIC_LVTPC      0x340
  80 #define         APIC_LVT0       0x350
  81 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  82 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  83 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  84 #define                 APIC_TIMER_BASE_CLKIN           0x0
  85 #define                 APIC_TIMER_BASE_TMBASE          0x1
  86 #define                 APIC_TIMER_BASE_DIV             0x2
  87 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  88 #define                 APIC_LVT_MASKED                 (1<<16)
  89 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  90 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  91 #define                 APIC_INPUT_POLARITY             (1<<13)
  92 #define                 APIC_SEND_PENDING               (1<<12)
  93 #define                 APIC_MODE_MASK                  0x700
  94 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  95 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  96 #define                         APIC_MODE_FIXED         0x0
  97 #define                         APIC_MODE_NMI           0x4
  98 #define                         APIC_MODE_EXTINT        0x7
  99 #define         APIC_LVT1       0x360
 100 #define         APIC_LVTERR     0x370
 101 #define         APIC_TMICT      0x380
 102 #define         APIC_TMCCT      0x390
 103 #define         APIC_TDCR       0x3E0
 104 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 105 #define                 APIC_TDR_DIV_1          0xB
 106 #define                 APIC_TDR_DIV_2          0x0
 107 #define                 APIC_TDR_DIV_4          0x1
 108 #define                 APIC_TDR_DIV_8          0x2
 109 #define                 APIC_TDR_DIV_16         0x3
 110 #define                 APIC_TDR_DIV_32         0x8
 111 #define                 APIC_TDR_DIV_64         0x9
 112 #define                 APIC_TDR_DIV_128        0xA
 113
 114 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 115
 116 #define MAX_IO_APICS 128
 117 #define MAX_LOCAL_APIC 256
 118
 119 /*
 120  * All x86-64 systems are xAPIC compatible.
 121  * In the following, "apicid" is a physical APIC ID.
 122  */
 123 #define XAPIC_DEST_CPUS_SHIFT   4
 124 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 125 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 126 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 127 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 128 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 129 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 130
 131 /*
 132  * the local APIC register structure, memory mapped. Not terribly well
 133  * tested, but we might eventually use this one in the future - the
 134  * problem why we cannot use it right now is the P5 APIC, it has an
 135  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 136  */
 137 #define u32 unsigned int
 138
 139 #define lapic ((volatile struct local_apic *)APIC_BASE)
 140
 141 struct local_apic {
 142
 143 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 144
 145 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 146
 147 /*020*/ struct { /* APIC ID Register */
 148                 u32   __reserved_1      : 24,
 149                         phys_apic_id    :  4,
 150                         __reserved_2    :  4;
 151                 u32 __reserved[3];
 152         } id;
 153
 154 /*030*/ const
 155         struct { /* APIC Version Register */
 156                 u32   version           :  8,
 157                         __reserved_1    :  8,
 158                         max_lvt         :  8,
 159                         __reserved_2    :  8;
 160                 u32 __reserved[3];
 161         } version;
 162
 163 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 164
 165 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 166
 167 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 168
 169 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 170
 171 /*080*/ struct { /* Task Priority Register */
 172                 u32   priority  :  8,
 173                         __reserved_1    : 24;
 174                 u32 __reserved_2[3];
 175         } tpr;
 176
 177 /*090*/ const
 178         struct { /* Arbitration Priority Register */
 179                 u32   priority  :  8,
 180                         __reserved_1    : 24;
 181                 u32 __reserved_2[3];
 182         } apr;
 183
 184 /*0A0*/ const
 185         struct { /* Processor Priority Register */
 186                 u32   priority  :  8,
 187                         __reserved_1    : 24;
 188                 u32 __reserved_2[3];
 189         } ppr;
 190
 191 /*0B0*/ struct { /* End Of Interrupt Register */
 192                 u32   eoi;
 193                 u32 __reserved[3];
 194         } eoi;
 195
 196 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 197
 198 /*0D0*/ struct { /* Logical Destination Register */
 199                 u32   __reserved_1      : 24,
 200                         logical_dest    :  8;
 201                 u32 __reserved_2[3];
 202         } ldr;
 203
 204 /*0E0*/ struct { /* Destination Format Register */
 205                 u32   __reserved_1      : 28,
 206                         model           :  4;
 207                 u32 __reserved_2[3];
 208         } dfr;
 209
 210 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 211                 u32     spurious_vector :  8,
 212                         apic_enabled    :  1,
 213                         focus_cpu       :  1,
 214                         __reserved_2    : 22;
 215                 u32 __reserved_3[3];
 216         } svr;
 217
 218 /*100*/ struct { /* In Service Register */
 219 /*170*/         u32 bitfield;
 220                 u32 __reserved[3];
 221         } isr [8];
 222
 223 /*180*/ struct { /* Trigger Mode Register */
 224 /*1F0*/         u32 bitfield;
 225                 u32 __reserved[3];
 226         } tmr [8];
 227
 228 /*200*/ struct { /* Interrupt Request Register */
 229 /*270*/         u32 bitfield;
 230                 u32 __reserved[3];
 231         } irr [8];
 232
 233 /*280*/ union { /* Error Status Register */
 234                 struct {
 235                         u32   send_cs_error                     :  1,
 236                                 receive_cs_error                :  1,
 237                                 send_accept_error               :  1,
 238                                 receive_accept_error            :  1,
 239                                 __reserved_1                    :  1,
 240                                 send_illegal_vector             :  1,
 241                                 receive_illegal_vector          :  1,
 242                                 illegal_register_address        :  1,
 243                                 __reserved_2                    : 24;
 244                         u32 __reserved_3[3];
 245                 } error_bits;
 246                 struct {
 247                         u32 errors;
 248                         u32 __reserved_3[3];
 249                 } all_errors;
 250         } esr;
 251
 252 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 253
 254 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 255
 256 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 257
 258 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 259
 260 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 261
 262 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 263
 264 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 265
 266 /*300*/ struct { /* Interrupt Command Register 1 */
 267                 u32   vector                    :  8,
 268                         delivery_mode           :  3,
 269                         destination_mode        :  1,
 270                         delivery_status         :  1,
 271                         __reserved_1            :  1,
 272                         level                   :  1,
 273                         trigger                 :  1,
 274                         __reserved_2            :  2,
 275                         shorthand               :  2,
 276                         __reserved_3            :  12;
 277                 u32 __reserved_4[3];
 278         } icr1;
 279
 280 /*310*/ struct { /* Interrupt Command Register 2 */
 281                 union {
 282                         u32   __reserved_1      : 24,
 283                                 phys_dest       :  4,
 284                                 __reserved_2    :  4;
 285                         u32   __reserved_3      : 24,
 286                                 logical_dest    :  8;
 287                 } dest;
 288                 u32 __reserved_4[3];
 289         } icr2;
 290
 291 /*320*/ struct { /* LVT - Timer */
 292                 u32   vector            :  8,
 293                         __reserved_1    :  4,
 294                         delivery_status :  1,
 295                         __reserved_2    :  3,
 296                         mask            :  1,
 297                         timer_mode      :  1,
 298                         __reserved_3    : 14;
 299                 u32 __reserved_4[3];
 300         } lvt_timer;
 301
 302 /*330*/ struct { /* LVT - Thermal Sensor */
 303                 u32  vector             :  8,
 304                         delivery_mode   :  3,
 305                         __reserved_1    :  1,
 306                         delivery_status :  1,
 307                         __reserved_2    :  3,
 308                         mask            :  1,
 309                         __reserved_3    : 15;
 310                 u32 __reserved_4[3];
 311         } lvt_thermal;
 312
 313 /*340*/ struct { /* LVT - Performance Counter */
 314                 u32   vector            :  8,
 315                         delivery_mode   :  3,
 316                         __reserved_1    :  1,
 317                         delivery_status :  1,
 318                         __reserved_2    :  3,
 319                         mask            :  1,
 320                         __reserved_3    : 15;
 321                 u32 __reserved_4[3];
 322         } lvt_pc;
 323
 324 /*350*/ struct { /* LVT - LINT0 */
 325                 u32   vector            :  8,
 326                         delivery_mode   :  3,
 327                         __reserved_1    :  1,
 328                         delivery_status :  1,
 329                         polarity        :  1,
 330                         remote_irr      :  1,
 331                         trigger         :  1,
 332                         mask            :  1,
 333                         __reserved_2    : 15;
 334                 u32 __reserved_3[3];
 335         } lvt_lint0;
 336
 337 /*360*/ struct { /* LVT - LINT1 */
 338                 u32   vector            :  8,
 339                         delivery_mode   :  3,
 340                         __reserved_1    :  1,
 341                         delivery_status :  1,
 342                         polarity        :  1,
 343                         remote_irr      :  1,
 344                         trigger         :  1,
 345                         mask            :  1,
 346                         __reserved_2    : 15;
 347                 u32 __reserved_3[3];
 348         } lvt_lint1;
 349
 350 /*370*/ struct { /* LVT - Error */
 351                 u32   vector            :  8,
 352                         __reserved_1    :  4,
 353                         delivery_status :  1,
 354                         __reserved_2    :  3,
 355                         mask            :  1,
 356                         __reserved_3    : 15;
 357                 u32 __reserved_4[3];
 358         } lvt_error;
 359
 360 /*380*/ struct { /* Timer Initial Count Register */
 361                 u32   initial_count;
 362                 u32 __reserved_2[3];
 363         } timer_icr;
 364
 365 /*390*/ const
 366         struct { /* Timer Current Count Register */
 367                 u32   curr_count;
 368                 u32 __reserved_2[3];
 369         } timer_ccr;
 370
 371 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 372
 373 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 374
 375 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 376
 377 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 378
 379 /*3E0*/ struct { /* Timer Divide Configuration Register */
 380                 u32   divisor           :  4,
 381                         __reserved_1    : 28;
 382                 u32 __reserved_2[3];
 383         } timer_dcr;
 384
 385 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 386
 387 } __attribute__ ((packed));
 388
 389 #undef u32
 390
 391 #define BAD_APICID 0xFFu
 392
 393 #endif