1 #ifndef __X86_64_MMU_CONTEXT_H
2 #define __X86_64_MMU_CONTEXT_H
5 #include <asm/atomic.h>
6 #include <asm/pgalloc.h>
9 #include <asm/pgtable.h>
10 #include <asm/tlbflush.h>
13 * possibly do the LDT unload here?
15 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
16 void destroy_context(struct mm_struct *mm);
18 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
20 #if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
21 if (read_pda(mmu_state) == TLBSTATE_OK)
22 write_pda(mmu_state, TLBSTATE_LAZY);
26 #define prepare_arch_switch(next) __prepare_arch_switch()
28 static inline void __prepare_arch_switch(void)
31 * Save away %es, %ds, %fs and %gs. Must happen before reload
32 * of cr3/ldt (i.e., not in __switch_to).
34 __asm__ __volatile__ (
35 "mov %%es,%0 ; mov %%ds,%1 ; mov %%fs,%2 ; mov %%gs,%3"
36 : "=m" (current->thread.es),
37 "=m" (current->thread.ds),
38 "=m" (current->thread.fsindex),
39 "=m" (current->thread.gsindex) );
41 if (current->thread.ds)
42 __asm__ __volatile__ ( "movl %0,%%ds" : : "r" (0) );
44 if (current->thread.es)
45 __asm__ __volatile__ ( "movl %0,%%es" : : "r" (0) );
47 if (current->thread.fsindex) {
48 __asm__ __volatile__ ( "movl %0,%%fs" : : "r" (0) );
49 current->thread.fs = 0;
52 if (current->thread.gsindex) {
54 current->thread.gs = 0;
58 extern void mm_pin(struct mm_struct *mm);
59 extern void mm_unpin(struct mm_struct *mm);
60 void mm_pin_all(void);
62 static inline void load_cr3(pgd_t *pgd)
64 asm volatile("movq %0,%%cr3" :: "r" (phys_to_machine(__pa(pgd))) :
68 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
69 struct task_struct *tsk)
71 unsigned cpu = smp_processor_id();
72 struct mmuext_op _op[3], *op = _op;
74 if (likely(prev != next)) {
75 BUG_ON(!next->context.pinned);
77 /* stop flush ipis for the previous mm */
78 cpu_clear(cpu, prev->cpu_vm_mask);
79 #if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
80 write_pda(mmu_state, TLBSTATE_OK);
81 write_pda(active_mm, next);
83 cpu_set(cpu, next->cpu_vm_mask);
85 /* load_cr3(next->pgd) */
86 op->cmd = MMUEXT_NEW_BASEPTR;
87 op->arg1.mfn = pfn_to_mfn(__pa(next->pgd) >> PAGE_SHIFT);
90 /* xen_new_user_pt(__pa(__user_pgd(next->pgd))) */
91 op->cmd = MMUEXT_NEW_USER_BASEPTR;
92 op->arg1.mfn = pfn_to_mfn(__pa(__user_pgd(next->pgd)) >> PAGE_SHIFT);
95 if (unlikely(next->context.ldt != prev->context.ldt)) {
96 /* load_LDT_nolock(&next->context, cpu) */
97 op->cmd = MMUEXT_SET_LDT;
98 op->arg1.linear_addr = (unsigned long)next->context.ldt;
99 op->arg2.nr_ents = next->context.size;
103 BUG_ON(HYPERVISOR_mmuext_op(_op, op-_op, NULL, DOMID_SELF));
105 #if defined(CONFIG_SMP) && !defined(CONFIG_XEN)
107 write_pda(mmu_state, TLBSTATE_OK);
108 if (read_pda(active_mm) != next)
110 if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
111 /* We were in lazy tlb mode and leave_mm disabled
112 * tlb flush IPI delivery. We must reload CR3
113 * to make sure to use no freed page tables.
116 xen_new_user_pt(__pa(__user_pgd(next->pgd)));
117 load_LDT_nolock(&next->context, cpu);
123 #define deactivate_mm(tsk,mm) do { \
125 asm volatile("movl %0,%%fs"::"r"(0)); \
128 static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
130 if (!next->context.pinned)
132 switch_mm(prev, next, NULL);