2 * include/asm-x86_64/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_X86_64_PROCESSOR_H
8 #define __ASM_X86_64_PROCESSOR_H
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
15 #include <linux/config.h>
16 #include <linux/threads.h>
18 #include <asm/current.h>
19 #include <asm/system.h>
20 #include <asm/mmsegment.h>
21 #include <asm/percpu.h>
22 #include <linux/personality.h>
24 #define TF_MASK 0x00000100
25 #define IF_MASK 0x00000200
26 #define IOPL_MASK 0x00003000
27 #define NT_MASK 0x00004000
28 #define VM_MASK 0x00020000
29 #define AC_MASK 0x00040000
30 #define VIF_MASK 0x00080000 /* virtual interrupt flag */
31 #define VIP_MASK 0x00100000 /* virtual interrupt pending */
32 #define ID_MASK 0x00200000
34 #define desc_empty(desc) \
35 (!((desc)->a + (desc)->b))
37 #define desc_equal(desc1, desc2) \
38 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
41 * Default implementation of macro that returns current
42 * instruction pointer ("program counter").
44 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
47 * CPU type and hardware bug flags. Kept separately for each CPU.
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
56 __u32 x86_capability[NCAPINTS];
57 char x86_vendor_id[16];
58 char x86_model_id[64];
59 int x86_cache_size; /* in KB */
61 int x86_cache_alignment;
62 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
63 __u8 x86_virt_bits, x86_phys_bits;
67 __u32 x86_cpuid_level; /* Max CPUID function supported */
68 unsigned long loops_per_jiffy;
69 } ____cacheline_aligned;
71 #define X86_VENDOR_INTEL 0
72 #define X86_VENDOR_CYRIX 1
73 #define X86_VENDOR_AMD 2
74 #define X86_VENDOR_UMC 3
75 #define X86_VENDOR_NEXGEN 4
76 #define X86_VENDOR_CENTAUR 5
77 #define X86_VENDOR_RISE 6
78 #define X86_VENDOR_TRANSMETA 7
79 #define X86_VENDOR_NUM 8
80 #define X86_VENDOR_UNKNOWN 0xff
83 extern struct cpuinfo_x86 cpu_data[];
84 #define current_cpu_data cpu_data[smp_processor_id()]
86 #define cpu_data (&boot_cpu_data)
87 #define current_cpu_data boot_cpu_data
90 extern char ignore_irq13;
92 extern void identify_cpu(struct cpuinfo_x86 *);
93 extern void print_cpu_info(struct cpuinfo_x86 *);
94 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
95 extern void dodgy_tsc(void);
100 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
101 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
102 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
103 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
104 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
105 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
106 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
107 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
108 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
109 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
110 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
111 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
112 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
113 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
114 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
115 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
116 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
119 * Intel CPU features in CR4
121 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
122 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
123 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
124 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
125 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
126 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
127 #define X86_CR4_MCE 0x0040 /* Machine check enable */
128 #define X86_CR4_PGE 0x0080 /* enable global pages */
129 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
130 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
131 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
134 * Save the cr4 feature set we're using (ie
135 * Pentium 4MB enable and PPro Global page
136 * enable), so that any CPU's that boot up
137 * after us can get the correct flags.
139 extern unsigned long mmu_cr4_features;
141 static inline void set_in_cr4 (unsigned long mask)
143 mmu_cr4_features |= mask;
146 case X86_CR4_OSXMMEXCPT:
150 const char *msg = "Xen unsupported cr4 update\n";
151 (void)HYPERVISOR_console_io(
152 CONSOLEIO_write, __builtin_strlen(msg),
159 #define load_cr3(pgdir) do { \
160 xen_pt_switch(__pa(pgdir)); \
161 per_cpu(cur_pgd, smp_processor_id()) = pgdir; \
162 } while (/* CONSTCOND */0)
168 #define MCA_bus__is_a_macro
172 * User space process size. 47bits.
174 #define TASK_SIZE (0x800000000000UL)
176 /* This decides where the kernel will search for a free chunk of vm
177 * space during mmap's.
179 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
180 #define TASK_UNMAPPED_32 PAGE_ALIGN(IA32_PAGE_OFFSET/3)
181 #define TASK_UNMAPPED_64 PAGE_ALIGN(TASK_SIZE/3)
182 #define TASK_UNMAPPED_BASE \
183 (test_thread_flag(TIF_IA32) ? TASK_UNMAPPED_32 : TASK_UNMAPPED_64)
188 #define IO_BITMAP_BITS 65536
189 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
190 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
191 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
192 #define INVALID_IO_BITMAP_OFFSET 0x8000
194 struct i387_fxsave_struct {
203 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
204 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
206 } __attribute__ ((aligned (16)));
209 struct i387_fxsave_struct fxsave;
224 * The extra 1 is there because the CPU will access an
225 * additional byte beyond the end of the IO permission
226 * bitmap. The extra byte must be all 1 bits, and must
227 * be within the limit. Thus we have:
229 * 128 bytes, the bitmap itself, for ports 0..0x3ff
230 * 8 bytes, for an extra "long" of ~0UL
232 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
233 } __attribute__((packed)) ____cacheline_aligned;
235 extern struct cpuinfo_x86 boot_cpu_data;
236 DECLARE_PER_CPU(struct tss_struct,init_tss);
237 DECLARE_PER_CPU(pgd_t *, cur_pgd);
239 #define ARCH_MIN_TASKALIGN 16
241 struct thread_struct {
244 unsigned long userrsp; /* Copy from PDA */
248 unsigned short es, ds, fsindex, gsindex;
249 /* Hardware debugging registers */
250 unsigned long debugreg0;
251 unsigned long debugreg1;
252 unsigned long debugreg2;
253 unsigned long debugreg3;
254 unsigned long debugreg6;
255 unsigned long debugreg7;
257 unsigned long cr2, trap_no, error_code;
258 /* floating point info */
259 union i387_union i387 __attribute__((aligned(16)));
260 /* IO permissions. the bitmap could be moved into the GDT, that would make
261 switch faster for a limited number of ioperm using tasks. -AK */
263 unsigned long *io_bitmap_ptr;
264 unsigned io_bitmap_max;
265 /* cached TLS descriptors. */
266 u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
267 } __attribute__((aligned(16)));
269 #define INIT_THREAD {}
272 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
274 #define STACKFAULT_STACK 1
275 #define DOUBLEFAULT_STACK 2
277 #define DEBUG_STACK 4
279 #define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
280 #define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
281 #define EXCEPTION_STACK_ORDER 0
283 #define start_thread(regs,new_rip,new_rsp) do { \
284 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
286 (regs)->rip = (new_rip); \
287 (regs)->rsp = (new_rsp); \
288 write_pda(oldrsp, (new_rsp)); \
289 (regs)->cs = __USER_CS; \
290 (regs)->ss = __USER_DS; \
291 (regs)->eflags = 0x200; \
298 /* Free all resources held by a thread. */
299 extern void release_thread(struct task_struct *);
301 /* Prepare to copy thread state - unlazy all lazy status */
302 extern void prepare_to_copy(struct task_struct *tsk);
305 * create a kernel thread without removing it from tasklists
307 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
310 * Return saved PC of a blocked thread.
311 * What is this good for? it will be always the scheduler or ret_from_fork.
313 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
315 extern unsigned long get_wchan(struct task_struct *p);
316 #define KSTK_EIP(tsk) \
317 (((struct pt_regs *)(tsk->thread.rsp0 - sizeof(struct pt_regs)))->rip)
318 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
321 struct microcode_header {
329 unsigned int datasize;
330 unsigned int totalsize;
331 unsigned int reserved[3];
335 struct microcode_header hdr;
336 unsigned int bits[0];
339 typedef struct microcode microcode_t;
340 typedef struct microcode_header microcode_header_t;
342 /* microcode format is extended from prescott processors */
343 struct extended_signature {
349 struct extended_sigtable {
352 unsigned int reserved[3];
353 struct extended_signature sigs[0];
356 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
357 #define MICROCODE_IOCFREE _IO('6',0)
360 #define ASM_NOP1 K8_NOP1
361 #define ASM_NOP2 K8_NOP2
362 #define ASM_NOP3 K8_NOP3
363 #define ASM_NOP4 K8_NOP4
364 #define ASM_NOP5 K8_NOP5
365 #define ASM_NOP6 K8_NOP6
366 #define ASM_NOP7 K8_NOP7
367 #define ASM_NOP8 K8_NOP8
370 #define K8_NOP1 ".byte 0x90\n"
371 #define K8_NOP2 ".byte 0x66,0x90\n"
372 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
373 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
374 #define K8_NOP5 K8_NOP3 K8_NOP2
375 #define K8_NOP6 K8_NOP3 K8_NOP3
376 #define K8_NOP7 K8_NOP4 K8_NOP3
377 #define K8_NOP8 K8_NOP4 K8_NOP4
379 #define ASM_NOP_MAX 8
381 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
382 extern inline void rep_nop(void)
384 __asm__ __volatile__("rep;nop": : :"memory");
387 /* Stop speculative execution */
388 extern inline void sync_core(void)
391 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
394 #define cpu_has_fpu 1
396 #define ARCH_HAS_PREFETCH
397 static inline void prefetch(void *x)
399 asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
402 #define ARCH_HAS_PREFETCHW 1
403 static inline void prefetchw(void *x)
405 alternative_input(ASM_NOP5,
411 #define ARCH_HAS_SPINLOCK_PREFETCH 1
413 #define spin_lock_prefetch(x) prefetchw(x)
415 #define cpu_relax() rep_nop()
418 * NSC/Cyrix CPU configuration register indexes
420 #define CX86_CCR0 0xc0
421 #define CX86_CCR1 0xc1
422 #define CX86_CCR2 0xc2
423 #define CX86_CCR3 0xc3
424 #define CX86_CCR4 0xe8
425 #define CX86_CCR5 0xe9
426 #define CX86_CCR6 0xea
427 #define CX86_CCR7 0xeb
428 #define CX86_DIR0 0xfe
429 #define CX86_DIR1 0xff
430 #define CX86_ARR_BASE 0xc4
431 #define CX86_RCR_BASE 0xdc
434 * NSC/Cyrix CPU indexed register access macros
437 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
439 #define setCx86(reg, data) do { \
441 outb((data), 0x23); \
444 static inline void __monitor(const void *eax, unsigned long ecx,
447 /* "monitor %eax,%ecx,%edx;" */
449 ".byte 0x0f,0x01,0xc8;"
450 : :"a" (eax), "c" (ecx), "d"(edx));
453 static inline void __mwait(unsigned long eax, unsigned long ecx)
455 /* "mwait %eax,%ecx;" */
457 ".byte 0x0f,0x01,0xc9;"
458 : :"a" (eax), "c" (ecx));
461 #define stack_current() \
463 struct thread_info *ti; \
464 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
468 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
470 extern unsigned long boot_option_idle_override;
471 /* Boot loader type from the setup header */
472 extern int bootloader_type;
474 #endif /* __ASM_X86_64_PROCESSOR_H */