1 /******************************************************************************
2 * arch-ia64/hypervisor-if.h
4 * Guest OS interface to IA64 Xen.
7 #ifndef __HYPERVISOR_IF_IA64_H__
8 #define __HYPERVISOR_IF_IA64_H__
10 // "packed" generates awful code
13 /* Pointers are naturally 64 bits in this architecture; no padding needed. */
14 #define _MEMORY_PADDING(_X)
15 #define MEMORY_PADDING
19 /* NB. Both the following are 64 bits each. */
20 typedef unsigned long memory_t; /* Full-sized pointer/address/memory-size. */
21 typedef unsigned long cpureg_t; /* Full-sized register. */
25 } PACKED execution_context_t;
28 * NB. This may become a 64-bit count with no shift. If this happens then the
29 * structure size will still be 8 bytes, so no other alignments will change.
32 u32 tsc_bits; /* 0: 32 bits read from the CPU's TSC. */
33 u32 tsc_bitshift; /* 4: 'tsc_bits' uses N:N+31 of TSC. */
34 } PACKED tsc_timestamp_t; /* 8 bytes */
36 #include <asm/tlb.h> /* TR_ENTRY */
42 unsigned long precover_ifs;
47 unsigned long unat; // not sure if this is needed until NaT arch is done
55 int interrupt_collection_enabled; // virtual psr.ic
56 int interrupt_delivery_enabled; // virtual psr.i
57 int pending_interruption;
58 int incomplete_regframe; // see SDM vol2 6.8
59 unsigned long delivery_mask[4];
60 int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual
61 int banknum; // 0 or 1, which virtual register bank is active
62 unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active
63 unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active
64 unsigned long rrs[8]; // region registers
65 unsigned long krs[8]; // kernel registers
66 unsigned long pkrs[8]; // protection key registers
67 // FIXME: These shouldn't be here as they can be overwritten by guests
68 // and validation at TLB miss time would be too expensive.
73 unsigned long itlb_pte;
74 unsigned long dtlb_pte;
76 unsigned long insvc[4];
80 unsigned long domain_itm;
81 unsigned long domain_itm_last;
82 unsigned long xen_itm;
83 unsigned long xen_timer_interval;
84 //} PACKED arch_shared_info_t;
85 } arch_vcpu_info_t; // DON'T PACK
88 } arch_shared_info_t; // DON'T PACK
91 * The following is all CPU context. Note that the i387_ctxt block is filled
92 * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
95 //unsigned long flags;
96 } PACKED full_execution_context_t;
98 #endif /* !__ASSEMBLY__ */
100 #endif /* __HYPERVISOR_IF_IA64_H__ */