1 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/82571.c linux-2.6.22-10/drivers/net/e1000e/82571.c
2 --- linux-2.6.22-0/drivers/net/e1000e/82571.c 1969-12-31 19:00:00.000000000 -0500
3 +++ linux-2.6.22-10/drivers/net/e1000e/82571.c 2007-11-21 13:55:28.000000000 -0500
5 +/*******************************************************************************
7 + Intel PRO/1000 Linux driver
8 + Copyright(c) 1999 - 2007 Intel Corporation.
10 + This program is free software; you can redistribute it and/or modify it
11 + under the terms and conditions of the GNU General Public License,
12 + version 2, as published by the Free Software Foundation.
14 + This program is distributed in the hope it will be useful, but WITHOUT
15 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 + You should have received a copy of the GNU General Public License along with
20 + this program; if not, write to the Free Software Foundation, Inc.,
21 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 + The full GNU General Public License is included in this distribution in
24 + the file called "COPYING".
26 + Contact Information:
27 + Linux NICS <linux.nics@intel.com>
28 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
29 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 +*******************************************************************************/
34 + * 82571EB Gigabit Ethernet Controller
35 + * 82571EB Gigabit Ethernet Controller (Fiber)
36 + * 82572EI Gigabit Ethernet Controller (Copper)
37 + * 82572EI Gigabit Ethernet Controller (Fiber)
38 + * 82572EI Gigabit Ethernet Controller
39 + * 82573V Gigabit Ethernet Controller (Copper)
40 + * 82573E Gigabit Ethernet Controller (Copper)
41 + * 82573L Gigabit Ethernet Controller
44 +#include <linux/netdevice.h>
45 +#include <linux/delay.h>
46 +#include <linux/pci.h>
50 +#define ID_LED_RESERVED_F746 0xF746
51 +#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
52 + (ID_LED_OFF1_ON2 << 8) | \
53 + (ID_LED_DEF1_DEF2 << 4) | \
56 +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
58 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
59 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
60 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
61 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
62 + u16 words, u16 *data);
63 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
64 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
65 +static s32 e1000_setup_link_82571(struct e1000_hw *hw);
66 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
69 + * e1000_init_phy_params_82571 - Init PHY func ptrs.
70 + * @hw: pointer to the HW structure
72 + * This is a function pointer entry point called by the api module.
74 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
76 + struct e1000_phy_info *phy = &hw->phy;
79 + if (hw->media_type != e1000_media_type_copper) {
80 + phy->type = e1000_phy_none;
85 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
86 + phy->reset_delay_us = 100;
88 + switch (hw->mac.type) {
91 + phy->type = e1000_phy_igp_2;
94 + phy->type = e1000_phy_m88;
97 + return -E1000_ERR_PHY;
101 + /* This can only be done after all function pointers are setup. */
102 + ret_val = e1000_get_phy_id_82571(hw);
104 + /* Verify phy id */
105 + switch (hw->mac.type) {
108 + if (phy->id != IGP01E1000_I_PHY_ID)
109 + return -E1000_ERR_PHY;
112 + if (phy->id != M88E1111_I_PHY_ID)
113 + return -E1000_ERR_PHY;
116 + return -E1000_ERR_PHY;
124 + * e1000_init_nvm_params_82571 - Init NVM func ptrs.
125 + * @hw: pointer to the HW structure
127 + * This is a function pointer entry point called by the api module.
129 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
131 + struct e1000_nvm_info *nvm = &hw->nvm;
132 + u32 eecd = er32(EECD);
135 + nvm->opcode_bits = 8;
136 + nvm->delay_usec = 1;
137 + switch (nvm->override) {
138 + case e1000_nvm_override_spi_large:
139 + nvm->page_size = 32;
140 + nvm->address_bits = 16;
142 + case e1000_nvm_override_spi_small:
143 + nvm->page_size = 8;
144 + nvm->address_bits = 8;
147 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
148 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
152 + switch (hw->mac.type) {
154 + if (((eecd >> 15) & 0x3) == 0x3) {
155 + nvm->type = e1000_nvm_flash_hw;
156 + nvm->word_size = 2048;
157 + /* Autonomous Flash update bit must be cleared due
158 + * to Flash update issue.
160 + eecd &= ~E1000_EECD_AUPDEN;
166 + nvm->type = e1000_nvm_eeprom_spi;
167 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
168 + E1000_EECD_SIZE_EX_SHIFT);
169 + /* Added to a constant, "size" becomes the left-shift value
170 + * for setting word_size.
172 + size += NVM_WORD_SIZE_BASE_SHIFT;
173 + nvm->word_size = 1 << size;
181 + * e1000_init_mac_params_82571 - Init MAC func ptrs.
182 + * @hw: pointer to the HW structure
184 + * This is a function pointer entry point called by the api module.
186 +static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
188 + struct e1000_hw *hw = &adapter->hw;
189 + struct e1000_mac_info *mac = &hw->mac;
190 + struct e1000_mac_operations *func = &mac->ops;
192 + /* Set media type */
193 + switch (adapter->pdev->device) {
194 + case E1000_DEV_ID_82571EB_FIBER:
195 + case E1000_DEV_ID_82572EI_FIBER:
196 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
197 + hw->media_type = e1000_media_type_fiber;
199 + case E1000_DEV_ID_82571EB_SERDES:
200 + case E1000_DEV_ID_82572EI_SERDES:
201 + hw->media_type = e1000_media_type_internal_serdes;
204 + hw->media_type = e1000_media_type_copper;
208 + /* Set mta register count */
209 + mac->mta_reg_count = 128;
210 + /* Set rar entry count */
211 + mac->rar_entry_count = E1000_RAR_ENTRIES;
212 + /* Set if manageability features are enabled. */
213 + mac->arc_subsystem_valid =
214 + (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
216 + /* check for link */
217 + switch (hw->media_type) {
218 + case e1000_media_type_copper:
219 + func->setup_physical_interface = e1000_setup_copper_link_82571;
220 + func->check_for_link = e1000e_check_for_copper_link;
221 + func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
223 + case e1000_media_type_fiber:
224 + func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;
225 + func->check_for_link = e1000e_check_for_fiber_link;
226 + func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;
228 + case e1000_media_type_internal_serdes:
229 + func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;
230 + func->check_for_link = e1000e_check_for_serdes_link;
231 + func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;
234 + return -E1000_ERR_CONFIG;
241 +static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter)
243 + struct e1000_hw *hw = &adapter->hw;
244 + static int global_quad_port_a; /* global port a indication */
245 + struct pci_dev *pdev = adapter->pdev;
246 + u16 eeprom_data = 0;
247 + int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
250 + rc = e1000_init_mac_params_82571(adapter);
254 + rc = e1000_init_nvm_params_82571(hw);
258 + rc = e1000_init_phy_params_82571(hw);
262 + /* tag quad port adapters first, it's used below */
263 + switch (pdev->device) {
264 + case E1000_DEV_ID_82571EB_QUAD_COPPER:
265 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
266 + case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
267 + adapter->flags |= FLAG_IS_QUAD_PORT;
268 + /* mark the first port */
269 + if (global_quad_port_a == 0)
270 + adapter->flags |= FLAG_IS_QUAD_PORT_A;
271 + /* Reset for multiple quad port adapters */
272 + global_quad_port_a++;
273 + if (global_quad_port_a == 4)
274 + global_quad_port_a = 0;
280 + switch (adapter->hw.mac.type) {
282 + /* these dual ports don't have WoL on port B at all */
283 + if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
284 + (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
285 + (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
287 + adapter->flags &= ~FLAG_HAS_WOL;
288 + /* quad ports only support WoL on port A */
289 + if (adapter->flags & FLAG_IS_QUAD_PORT &&
290 + (!adapter->flags & FLAG_IS_QUAD_PORT_A))
291 + adapter->flags &= ~FLAG_HAS_WOL;
295 + if (pdev->device == E1000_DEV_ID_82573L) {
296 + e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
298 + if (eeprom_data & NVM_WORD1A_ASPM_MASK)
299 + adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
310 + * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
311 + * @hw: pointer to the HW structure
313 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
314 + * revision in the hardware structure.
316 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
318 + struct e1000_phy_info *phy = &hw->phy;
320 + switch (hw->mac.type) {
323 + /* The 82571 firmware may still be configuring the PHY.
324 + * In this case, we cannot access the PHY until the
325 + * configuration is done. So we explicitly set the
327 + phy->id = IGP01E1000_I_PHY_ID;
330 + return e1000e_get_phy_id(hw);
333 + return -E1000_ERR_PHY;
341 + * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
342 + * @hw: pointer to the HW structure
344 + * Acquire the HW semaphore to access the PHY or NVM
346 +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
349 + s32 timeout = hw->nvm.word_size + 1;
352 + /* Get the FW semaphore. */
353 + for (i = 0; i < timeout; i++) {
355 + ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
357 + /* Semaphore acquired if bit latched */
358 + if (er32(SWSM) & E1000_SWSM_SWESMBI)
364 + if (i == timeout) {
365 + /* Release semaphores */
366 + e1000e_put_hw_semaphore(hw);
367 + hw_dbg(hw, "Driver can't access the NVM\n");
368 + return -E1000_ERR_NVM;
375 + * e1000_put_hw_semaphore_82571 - Release hardware semaphore
376 + * @hw: pointer to the HW structure
378 + * Release hardware semaphore used to access the PHY or NVM
380 +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
386 + swsm &= ~E1000_SWSM_SWESMBI;
392 + * e1000_acquire_nvm_82571 - Request for access to the EEPROM
393 + * @hw: pointer to the HW structure
395 + * To gain access to the EEPROM, first we must obtain a hardware semaphore.
396 + * Then for non-82573 hardware, set the EEPROM access request bit and wait
397 + * for EEPROM access grant bit. If the access grant bit is not set, release
398 + * hardware semaphore.
400 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
404 + ret_val = e1000_get_hw_semaphore_82571(hw);
408 + if (hw->mac.type != e1000_82573)
409 + ret_val = e1000e_acquire_nvm(hw);
412 + e1000_put_hw_semaphore_82571(hw);
418 + * e1000_release_nvm_82571 - Release exclusive access to EEPROM
419 + * @hw: pointer to the HW structure
421 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
423 +static void e1000_release_nvm_82571(struct e1000_hw *hw)
425 + e1000e_release_nvm(hw);
426 + e1000_put_hw_semaphore_82571(hw);
430 + * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
431 + * @hw: pointer to the HW structure
432 + * @offset: offset within the EEPROM to be written to
433 + * @words: number of words to write
434 + * @data: 16 bit word(s) to be written to the EEPROM
436 + * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
438 + * If e1000e_update_nvm_checksum is not called after this function, the
439 + * EEPROM will most likley contain an invalid checksum.
441 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
446 + switch (hw->mac.type) {
448 + ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
452 + ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
455 + ret_val = -E1000_ERR_NVM;
463 + * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
464 + * @hw: pointer to the HW structure
466 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
467 + * up to the checksum. Then calculates the EEPROM checksum and writes the
468 + * value to the EEPROM.
470 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
476 + ret_val = e1000e_update_nvm_checksum_generic(hw);
480 + /* If our nvm is an EEPROM, then we're done
481 + * otherwise, commit the checksum to the flash NVM. */
482 + if (hw->nvm.type != e1000_nvm_flash_hw)
485 + /* Check for pending operations. */
486 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
488 + if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
492 + if (i == E1000_FLASH_UPDATES)
493 + return -E1000_ERR_NVM;
495 + /* Reset the firmware if using STM opcode. */
496 + if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
497 + /* The enabling of and the actual reset must be done
498 + * in two write cycles.
500 + ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
502 + ew32(HICR, E1000_HICR_FW_RESET);
505 + /* Commit the write to flash */
506 + eecd = er32(EECD) | E1000_EECD_FLUPD;
509 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
511 + if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
515 + if (i == E1000_FLASH_UPDATES)
516 + return -E1000_ERR_NVM;
522 + * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
523 + * @hw: pointer to the HW structure
525 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
526 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
528 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
530 + if (hw->nvm.type == e1000_nvm_flash_hw)
531 + e1000_fix_nvm_checksum_82571(hw);
533 + return e1000e_validate_nvm_checksum_generic(hw);
537 + * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
538 + * @hw: pointer to the HW structure
539 + * @offset: offset within the EEPROM to be written to
540 + * @words: number of words to write
541 + * @data: 16 bit word(s) to be written to the EEPROM
543 + * After checking for invalid values, poll the EEPROM to ensure the previous
544 + * command has completed before trying to write the next word. After write
545 + * poll for completion.
547 + * If e1000e_update_nvm_checksum is not called after this function, the
548 + * EEPROM will most likley contain an invalid checksum.
550 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
551 + u16 words, u16 *data)
553 + struct e1000_nvm_info *nvm = &hw->nvm;
558 + /* A check for invalid values: offset too large, too many words,
559 + * and not enough words. */
560 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
562 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
563 + return -E1000_ERR_NVM;
566 + for (i = 0; i < words; i++) {
567 + eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
568 + ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
569 + E1000_NVM_RW_REG_START;
571 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
577 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
586 + * e1000_get_cfg_done_82571 - Poll for configuration done
587 + * @hw: pointer to the HW structure
589 + * Reads the management control register for the config done bit to be set.
591 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
593 + s32 timeout = PHY_CFG_TIMEOUT;
596 + if (er32(EEMNGCTL) &
597 + E1000_NVM_CFG_DONE_PORT_0)
603 + hw_dbg(hw, "MNG configuration cycle has not completed.\n");
604 + return -E1000_ERR_RESET;
611 + * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
612 + * @hw: pointer to the HW structure
613 + * @active: TRUE to enable LPLU, FALSE to disable
615 + * Sets the LPLU D0 state according to the active flag. When activating LPLU
616 + * this function also disables smart speed and vice versa. LPLU will not be
617 + * activated unless the device autonegotiation advertisement meets standards
618 + * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
619 + * pointer entry point only called by PHY setup routines.
621 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
623 + struct e1000_phy_info *phy = &hw->phy;
627 + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
632 + data |= IGP02E1000_PM_D0_LPLU;
633 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
637 + /* When LPLU is enabled, we should disable SmartSpeed */
638 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
639 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
640 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
644 + data &= ~IGP02E1000_PM_D0_LPLU;
645 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
646 + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
647 + * during Dx states where the power conservation is most
648 + * important. During driver activity we should enable
649 + * SmartSpeed, so performance is maintained. */
650 + if (phy->smart_speed == e1000_smart_speed_on) {
651 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
656 + data |= IGP01E1000_PSCFR_SMART_SPEED;
657 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
661 + } else if (phy->smart_speed == e1000_smart_speed_off) {
662 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
667 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
668 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
679 + * e1000_reset_hw_82571 - Reset hardware
680 + * @hw: pointer to the HW structure
682 + * This resets the hardware into a known state. This is a
683 + * function pointer entry point called by the api module.
685 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
694 + /* Prevent the PCI-E bus from sticking if there is no TLP connection
695 + * on the last TLP read/write transaction when MAC is reset.
697 + ret_val = e1000e_disable_pcie_master(hw);
699 + hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
701 + hw_dbg(hw, "Masking off all interrupts\n");
702 + ew32(IMC, 0xffffffff);
705 + ew32(TCTL, E1000_TCTL_PSP);
710 + /* Must acquire the MDIO ownership before MAC reset.
711 + * Ownership defaults to firmware after a reset. */
712 + if (hw->mac.type == e1000_82573) {
713 + extcnf_ctrl = er32(EXTCNF_CTRL);
714 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
717 + ew32(EXTCNF_CTRL, extcnf_ctrl);
718 + extcnf_ctrl = er32(EXTCNF_CTRL);
720 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
723 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
727 + } while (i < MDIO_OWNERSHIP_TIMEOUT);
732 + hw_dbg(hw, "Issuing a global reset to MAC\n");
733 + ew32(CTRL, ctrl | E1000_CTRL_RST);
735 + if (hw->nvm.type == e1000_nvm_flash_hw) {
737 + ctrl_ext = er32(CTRL_EXT);
738 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
739 + ew32(CTRL_EXT, ctrl_ext);
743 + ret_val = e1000e_get_auto_rd_done(hw);
745 + /* We don't want to continue accessing MAC registers. */
748 + /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
749 + * Need to wait for Phy configuration completion before accessing
752 + if (hw->mac.type == e1000_82573)
755 + /* Clear any pending interrupt events. */
756 + ew32(IMC, 0xffffffff);
763 + * e1000_init_hw_82571 - Initialize hardware
764 + * @hw: pointer to the HW structure
766 + * This inits the hardware readying it for operation.
768 +static s32 e1000_init_hw_82571(struct e1000_hw *hw)
770 + struct e1000_mac_info *mac = &hw->mac;
774 + u16 rar_count = mac->rar_entry_count;
776 + e1000_initialize_hw_bits_82571(hw);
778 + /* Initialize identification LED */
779 + ret_val = e1000e_id_led_init(hw);
781 + hw_dbg(hw, "Error initializing identification LED\n");
785 + /* Disabling VLAN filtering */
786 + hw_dbg(hw, "Initializing the IEEE VLAN\n");
787 + e1000e_clear_vfta(hw);
789 + /* Setup the receive address. */
790 + /* If, however, a locally administered address was assigned to the
791 + * 82571, we must reserve a RAR for it to work around an issue where
792 + * resetting one port will reload the MAC on the other port.
794 + if (e1000e_get_laa_state_82571(hw))
796 + e1000e_init_rx_addrs(hw, rar_count);
798 + /* Zero out the Multicast HASH table */
799 + hw_dbg(hw, "Zeroing the MTA\n");
800 + for (i = 0; i < mac->mta_reg_count; i++)
801 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
803 + /* Setup link and flow control */
804 + ret_val = e1000_setup_link_82571(hw);
806 + /* Set the transmit descriptor write-back policy */
807 + reg_data = er32(TXDCTL);
808 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
809 + E1000_TXDCTL_FULL_TX_DESC_WB |
810 + E1000_TXDCTL_COUNT_DESC;
811 + ew32(TXDCTL, reg_data);
813 + /* ...for both queues. */
814 + if (mac->type != e1000_82573) {
815 + reg_data = er32(TXDCTL1);
816 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
817 + E1000_TXDCTL_FULL_TX_DESC_WB |
818 + E1000_TXDCTL_COUNT_DESC;
819 + ew32(TXDCTL1, reg_data);
821 + e1000e_enable_tx_pkt_filtering(hw);
822 + reg_data = er32(GCR);
823 + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
824 + ew32(GCR, reg_data);
827 + /* Clear all of the statistics registers (clear on read). It is
828 + * important that we do this after we have tried to establish link
829 + * because the symbol error count will increment wildly if there
832 + e1000_clear_hw_cntrs_82571(hw);
838 + * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
839 + * @hw: pointer to the HW structure
841 + * Initializes required hardware-dependent bits needed for normal operation.
843 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
847 + /* Transmit Descriptor Control 0 */
848 + reg = er32(TXDCTL);
852 + /* Transmit Descriptor Control 1 */
853 + reg = er32(TXDCTL1);
855 + ew32(TXDCTL1, reg);
857 + /* Transmit Arbitration Control 0 */
859 + reg &= ~(0xF << 27); /* 30:27 */
860 + switch (hw->mac.type) {
863 + reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
870 + /* Transmit Arbitration Control 1 */
872 + switch (hw->mac.type) {
875 + reg &= ~((1 << 29) | (1 << 30));
876 + reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
877 + if (er32(TCTL) & E1000_TCTL_MULR)
887 + /* Device Control */
888 + if (hw->mac.type == e1000_82573) {
894 + /* Extended Device Control */
895 + if (hw->mac.type == e1000_82573) {
896 + reg = er32(CTRL_EXT);
899 + ew32(CTRL_EXT, reg);
904 + * e1000e_clear_vfta - Clear VLAN filter table
905 + * @hw: pointer to the HW structure
907 + * Clears the register array which contains the VLAN filter table by
908 + * setting all the values to 0.
910 +void e1000e_clear_vfta(struct e1000_hw *hw)
913 + u32 vfta_value = 0;
914 + u32 vfta_offset = 0;
915 + u32 vfta_bit_in_reg = 0;
917 + if (hw->mac.type == e1000_82573) {
918 + if (hw->mng_cookie.vlan_id != 0) {
919 + /* The VFTA is a 4096b bit-field, each identifying
920 + * a single VLAN ID. The following operations
921 + * determine which 32b entry (i.e. offset) into the
922 + * array we want to set the VLAN ID (i.e. bit) of
923 + * the manageability unit.
925 + vfta_offset = (hw->mng_cookie.vlan_id >>
926 + E1000_VFTA_ENTRY_SHIFT) &
927 + E1000_VFTA_ENTRY_MASK;
928 + vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
929 + E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
932 + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
933 + /* If the offset we want to clear is the same offset of the
934 + * manageability VLAN ID, then clear all bits except that of
935 + * the manageability unit.
937 + vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
938 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
944 + * e1000_mc_addr_list_update_82571 - Update Multicast addresses
945 + * @hw: pointer to the HW structure
946 + * @mc_addr_list: array of multicast addresses to program
947 + * @mc_addr_count: number of multicast addresses to program
948 + * @rar_used_count: the first RAR register free to program
949 + * @rar_count: total number of supported Receive Address Registers
951 + * Updates the Receive Address Registers and Multicast Table Array.
952 + * The caller must have a packed mc_addr_list of multicast addresses.
953 + * The parameter rar_count will usually be hw->mac.rar_entry_count
954 + * unless there are workarounds that change this.
956 +static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw,
959 + u32 rar_used_count,
962 + if (e1000e_get_laa_state_82571(hw))
965 + e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count,
966 + rar_used_count, rar_count);
970 + * e1000_setup_link_82571 - Setup flow control and link settings
971 + * @hw: pointer to the HW structure
973 + * Determines which flow control settings to use, then configures flow
974 + * control. Calls the appropriate media-specific link configuration
975 + * function. Assuming the adapter has a valid link partner, a valid link
976 + * should be established. Assumes the hardware has previously been reset
977 + * and the transmitter and receiver are not enabled.
979 +static s32 e1000_setup_link_82571(struct e1000_hw *hw)
981 + /* 82573 does not have a word in the NVM to determine
982 + * the default flow control setting, so we explicitly
985 + if (hw->mac.type == e1000_82573)
986 + hw->mac.fc = e1000_fc_full;
988 + return e1000e_setup_link(hw);
992 + * e1000_setup_copper_link_82571 - Configure copper link settings
993 + * @hw: pointer to the HW structure
995 + * Configures the link for auto-neg or forced speed and duplex. Then we check
996 + * for link, once link is established calls to configure collision distance
997 + * and flow control are called.
999 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1005 + ctrl = er32(CTRL);
1006 + ctrl |= E1000_CTRL_SLU;
1007 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1010 + switch (hw->phy.type) {
1011 + case e1000_phy_m88:
1012 + ret_val = e1000e_copper_link_setup_m88(hw);
1014 + case e1000_phy_igp_2:
1015 + ret_val = e1000e_copper_link_setup_igp(hw);
1016 + /* Setup activity LED */
1017 + led_ctrl = er32(LEDCTL);
1018 + led_ctrl &= IGP_ACTIVITY_LED_MASK;
1019 + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1020 + ew32(LEDCTL, led_ctrl);
1023 + return -E1000_ERR_PHY;
1030 + ret_val = e1000e_setup_copper_link(hw);
1036 + * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1037 + * @hw: pointer to the HW structure
1039 + * Configures collision distance and flow control for fiber and serdes links.
1040 + * Upon successful setup, poll for link.
1042 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1044 + switch (hw->mac.type) {
1047 + /* If SerDes loopback mode is entered, there is no form
1048 + * of reset to take the adapter out of that mode. So we
1049 + * have to explicitly take the adapter out of loopback
1050 + * mode. This prevents drivers from twidling their thumbs
1051 + * if another tool failed to take it out of loopback mode.
1054 + E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1060 + return e1000e_setup_fiber_serdes_link(hw);
1064 + * e1000_valid_led_default_82571 - Verify a valid default LED config
1065 + * @hw: pointer to the HW structure
1066 + * @data: pointer to the NVM (EEPROM)
1068 + * Read the EEPROM for the current default LED configuration. If the
1069 + * LED configuration is not valid, set to a valid LED configuration.
1071 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1075 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1077 + hw_dbg(hw, "NVM Read Error\n");
1081 + if (hw->mac.type == e1000_82573 &&
1082 + *data == ID_LED_RESERVED_F746)
1083 + *data = ID_LED_DEFAULT_82573;
1084 + else if (*data == ID_LED_RESERVED_0000 ||
1085 + *data == ID_LED_RESERVED_FFFF)
1086 + *data = ID_LED_DEFAULT;
1092 + * e1000e_get_laa_state_82571 - Get locally administered address state
1093 + * @hw: pointer to the HW structure
1095 + * Retrieve and return the current locally administed address state.
1097 +bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1099 + if (hw->mac.type != e1000_82571)
1102 + return hw->dev_spec.e82571.laa_is_present;
1106 + * e1000e_set_laa_state_82571 - Set locally administered address state
1107 + * @hw: pointer to the HW structure
1108 + * @state: enable/disable locally administered address
1110 + * Enable/Disable the current locally administed address state.
1112 +void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1114 + if (hw->mac.type != e1000_82571)
1117 + hw->dev_spec.e82571.laa_is_present = state;
1119 + /* If workaround is activated... */
1121 + /* Hold a copy of the LAA in RAR[14] This is done so that
1122 + * between the time RAR[0] gets clobbered and the time it
1123 + * gets fixed, the actual LAA is in one of the RARs and no
1124 + * incoming packets directed to this port are dropped.
1125 + * Eventually the LAA will be in RAR[0] and RAR[14].
1127 + e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1131 + * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1132 + * @hw: pointer to the HW structure
1134 + * Verifies that the EEPROM has completed the update. After updating the
1135 + * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1136 + * the checksum fix is not implemented, we need to set the bit and update
1137 + * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1138 + * we need to return bad checksum.
1140 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1142 + struct e1000_nvm_info *nvm = &hw->nvm;
1146 + if (nvm->type != e1000_nvm_flash_hw)
1149 + /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1150 + * 10h-12h. Checksum may need to be fixed.
1152 + ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1156 + if (!(data & 0x10)) {
1157 + /* Read 0x23 and check bit 15. This bit is a 1
1158 + * when the checksum has already been fixed. If
1159 + * the checksum is still wrong and this bit is a
1160 + * 1, we need to return bad checksum. Otherwise,
1161 + * we need to set this bit to a 1 and update the
1164 + ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1168 + if (!(data & 0x8000)) {
1170 + ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1173 + ret_val = e1000e_update_nvm_checksum(hw);
1181 + * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1182 + * @hw: pointer to the HW structure
1184 + * Clears the hardware counters by reading the counter registers.
1186 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1190 + e1000e_clear_hw_cntrs_base(hw);
1192 + temp = er32(PRC64);
1193 + temp = er32(PRC127);
1194 + temp = er32(PRC255);
1195 + temp = er32(PRC511);
1196 + temp = er32(PRC1023);
1197 + temp = er32(PRC1522);
1198 + temp = er32(PTC64);
1199 + temp = er32(PTC127);
1200 + temp = er32(PTC255);
1201 + temp = er32(PTC511);
1202 + temp = er32(PTC1023);
1203 + temp = er32(PTC1522);
1205 + temp = er32(ALGNERRC);
1206 + temp = er32(RXERRC);
1207 + temp = er32(TNCRS);
1208 + temp = er32(CEXTERR);
1209 + temp = er32(TSCTC);
1210 + temp = er32(TSCTFC);
1212 + temp = er32(MGTPRC);
1213 + temp = er32(MGTPDC);
1214 + temp = er32(MGTPTC);
1217 + temp = er32(ICRXOC);
1219 + temp = er32(ICRXPTC);
1220 + temp = er32(ICRXATC);
1221 + temp = er32(ICTXPTC);
1222 + temp = er32(ICTXATC);
1223 + temp = er32(ICTXQEC);
1224 + temp = er32(ICTXQMTC);
1225 + temp = er32(ICRXDMTC);
1228 +static struct e1000_mac_operations e82571_mac_ops = {
1229 + .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1230 + /* .check_for_link: media type dependent */
1231 + .cleanup_led = e1000e_cleanup_led_generic,
1232 + .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1233 + .get_bus_info = e1000e_get_bus_info_pcie,
1234 + /* .get_link_up_info: media type dependent */
1235 + .led_on = e1000e_led_on_generic,
1236 + .led_off = e1000e_led_off_generic,
1237 + .mc_addr_list_update = e1000_mc_addr_list_update_82571,
1238 + .reset_hw = e1000_reset_hw_82571,
1239 + .init_hw = e1000_init_hw_82571,
1240 + .setup_link = e1000_setup_link_82571,
1241 + /* .setup_physical_interface: media type dependent */
1244 +static struct e1000_phy_operations e82_phy_ops_igp = {
1245 + .acquire_phy = e1000_get_hw_semaphore_82571,
1246 + .check_reset_block = e1000e_check_reset_block_generic,
1247 + .commit_phy = NULL,
1248 + .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1249 + .get_cfg_done = e1000_get_cfg_done_82571,
1250 + .get_cable_length = e1000e_get_cable_length_igp_2,
1251 + .get_phy_info = e1000e_get_phy_info_igp,
1252 + .read_phy_reg = e1000e_read_phy_reg_igp,
1253 + .release_phy = e1000_put_hw_semaphore_82571,
1254 + .reset_phy = e1000e_phy_hw_reset_generic,
1255 + .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1256 + .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1257 + .write_phy_reg = e1000e_write_phy_reg_igp,
1260 +static struct e1000_phy_operations e82_phy_ops_m88 = {
1261 + .acquire_phy = e1000_get_hw_semaphore_82571,
1262 + .check_reset_block = e1000e_check_reset_block_generic,
1263 + .commit_phy = e1000e_phy_sw_reset,
1264 + .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1265 + .get_cfg_done = e1000e_get_cfg_done,
1266 + .get_cable_length = e1000e_get_cable_length_m88,
1267 + .get_phy_info = e1000e_get_phy_info_m88,
1268 + .read_phy_reg = e1000e_read_phy_reg_m88,
1269 + .release_phy = e1000_put_hw_semaphore_82571,
1270 + .reset_phy = e1000e_phy_hw_reset_generic,
1271 + .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1272 + .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1273 + .write_phy_reg = e1000e_write_phy_reg_m88,
1276 +static struct e1000_nvm_operations e82571_nvm_ops = {
1277 + .acquire_nvm = e1000_acquire_nvm_82571,
1278 + .read_nvm = e1000e_read_nvm_spi,
1279 + .release_nvm = e1000_release_nvm_82571,
1280 + .update_nvm = e1000_update_nvm_checksum_82571,
1281 + .valid_led_default = e1000_valid_led_default_82571,
1282 + .validate_nvm = e1000_validate_nvm_checksum_82571,
1283 + .write_nvm = e1000_write_nvm_82571,
1286 +static struct e1000_nvm_operations e82573_nvm_ops = {
1287 + .acquire_nvm = e1000_acquire_nvm_82571,
1288 + .read_nvm = e1000e_read_nvm_eerd,
1289 + .release_nvm = e1000_release_nvm_82571,
1290 + .update_nvm = e1000_update_nvm_checksum_82571,
1291 + .valid_led_default = e1000_valid_led_default_82571,
1292 + .validate_nvm = e1000_validate_nvm_checksum_82571,
1293 + .write_nvm = e1000_write_nvm_82571,
1296 +struct e1000_info e1000_82571_info = {
1297 + .mac = e1000_82571,
1298 + .flags = FLAG_HAS_HW_VLAN_FILTER
1299 + | FLAG_HAS_JUMBO_FRAMES
1300 + | FLAG_HAS_STATS_PTC_PRC
1302 + | FLAG_APME_IN_CTRL3
1303 + | FLAG_RX_CSUM_ENABLED
1304 + | FLAG_HAS_CTRLEXT_ON_LOAD
1305 + | FLAG_HAS_STATS_ICR_ICT
1306 + | FLAG_HAS_SMART_POWER_DOWN
1307 + | FLAG_RESET_OVERWRITES_LAA /* errata */
1308 + | FLAG_TARC_SPEED_MODE_BIT /* errata */
1309 + | FLAG_APME_CHECK_PORT_B,
1311 + .get_invariants = e1000_get_invariants_82571,
1312 + .mac_ops = &e82571_mac_ops,
1313 + .phy_ops = &e82_phy_ops_igp,
1314 + .nvm_ops = &e82571_nvm_ops,
1317 +struct e1000_info e1000_82572_info = {
1318 + .mac = e1000_82572,
1319 + .flags = FLAG_HAS_HW_VLAN_FILTER
1320 + | FLAG_HAS_JUMBO_FRAMES
1321 + | FLAG_HAS_STATS_PTC_PRC
1323 + | FLAG_APME_IN_CTRL3
1324 + | FLAG_RX_CSUM_ENABLED
1325 + | FLAG_HAS_CTRLEXT_ON_LOAD
1326 + | FLAG_HAS_STATS_ICR_ICT
1327 + | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1329 + .get_invariants = e1000_get_invariants_82571,
1330 + .mac_ops = &e82571_mac_ops,
1331 + .phy_ops = &e82_phy_ops_igp,
1332 + .nvm_ops = &e82571_nvm_ops,
1335 +struct e1000_info e1000_82573_info = {
1336 + .mac = e1000_82573,
1337 + .flags = FLAG_HAS_HW_VLAN_FILTER
1338 + | FLAG_HAS_JUMBO_FRAMES
1339 + | FLAG_HAS_STATS_PTC_PRC
1341 + | FLAG_APME_IN_CTRL3
1342 + | FLAG_RX_CSUM_ENABLED
1343 + | FLAG_HAS_STATS_ICR_ICT
1344 + | FLAG_HAS_SMART_POWER_DOWN
1348 + | FLAG_HAS_SWSM_ON_LOAD,
1350 + .get_invariants = e1000_get_invariants_82571,
1351 + .mac_ops = &e82571_mac_ops,
1352 + .phy_ops = &e82_phy_ops_m88,
1353 + .nvm_ops = &e82573_nvm_ops,
1356 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/defines.h linux-2.6.22-10/drivers/net/e1000e/defines.h
1357 --- linux-2.6.22-0/drivers/net/e1000e/defines.h 1969-12-31 19:00:00.000000000 -0500
1358 +++ linux-2.6.22-10/drivers/net/e1000e/defines.h 2007-11-21 13:55:18.000000000 -0500
1360 +/*******************************************************************************
1362 + Intel PRO/1000 Linux driver
1363 + Copyright(c) 1999 - 2007 Intel Corporation.
1365 + This program is free software; you can redistribute it and/or modify it
1366 + under the terms and conditions of the GNU General Public License,
1367 + version 2, as published by the Free Software Foundation.
1369 + This program is distributed in the hope it will be useful, but WITHOUT
1370 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1371 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1374 + You should have received a copy of the GNU General Public License along with
1375 + this program; if not, write to the Free Software Foundation, Inc.,
1376 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1378 + The full GNU General Public License is included in this distribution in
1379 + the file called "COPYING".
1381 + Contact Information:
1382 + Linux NICS <linux.nics@intel.com>
1383 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1384 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
1386 +*******************************************************************************/
1388 +#ifndef _E1000_DEFINES_H_
1389 +#define _E1000_DEFINES_H_
1391 +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1392 +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1393 +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
1394 +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1395 +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1396 +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
1397 +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
1398 +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1399 +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1400 +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
1401 +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1402 +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
1403 +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
1404 +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
1405 +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
1406 +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
1407 +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
1408 +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
1410 +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1411 +#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1412 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1414 +/* Definitions for power management and wakeup registers */
1415 +/* Wake Up Control */
1416 +#define E1000_WUC_APME 0x00000001 /* APM Enable */
1417 +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1419 +/* Wake Up Filter Control */
1420 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1421 +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1422 +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1423 +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1424 +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1426 +/* Extended Device Control */
1427 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1428 +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1429 +#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1430 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1431 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
1432 +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1433 +#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1434 +#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1436 +/* Receive Decriptor bit definitions */
1437 +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
1438 +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
1439 +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
1440 +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1441 +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1442 +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
1443 +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
1444 +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
1445 +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
1446 +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
1447 +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
1448 +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
1449 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1451 +#define E1000_RXDEXT_STATERR_CE 0x01000000
1452 +#define E1000_RXDEXT_STATERR_SE 0x02000000
1453 +#define E1000_RXDEXT_STATERR_SEQ 0x04000000
1454 +#define E1000_RXDEXT_STATERR_CXE 0x10000000
1455 +#define E1000_RXDEXT_STATERR_RXE 0x80000000
1457 +/* mask to determine if packets should be dropped due to frame errors */
1458 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
1459 + E1000_RXD_ERR_CE | \
1460 + E1000_RXD_ERR_SE | \
1461 + E1000_RXD_ERR_SEQ | \
1462 + E1000_RXD_ERR_CXE | \
1463 + E1000_RXD_ERR_RXE)
1465 +/* Same mask, but for extended and packet split descriptors */
1466 +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
1467 + E1000_RXDEXT_STATERR_CE | \
1468 + E1000_RXDEXT_STATERR_SE | \
1469 + E1000_RXDEXT_STATERR_SEQ | \
1470 + E1000_RXDEXT_STATERR_CXE | \
1471 + E1000_RXDEXT_STATERR_RXE)
1473 +#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
1475 +/* Management Control */
1476 +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1477 +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1478 +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1479 +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1480 +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1481 +#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1483 +#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1486 +/* Receive Control */
1487 +#define E1000_RCTL_EN 0x00000002 /* enable */
1488 +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1489 +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1490 +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1491 +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1492 +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1493 +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1494 +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1495 +#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1496 +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1497 +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1498 +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1499 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1500 +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1501 +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1502 +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1503 +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1504 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1505 +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1506 +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1507 +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1508 +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1509 +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1510 +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1511 +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1512 +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1514 +/* Use byte values for the following shift parameters
1516 + * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1517 + * E1000_PSRCTL_BSIZE0_MASK) |
1518 + * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1519 + * E1000_PSRCTL_BSIZE1_MASK) |
1520 + * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1521 + * E1000_PSRCTL_BSIZE2_MASK) |
1522 + * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1523 + * E1000_PSRCTL_BSIZE3_MASK))
1524 + * where value0 = [128..16256], default=256
1525 + * value1 = [1024..64512], default=4096
1526 + * value2 = [0..64512], default=4096
1527 + * value3 = [0..64512], default=0
1530 +#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1531 +#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1532 +#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1533 +#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1535 +#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1536 +#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1537 +#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1538 +#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1540 +/* SWFW_SYNC Definitions */
1541 +#define E1000_SWFW_EEP_SM 0x1
1542 +#define E1000_SWFW_PHY0_SM 0x2
1543 +#define E1000_SWFW_PHY1_SM 0x4
1545 +/* Device Control */
1546 +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1547 +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1548 +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1549 +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1550 +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1551 +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1552 +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1553 +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1554 +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1555 +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1556 +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1557 +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1558 +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1559 +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1560 +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1561 +#define E1000_CTRL_RST 0x04000000 /* Global reset */
1562 +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1563 +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1564 +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1565 +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1567 +/* Bit definitions for the Management Data IO (MDIO) and Management Data
1568 + * Clock (MDC) pins in the Device Control Register.
1571 +/* Device Status */
1572 +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1573 +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1574 +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1575 +#define E1000_STATUS_FUNC_SHIFT 2
1576 +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1577 +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1578 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1579 +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1580 +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1581 +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
1582 +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1584 +/* Constants used to intrepret the masked PCI-X bus speed. */
1586 +#define HALF_DUPLEX 1
1587 +#define FULL_DUPLEX 2
1590 +#define ADVERTISE_10_HALF 0x0001
1591 +#define ADVERTISE_10_FULL 0x0002
1592 +#define ADVERTISE_100_HALF 0x0004
1593 +#define ADVERTISE_100_FULL 0x0008
1594 +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
1595 +#define ADVERTISE_1000_FULL 0x0020
1597 +/* 1000/H is not supported, nor spec-compliant. */
1598 +#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
1599 + ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
1600 + ADVERTISE_1000_FULL)
1601 +#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
1602 + ADVERTISE_100_HALF | ADVERTISE_100_FULL)
1603 +#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
1604 +#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
1605 +#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
1607 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
1610 +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1611 +#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1612 +#define E1000_LEDCTL_LED0_IVRT 0x00000040
1613 +#define E1000_LEDCTL_LED0_BLINK 0x00000080
1615 +#define E1000_LEDCTL_MODE_LED_ON 0xE
1616 +#define E1000_LEDCTL_MODE_LED_OFF 0xF
1618 +/* Transmit Descriptor bit definitions */
1619 +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
1620 +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1621 +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1622 +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
1623 +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1624 +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1625 +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
1626 +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
1627 +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1628 +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1629 +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
1630 +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1631 +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
1632 +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
1633 +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
1634 +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
1635 +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
1636 +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
1637 +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
1639 +/* Transmit Control */
1640 +#define E1000_TCTL_EN 0x00000002 /* enable tx */
1641 +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1642 +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1643 +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1644 +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1645 +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1647 +/* Transmit Arbitration Count */
1649 +/* SerDes Control */
1650 +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
1652 +/* Receive Checksum Control */
1653 +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1654 +#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1656 +/* Header split receive */
1657 +#define E1000_RFCTL_EXTEN 0x00008000
1658 +#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1659 +#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1661 +/* Collision related configuration parameters */
1662 +#define E1000_COLLISION_THRESHOLD 15
1663 +#define E1000_CT_SHIFT 4
1664 +#define E1000_COLLISION_DISTANCE 63
1665 +#define E1000_COLD_SHIFT 12
1667 +/* Default values for the transmit IPG register */
1668 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1670 +#define E1000_TIPG_IPGT_MASK 0x000003FF
1672 +#define DEFAULT_82543_TIPG_IPGR1 8
1673 +#define E1000_TIPG_IPGR1_SHIFT 10
1675 +#define DEFAULT_82543_TIPG_IPGR2 6
1676 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
1677 +#define E1000_TIPG_IPGR2_SHIFT 20
1679 +#define MAX_JUMBO_FRAME_SIZE 0x3F00
1681 +/* Extended Configuration Control and Size */
1682 +#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
1683 +#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
1684 +#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
1685 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
1686 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
1687 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
1688 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
1690 +#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1691 +#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1692 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1693 +#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1695 +#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1697 +/* PBA constants */
1698 +#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
1699 +#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1701 +#define E1000_PBS_16K E1000_PBA_16K
1705 +#define IFS_RATIO 4
1706 +#define IFS_STEP 10
1707 +#define MIN_NUM_XMITS 1000
1709 +/* SW Semaphore Register */
1710 +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1711 +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1712 +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1714 +/* Interrupt Cause Read */
1715 +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1716 +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1717 +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1718 +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1719 +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1720 +#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1722 +/* This defines the bits that are set in the Interrupt Mask
1723 + * Set/Read Register. Each bit is documented below:
1724 + * o RXT0 = Receiver Timer Interrupt (ring 0)
1725 + * o TXDW = Transmit Descriptor Written Back
1726 + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
1727 + * o RXSEQ = Receive Sequence Error
1728 + * o LSC = Link Status Change
1730 +#define IMS_ENABLE_MASK ( \
1731 + E1000_IMS_RXT0 | \
1732 + E1000_IMS_TXDW | \
1733 + E1000_IMS_RXDMT0 | \
1734 + E1000_IMS_RXSEQ | \
1737 +/* Interrupt Mask Set */
1738 +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1739 +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1740 +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1741 +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1742 +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1744 +/* Interrupt Cause Set */
1745 +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1746 +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1748 +/* Transmit Descriptor Control */
1749 +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1750 +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1751 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1752 +#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
1753 +#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1754 + still to be processed. */
1756 +/* Flow Control Constants */
1757 +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1758 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1759 +#define FLOW_CONTROL_TYPE 0x8808
1761 +/* 802.1q VLAN Packet Size */
1762 +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
1764 +/* Receive Address */
1765 +/* Number of high/low register pairs in the RAR. The RAR (Receive Address
1766 + * Registers) holds the directed and multicast addresses that we monitor.
1767 + * Technically, we have 16 spots. However, we reserve one of these spots
1768 + * (RAR[15]) for our directed address used by controllers with
1769 + * manageability enabled, allowing us room for 15 multicast addresses.
1771 +#define E1000_RAR_ENTRIES 15
1772 +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1775 +#define E1000_ERR_NVM 1
1776 +#define E1000_ERR_PHY 2
1777 +#define E1000_ERR_CONFIG 3
1778 +#define E1000_ERR_PARAM 4
1779 +#define E1000_ERR_MAC_INIT 5
1780 +#define E1000_ERR_PHY_TYPE 6
1781 +#define E1000_ERR_RESET 9
1782 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10
1783 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11
1784 +#define E1000_BLK_PHY_RESET 12
1785 +#define E1000_ERR_SWFW_SYNC 13
1786 +#define E1000_NOT_IMPLEMENTED 14
1788 +/* Loop limit on how long we wait for auto-negotiation to complete */
1789 +#define FIBER_LINK_UP_LIMIT 50
1790 +#define COPPER_LINK_UP_LIMIT 10
1791 +#define PHY_AUTO_NEG_LIMIT 45
1792 +#define PHY_FORCE_LIMIT 20
1793 +/* Number of 100 microseconds we wait for PCI Express master disable */
1794 +#define MASTER_DISABLE_TIMEOUT 800
1795 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */
1796 +#define PHY_CFG_TIMEOUT 100
1797 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
1798 +#define MDIO_OWNERSHIP_TIMEOUT 10
1799 +/* Number of milliseconds for NVM auto read done after MAC reset. */
1800 +#define AUTO_READ_DONE_TIMEOUT 10
1803 +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1805 +/* Transmit Configuration Word */
1806 +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1807 +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1808 +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1809 +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1810 +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1812 +/* Receive Configuration Word */
1813 +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1814 +#define E1000_RXCW_C 0x20000000 /* Receive config */
1815 +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1817 +/* PCI Express Control */
1818 +#define E1000_GCR_RXD_NO_SNOOP 0x00000001
1819 +#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1820 +#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1821 +#define E1000_GCR_TXD_NO_SNOOP 0x00000008
1822 +#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1823 +#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1825 +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1826 + E1000_GCR_RXDSCW_NO_SNOOP | \
1827 + E1000_GCR_RXDSCR_NO_SNOOP | \
1828 + E1000_GCR_TXD_NO_SNOOP | \
1829 + E1000_GCR_TXDSCW_NO_SNOOP | \
1830 + E1000_GCR_TXDSCR_NO_SNOOP)
1832 +/* PHY Control Register */
1833 +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1834 +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1835 +#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1836 +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1837 +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1838 +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1839 +#define MII_CR_SPEED_1000 0x0040
1840 +#define MII_CR_SPEED_100 0x2000
1841 +#define MII_CR_SPEED_10 0x0000
1843 +/* PHY Status Register */
1844 +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1845 +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1847 +/* Autoneg Advertisement Register */
1848 +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1849 +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1850 +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1851 +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1852 +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1853 +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1855 +/* Link Partner Ability Register (Base Page) */
1856 +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1857 +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1859 +/* Autoneg Expansion Register */
1861 +/* 1000BASE-T Control Register */
1862 +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1863 +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1864 + /* 0=DTE device */
1865 +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1866 + /* 0=Configure PHY as Slave */
1867 +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1868 + /* 0=Automatic Master/Slave config */
1870 +/* 1000BASE-T Status Register */
1871 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1872 +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1875 +/* PHY 1000 MII Register/Bit Definitions */
1876 +/* PHY Registers defined by IEEE */
1877 +#define PHY_CONTROL 0x00 /* Control Register */
1878 +#define PHY_STATUS 0x01 /* Status Regiser */
1879 +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1880 +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1881 +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1882 +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1883 +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1884 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1887 +#define E1000_EECD_SK 0x00000001 /* NVM Clock */
1888 +#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1889 +#define E1000_EECD_DI 0x00000004 /* NVM Data In */
1890 +#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1891 +#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1892 +#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1893 +#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1894 +#define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type
1895 + * (0-small, 1-large) */
1896 +#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1897 +#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1898 +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1899 +#define E1000_EECD_SIZE_EX_SHIFT 11
1900 +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1901 +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1902 +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1904 +#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
1905 +#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1906 +#define E1000_NVM_RW_REG_START 1 /* Start operation */
1907 +#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1908 +#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1909 +#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1910 +#define E1000_FLASH_UPDATES 2000
1912 +/* NVM Word Offsets */
1913 +#define NVM_ID_LED_SETTINGS 0x0004
1914 +#define NVM_INIT_CONTROL2_REG 0x000F
1915 +#define NVM_INIT_CONTROL3_PORT_B 0x0014
1916 +#define NVM_INIT_3GIO_3 0x001A
1917 +#define NVM_INIT_CONTROL3_PORT_A 0x0024
1918 +#define NVM_CFG 0x0012
1919 +#define NVM_CHECKSUM_REG 0x003F
1921 +#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1922 +#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1924 +/* Mask bits for fields in Word 0x0f of the NVM */
1925 +#define NVM_WORD0F_PAUSE_MASK 0x3000
1926 +#define NVM_WORD0F_PAUSE 0x1000
1927 +#define NVM_WORD0F_ASM_DIR 0x2000
1929 +/* Mask bits for fields in Word 0x1a of the NVM */
1930 +#define NVM_WORD1A_ASPM_MASK 0x000C
1932 +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1933 +#define NVM_SUM 0xBABA
1935 +#define NVM_WORD_SIZE_BASE_SHIFT 6
1937 +/* NVM Commands - Microwire */
1939 +/* NVM Commands - SPI */
1940 +#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1941 +#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1942 +#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1943 +#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1944 +#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1945 +#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1947 +/* SPI NVM Status Register */
1948 +#define NVM_STATUS_RDY_SPI 0x01
1950 +/* Word definitions for ID LED Settings */
1951 +#define ID_LED_RESERVED_0000 0x0000
1952 +#define ID_LED_RESERVED_FFFF 0xFFFF
1953 +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1954 + (ID_LED_OFF1_OFF2 << 8) | \
1955 + (ID_LED_DEF1_DEF2 << 4) | \
1956 + (ID_LED_DEF1_DEF2))
1957 +#define ID_LED_DEF1_DEF2 0x1
1958 +#define ID_LED_DEF1_ON2 0x2
1959 +#define ID_LED_DEF1_OFF2 0x3
1960 +#define ID_LED_ON1_DEF2 0x4
1961 +#define ID_LED_ON1_ON2 0x5
1962 +#define ID_LED_ON1_OFF2 0x6
1963 +#define ID_LED_OFF1_DEF2 0x7
1964 +#define ID_LED_OFF1_ON2 0x8
1965 +#define ID_LED_OFF1_OFF2 0x9
1967 +#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1968 +#define IGP_ACTIVITY_LED_ENABLE 0x0300
1969 +#define IGP_LED3_MODE 0x07000000
1971 +/* PCI/PCI-X/PCI-EX Config space */
1972 +#define PCI_HEADER_TYPE_REGISTER 0x0E
1973 +#define PCIE_LINK_STATUS 0x12
1975 +#define PCI_HEADER_TYPE_MULTIFUNC 0x80
1976 +#define PCIE_LINK_WIDTH_MASK 0x3F0
1977 +#define PCIE_LINK_WIDTH_SHIFT 4
1979 +#define PHY_REVISION_MASK 0xFFFFFFF0
1980 +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1981 +#define MAX_PHY_MULTI_PAGE_REG 0xF
1983 +/* Bit definitions for valid PHY IDs. */
1987 +#define M88E1000_E_PHY_ID 0x01410C50
1988 +#define M88E1000_I_PHY_ID 0x01410C30
1989 +#define M88E1011_I_PHY_ID 0x01410C20
1990 +#define IGP01E1000_I_PHY_ID 0x02A80380
1991 +#define M88E1111_I_PHY_ID 0x01410CC0
1992 +#define GG82563_E_PHY_ID 0x01410CA0
1993 +#define IGP03E1000_E_PHY_ID 0x02A80390
1994 +#define IFE_E_PHY_ID 0x02A80330
1995 +#define IFE_PLUS_E_PHY_ID 0x02A80320
1996 +#define IFE_C_E_PHY_ID 0x02A80310
1998 +/* M88E1000 Specific Registers */
1999 +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2000 +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2001 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2003 +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2004 +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2006 +/* M88E1000 PHY Specific Control Register */
2007 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2008 +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2009 + /* Manual MDI configuration */
2010 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2011 +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2012 + * 100BASE-TX/10BASE-T:
2015 +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2018 + /* 1=Enable Extended 10BASE-T distance
2019 + * (Lower 10BASE-T RX Threshold)
2020 + * 0=Normal 10BASE-T RX Threshold */
2021 + /* 1=5-Bit interface in 100BASE-TX
2022 + * 0=MII interface in 100BASE-TX */
2023 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2025 +/* M88E1000 PHY Specific Status Register */
2026 +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2027 +#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2028 +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2029 +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2030 + * 3=110-140M;4=>140M */
2031 +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2032 +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2034 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2036 +/* Number of times we will attempt to autonegotiate before downshifting if we
2037 + * are the master */
2038 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2039 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2040 +/* Number of times we will attempt to autonegotiate before downshifting if we
2041 + * are the slave */
2042 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2043 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2044 +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2046 +/* M88EC018 Rev 2 specific DownShift settings */
2047 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2048 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2052 + * 4-0: register offset
2054 +#define GG82563_PAGE_SHIFT 5
2055 +#define GG82563_REG(page, reg) \
2056 + (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2057 +#define GG82563_MIN_ALT_REG 30
2059 +/* GG82563 Specific Registers */
2060 +#define GG82563_PHY_SPEC_CTRL \
2061 + GG82563_REG(0, 16) /* PHY Specific Control */
2062 +#define GG82563_PHY_PAGE_SELECT \
2063 + GG82563_REG(0, 22) /* Page Select */
2064 +#define GG82563_PHY_SPEC_CTRL_2 \
2065 + GG82563_REG(0, 26) /* PHY Specific Control 2 */
2066 +#define GG82563_PHY_PAGE_SELECT_ALT \
2067 + GG82563_REG(0, 29) /* Alternate Page Select */
2069 +#define GG82563_PHY_MAC_SPEC_CTRL \
2070 + GG82563_REG(2, 21) /* MAC Specific Control Register */
2072 +#define GG82563_PHY_DSP_DISTANCE \
2073 + GG82563_REG(5, 26) /* DSP Distance */
2075 +/* Page 193 - Port Control Registers */
2076 +#define GG82563_PHY_KMRN_MODE_CTRL \
2077 + GG82563_REG(193, 16) /* Kumeran Mode Control */
2078 +#define GG82563_PHY_PWR_MGMT_CTRL \
2079 + GG82563_REG(193, 20) /* Power Management Control */
2081 +/* Page 194 - KMRN Registers */
2082 +#define GG82563_PHY_INBAND_CTRL \
2083 + GG82563_REG(194, 18) /* Inband Control */
2086 +#define E1000_MDIC_REG_SHIFT 16
2087 +#define E1000_MDIC_PHY_SHIFT 21
2088 +#define E1000_MDIC_OP_WRITE 0x04000000
2089 +#define E1000_MDIC_OP_READ 0x08000000
2090 +#define E1000_MDIC_READY 0x10000000
2091 +#define E1000_MDIC_ERROR 0x40000000
2093 +/* SerDes Control */
2094 +#define E1000_GEN_POLL_TIMEOUT 640
2096 +#endif /* _E1000_DEFINES_H_ */
2097 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000.h linux-2.6.22-10/drivers/net/e1000e/e1000.h
2098 --- linux-2.6.22-0/drivers/net/e1000e/e1000.h 1969-12-31 19:00:00.000000000 -0500
2099 +++ linux-2.6.22-10/drivers/net/e1000e/e1000.h 2007-11-21 13:55:34.000000000 -0500
2101 +/*******************************************************************************
2103 + Intel PRO/1000 Linux driver
2104 + Copyright(c) 1999 - 2007 Intel Corporation.
2106 + This program is free software; you can redistribute it and/or modify it
2107 + under the terms and conditions of the GNU General Public License,
2108 + version 2, as published by the Free Software Foundation.
2110 + This program is distributed in the hope it will be useful, but WITHOUT
2111 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2112 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2115 + You should have received a copy of the GNU General Public License along with
2116 + this program; if not, write to the Free Software Foundation, Inc.,
2117 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2119 + The full GNU General Public License is included in this distribution in
2120 + the file called "COPYING".
2122 + Contact Information:
2123 + Linux NICS <linux.nics@intel.com>
2124 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
2125 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
2127 +*******************************************************************************/
2129 +/* Linux PRO/1000 Ethernet Driver main header file */
2134 +#include <linux/types.h>
2135 +#include <linux/timer.h>
2136 +#include <linux/workqueue.h>
2137 +#include <linux/io.h>
2138 +#include <linux/netdevice.h>
2144 +#define ndev_printk(level, netdev, format, arg...) \
2145 + printk(level "%s: %s: " format, (netdev)->dev.parent->bus_id, \
2146 + (netdev)->name, ## arg)
2149 +#define ndev_dbg(netdev, format, arg...) \
2150 + ndev_printk(KERN_DEBUG , netdev, format, ## arg)
2152 +#define ndev_dbg(netdev, format, arg...) do { (void)(netdev); } while (0)
2155 +#define ndev_err(netdev, format, arg...) \
2156 + ndev_printk(KERN_ERR , netdev, format, ## arg)
2157 +#define ndev_info(netdev, format, arg...) \
2158 + ndev_printk(KERN_INFO , netdev, format, ## arg)
2159 +#define ndev_warn(netdev, format, arg...) \
2160 + ndev_printk(KERN_WARNING , netdev, format, ## arg)
2161 +#define ndev_notice(netdev, format, arg...) \
2162 + ndev_printk(KERN_NOTICE , netdev, format, ## arg)
2165 +/* TX/RX descriptor defines */
2166 +#define E1000_DEFAULT_TXD 256
2167 +#define E1000_MAX_TXD 4096
2168 +#define E1000_MIN_TXD 80
2170 +#define E1000_DEFAULT_RXD 256
2171 +#define E1000_MAX_RXD 4096
2172 +#define E1000_MIN_RXD 80
2174 +/* Early Receive defines */
2175 +#define E1000_ERT_2048 0x100
2177 +#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
2179 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
2180 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
2181 +#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
2183 +#define AUTO_ALL_MODES 0
2184 +#define E1000_EEPROM_APME 0x0400
2186 +#define E1000_MNG_VLAN_NONE (-1)
2188 +/* Number of packet split data buffers (not including the header buffer) */
2189 +#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
2191 +enum e1000_boards {
2195 + board_80003es2lan,
2200 +struct e1000_queue_stats {
2205 +struct e1000_ps_page {
2206 + struct page *page;
2207 + u64 dma; /* must be u64 - written to hw */
2211 + * wrappers around a pointer to a socket buffer,
2212 + * so a DMA handle can be stored along with the buffer
2214 +struct e1000_buffer {
2216 + struct sk_buff *skb;
2220 + unsigned long time_stamp;
2222 + u16 next_to_watch;
2225 + struct page *page;
2230 +struct e1000_ring {
2231 + void *desc; /* pointer to ring memory */
2232 + dma_addr_t dma; /* phys address of ring */
2233 + unsigned int size; /* length of ring in bytes */
2234 + unsigned int count; /* number of desc. in ring */
2237 + u16 next_to_clean;
2242 + /* array of buffer information structs */
2243 + struct e1000_buffer *buffer_info;
2248 + bool last_tx_tso; /* used to mark tso desc. */
2252 + /* arrays of page information for packet split */
2253 + struct e1000_ps_page *ps_pages;
2254 + struct sk_buff *rx_skb_top;
2258 + struct e1000_queue_stats stats;
2261 +/* board specific private data structure */
2262 +struct e1000_adapter {
2263 + struct timer_list watchdog_timer;
2264 + struct timer_list phy_info_timer;
2265 + struct timer_list blink_timer;
2267 + struct work_struct reset_task;
2268 + struct work_struct watchdog_task;
2270 + const struct e1000_info *ei;
2272 + struct vlan_group *vlgrp;
2274 + u32 rx_buffer_len;
2279 + spinlock_t tx_queue_lock; /* prevent concurrent tail updates */
2281 + /* this is still needed for 82571 and above */
2284 + /* track device up/down/testing state */
2285 + unsigned long state;
2287 + /* Interrupt Throttle Rate */
2296 + struct e1000_ring *tx_ring /* One per active queue */
2297 + ____cacheline_aligned_in_smp;
2299 + unsigned long tx_queue_len;
2300 + unsigned int restart_queue;
2303 + bool detect_tx_hung;
2304 + u8 tx_timeout_factor;
2307 + u32 tx_abs_int_delay;
2309 + unsigned int total_tx_bytes;
2310 + unsigned int total_tx_packets;
2311 + unsigned int total_rx_bytes;
2312 + unsigned int total_rx_packets;
2319 + u32 tx_timeout_count;
2323 + u32 tx_dma_failed;
2328 + bool (*clean_rx) (struct e1000_adapter *adapter,
2329 + int *work_done, int work_to_do)
2330 + ____cacheline_aligned_in_smp;
2331 + void (*alloc_rx_buf) (struct e1000_adapter *adapter,
2332 + int cleaned_count);
2333 + struct e1000_ring *rx_ring;
2336 + u32 rx_abs_int_delay;
2344 + u32 alloc_rx_buff_failed;
2345 + u32 rx_dma_failed;
2347 + unsigned int rx_ps_pages;
2350 + /* OS defined structs */
2351 + struct net_device *netdev;
2352 + struct pci_dev *pdev;
2353 + struct net_device_stats net_stats;
2354 + spinlock_t stats_lock; /* prevent concurrent stats updates */
2356 + /* structs defined in e1000_hw.h */
2357 + struct e1000_hw hw;
2359 + struct e1000_hw_stats stats;
2360 + struct e1000_phy_info phy_info;
2361 + struct e1000_phy_stats phy_stats;
2363 + struct e1000_ring test_tx_ring;
2364 + struct e1000_ring test_rx_ring;
2375 + unsigned long led_status;
2377 + unsigned int flags;
2380 +struct e1000_info {
2381 + enum e1000_mac_type mac;
2382 + unsigned int flags;
2384 + s32 (*get_invariants)(struct e1000_adapter *);
2385 + struct e1000_mac_operations *mac_ops;
2386 + struct e1000_phy_operations *phy_ops;
2387 + struct e1000_nvm_operations *nvm_ops;
2390 +/* hardware capability, feature, and workaround flags */
2391 +#define FLAG_HAS_AMT (1 << 0)
2392 +#define FLAG_HAS_FLASH (1 << 1)
2393 +#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
2394 +#define FLAG_HAS_WOL (1 << 3)
2395 +#define FLAG_HAS_ERT (1 << 4)
2396 +#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
2397 +#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
2398 +#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
2399 +#define FLAG_HAS_ASPM (1 << 8)
2400 +#define FLAG_HAS_STATS_ICR_ICT (1 << 9)
2401 +#define FLAG_HAS_STATS_PTC_PRC (1 << 10)
2402 +#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
2403 +#define FLAG_IS_QUAD_PORT_A (1 << 12)
2404 +#define FLAG_IS_QUAD_PORT (1 << 13)
2405 +#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
2406 +#define FLAG_APME_IN_WUC (1 << 15)
2407 +#define FLAG_APME_IN_CTRL3 (1 << 16)
2408 +#define FLAG_APME_CHECK_PORT_B (1 << 17)
2409 +#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
2410 +#define FLAG_NO_WAKE_UCAST (1 << 19)
2411 +#define FLAG_MNG_PT_ENABLED (1 << 20)
2412 +#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
2413 +#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
2414 +#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
2415 +#define FLAG_RX_NEEDS_RESTART (1 << 24)
2416 +#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
2417 +#define FLAG_SMART_POWER_DOWN (1 << 26)
2418 +#define FLAG_MSI_ENABLED (1 << 27)
2419 +#define FLAG_RX_CSUM_ENABLED (1 << 28)
2420 +#define FLAG_TSO_FORCE (1 << 29)
2422 +#define E1000_RX_DESC_PS(R, i) \
2423 + (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
2424 +#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
2425 +#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
2426 +#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
2427 +#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
2429 +enum e1000_state_t {
2431 + __E1000_RESETTING,
2435 +enum latency_range {
2436 + lowest_latency = 0,
2439 + latency_invalid = 255
2442 +extern char e1000e_driver_name[];
2443 +extern const char e1000e_driver_version[];
2445 +extern void e1000e_check_options(struct e1000_adapter *adapter);
2446 +extern void e1000e_set_ethtool_ops(struct net_device *netdev);
2448 +extern int e1000e_up(struct e1000_adapter *adapter);
2449 +extern void e1000e_down(struct e1000_adapter *adapter);
2450 +extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
2451 +extern void e1000e_reset(struct e1000_adapter *adapter);
2452 +extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
2453 +extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
2454 +extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
2455 +extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
2456 +extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
2457 +extern void e1000e_update_stats(struct e1000_adapter *adapter);
2459 +extern unsigned int copybreak;
2461 +extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
2463 +extern struct e1000_info e1000_82571_info;
2464 +extern struct e1000_info e1000_82572_info;
2465 +extern struct e1000_info e1000_82573_info;
2466 +extern struct e1000_info e1000_ich8_info;
2467 +extern struct e1000_info e1000_ich9_info;
2468 +extern struct e1000_info e1000_es2_info;
2470 +extern s32 e1000e_commit_phy(struct e1000_hw *hw);
2472 +extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
2474 +extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
2475 +extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
2477 +extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2479 +extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
2480 +extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
2482 +extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
2483 +extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
2484 +extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
2485 +extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
2486 +extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
2487 +extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
2488 +extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
2489 +extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
2490 +extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
2491 +extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
2492 +extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
2493 +extern s32 e1000e_id_led_init(struct e1000_hw *hw);
2494 +extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
2495 +extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
2496 +extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
2497 +extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
2498 +extern s32 e1000e_setup_link(struct e1000_hw *hw);
2499 +extern void e1000e_clear_vfta(struct e1000_hw *hw);
2500 +extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
2501 +extern void e1000e_mc_addr_list_update_generic(struct e1000_hw *hw,
2502 + u8 *mc_addr_list, u32 mc_addr_count,
2503 + u32 rar_used_count, u32 rar_count);
2504 +extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
2505 +extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
2506 +extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
2507 +extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
2508 +extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
2509 +extern void e1000e_config_collision_dist(struct e1000_hw *hw);
2510 +extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
2511 +extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
2512 +extern s32 e1000e_blink_led(struct e1000_hw *hw);
2513 +extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
2514 +extern void e1000e_reset_adaptive(struct e1000_hw *hw);
2515 +extern void e1000e_update_adaptive(struct e1000_hw *hw);
2517 +extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
2518 +extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
2519 +extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
2520 +extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
2521 +extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
2522 +extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
2523 +extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
2524 +extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
2525 +extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
2526 +extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
2527 +extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
2528 +extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
2529 +extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
2530 +extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
2531 +extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
2532 +extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
2533 +extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
2534 +extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
2535 +extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
2536 +extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
2537 +extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
2538 +extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
2539 +extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2540 + u32 usec_interval, bool *success);
2541 +extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
2542 +extern s32 e1000e_check_downshift(struct e1000_hw *hw);
2544 +static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
2546 + return hw->phy.ops.reset_phy(hw);
2549 +static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
2551 + return hw->phy.ops.check_reset_block(hw);
2554 +static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
2556 + return hw->phy.ops.read_phy_reg(hw, offset, data);
2559 +static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
2561 + return hw->phy.ops.write_phy_reg(hw, offset, data);
2564 +static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
2566 + return hw->phy.ops.get_cable_length(hw);
2569 +extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
2570 +extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
2571 +extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
2572 +extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
2573 +extern s32 e1000e_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
2574 +extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
2575 +extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
2576 +extern void e1000e_release_nvm(struct e1000_hw *hw);
2577 +extern void e1000e_reload_nvm(struct e1000_hw *hw);
2578 +extern s32 e1000e_read_mac_addr(struct e1000_hw *hw);
2580 +static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
2582 + return hw->nvm.ops.validate_nvm(hw);
2585 +static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
2587 + return hw->nvm.ops.update_nvm(hw);
2590 +static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2592 + return hw->nvm.ops.read_nvm(hw, offset, words, data);
2595 +static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2597 + return hw->nvm.ops.write_nvm(hw, offset, words, data);
2600 +static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
2602 + return hw->phy.ops.get_phy_info(hw);
2605 +extern bool e1000e_check_mng_mode(struct e1000_hw *hw);
2606 +extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
2607 +extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
2609 +static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
2611 + return readl(hw->hw_addr + reg);
2614 +static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
2616 + writel(val, hw->hw_addr + reg);
2619 +#endif /* _E1000_H_ */
2620 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/es2lan.c linux-2.6.22-10/drivers/net/e1000e/es2lan.c
2621 --- linux-2.6.22-0/drivers/net/e1000e/es2lan.c 1969-12-31 19:00:00.000000000 -0500
2622 +++ linux-2.6.22-10/drivers/net/e1000e/es2lan.c 2007-11-21 13:55:28.000000000 -0500
2624 +/*******************************************************************************
2626 + Intel PRO/1000 Linux driver
2627 + Copyright(c) 1999 - 2007 Intel Corporation.
2629 + This program is free software; you can redistribute it and/or modify it
2630 + under the terms and conditions of the GNU General Public License,
2631 + version 2, as published by the Free Software Foundation.
2633 + This program is distributed in the hope it will be useful, but WITHOUT
2634 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2635 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2638 + You should have received a copy of the GNU General Public License along with
2639 + this program; if not, write to the Free Software Foundation, Inc.,
2640 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2642 + The full GNU General Public License is included in this distribution in
2643 + the file called "COPYING".
2645 + Contact Information:
2646 + Linux NICS <linux.nics@intel.com>
2647 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
2648 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
2650 +*******************************************************************************/
2653 + * 80003ES2LAN Gigabit Ethernet Controller (Copper)
2654 + * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
2657 +#include <linux/netdevice.h>
2658 +#include <linux/ethtool.h>
2659 +#include <linux/delay.h>
2660 +#include <linux/pci.h>
2664 +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
2665 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
2666 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
2668 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
2669 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
2670 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
2672 +#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
2673 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
2675 +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2676 +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
2678 +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
2679 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
2681 +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2682 +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
2683 +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2684 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
2685 +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
2686 +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
2688 +/* PHY Specific Control Register 2 (Page 0, Register 26) */
2689 +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
2690 + /* 1=Reverse Auto-Negotiation */
2692 +/* MAC Specific Control Register (Page 2, Register 21) */
2693 +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2694 +#define GG82563_MSCR_TX_CLK_MASK 0x0007
2695 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
2696 +#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
2697 +#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
2699 +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2701 +/* DSP Distance Register (Page 5, Register 26) */
2702 +#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
2708 +/* Kumeran Mode Control Register (Page 193, Register 16) */
2709 +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2711 +/* Power Management Control Register (Page 193, Register 20) */
2712 +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
2713 + /* 1=Enable SERDES Electrical Idle */
2715 +/* In-Band Control Register (Page 194, Register 18) */
2716 +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
2718 +/* A table for the GG82563 cable length where the range is defined
2719 + * with a lower bound at "index" and the upper bound at
2722 +static const u16 e1000_gg82563_cable_length_table[] =
2723 + { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
2725 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
2726 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
2727 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
2728 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
2729 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
2730 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
2731 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
2734 + * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
2735 + * @hw: pointer to the HW structure
2737 + * This is a function pointer entry point called by the api module.
2739 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
2741 + struct e1000_phy_info *phy = &hw->phy;
2744 + if (hw->media_type != e1000_media_type_copper) {
2745 + phy->type = e1000_phy_none;
2750 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2751 + phy->reset_delay_us = 100;
2752 + phy->type = e1000_phy_gg82563;
2754 + /* This can only be done after all function pointers are setup. */
2755 + ret_val = e1000e_get_phy_id(hw);
2757 + /* Verify phy id */
2758 + if (phy->id != GG82563_E_PHY_ID)
2759 + return -E1000_ERR_PHY;
2765 + * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
2766 + * @hw: pointer to the HW structure
2768 + * This is a function pointer entry point called by the api module.
2770 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
2772 + struct e1000_nvm_info *nvm = &hw->nvm;
2773 + u32 eecd = er32(EECD);
2776 + nvm->opcode_bits = 8;
2777 + nvm->delay_usec = 1;
2778 + switch (nvm->override) {
2779 + case e1000_nvm_override_spi_large:
2780 + nvm->page_size = 32;
2781 + nvm->address_bits = 16;
2783 + case e1000_nvm_override_spi_small:
2784 + nvm->page_size = 8;
2785 + nvm->address_bits = 8;
2788 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
2789 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
2793 + nvm->type = e1000_nvm_eeprom_spi;
2795 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
2796 + E1000_EECD_SIZE_EX_SHIFT);
2798 + /* Added to a constant, "size" becomes the left-shift value
2799 + * for setting word_size.
2801 + size += NVM_WORD_SIZE_BASE_SHIFT;
2802 + nvm->word_size = 1 << size;
2808 + * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
2809 + * @hw: pointer to the HW structure
2811 + * This is a function pointer entry point called by the api module.
2813 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
2815 + struct e1000_hw *hw = &adapter->hw;
2816 + struct e1000_mac_info *mac = &hw->mac;
2817 + struct e1000_mac_operations *func = &mac->ops;
2819 + /* Set media type */
2820 + switch (adapter->pdev->device) {
2821 + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
2822 + hw->media_type = e1000_media_type_internal_serdes;
2825 + hw->media_type = e1000_media_type_copper;
2829 + /* Set mta register count */
2830 + mac->mta_reg_count = 128;
2831 + /* Set rar entry count */
2832 + mac->rar_entry_count = E1000_RAR_ENTRIES;
2833 + /* Set if manageability features are enabled. */
2834 + mac->arc_subsystem_valid =
2835 + (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
2837 + /* check for link */
2838 + switch (hw->media_type) {
2839 + case e1000_media_type_copper:
2840 + func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
2841 + func->check_for_link = e1000e_check_for_copper_link;
2843 + case e1000_media_type_fiber:
2844 + func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
2845 + func->check_for_link = e1000e_check_for_fiber_link;
2847 + case e1000_media_type_internal_serdes:
2848 + func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
2849 + func->check_for_link = e1000e_check_for_serdes_link;
2852 + return -E1000_ERR_CONFIG;
2859 +static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter)
2861 + struct e1000_hw *hw = &adapter->hw;
2864 + rc = e1000_init_mac_params_80003es2lan(adapter);
2868 + rc = e1000_init_nvm_params_80003es2lan(hw);
2872 + rc = e1000_init_phy_params_80003es2lan(hw);
2880 + * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
2881 + * @hw: pointer to the HW structure
2883 + * A wrapper to acquire access rights to the correct PHY. This is a
2884 + * function pointer entry point called by the api module.
2886 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
2890 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
2892 + return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
2896 + * e1000_release_phy_80003es2lan - Release rights to access PHY
2897 + * @hw: pointer to the HW structure
2899 + * A wrapper to release access rights to the correct PHY. This is a
2900 + * function pointer entry point called by the api module.
2902 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
2906 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
2907 + e1000_release_swfw_sync_80003es2lan(hw, mask);
2911 + * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
2912 + * @hw: pointer to the HW structure
2914 + * Acquire the semaphore to access the EEPROM. This is a function
2915 + * pointer entry point called by the api module.
2917 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
2921 + ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
2925 + ret_val = e1000e_acquire_nvm(hw);
2928 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
2934 + * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
2935 + * @hw: pointer to the HW structure
2937 + * Release the semaphore used to access the EEPROM. This is a
2938 + * function pointer entry point called by the api module.
2940 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
2942 + e1000e_release_nvm(hw);
2943 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
2947 + * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
2948 + * @hw: pointer to the HW structure
2949 + * @mask: specifies which semaphore to acquire
2951 + * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
2952 + * will also specify which port we're acquiring the lock for.
2954 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
2957 + u32 swmask = mask;
2958 + u32 fwmask = mask << 16;
2960 + s32 timeout = 200;
2962 + while (i < timeout) {
2963 + if (e1000e_get_hw_semaphore(hw))
2964 + return -E1000_ERR_SWFW_SYNC;
2966 + swfw_sync = er32(SW_FW_SYNC);
2967 + if (!(swfw_sync & (fwmask | swmask)))
2970 + /* Firmware currently using resource (fwmask)
2971 + * or other software thread using resource (swmask) */
2972 + e1000e_put_hw_semaphore(hw);
2977 + if (i == timeout) {
2979 + "Driver can't access resource, SW_FW_SYNC timeout.\n");
2980 + return -E1000_ERR_SWFW_SYNC;
2983 + swfw_sync |= swmask;
2984 + ew32(SW_FW_SYNC, swfw_sync);
2986 + e1000e_put_hw_semaphore(hw);
2992 + * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
2993 + * @hw: pointer to the HW structure
2994 + * @mask: specifies which semaphore to acquire
2996 + * Release the SW/FW semaphore used to access the PHY or NVM. The mask
2997 + * will also specify which port we're releasing the lock for.
2999 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
3003 + while (e1000e_get_hw_semaphore(hw) != 0);
3006 + swfw_sync = er32(SW_FW_SYNC);
3007 + swfw_sync &= ~mask;
3008 + ew32(SW_FW_SYNC, swfw_sync);
3010 + e1000e_put_hw_semaphore(hw);
3014 + * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
3015 + * @hw: pointer to the HW structure
3016 + * @offset: offset of the register to read
3017 + * @data: pointer to the data returned from the operation
3019 + * Read the GG82563 PHY register. This is a function pointer entry
3020 + * point called by the api module.
3022 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
3023 + u32 offset, u16 *data)
3029 + /* Select Configuration Page */
3030 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
3031 + page_select = GG82563_PHY_PAGE_SELECT;
3033 + /* Use Alternative Page Select register to access
3034 + * registers 30 and 31
3036 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
3038 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
3039 + ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
3043 + /* The "ready" bit in the MDIC register may be incorrectly set
3044 + * before the device has completed the "Page Select" MDI
3045 + * transaction. So we wait 200us after each MDI command...
3049 + /* ...and verify the command was successful. */
3050 + ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
3052 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
3053 + ret_val = -E1000_ERR_PHY;
3059 + ret_val = e1000e_read_phy_reg_m88(hw,
3060 + MAX_PHY_REG_ADDRESS & offset,
3069 + * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
3070 + * @hw: pointer to the HW structure
3071 + * @offset: offset of the register to read
3072 + * @data: value to write to the register
3074 + * Write to the GG82563 PHY register. This is a function pointer entry
3075 + * point called by the api module.
3077 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
3078 + u32 offset, u16 data)
3084 + /* Select Configuration Page */
3085 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
3086 + page_select = GG82563_PHY_PAGE_SELECT;
3088 + /* Use Alternative Page Select register to access
3089 + * registers 30 and 31
3091 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
3093 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
3094 + ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
3099 + /* The "ready" bit in the MDIC register may be incorrectly set
3100 + * before the device has completed the "Page Select" MDI
3101 + * transaction. So we wait 200us after each MDI command...
3105 + /* ...and verify the command was successful. */
3106 + ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
3108 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
3109 + return -E1000_ERR_PHY;
3113 + ret_val = e1000e_write_phy_reg_m88(hw,
3114 + MAX_PHY_REG_ADDRESS & offset,
3123 + * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
3124 + * @hw: pointer to the HW structure
3125 + * @offset: offset of the register to read
3126 + * @words: number of words to write
3127 + * @data: buffer of data to write to the NVM
3129 + * Write "words" of data to the ESB2 NVM. This is a function
3130 + * pointer entry point called by the api module.
3132 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
3133 + u16 words, u16 *data)
3135 + return e1000e_write_nvm_spi(hw, offset, words, data);
3139 + * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
3140 + * @hw: pointer to the HW structure
3142 + * Wait a specific amount of time for manageability processes to complete.
3143 + * This is a function pointer entry point called by the phy module.
3145 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
3147 + s32 timeout = PHY_CFG_TIMEOUT;
3148 + u32 mask = E1000_NVM_CFG_DONE_PORT_0;
3150 + if (hw->bus.func == 1)
3151 + mask = E1000_NVM_CFG_DONE_PORT_1;
3154 + if (er32(EEMNGCTL) & mask)
3160 + hw_dbg(hw, "MNG configuration cycle has not completed.\n");
3161 + return -E1000_ERR_RESET;
3168 + * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
3169 + * @hw: pointer to the HW structure
3171 + * Force the speed and duplex settings onto the PHY. This is a
3172 + * function pointer entry point called by the phy module.
3174 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
3180 + /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
3181 + * forced whenever speed and duplex are forced.
3183 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3187 + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
3188 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
3192 + hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
3194 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3198 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3200 + /* Reset the phy to commit changes. */
3201 + phy_data |= MII_CR_RESET;
3203 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3209 + if (hw->phy.wait_for_link) {
3210 + hw_dbg(hw, "Waiting for forced speed/duplex link "
3211 + "on GG82563 phy.\n");
3213 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3219 + /* We didn't get link.
3220 + * Reset the DSP and cross our fingers.
3222 + ret_val = e1000e_phy_reset_dsp(hw);
3227 + /* Try once more */
3228 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3234 + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
3238 + /* Resetting the phy means we need to verify the TX_CLK corresponds
3239 + * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
3241 + phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
3242 + if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
3243 + phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
3245 + phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
3247 + /* In addition, we must re-enable CRS on Tx for both half and full
3250 + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
3251 + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
3257 + * e1000_get_cable_length_80003es2lan - Set approximate cable length
3258 + * @hw: pointer to the HW structure
3260 + * Find the approximate cable length as measured by the GG82563 PHY.
3261 + * This is a function pointer entry point called by the phy module.
3263 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
3265 + struct e1000_phy_info *phy = &hw->phy;
3270 + ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
3274 + index = phy_data & GG82563_DSPD_CABLE_LENGTH;
3275 + phy->min_cable_length = e1000_gg82563_cable_length_table[index];
3276 + phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
3278 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
3284 + * e1000_get_link_up_info_80003es2lan - Report speed and duplex
3285 + * @hw: pointer to the HW structure
3286 + * @speed: pointer to speed buffer
3287 + * @duplex: pointer to duplex buffer
3289 + * Retrieve the current speed and duplex configuration.
3290 + * This is a function pointer entry point called by the api module.
3292 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
3297 + if (hw->media_type == e1000_media_type_copper) {
3298 + ret_val = e1000e_get_speed_and_duplex_copper(hw,
3303 + if (*speed == SPEED_1000)
3304 + ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
3306 + ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
3309 + ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
3318 + * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
3319 + * @hw: pointer to the HW structure
3321 + * Perform a global reset to the ESB2 controller.
3322 + * This is a function pointer entry point called by the api module.
3324 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
3330 + /* Prevent the PCI-E bus from sticking if there is no TLP connection
3331 + * on the last TLP read/write transaction when MAC is reset.
3333 + ret_val = e1000e_disable_pcie_master(hw);
3335 + hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
3337 + hw_dbg(hw, "Masking off all interrupts\n");
3338 + ew32(IMC, 0xffffffff);
3341 + ew32(TCTL, E1000_TCTL_PSP);
3346 + ctrl = er32(CTRL);
3348 + hw_dbg(hw, "Issuing a global reset to MAC\n");
3349 + ew32(CTRL, ctrl | E1000_CTRL_RST);
3351 + ret_val = e1000e_get_auto_rd_done(hw);
3353 + /* We don't want to continue accessing MAC registers. */
3356 + /* Clear any pending interrupt events. */
3357 + ew32(IMC, 0xffffffff);
3364 + * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
3365 + * @hw: pointer to the HW structure
3367 + * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
3368 + * This is a function pointer entry point called by the api module.
3370 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
3372 + struct e1000_mac_info *mac = &hw->mac;
3377 + e1000_initialize_hw_bits_80003es2lan(hw);
3379 + /* Initialize identification LED */
3380 + ret_val = e1000e_id_led_init(hw);
3382 + hw_dbg(hw, "Error initializing identification LED\n");
3386 + /* Disabling VLAN filtering */
3387 + hw_dbg(hw, "Initializing the IEEE VLAN\n");
3388 + e1000e_clear_vfta(hw);
3390 + /* Setup the receive address. */
3391 + e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3393 + /* Zero out the Multicast HASH table */
3394 + hw_dbg(hw, "Zeroing the MTA\n");
3395 + for (i = 0; i < mac->mta_reg_count; i++)
3396 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3398 + /* Setup link and flow control */
3399 + ret_val = e1000e_setup_link(hw);
3401 + /* Set the transmit descriptor write-back policy */
3402 + reg_data = er32(TXDCTL);
3403 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
3404 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
3405 + ew32(TXDCTL, reg_data);
3407 + /* ...for both queues. */
3408 + reg_data = er32(TXDCTL1);
3409 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
3410 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
3411 + ew32(TXDCTL1, reg_data);
3413 + /* Enable retransmit on late collisions */
3414 + reg_data = er32(TCTL);
3415 + reg_data |= E1000_TCTL_RTLC;
3416 + ew32(TCTL, reg_data);
3418 + /* Configure Gigabit Carry Extend Padding */
3419 + reg_data = er32(TCTL_EXT);
3420 + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
3421 + reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
3422 + ew32(TCTL_EXT, reg_data);
3424 + /* Configure Transmit Inter-Packet Gap */
3425 + reg_data = er32(TIPG);
3426 + reg_data &= ~E1000_TIPG_IPGT_MASK;
3427 + reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
3428 + ew32(TIPG, reg_data);
3430 + reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
3431 + reg_data &= ~0x00100000;
3432 + E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
3434 + /* Clear all of the statistics registers (clear on read). It is
3435 + * important that we do this after we have tried to establish link
3436 + * because the symbol error count will increment wildly if there
3439 + e1000_clear_hw_cntrs_80003es2lan(hw);
3445 + * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
3446 + * @hw: pointer to the HW structure
3448 + * Initializes required hardware-dependent bits needed for normal operation.
3450 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
3454 + /* Transmit Descriptor Control 0 */
3455 + reg = er32(TXDCTL);
3457 + ew32(TXDCTL, reg);
3459 + /* Transmit Descriptor Control 1 */
3460 + reg = er32(TXDCTL1);
3462 + ew32(TXDCTL1, reg);
3464 + /* Transmit Arbitration Control 0 */
3465 + reg = er32(TARC0);
3466 + reg &= ~(0xF << 27); /* 30:27 */
3467 + if (hw->media_type != e1000_media_type_copper)
3468 + reg &= ~(1 << 20);
3471 + /* Transmit Arbitration Control 1 */
3472 + reg = er32(TARC1);
3473 + if (er32(TCTL) & E1000_TCTL_MULR)
3474 + reg &= ~(1 << 28);
3481 + * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
3482 + * @hw: pointer to the HW structure
3484 + * Setup some GG82563 PHY registers for obtaining link
3486 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
3488 + struct e1000_phy_info *phy = &hw->phy;
3493 + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
3498 + data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
3499 + /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
3500 + data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
3502 + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
3508 + * MDI/MDI-X = 0 (default)
3509 + * 0 - Auto for all speeds
3512 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3514 + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
3518 + data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
3520 + switch (phy->mdix) {
3522 + data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
3525 + data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
3529 + data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
3534 + * disable_polarity_correction = 0 (default)
3535 + * Automatic Correction for Reversed Cable Polarity
3539 + data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
3540 + if (phy->disable_polarity_correction)
3541 + data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
3543 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
3547 + /* SW Reset the PHY so all changes take effect */
3548 + ret_val = e1000e_commit_phy(hw);
3550 + hw_dbg(hw, "Error Resetting the PHY\n");
3554 + /* Bypass RX and TX FIFO's */
3555 + ret_val = e1000e_write_kmrn_reg(hw,
3556 + E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
3557 + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
3558 + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
3562 + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
3566 + data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
3567 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
3571 + ctrl_ext = er32(CTRL_EXT);
3572 + ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
3573 + ew32(CTRL_EXT, ctrl_ext);
3575 + ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
3579 + /* Do not init these registers when the HW is in IAMT mode, since the
3580 + * firmware will have already initialized them. We only initialize
3581 + * them if the HW is not in IAMT mode.
3583 + if (!e1000e_check_mng_mode(hw)) {
3584 + /* Enable Electrical Idle on the PHY */
3585 + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
3586 + ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
3590 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
3594 + data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3595 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
3600 + /* Workaround: Disable padding in Kumeran interface in the MAC
3601 + * and in the PHY to avoid CRC errors.
3603 + ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
3607 + data |= GG82563_ICR_DIS_PADDING;
3608 + ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
3616 + * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
3617 + * @hw: pointer to the HW structure
3619 + * Essentially a wrapper for setting up all things "copper" related.
3620 + * This is a function pointer entry point called by the mac module.
3622 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
3628 + ctrl = er32(CTRL);
3629 + ctrl |= E1000_CTRL_SLU;
3630 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3633 + /* Set the mac to wait the maximum time between each
3634 + * iteration and increase the max iterations when
3635 + * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3636 + ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
3639 + ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
3643 + ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
3646 + ret_val = e1000e_read_kmrn_reg(hw,
3647 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
3651 + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
3652 + ret_val = e1000e_write_kmrn_reg(hw,
3653 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
3658 + ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
3662 + ret_val = e1000e_setup_copper_link(hw);
3668 + * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
3669 + * @hw: pointer to the HW structure
3670 + * @duplex: current duplex setting
3672 + * Configure the KMRN interface by applying last minute quirks for
3673 + * 10/100 operation.
3675 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
3681 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
3682 + ret_val = e1000e_write_kmrn_reg(hw,
3683 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
3688 + /* Configure Transmit Inter-Packet Gap */
3689 + tipg = er32(TIPG);
3690 + tipg &= ~E1000_TIPG_IPGT_MASK;
3691 + tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
3694 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3698 + if (duplex == HALF_DUPLEX)
3699 + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3701 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3703 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3709 + * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
3710 + * @hw: pointer to the HW structure
3712 + * Configure the KMRN interface by applying last minute quirks for
3713 + * gigabit operation.
3715 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
3721 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
3722 + ret_val = e1000e_write_kmrn_reg(hw,
3723 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
3728 + /* Configure Transmit Inter-Packet Gap */
3729 + tipg = er32(TIPG);
3730 + tipg &= ~E1000_TIPG_IPGT_MASK;
3731 + tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
3734 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3738 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3739 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3745 + * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
3746 + * @hw: pointer to the HW structure
3748 + * Clears the hardware counters by reading the counter registers.
3750 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
3754 + e1000e_clear_hw_cntrs_base(hw);
3756 + temp = er32(PRC64);
3757 + temp = er32(PRC127);
3758 + temp = er32(PRC255);
3759 + temp = er32(PRC511);
3760 + temp = er32(PRC1023);
3761 + temp = er32(PRC1522);
3762 + temp = er32(PTC64);
3763 + temp = er32(PTC127);
3764 + temp = er32(PTC255);
3765 + temp = er32(PTC511);
3766 + temp = er32(PTC1023);
3767 + temp = er32(PTC1522);
3769 + temp = er32(ALGNERRC);
3770 + temp = er32(RXERRC);
3771 + temp = er32(TNCRS);
3772 + temp = er32(CEXTERR);
3773 + temp = er32(TSCTC);
3774 + temp = er32(TSCTFC);
3776 + temp = er32(MGTPRC);
3777 + temp = er32(MGTPDC);
3778 + temp = er32(MGTPTC);
3781 + temp = er32(ICRXOC);
3783 + temp = er32(ICRXPTC);
3784 + temp = er32(ICRXATC);
3785 + temp = er32(ICTXPTC);
3786 + temp = er32(ICTXATC);
3787 + temp = er32(ICTXQEC);
3788 + temp = er32(ICTXQMTC);
3789 + temp = er32(ICRXDMTC);
3792 +static struct e1000_mac_operations es2_mac_ops = {
3793 + .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
3794 + /* check_for_link dependent on media type */
3795 + .cleanup_led = e1000e_cleanup_led_generic,
3796 + .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
3797 + .get_bus_info = e1000e_get_bus_info_pcie,
3798 + .get_link_up_info = e1000_get_link_up_info_80003es2lan,
3799 + .led_on = e1000e_led_on_generic,
3800 + .led_off = e1000e_led_off_generic,
3801 + .mc_addr_list_update = e1000e_mc_addr_list_update_generic,
3802 + .reset_hw = e1000_reset_hw_80003es2lan,
3803 + .init_hw = e1000_init_hw_80003es2lan,
3804 + .setup_link = e1000e_setup_link,
3805 + /* setup_physical_interface dependent on media type */
3808 +static struct e1000_phy_operations es2_phy_ops = {
3809 + .acquire_phy = e1000_acquire_phy_80003es2lan,
3810 + .check_reset_block = e1000e_check_reset_block_generic,
3811 + .commit_phy = e1000e_phy_sw_reset,
3812 + .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
3813 + .get_cfg_done = e1000_get_cfg_done_80003es2lan,
3814 + .get_cable_length = e1000_get_cable_length_80003es2lan,
3815 + .get_phy_info = e1000e_get_phy_info_m88,
3816 + .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan,
3817 + .release_phy = e1000_release_phy_80003es2lan,
3818 + .reset_phy = e1000e_phy_hw_reset_generic,
3819 + .set_d0_lplu_state = NULL,
3820 + .set_d3_lplu_state = e1000e_set_d3_lplu_state,
3821 + .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan,
3824 +static struct e1000_nvm_operations es2_nvm_ops = {
3825 + .acquire_nvm = e1000_acquire_nvm_80003es2lan,
3826 + .read_nvm = e1000e_read_nvm_eerd,
3827 + .release_nvm = e1000_release_nvm_80003es2lan,
3828 + .update_nvm = e1000e_update_nvm_checksum_generic,
3829 + .valid_led_default = e1000e_valid_led_default,
3830 + .validate_nvm = e1000e_validate_nvm_checksum_generic,
3831 + .write_nvm = e1000_write_nvm_80003es2lan,
3834 +struct e1000_info e1000_es2_info = {
3835 + .mac = e1000_80003es2lan,
3836 + .flags = FLAG_HAS_HW_VLAN_FILTER
3837 + | FLAG_HAS_JUMBO_FRAMES
3838 + | FLAG_HAS_STATS_PTC_PRC
3840 + | FLAG_APME_IN_CTRL3
3841 + | FLAG_RX_CSUM_ENABLED
3842 + | FLAG_HAS_CTRLEXT_ON_LOAD
3843 + | FLAG_HAS_STATS_ICR_ICT
3844 + | FLAG_RX_NEEDS_RESTART /* errata */
3845 + | FLAG_TARC_SET_BIT_ZERO /* errata */
3846 + | FLAG_APME_CHECK_PORT_B
3847 + | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3848 + | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
3850 + .get_invariants = e1000_get_invariants_80003es2lan,
3851 + .mac_ops = &es2_mac_ops,
3852 + .phy_ops = &es2_phy_ops,
3853 + .nvm_ops = &es2_nvm_ops,
3856 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/ethtool.c linux-2.6.22-10/drivers/net/e1000e/ethtool.c
3857 --- linux-2.6.22-0/drivers/net/e1000e/ethtool.c 1969-12-31 19:00:00.000000000 -0500
3858 +++ linux-2.6.22-10/drivers/net/e1000e/ethtool.c 2007-11-21 13:55:34.000000000 -0500
3860 +/*******************************************************************************
3862 + Intel PRO/1000 Linux driver
3863 + Copyright(c) 1999 - 2007 Intel Corporation.
3865 + This program is free software; you can redistribute it and/or modify it
3866 + under the terms and conditions of the GNU General Public License,
3867 + version 2, as published by the Free Software Foundation.
3869 + This program is distributed in the hope it will be useful, but WITHOUT
3870 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3871 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3874 + You should have received a copy of the GNU General Public License along with
3875 + this program; if not, write to the Free Software Foundation, Inc.,
3876 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3878 + The full GNU General Public License is included in this distribution in
3879 + the file called "COPYING".
3881 + Contact Information:
3882 + Linux NICS <linux.nics@intel.com>
3883 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
3884 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
3886 +*******************************************************************************/
3888 +/* ethtool support for e1000 */
3890 +#include <linux/netdevice.h>
3891 +#include <linux/ethtool.h>
3892 +#include <linux/pci.h>
3893 +#include <linux/delay.h>
3897 +struct e1000_stats {
3898 + char stat_string[ETH_GSTRING_LEN];
3903 +#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
3904 + offsetof(struct e1000_adapter, m)
3905 +static const struct e1000_stats e1000_gstrings_stats[] = {
3906 + { "rx_packets", E1000_STAT(stats.gprc) },
3907 + { "tx_packets", E1000_STAT(stats.gptc) },
3908 + { "rx_bytes", E1000_STAT(stats.gorcl) },
3909 + { "tx_bytes", E1000_STAT(stats.gotcl) },
3910 + { "rx_broadcast", E1000_STAT(stats.bprc) },
3911 + { "tx_broadcast", E1000_STAT(stats.bptc) },
3912 + { "rx_multicast", E1000_STAT(stats.mprc) },
3913 + { "tx_multicast", E1000_STAT(stats.mptc) },
3914 + { "rx_errors", E1000_STAT(net_stats.rx_errors) },
3915 + { "tx_errors", E1000_STAT(net_stats.tx_errors) },
3916 + { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
3917 + { "multicast", E1000_STAT(stats.mprc) },
3918 + { "collisions", E1000_STAT(stats.colc) },
3919 + { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
3920 + { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
3921 + { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
3922 + { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
3923 + { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
3924 + { "rx_missed_errors", E1000_STAT(stats.mpc) },
3925 + { "tx_aborted_errors", E1000_STAT(stats.ecol) },
3926 + { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
3927 + { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
3928 + { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
3929 + { "tx_window_errors", E1000_STAT(stats.latecol) },
3930 + { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
3931 + { "tx_deferred_ok", E1000_STAT(stats.dc) },
3932 + { "tx_single_coll_ok", E1000_STAT(stats.scc) },
3933 + { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
3934 + { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
3935 + { "tx_restart_queue", E1000_STAT(restart_queue) },
3936 + { "rx_long_length_errors", E1000_STAT(stats.roc) },
3937 + { "rx_short_length_errors", E1000_STAT(stats.ruc) },
3938 + { "rx_align_errors", E1000_STAT(stats.algnerrc) },
3939 + { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
3940 + { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
3941 + { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
3942 + { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
3943 + { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
3944 + { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
3945 + { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
3946 + { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
3947 + { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
3948 + { "rx_header_split", E1000_STAT(rx_hdr_split) },
3949 + { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
3950 + { "tx_smbus", E1000_STAT(stats.mgptc) },
3951 + { "rx_smbus", E1000_STAT(stats.mgprc) },
3952 + { "dropped_smbus", E1000_STAT(stats.mgpdc) },
3953 + { "rx_dma_failed", E1000_STAT(rx_dma_failed) },
3954 + { "tx_dma_failed", E1000_STAT(tx_dma_failed) },
3957 +#define E1000_GLOBAL_STATS_LEN \
3958 + sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
3959 +#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN)
3960 +static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
3961 + "Register test (offline)", "Eeprom test (offline)",
3962 + "Interrupt test (offline)", "Loopback test (offline)",
3963 + "Link test (on/offline)"
3965 +#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN
3967 +static int e1000_get_settings(struct net_device *netdev,
3968 + struct ethtool_cmd *ecmd)
3970 + struct e1000_adapter *adapter = netdev_priv(netdev);
3971 + struct e1000_hw *hw = &adapter->hw;
3973 + if (hw->media_type == e1000_media_type_copper) {
3975 + ecmd->supported = (SUPPORTED_10baseT_Half |
3976 + SUPPORTED_10baseT_Full |
3977 + SUPPORTED_100baseT_Half |
3978 + SUPPORTED_100baseT_Full |
3979 + SUPPORTED_1000baseT_Full |
3980 + SUPPORTED_Autoneg |
3982 + if (hw->phy.type == e1000_phy_ife)
3983 + ecmd->supported &= ~SUPPORTED_1000baseT_Full;
3984 + ecmd->advertising = ADVERTISED_TP;
3986 + if (hw->mac.autoneg == 1) {
3987 + ecmd->advertising |= ADVERTISED_Autoneg;
3988 + /* the e1000 autoneg seems to match ethtool nicely */
3989 + ecmd->advertising |= hw->phy.autoneg_advertised;
3992 + ecmd->port = PORT_TP;
3993 + ecmd->phy_address = hw->phy.addr;
3994 + ecmd->transceiver = XCVR_INTERNAL;
3997 + ecmd->supported = (SUPPORTED_1000baseT_Full |
3999 + SUPPORTED_Autoneg);
4001 + ecmd->advertising = (ADVERTISED_1000baseT_Full |
4002 + ADVERTISED_FIBRE |
4003 + ADVERTISED_Autoneg);
4005 + ecmd->port = PORT_FIBRE;
4006 + ecmd->transceiver = XCVR_EXTERNAL;
4009 + if (er32(STATUS) & E1000_STATUS_LU) {
4011 + adapter->hw.mac.ops.get_link_up_info(hw, &adapter->link_speed,
4012 + &adapter->link_duplex);
4013 + ecmd->speed = adapter->link_speed;
4015 + /* unfortunately FULL_DUPLEX != DUPLEX_FULL
4016 + * and HALF_DUPLEX != DUPLEX_HALF */
4018 + if (adapter->link_duplex == FULL_DUPLEX)
4019 + ecmd->duplex = DUPLEX_FULL;
4021 + ecmd->duplex = DUPLEX_HALF;
4024 + ecmd->duplex = -1;
4027 + ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) ||
4028 + hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4032 +static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
4034 + struct e1000_mac_info *mac = &adapter->hw.mac;
4038 + /* Fiber NICs only allow 1000 gbps Full duplex */
4039 + if ((adapter->hw.media_type == e1000_media_type_fiber) &&
4040 + spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4041 + ndev_err(adapter->netdev, "Unsupported Speed/Duplex "
4042 + "configuration\n");
4046 + switch (spddplx) {
4047 + case SPEED_10 + DUPLEX_HALF:
4048 + mac->forced_speed_duplex = ADVERTISE_10_HALF;
4050 + case SPEED_10 + DUPLEX_FULL:
4051 + mac->forced_speed_duplex = ADVERTISE_10_FULL;
4053 + case SPEED_100 + DUPLEX_HALF:
4054 + mac->forced_speed_duplex = ADVERTISE_100_HALF;
4056 + case SPEED_100 + DUPLEX_FULL:
4057 + mac->forced_speed_duplex = ADVERTISE_100_FULL;
4059 + case SPEED_1000 + DUPLEX_FULL:
4061 + adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4063 + case SPEED_1000 + DUPLEX_HALF: /* not supported */
4065 + ndev_err(adapter->netdev, "Unsupported Speed/Duplex "
4066 + "configuration\n");
4072 +static int e1000_set_settings(struct net_device *netdev,
4073 + struct ethtool_cmd *ecmd)
4075 + struct e1000_adapter *adapter = netdev_priv(netdev);
4076 + struct e1000_hw *hw = &adapter->hw;
4078 + /* When SoL/IDER sessions are active, autoneg/speed/duplex
4079 + * cannot be changed */
4080 + if (e1000_check_reset_block(hw)) {
4081 + ndev_err(netdev, "Cannot change link "
4082 + "characteristics when SoL/IDER is active.\n");
4086 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4089 + if (ecmd->autoneg == AUTONEG_ENABLE) {
4090 + hw->mac.autoneg = 1;
4091 + if (hw->media_type == e1000_media_type_fiber)
4092 + hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
4093 + ADVERTISED_FIBRE |
4094 + ADVERTISED_Autoneg;
4096 + hw->phy.autoneg_advertised = ecmd->advertising |
4098 + ADVERTISED_Autoneg;
4099 + ecmd->advertising = hw->phy.autoneg_advertised;
4101 + if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
4102 + clear_bit(__E1000_RESETTING, &adapter->state);
4107 + /* reset the link */
4109 + if (netif_running(adapter->netdev)) {
4110 + e1000e_down(adapter);
4111 + e1000e_up(adapter);
4113 + e1000e_reset(adapter);
4116 + clear_bit(__E1000_RESETTING, &adapter->state);
4120 +static void e1000_get_pauseparam(struct net_device *netdev,
4121 + struct ethtool_pauseparam *pause)
4123 + struct e1000_adapter *adapter = netdev_priv(netdev);
4124 + struct e1000_hw *hw = &adapter->hw;
4127 + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
4129 + if (hw->mac.fc == e1000_fc_rx_pause) {
4130 + pause->rx_pause = 1;
4131 + } else if (hw->mac.fc == e1000_fc_tx_pause) {
4132 + pause->tx_pause = 1;
4133 + } else if (hw->mac.fc == e1000_fc_full) {
4134 + pause->rx_pause = 1;
4135 + pause->tx_pause = 1;
4139 +static int e1000_set_pauseparam(struct net_device *netdev,
4140 + struct ethtool_pauseparam *pause)
4142 + struct e1000_adapter *adapter = netdev_priv(netdev);
4143 + struct e1000_hw *hw = &adapter->hw;
4146 + adapter->fc_autoneg = pause->autoneg;
4148 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4151 + if (pause->rx_pause && pause->tx_pause)
4152 + hw->mac.fc = e1000_fc_full;
4153 + else if (pause->rx_pause && !pause->tx_pause)
4154 + hw->mac.fc = e1000_fc_rx_pause;
4155 + else if (!pause->rx_pause && pause->tx_pause)
4156 + hw->mac.fc = e1000_fc_tx_pause;
4157 + else if (!pause->rx_pause && !pause->tx_pause)
4158 + hw->mac.fc = e1000_fc_none;
4160 + hw->mac.original_fc = hw->mac.fc;
4162 + if (adapter->fc_autoneg == AUTONEG_ENABLE) {
4163 + if (netif_running(adapter->netdev)) {
4164 + e1000e_down(adapter);
4165 + e1000e_up(adapter);
4167 + e1000e_reset(adapter);
4170 + retval = ((hw->media_type == e1000_media_type_fiber) ?
4171 + hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw));
4174 + clear_bit(__E1000_RESETTING, &adapter->state);
4178 +static u32 e1000_get_rx_csum(struct net_device *netdev)
4180 + struct e1000_adapter *adapter = netdev_priv(netdev);
4181 + return (adapter->flags & FLAG_RX_CSUM_ENABLED);
4184 +static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
4186 + struct e1000_adapter *adapter = netdev_priv(netdev);
4189 + adapter->flags |= FLAG_RX_CSUM_ENABLED;
4191 + adapter->flags &= ~FLAG_RX_CSUM_ENABLED;
4193 + if (netif_running(netdev))
4194 + e1000e_reinit_locked(adapter);
4196 + e1000e_reset(adapter);
4200 +static u32 e1000_get_tx_csum(struct net_device *netdev)
4202 + return ((netdev->features & NETIF_F_HW_CSUM) != 0);
4205 +static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
4208 + netdev->features |= NETIF_F_HW_CSUM;
4210 + netdev->features &= ~NETIF_F_HW_CSUM;
4215 +static int e1000_set_tso(struct net_device *netdev, u32 data)
4217 + struct e1000_adapter *adapter = netdev_priv(netdev);
4220 + netdev->features |= NETIF_F_TSO;
4221 + netdev->features |= NETIF_F_TSO6;
4223 + netdev->features &= ~NETIF_F_TSO;
4224 + netdev->features &= ~NETIF_F_TSO6;
4227 + ndev_info(netdev, "TSO is %s\n",
4228 + data ? "Enabled" : "Disabled");
4229 + adapter->flags |= FLAG_TSO_FORCE;
4233 +static u32 e1000_get_msglevel(struct net_device *netdev)
4235 + struct e1000_adapter *adapter = netdev_priv(netdev);
4236 + return adapter->msg_enable;
4239 +static void e1000_set_msglevel(struct net_device *netdev, u32 data)
4241 + struct e1000_adapter *adapter = netdev_priv(netdev);
4242 + adapter->msg_enable = data;
4245 +static int e1000_get_regs_len(struct net_device *netdev)
4247 +#define E1000_REGS_LEN 32 /* overestimate */
4248 + return E1000_REGS_LEN * sizeof(u32);
4251 +static void e1000_get_regs(struct net_device *netdev,
4252 + struct ethtool_regs *regs, void *p)
4254 + struct e1000_adapter *adapter = netdev_priv(netdev);
4255 + struct e1000_hw *hw = &adapter->hw;
4256 + u32 *regs_buff = p;
4260 + memset(p, 0, E1000_REGS_LEN * sizeof(u32));
4262 + pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id);
4264 + regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device;
4266 + regs_buff[0] = er32(CTRL);
4267 + regs_buff[1] = er32(STATUS);
4269 + regs_buff[2] = er32(RCTL);
4270 + regs_buff[3] = er32(RDLEN);
4271 + regs_buff[4] = er32(RDH);
4272 + regs_buff[5] = er32(RDT);
4273 + regs_buff[6] = er32(RDTR);
4275 + regs_buff[7] = er32(TCTL);
4276 + regs_buff[8] = er32(TDLEN);
4277 + regs_buff[9] = er32(TDH);
4278 + regs_buff[10] = er32(TDT);
4279 + regs_buff[11] = er32(TIDV);
4281 + regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
4282 + if (hw->phy.type == e1000_phy_m88) {
4283 + e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4284 + regs_buff[13] = (u32)phy_data; /* cable length */
4285 + regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
4286 + regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
4287 + regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
4288 + e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4289 + regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
4290 + regs_buff[18] = regs_buff[13]; /* cable polarity */
4291 + regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
4292 + regs_buff[20] = regs_buff[17]; /* polarity correction */
4293 + /* phy receive errors */
4294 + regs_buff[22] = adapter->phy_stats.receive_errors;
4295 + regs_buff[23] = regs_buff[13]; /* mdix mode */
4297 + regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
4298 + e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
4299 + regs_buff[24] = (u32)phy_data; /* phy local receiver status */
4300 + regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
4303 +static int e1000_get_eeprom_len(struct net_device *netdev)
4305 + struct e1000_adapter *adapter = netdev_priv(netdev);
4306 + return adapter->hw.nvm.word_size * 2;
4309 +static int e1000_get_eeprom(struct net_device *netdev,
4310 + struct ethtool_eeprom *eeprom, u8 *bytes)
4312 + struct e1000_adapter *adapter = netdev_priv(netdev);
4313 + struct e1000_hw *hw = &adapter->hw;
4320 + if (eeprom->len == 0)
4323 + eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16);
4325 + first_word = eeprom->offset >> 1;
4326 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
4328 + eeprom_buff = kmalloc(sizeof(u16) *
4329 + (last_word - first_word + 1), GFP_KERNEL);
4333 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
4334 + ret_val = e1000_read_nvm(hw, first_word,
4335 + last_word - first_word + 1,
4338 + for (i = 0; i < last_word - first_word + 1; i++) {
4339 + ret_val = e1000_read_nvm(hw, first_word + i, 1,
4346 + /* Device's eeprom is always little-endian, word addressable */
4347 + for (i = 0; i < last_word - first_word + 1; i++)
4348 + le16_to_cpus(&eeprom_buff[i]);
4350 + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
4351 + kfree(eeprom_buff);
4356 +static int e1000_set_eeprom(struct net_device *netdev,
4357 + struct ethtool_eeprom *eeprom, u8 *bytes)
4359 + struct e1000_adapter *adapter = netdev_priv(netdev);
4360 + struct e1000_hw *hw = &adapter->hw;
4369 + if (eeprom->len == 0)
4370 + return -EOPNOTSUPP;
4372 + if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16)))
4375 + max_len = hw->nvm.word_size * 2;
4377 + first_word = eeprom->offset >> 1;
4378 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
4379 + eeprom_buff = kmalloc(max_len, GFP_KERNEL);
4383 + ptr = (void *)eeprom_buff;
4385 + if (eeprom->offset & 1) {
4386 + /* need read/modify/write of first changed EEPROM word */
4387 + /* only the second byte of the word is being modified */
4388 + ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]);
4391 + if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0))
4392 + /* need read/modify/write of last changed EEPROM word */
4393 + /* only the first byte of the word is being modified */
4394 + ret_val = e1000_read_nvm(hw, last_word, 1,
4395 + &eeprom_buff[last_word - first_word]);
4397 + /* Device's eeprom is always little-endian, word addressable */
4398 + for (i = 0; i < last_word - first_word + 1; i++)
4399 + le16_to_cpus(&eeprom_buff[i]);
4401 + memcpy(ptr, bytes, eeprom->len);
4403 + for (i = 0; i < last_word - first_word + 1; i++)
4404 + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
4406 + ret_val = e1000_write_nvm(hw, first_word,
4407 + last_word - first_word + 1, eeprom_buff);
4409 + /* Update the checksum over the first part of the EEPROM if needed
4410 + * and flush shadow RAM for 82573 controllers */
4411 + if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) ||
4412 + (hw->mac.type == e1000_82573)))
4413 + e1000e_update_nvm_checksum(hw);
4415 + kfree(eeprom_buff);
4419 +static void e1000_get_drvinfo(struct net_device *netdev,
4420 + struct ethtool_drvinfo *drvinfo)
4422 + struct e1000_adapter *adapter = netdev_priv(netdev);
4423 + char firmware_version[32];
4426 + strncpy(drvinfo->driver, e1000e_driver_name, 32);
4427 + strncpy(drvinfo->version, e1000e_driver_version, 32);
4429 + /* EEPROM image version # is reported as firmware version # for
4430 + * PCI-E controllers */
4431 + e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data);
4432 + sprintf(firmware_version, "%d.%d-%d",
4433 + (eeprom_data & 0xF000) >> 12,
4434 + (eeprom_data & 0x0FF0) >> 4,
4435 + eeprom_data & 0x000F);
4437 + strncpy(drvinfo->fw_version, firmware_version, 32);
4438 + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
4439 + drvinfo->n_stats = E1000_STATS_LEN;
4440 + drvinfo->testinfo_len = E1000_TEST_LEN;
4441 + drvinfo->regdump_len = e1000_get_regs_len(netdev);
4442 + drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
4445 +static void e1000_get_ringparam(struct net_device *netdev,
4446 + struct ethtool_ringparam *ring)
4448 + struct e1000_adapter *adapter = netdev_priv(netdev);
4449 + struct e1000_ring *tx_ring = adapter->tx_ring;
4450 + struct e1000_ring *rx_ring = adapter->rx_ring;
4452 + ring->rx_max_pending = E1000_MAX_RXD;
4453 + ring->tx_max_pending = E1000_MAX_TXD;
4454 + ring->rx_mini_max_pending = 0;
4455 + ring->rx_jumbo_max_pending = 0;
4456 + ring->rx_pending = rx_ring->count;
4457 + ring->tx_pending = tx_ring->count;
4458 + ring->rx_mini_pending = 0;
4459 + ring->rx_jumbo_pending = 0;
4462 +static int e1000_set_ringparam(struct net_device *netdev,
4463 + struct ethtool_ringparam *ring)
4465 + struct e1000_adapter *adapter = netdev_priv(netdev);
4466 + struct e1000_ring *tx_ring, *tx_old;
4467 + struct e1000_ring *rx_ring, *rx_old;
4470 + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
4473 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4476 + if (netif_running(adapter->netdev))
4477 + e1000e_down(adapter);
4479 + tx_old = adapter->tx_ring;
4480 + rx_old = adapter->rx_ring;
4483 + tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
4485 + goto err_alloc_tx;
4487 + rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
4489 + goto err_alloc_rx;
4491 + adapter->tx_ring = tx_ring;
4492 + adapter->rx_ring = rx_ring;
4494 + rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
4495 + rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD));
4496 + rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
4498 + tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
4499 + tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD));
4500 + tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
4502 + if (netif_running(adapter->netdev)) {
4503 + /* Try to get new resources before deleting old */
4504 + err = e1000e_setup_rx_resources(adapter);
4506 + goto err_setup_rx;
4507 + err = e1000e_setup_tx_resources(adapter);
4509 + goto err_setup_tx;
4511 + /* save the new, restore the old in order to free it,
4512 + * then restore the new back again */
4513 + adapter->rx_ring = rx_old;
4514 + adapter->tx_ring = tx_old;
4515 + e1000e_free_rx_resources(adapter);
4516 + e1000e_free_tx_resources(adapter);
4519 + adapter->rx_ring = rx_ring;
4520 + adapter->tx_ring = tx_ring;
4521 + err = e1000e_up(adapter);
4526 + clear_bit(__E1000_RESETTING, &adapter->state);
4529 + e1000e_free_rx_resources(adapter);
4531 + adapter->rx_ring = rx_old;
4532 + adapter->tx_ring = tx_old;
4537 + e1000e_up(adapter);
4539 + clear_bit(__E1000_RESETTING, &adapter->state);
4543 +#define REG_PATTERN_TEST(R, M, W) REG_PATTERN_TEST_ARRAY(R, 0, M, W)
4544 +#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, writeable) \
4548 + u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
4549 + for (_pat = 0; _pat < ARRAY_SIZE(_test); _pat++) { \
4550 + E1000_WRITE_REG_ARRAY(hw, reg, offset, \
4551 + (_test[_pat] & writeable)); \
4552 + _value = E1000_READ_REG_ARRAY(hw, reg, offset); \
4553 + if (_value != (_test[_pat] & writeable & mask)) { \
4554 + ndev_err(netdev, "pattern test reg %04X " \
4555 + "failed: got 0x%08X expected 0x%08X\n", \
4557 + value, (_test[_pat] & writeable & mask)); \
4564 +#define REG_SET_AND_CHECK(R, M, W) \
4567 + __ew32(hw, R, W & M); \
4568 + _value = __er32(hw, R); \
4569 + if ((W & M) != (_value & M)) { \
4570 + ndev_err(netdev, "set/check reg %04X test failed: " \
4571 + "got 0x%08X expected 0x%08X\n", R, (_value & M), \
4578 +static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
4580 + struct e1000_hw *hw = &adapter->hw;
4581 + struct e1000_mac_info *mac = &adapter->hw.mac;
4582 + struct net_device *netdev = adapter->netdev;
4589 + /* The status register is Read Only, so a write should fail.
4590 + * Some bits that get toggled are ignored.
4592 + switch (mac->type) {
4593 + /* there are several bits on newer hardware that are r/w */
4596 + case e1000_80003es2lan:
4597 + toggle = 0x7FFFF3FF;
4600 + case e1000_ich8lan:
4601 + case e1000_ich9lan:
4602 + toggle = 0x7FFFF033;
4605 + toggle = 0xFFFFF833;
4609 + before = er32(STATUS);
4610 + value = (er32(STATUS) & toggle);
4611 + ew32(STATUS, toggle);
4612 + after = er32(STATUS) & toggle;
4613 + if (value != after) {
4614 + ndev_err(netdev, "failed STATUS register test got: "
4615 + "0x%08X expected: 0x%08X\n", after, value);
4619 + /* restore previous status */
4620 + ew32(STATUS, before);
4622 + if ((mac->type != e1000_ich8lan) &&
4623 + (mac->type != e1000_ich9lan)) {
4624 + REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
4625 + REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
4626 + REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
4627 + REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
4630 + REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
4631 + REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
4632 + REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF);
4633 + REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF);
4634 + REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF);
4635 + REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
4636 + REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
4637 + REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
4638 + REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
4639 + REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF);
4641 + REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
4643 + before = (((mac->type == e1000_ich8lan) ||
4644 + (mac->type == e1000_ich9lan)) ? 0x06C3B33E : 0x06DFB3FE);
4645 + REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
4646 + REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
4648 + REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x01FFFFFF);
4649 + REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFF000, 0xFFFFFFFF);
4650 + REG_PATTERN_TEST(E1000_TXCW, 0x0000FFFF, 0x0000FFFF);
4651 + REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFF000, 0xFFFFFFFF);
4653 + for (i = 0; i < mac->mta_reg_count; i++)
4654 + REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
4660 +static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
4667 + /* Read and add up the contents of the EEPROM */
4668 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
4669 + if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) {
4676 + /* If Checksum is not Correct return error else test passed */
4677 + if ((checksum != (u16) NVM_SUM) && !(*data))
4683 +static irqreturn_t e1000_test_intr(int irq, void *data)
4685 + struct net_device *netdev = (struct net_device *) data;
4686 + struct e1000_adapter *adapter = netdev_priv(netdev);
4687 + struct e1000_hw *hw = &adapter->hw;
4689 + adapter->test_icr |= er32(ICR);
4691 + return IRQ_HANDLED;
4694 +static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
4696 + struct net_device *netdev = adapter->netdev;
4697 + struct e1000_hw *hw = &adapter->hw;
4699 + u32 shared_int = 1;
4700 + u32 irq = adapter->pdev->irq;
4705 + /* NOTE: we don't test MSI interrupts here, yet */
4706 + /* Hook up test interrupt handler just for this test */
4707 + if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
4710 + } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
4711 + netdev->name, netdev)) {
4715 + ndev_info(netdev, "testing %s interrupt\n",
4716 + (shared_int ? "shared" : "unshared"));
4718 + /* Disable all the interrupts */
4719 + ew32(IMC, 0xFFFFFFFF);
4722 + /* Test each interrupt */
4723 + for (i = 0; i < 10; i++) {
4725 + if (((adapter->hw.mac.type == e1000_ich8lan) ||
4726 + (adapter->hw.mac.type == e1000_ich9lan)) && i == 8)
4729 + /* Interrupt to test */
4732 + if (!shared_int) {
4733 + /* Disable the interrupt to be reported in
4734 + * the cause register and then force the same
4735 + * interrupt and see if one gets posted. If
4736 + * an interrupt was posted to the bus, the
4739 + adapter->test_icr = 0;
4744 + if (adapter->test_icr & mask) {
4750 + /* Enable the interrupt to be reported in
4751 + * the cause register and then force the same
4752 + * interrupt and see if one gets posted. If
4753 + * an interrupt was not posted to the bus, the
4756 + adapter->test_icr = 0;
4761 + if (!(adapter->test_icr & mask)) {
4766 + if (!shared_int) {
4767 + /* Disable the other interrupts to be reported in
4768 + * the cause register and then force the other
4769 + * interrupts and see if any get posted. If
4770 + * an interrupt was posted to the bus, the
4773 + adapter->test_icr = 0;
4774 + ew32(IMC, ~mask & 0x00007FFF);
4775 + ew32(ICS, ~mask & 0x00007FFF);
4778 + if (adapter->test_icr) {
4785 + /* Disable all the interrupts */
4786 + ew32(IMC, 0xFFFFFFFF);
4789 + /* Unhook test interrupt handler */
4790 + free_irq(irq, netdev);
4795 +static void e1000_free_desc_rings(struct e1000_adapter *adapter)
4797 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
4798 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
4799 + struct pci_dev *pdev = adapter->pdev;
4802 + if (tx_ring->desc && tx_ring->buffer_info) {
4803 + for (i = 0; i < tx_ring->count; i++) {
4804 + if (tx_ring->buffer_info[i].dma)
4805 + pci_unmap_single(pdev,
4806 + tx_ring->buffer_info[i].dma,
4807 + tx_ring->buffer_info[i].length,
4808 + PCI_DMA_TODEVICE);
4809 + if (tx_ring->buffer_info[i].skb)
4810 + dev_kfree_skb(tx_ring->buffer_info[i].skb);
4814 + if (rx_ring->desc && rx_ring->buffer_info) {
4815 + for (i = 0; i < rx_ring->count; i++) {
4816 + if (rx_ring->buffer_info[i].dma)
4817 + pci_unmap_single(pdev,
4818 + rx_ring->buffer_info[i].dma,
4819 + 2048, PCI_DMA_FROMDEVICE);
4820 + if (rx_ring->buffer_info[i].skb)
4821 + dev_kfree_skb(rx_ring->buffer_info[i].skb);
4825 + if (tx_ring->desc) {
4826 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4828 + tx_ring->desc = NULL;
4830 + if (rx_ring->desc) {
4831 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4833 + rx_ring->desc = NULL;
4836 + kfree(tx_ring->buffer_info);
4837 + tx_ring->buffer_info = NULL;
4838 + kfree(rx_ring->buffer_info);
4839 + rx_ring->buffer_info = NULL;
4842 +static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
4844 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
4845 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
4846 + struct pci_dev *pdev = adapter->pdev;
4847 + struct e1000_hw *hw = &adapter->hw;
4853 + /* Setup Tx descriptor ring and Tx buffers */
4855 + if (!tx_ring->count)
4856 + tx_ring->count = E1000_DEFAULT_TXD;
4858 + size = tx_ring->count * sizeof(struct e1000_buffer);
4859 + tx_ring->buffer_info = kmalloc(size, GFP_KERNEL);
4860 + if (!tx_ring->buffer_info) {
4864 + memset(tx_ring->buffer_info, 0, size);
4866 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
4867 + tx_ring->size = ALIGN(tx_ring->size, 4096);
4868 + tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4869 + &tx_ring->dma, GFP_KERNEL);
4870 + if (!tx_ring->desc) {
4874 + memset(tx_ring->desc, 0, tx_ring->size);
4875 + tx_ring->next_to_use = 0;
4876 + tx_ring->next_to_clean = 0;
4879 + ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
4880 + ew32(TDBAH, ((u64) tx_ring->dma >> 32));
4882 + tx_ring->count * sizeof(struct e1000_tx_desc));
4886 + E1000_TCTL_PSP | E1000_TCTL_EN |
4887 + E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
4888 + E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
4890 + for (i = 0; i < tx_ring->count; i++) {
4891 + struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
4892 + struct sk_buff *skb;
4893 + unsigned int skb_size = 1024;
4895 + skb = alloc_skb(skb_size, GFP_KERNEL);
4900 + skb_put(skb, skb_size);
4901 + tx_ring->buffer_info[i].skb = skb;
4902 + tx_ring->buffer_info[i].length = skb->len;
4903 + tx_ring->buffer_info[i].dma =
4904 + pci_map_single(pdev, skb->data, skb->len,
4905 + PCI_DMA_TODEVICE);
4906 + if (pci_dma_mapping_error(tx_ring->buffer_info[i].dma)) {
4910 + tx_desc->buffer_addr = cpu_to_le64(
4911 + tx_ring->buffer_info[i].dma);
4912 + tx_desc->lower.data = cpu_to_le32(skb->len);
4913 + tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
4914 + E1000_TXD_CMD_IFCS |
4915 + E1000_TXD_CMD_RPS);
4916 + tx_desc->upper.data = 0;
4919 + /* Setup Rx descriptor ring and Rx buffers */
4921 + if (!rx_ring->count)
4922 + rx_ring->count = E1000_DEFAULT_RXD;
4924 + size = rx_ring->count * sizeof(struct e1000_buffer);
4925 + rx_ring->buffer_info = kmalloc(size, GFP_KERNEL);
4926 + if (!rx_ring->buffer_info) {
4930 + memset(rx_ring->buffer_info, 0, size);
4932 + rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
4933 + rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4934 + &rx_ring->dma, GFP_KERNEL);
4935 + if (!rx_ring->desc) {
4939 + memset(rx_ring->desc, 0, rx_ring->size);
4940 + rx_ring->next_to_use = 0;
4941 + rx_ring->next_to_clean = 0;
4943 + rctl = er32(RCTL);
4944 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
4945 + ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF));
4946 + ew32(RDBAH, ((u64) rx_ring->dma >> 32));
4947 + ew32(RDLEN, rx_ring->size);
4950 + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
4951 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
4952 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4955 + for (i = 0; i < rx_ring->count; i++) {
4956 + struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
4957 + struct sk_buff *skb;
4959 + skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL);
4964 + skb_reserve(skb, NET_IP_ALIGN);
4965 + rx_ring->buffer_info[i].skb = skb;
4966 + rx_ring->buffer_info[i].dma =
4967 + pci_map_single(pdev, skb->data, 2048,
4968 + PCI_DMA_FROMDEVICE);
4969 + if (pci_dma_mapping_error(rx_ring->buffer_info[i].dma)) {
4973 + rx_desc->buffer_addr =
4974 + cpu_to_le64(rx_ring->buffer_info[i].dma);
4975 + memset(skb->data, 0x00, skb->len);
4981 + e1000_free_desc_rings(adapter);
4985 +static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
4987 + /* Write out to PHY registers 29 and 30 to disable the Receiver. */
4988 + e1e_wphy(&adapter->hw, 29, 0x001F);
4989 + e1e_wphy(&adapter->hw, 30, 0x8FFC);
4990 + e1e_wphy(&adapter->hw, 29, 0x001A);
4991 + e1e_wphy(&adapter->hw, 30, 0x8FF0);
4994 +static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
4996 + struct e1000_hw *hw = &adapter->hw;
5000 + adapter->hw.mac.autoneg = 0;
5002 + if (adapter->hw.phy.type == e1000_phy_m88) {
5003 + /* Auto-MDI/MDIX Off */
5004 + e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
5005 + /* reset to update Auto-MDI/MDIX */
5006 + e1e_wphy(hw, PHY_CONTROL, 0x9140);
5008 + e1e_wphy(hw, PHY_CONTROL, 0x8140);
5009 + } else if (adapter->hw.phy.type == e1000_phy_gg82563)
5010 + e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
5012 + ctrl_reg = er32(CTRL);
5014 + if (adapter->hw.phy.type == e1000_phy_ife) {
5015 + /* force 100, set loopback */
5016 + e1e_wphy(hw, PHY_CONTROL, 0x6100);
5018 + /* Now set up the MAC to the same speed/duplex as the PHY. */
5019 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
5020 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
5021 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
5022 + E1000_CTRL_SPD_100 |/* Force Speed to 100 */
5023 + E1000_CTRL_FD); /* Force Duplex to FULL */
5025 + /* force 1000, set loopback */
5026 + e1e_wphy(hw, PHY_CONTROL, 0x4140);
5028 + /* Now set up the MAC to the same speed/duplex as the PHY. */
5029 + ctrl_reg = er32(CTRL);
5030 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
5031 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
5032 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
5033 + E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
5034 + E1000_CTRL_FD); /* Force Duplex to FULL */
5037 + if (adapter->hw.media_type == e1000_media_type_copper &&
5038 + adapter->hw.phy.type == e1000_phy_m88) {
5039 + ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
5041 + /* Set the ILOS bit on the fiber Nic if half duplex link is
5043 + stat_reg = er32(STATUS);
5044 + if ((stat_reg & E1000_STATUS_FD) == 0)
5045 + ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
5048 + ew32(CTRL, ctrl_reg);
5050 + /* Disable the receiver on the PHY so when a cable is plugged in, the
5051 + * PHY does not begin to autoneg when a cable is reconnected to the NIC.
5053 + if (adapter->hw.phy.type == e1000_phy_m88)
5054 + e1000_phy_disable_receiver(adapter);
5061 +static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
5063 + struct e1000_hw *hw = &adapter->hw;
5064 + u32 ctrl = er32(CTRL);
5067 + /* special requirements for 82571/82572 fiber adapters */
5069 + /* jump through hoops to make sure link is up because serdes
5070 + * link is hardwired up */
5071 + ctrl |= E1000_CTRL_SLU;
5074 + /* disable autoneg */
5075 + ctrl = er32(TXCW);
5076 + ctrl &= ~(1 << 31);
5079 + link = (er32(STATUS) & E1000_STATUS_LU);
5082 + /* set invert loss of signal */
5083 + ctrl = er32(CTRL);
5084 + ctrl |= E1000_CTRL_ILOS;
5088 + /* special write to serdes control register to enable SerDes analog
5090 +#define E1000_SERDES_LB_ON 0x410
5091 + ew32(SCTL, E1000_SERDES_LB_ON);
5097 +/* only call this for fiber/serdes connections to es2lan */
5098 +static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
5100 + struct e1000_hw *hw = &adapter->hw;
5101 + u32 ctrlext = er32(CTRL_EXT);
5102 + u32 ctrl = er32(CTRL);
5104 + /* save CTRL_EXT to restore later, reuse an empty variable (unused
5105 + on mac_type 80003es2lan) */
5106 + adapter->tx_fifo_head = ctrlext;
5108 + /* clear the serdes mode bits, putting the device into mac loopback */
5109 + ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
5110 + ew32(CTRL_EXT, ctrlext);
5112 + /* force speed to 1000/FD, link up */
5113 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
5114 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
5115 + E1000_CTRL_SPD_1000 | E1000_CTRL_FD);
5118 + /* set mac loopback */
5119 + ctrl = er32(RCTL);
5120 + ctrl |= E1000_RCTL_LBM_MAC;
5123 + /* set testing mode parameters (no need to reset later) */
5124 +#define KMRNCTRLSTA_OPMODE (0x1F << 16)
5125 +#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582
5127 + (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII));
5132 +static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
5134 + struct e1000_hw *hw = &adapter->hw;
5137 + if (hw->media_type == e1000_media_type_fiber ||
5138 + hw->media_type == e1000_media_type_internal_serdes) {
5139 + switch (hw->mac.type) {
5140 + case e1000_80003es2lan:
5141 + return e1000_set_es2lan_mac_loopback(adapter);
5145 + return e1000_set_82571_fiber_loopback(adapter);
5148 + rctl = er32(RCTL);
5149 + rctl |= E1000_RCTL_LBM_TCVR;
5153 + } else if (hw->media_type == e1000_media_type_copper) {
5154 + return e1000_integrated_phy_loopback(adapter);
5160 +static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
5162 + struct e1000_hw *hw = &adapter->hw;
5166 + rctl = er32(RCTL);
5167 + rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
5170 + switch (hw->mac.type) {
5171 + case e1000_80003es2lan:
5172 + if (hw->media_type == e1000_media_type_fiber ||
5173 + hw->media_type == e1000_media_type_internal_serdes) {
5174 + /* restore CTRL_EXT, stealing space from tx_fifo_head */
5176 + adapter->tx_fifo_head);
5177 + adapter->tx_fifo_head = 0;
5179 + /* fall through */
5182 + if (hw->media_type == e1000_media_type_fiber ||
5183 + hw->media_type == e1000_media_type_internal_serdes) {
5184 +#define E1000_SERDES_LB_OFF 0x400
5185 + ew32(SCTL, E1000_SERDES_LB_OFF);
5189 + /* Fall Through */
5191 + hw->mac.autoneg = 1;
5192 + if (hw->phy.type == e1000_phy_gg82563)
5193 + e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
5194 + e1e_rphy(hw, PHY_CONTROL, &phy_reg);
5195 + if (phy_reg & MII_CR_LOOPBACK) {
5196 + phy_reg &= ~MII_CR_LOOPBACK;
5197 + e1e_wphy(hw, PHY_CONTROL, phy_reg);
5198 + e1000e_commit_phy(hw);
5204 +static void e1000_create_lbtest_frame(struct sk_buff *skb,
5205 + unsigned int frame_size)
5207 + memset(skb->data, 0xFF, frame_size);
5209 + memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
5210 + memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
5211 + memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
5214 +static int e1000_check_lbtest_frame(struct sk_buff *skb,
5215 + unsigned int frame_size)
5218 + if (*(skb->data + 3) == 0xFF)
5219 + if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
5220 + (*(skb->data + frame_size / 2 + 12) == 0xAF))
5225 +static int e1000_run_loopback_test(struct e1000_adapter *adapter)
5227 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
5228 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
5229 + struct pci_dev *pdev = adapter->pdev;
5230 + struct e1000_hw *hw = &adapter->hw;
5235 + unsigned long time;
5237 + ew32(RDT, rx_ring->count - 1);
5239 + /* Calculate the loop count based on the largest descriptor ring
5240 + * The idea is to wrap the largest ring a number of times using 64
5241 + * send/receive pairs during each loop
5244 + if (rx_ring->count <= tx_ring->count)
5245 + lc = ((tx_ring->count / 64) * 2) + 1;
5247 + lc = ((rx_ring->count / 64) * 2) + 1;
5251 + for (j = 0; j <= lc; j++) { /* loop count loop */
5252 + for (i = 0; i < 64; i++) { /* send the packets */
5253 + e1000_create_lbtest_frame(
5254 + tx_ring->buffer_info[i].skb, 1024);
5255 + pci_dma_sync_single_for_device(pdev,
5256 + tx_ring->buffer_info[k].dma,
5257 + tx_ring->buffer_info[k].length,
5258 + PCI_DMA_TODEVICE);
5260 + if (k == tx_ring->count)
5265 + time = jiffies; /* set the start time for the receive */
5267 + do { /* receive the sent packets */
5268 + pci_dma_sync_single_for_cpu(pdev,
5269 + rx_ring->buffer_info[l].dma, 2048,
5270 + PCI_DMA_FROMDEVICE);
5272 + ret_val = e1000_check_lbtest_frame(
5273 + rx_ring->buffer_info[l].skb, 1024);
5277 + if (l == rx_ring->count)
5279 + /* time + 20 msecs (200 msecs on 2.4) is more than
5280 + * enough time to complete the receives, if it's
5281 + * exceeded, break and error off
5283 + } while ((good_cnt < 64) && !time_after(jiffies, time + 20));
5284 + if (good_cnt != 64) {
5285 + ret_val = 13; /* ret_val is the same as mis-compare */
5288 + if (jiffies >= (time + 2)) {
5289 + ret_val = 14; /* error code for time out error */
5292 + } /* end loop count loop */
5296 +static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
5298 + /* PHY loopback cannot be performed if SoL/IDER
5299 + * sessions are active */
5300 + if (e1000_check_reset_block(&adapter->hw)) {
5301 + ndev_err(adapter->netdev, "Cannot do PHY loopback test "
5302 + "when SoL/IDER is active.\n");
5307 + *data = e1000_setup_desc_rings(adapter);
5311 + *data = e1000_setup_loopback_test(adapter);
5313 + goto err_loopback;
5315 + *data = e1000_run_loopback_test(adapter);
5316 + e1000_loopback_cleanup(adapter);
5319 + e1000_free_desc_rings(adapter);
5324 +static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
5326 + struct e1000_hw *hw = &adapter->hw;
5329 + if (hw->media_type == e1000_media_type_internal_serdes) {
5331 + hw->mac.serdes_has_link = 0;
5333 + /* On some blade server designs, link establishment
5334 + * could take as long as 2-3 minutes */
5336 + hw->mac.ops.check_for_link(hw);
5337 + if (hw->mac.serdes_has_link)
5340 + } while (i++ < 3750);
5344 + hw->mac.ops.check_for_link(hw);
5345 + if (hw->mac.autoneg)
5348 + if (!(er32(STATUS) &
5355 +static int e1000_diag_test_count(struct net_device *netdev)
5357 + return E1000_TEST_LEN;
5360 +static void e1000_diag_test(struct net_device *netdev,
5361 + struct ethtool_test *eth_test, u64 *data)
5363 + struct e1000_adapter *adapter = netdev_priv(netdev);
5364 + u16 autoneg_advertised;
5365 + u8 forced_speed_duplex;
5367 + bool if_running = netif_running(netdev);
5369 + set_bit(__E1000_TESTING, &adapter->state);
5370 + if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
5371 + /* Offline tests */
5373 + /* save speed, duplex, autoneg settings */
5374 + autoneg_advertised = adapter->hw.phy.autoneg_advertised;
5375 + forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
5376 + autoneg = adapter->hw.mac.autoneg;
5378 + ndev_info(netdev, "offline testing starting\n");
5380 + /* Link test performed before hardware reset so autoneg doesn't
5381 + * interfere with test result */
5382 + if (e1000_link_test(adapter, &data[4]))
5383 + eth_test->flags |= ETH_TEST_FL_FAILED;
5386 + /* indicate we're in test mode */
5387 + dev_close(netdev);
5389 + e1000e_reset(adapter);
5391 + if (e1000_reg_test(adapter, &data[0]))
5392 + eth_test->flags |= ETH_TEST_FL_FAILED;
5394 + e1000e_reset(adapter);
5395 + if (e1000_eeprom_test(adapter, &data[1]))
5396 + eth_test->flags |= ETH_TEST_FL_FAILED;
5398 + e1000e_reset(adapter);
5399 + if (e1000_intr_test(adapter, &data[2]))
5400 + eth_test->flags |= ETH_TEST_FL_FAILED;
5402 + e1000e_reset(adapter);
5403 + /* make sure the phy is powered up */
5404 + e1000e_power_up_phy(adapter);
5405 + if (e1000_loopback_test(adapter, &data[3]))
5406 + eth_test->flags |= ETH_TEST_FL_FAILED;
5408 + /* restore speed, duplex, autoneg settings */
5409 + adapter->hw.phy.autoneg_advertised = autoneg_advertised;
5410 + adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
5411 + adapter->hw.mac.autoneg = autoneg;
5413 + /* force this routine to wait until autoneg complete/timeout */
5414 + adapter->hw.phy.wait_for_link = 1;
5415 + e1000e_reset(adapter);
5416 + adapter->hw.phy.wait_for_link = 0;
5418 + clear_bit(__E1000_TESTING, &adapter->state);
5422 + ndev_info(netdev, "online testing starting\n");
5423 + /* Online tests */
5424 + if (e1000_link_test(adapter, &data[4]))
5425 + eth_test->flags |= ETH_TEST_FL_FAILED;
5427 + /* Online tests aren't run; pass by default */
5433 + clear_bit(__E1000_TESTING, &adapter->state);
5435 + msleep_interruptible(4 * 1000);
5438 +static void e1000_get_wol(struct net_device *netdev,
5439 + struct ethtool_wolinfo *wol)
5441 + struct e1000_adapter *adapter = netdev_priv(netdev);
5443 + wol->supported = 0;
5446 + if (!(adapter->flags & FLAG_HAS_WOL))
5449 + wol->supported = WAKE_UCAST | WAKE_MCAST |
5450 + WAKE_BCAST | WAKE_MAGIC;
5452 + /* apply any specific unsupported masks here */
5453 + if (adapter->flags & FLAG_NO_WAKE_UCAST) {
5454 + wol->supported &= ~WAKE_UCAST;
5456 + if (adapter->wol & E1000_WUFC_EX)
5457 + ndev_err(netdev, "Interface does not support "
5458 + "directed (unicast) frame wake-up packets\n");
5461 + if (adapter->wol & E1000_WUFC_EX)
5462 + wol->wolopts |= WAKE_UCAST;
5463 + if (adapter->wol & E1000_WUFC_MC)
5464 + wol->wolopts |= WAKE_MCAST;
5465 + if (adapter->wol & E1000_WUFC_BC)
5466 + wol->wolopts |= WAKE_BCAST;
5467 + if (adapter->wol & E1000_WUFC_MAG)
5468 + wol->wolopts |= WAKE_MAGIC;
5471 +static int e1000_set_wol(struct net_device *netdev,
5472 + struct ethtool_wolinfo *wol)
5474 + struct e1000_adapter *adapter = netdev_priv(netdev);
5476 + if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
5477 + return -EOPNOTSUPP;
5479 + if (!(adapter->flags & FLAG_HAS_WOL))
5480 + return wol->wolopts ? -EOPNOTSUPP : 0;
5482 + /* these settings will always override what we currently have */
5485 + if (wol->wolopts & WAKE_UCAST)
5486 + adapter->wol |= E1000_WUFC_EX;
5487 + if (wol->wolopts & WAKE_MCAST)
5488 + adapter->wol |= E1000_WUFC_MC;
5489 + if (wol->wolopts & WAKE_BCAST)
5490 + adapter->wol |= E1000_WUFC_BC;
5491 + if (wol->wolopts & WAKE_MAGIC)
5492 + adapter->wol |= E1000_WUFC_MAG;
5497 +/* toggle LED 4 times per second = 2 "blinks" per second */
5498 +#define E1000_ID_INTERVAL (HZ/4)
5500 +/* bit defines for adapter->led_status */
5501 +#define E1000_LED_ON 0
5503 +static void e1000_led_blink_callback(unsigned long data)
5505 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
5507 + if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
5508 + adapter->hw.mac.ops.led_off(&adapter->hw);
5510 + adapter->hw.mac.ops.led_on(&adapter->hw);
5512 + mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
5515 +static int e1000_phys_id(struct net_device *netdev, u32 data)
5517 + struct e1000_adapter *adapter = netdev_priv(netdev);
5519 + if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
5520 + data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
5522 + if (adapter->hw.phy.type == e1000_phy_ife) {
5523 + if (!adapter->blink_timer.function) {
5524 + init_timer(&adapter->blink_timer);
5525 + adapter->blink_timer.function =
5526 + e1000_led_blink_callback;
5527 + adapter->blink_timer.data = (unsigned long) adapter;
5529 + mod_timer(&adapter->blink_timer, jiffies);
5530 + msleep_interruptible(data * 1000);
5531 + del_timer_sync(&adapter->blink_timer);
5532 + e1e_wphy(&adapter->hw,
5533 + IFE_PHY_SPECIAL_CONTROL_LED, 0);
5535 + e1000e_blink_led(&adapter->hw);
5536 + msleep_interruptible(data * 1000);
5539 + adapter->hw.mac.ops.led_off(&adapter->hw);
5540 + clear_bit(E1000_LED_ON, &adapter->led_status);
5541 + adapter->hw.mac.ops.cleanup_led(&adapter->hw);
5546 +static int e1000_nway_reset(struct net_device *netdev)
5548 + struct e1000_adapter *adapter = netdev_priv(netdev);
5549 + if (netif_running(netdev))
5550 + e1000e_reinit_locked(adapter);
5554 +static int e1000_get_stats_count(struct net_device *netdev)
5556 + return E1000_STATS_LEN;
5559 +static void e1000_get_ethtool_stats(struct net_device *netdev,
5560 + struct ethtool_stats *stats,
5563 + struct e1000_adapter *adapter = netdev_priv(netdev);
5566 + e1000e_update_stats(adapter);
5567 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
5568 + char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
5569 + data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
5570 + sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
5574 +static void e1000_get_strings(struct net_device *netdev, u32 stringset,
5580 + switch (stringset) {
5582 + memcpy(data, *e1000_gstrings_test,
5583 + E1000_TEST_LEN*ETH_GSTRING_LEN);
5585 + case ETH_SS_STATS:
5586 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
5587 + memcpy(p, e1000_gstrings_stats[i].stat_string,
5589 + p += ETH_GSTRING_LEN;
5595 +static const struct ethtool_ops e1000_ethtool_ops = {
5596 + .get_settings = e1000_get_settings,
5597 + .set_settings = e1000_set_settings,
5598 + .get_drvinfo = e1000_get_drvinfo,
5599 + .get_regs_len = e1000_get_regs_len,
5600 + .get_regs = e1000_get_regs,
5601 + .get_wol = e1000_get_wol,
5602 + .set_wol = e1000_set_wol,
5603 + .get_msglevel = e1000_get_msglevel,
5604 + .set_msglevel = e1000_set_msglevel,
5605 + .nway_reset = e1000_nway_reset,
5606 + .get_link = ethtool_op_get_link,
5607 + .get_eeprom_len = e1000_get_eeprom_len,
5608 + .get_eeprom = e1000_get_eeprom,
5609 + .set_eeprom = e1000_set_eeprom,
5610 + .get_ringparam = e1000_get_ringparam,
5611 + .set_ringparam = e1000_set_ringparam,
5612 + .get_pauseparam = e1000_get_pauseparam,
5613 + .set_pauseparam = e1000_set_pauseparam,
5614 + .get_rx_csum = e1000_get_rx_csum,
5615 + .set_rx_csum = e1000_set_rx_csum,
5616 + .get_tx_csum = e1000_get_tx_csum,
5617 + .set_tx_csum = e1000_set_tx_csum,
5618 + .get_sg = ethtool_op_get_sg,
5619 + .set_sg = ethtool_op_set_sg,
5620 + .get_tso = ethtool_op_get_tso,
5621 + .set_tso = e1000_set_tso,
5622 + .self_test_count = e1000_diag_test_count,
5623 + .self_test = e1000_diag_test,
5624 + .get_strings = e1000_get_strings,
5625 + .phys_id = e1000_phys_id,
5626 + .get_stats_count = e1000_get_stats_count,
5627 + .get_ethtool_stats = e1000_get_ethtool_stats,
5630 +void e1000e_set_ethtool_ops(struct net_device *netdev)
5632 + SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
5634 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/hw.h linux-2.6.22-10/drivers/net/e1000e/hw.h
5635 --- linux-2.6.22-0/drivers/net/e1000e/hw.h 1969-12-31 19:00:00.000000000 -0500
5636 +++ linux-2.6.22-10/drivers/net/e1000e/hw.h 2007-11-21 13:55:23.000000000 -0500
5638 +/*******************************************************************************
5640 + Intel PRO/1000 Linux driver
5641 + Copyright(c) 1999 - 2007 Intel Corporation.
5643 + This program is free software; you can redistribute it and/or modify it
5644 + under the terms and conditions of the GNU General Public License,
5645 + version 2, as published by the Free Software Foundation.
5647 + This program is distributed in the hope it will be useful, but WITHOUT
5648 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5649 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5652 + You should have received a copy of the GNU General Public License along with
5653 + this program; if not, write to the Free Software Foundation, Inc.,
5654 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5656 + The full GNU General Public License is included in this distribution in
5657 + the file called "COPYING".
5659 + Contact Information:
5660 + Linux NICS <linux.nics@intel.com>
5661 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
5662 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
5664 +*******************************************************************************/
5666 +#ifndef _E1000_HW_H_
5667 +#define _E1000_HW_H_
5669 +#include <linux/types.h>
5672 +struct e1000_adapter;
5674 +#include "defines.h"
5676 +#define er32(reg) __er32(hw, E1000_##reg)
5677 +#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
5678 +#define e1e_flush() er32(STATUS)
5680 +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
5681 + (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
5683 +#define E1000_READ_REG_ARRAY(a, reg, offset) \
5684 + (readl((a)->hw_addr + reg + ((offset) << 2)))
5686 +enum e1e_registers {
5687 + E1000_CTRL = 0x00000, /* Device Control - RW */
5688 + E1000_STATUS = 0x00008, /* Device Status - RO */
5689 + E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
5690 + E1000_EERD = 0x00014, /* EEPROM Read - RW */
5691 + E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
5692 + E1000_FLA = 0x0001C, /* Flash Access - RW */
5693 + E1000_MDIC = 0x00020, /* MDI Control - RW */
5694 + E1000_SCTL = 0x00024, /* SerDes Control - RW */
5695 + E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
5696 + E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
5697 + E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
5698 + E1000_FCT = 0x00030, /* Flow Control Type - RW */
5699 + E1000_VET = 0x00038, /* VLAN Ether Type - RW */
5700 + E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
5701 + E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
5702 + E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
5703 + E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
5704 + E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
5705 + E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
5706 + E1000_RCTL = 0x00100, /* RX Control - RW */
5707 + E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
5708 + E1000_TXCW = 0x00178, /* TX Configuration Word - RW */
5709 + E1000_RXCW = 0x00180, /* RX Configuration Word - RO */
5710 + E1000_TCTL = 0x00400, /* TX Control - RW */
5711 + E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */
5712 + E1000_TIPG = 0x00410, /* TX Inter-packet gap -RW */
5713 + E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */
5714 + E1000_LEDCTL = 0x00E00, /* LED Control - RW */
5715 + E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
5716 + E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
5717 + E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
5718 + E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
5719 + E1000_PBS = 0x01008, /* Packet Buffer Size */
5720 + E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
5721 + E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
5722 + E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
5723 + E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
5724 + E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
5725 + E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
5726 + E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
5727 + E1000_RDBAL = 0x02800, /* RX Descriptor Base Address Low - RW */
5728 + E1000_RDBAH = 0x02804, /* RX Descriptor Base Address High - RW */
5729 + E1000_RDLEN = 0x02808, /* RX Descriptor Length - RW */
5730 + E1000_RDH = 0x02810, /* RX Descriptor Head - RW */
5731 + E1000_RDT = 0x02818, /* RX Descriptor Tail - RW */
5732 + E1000_RDTR = 0x02820, /* RX Delay Timer - RW */
5733 + E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
5735 +/* Convenience macros
5737 + * Note: "_n" is the queue number of the register to be written to.
5740 + * E1000_RDBAL_REG(current_rx_queue)
5743 +#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
5744 + E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
5745 + E1000_TDBAL = 0x03800, /* TX Descriptor Base Address Low - RW */
5746 + E1000_TDBAH = 0x03804, /* TX Descriptor Base Address High - RW */
5747 + E1000_TDLEN = 0x03808, /* TX Descriptor Length - RW */
5748 + E1000_TDH = 0x03810, /* TX Descriptor Head - RW */
5749 + E1000_TDT = 0x03818, /* TX Descriptor Tail - RW */
5750 + E1000_TIDV = 0x03820, /* TX Interrupt Delay Value - RW */
5751 + E1000_TXDCTL = 0x03828, /* TX Descriptor Control - RW */
5752 + E1000_TADV = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */
5753 + E1000_TARC0 = 0x03840, /* TX Arbitration Count (0) */
5754 + E1000_TXDCTL1 = 0x03928, /* TX Descriptor Control (1) - RW */
5755 + E1000_TARC1 = 0x03940, /* TX Arbitration Count (1) */
5756 + E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
5757 + E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
5758 + E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
5759 + E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
5760 + E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
5761 + E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
5762 + E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
5763 + E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
5764 + E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
5765 + E1000_COLC = 0x04028, /* Collision Count - R/clr */
5766 + E1000_DC = 0x04030, /* Defer Count - R/clr */
5767 + E1000_TNCRS = 0x04034, /* TX-No CRS - R/clr */
5768 + E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
5769 + E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
5770 + E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
5771 + E1000_XONRXC = 0x04048, /* XON RX Count - R/clr */
5772 + E1000_XONTXC = 0x0404C, /* XON TX Count - R/clr */
5773 + E1000_XOFFRXC = 0x04050, /* XOFF RX Count - R/clr */
5774 + E1000_XOFFTXC = 0x04054, /* XOFF TX Count - R/clr */
5775 + E1000_FCRUC = 0x04058, /* Flow Control RX Unsupported Count- R/clr */
5776 + E1000_PRC64 = 0x0405C, /* Packets RX (64 bytes) - R/clr */
5777 + E1000_PRC127 = 0x04060, /* Packets RX (65-127 bytes) - R/clr */
5778 + E1000_PRC255 = 0x04064, /* Packets RX (128-255 bytes) - R/clr */
5779 + E1000_PRC511 = 0x04068, /* Packets RX (255-511 bytes) - R/clr */
5780 + E1000_PRC1023 = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */
5781 + E1000_PRC1522 = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */
5782 + E1000_GPRC = 0x04074, /* Good Packets RX Count - R/clr */
5783 + E1000_BPRC = 0x04078, /* Broadcast Packets RX Count - R/clr */
5784 + E1000_MPRC = 0x0407C, /* Multicast Packets RX Count - R/clr */
5785 + E1000_GPTC = 0x04080, /* Good Packets TX Count - R/clr */
5786 + E1000_GORCL = 0x04088, /* Good Octets RX Count Low - R/clr */
5787 + E1000_GORCH = 0x0408C, /* Good Octets RX Count High - R/clr */
5788 + E1000_GOTCL = 0x04090, /* Good Octets TX Count Low - R/clr */
5789 + E1000_GOTCH = 0x04094, /* Good Octets TX Count High - R/clr */
5790 + E1000_RNBC = 0x040A0, /* RX No Buffers Count - R/clr */
5791 + E1000_RUC = 0x040A4, /* RX Undersize Count - R/clr */
5792 + E1000_RFC = 0x040A8, /* RX Fragment Count - R/clr */
5793 + E1000_ROC = 0x040AC, /* RX Oversize Count - R/clr */
5794 + E1000_RJC = 0x040B0, /* RX Jabber Count - R/clr */
5795 + E1000_MGTPRC = 0x040B4, /* Management Packets RX Count - R/clr */
5796 + E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
5797 + E1000_MGTPTC = 0x040BC, /* Management Packets TX Count - R/clr */
5798 + E1000_TORL = 0x040C0, /* Total Octets RX Low - R/clr */
5799 + E1000_TORH = 0x040C4, /* Total Octets RX High - R/clr */
5800 + E1000_TOTL = 0x040C8, /* Total Octets TX Low - R/clr */
5801 + E1000_TOTH = 0x040CC, /* Total Octets TX High - R/clr */
5802 + E1000_TPR = 0x040D0, /* Total Packets RX - R/clr */
5803 + E1000_TPT = 0x040D4, /* Total Packets TX - R/clr */
5804 + E1000_PTC64 = 0x040D8, /* Packets TX (64 bytes) - R/clr */
5805 + E1000_PTC127 = 0x040DC, /* Packets TX (65-127 bytes) - R/clr */
5806 + E1000_PTC255 = 0x040E0, /* Packets TX (128-255 bytes) - R/clr */
5807 + E1000_PTC511 = 0x040E4, /* Packets TX (256-511 bytes) - R/clr */
5808 + E1000_PTC1023 = 0x040E8, /* Packets TX (512-1023 bytes) - R/clr */
5809 + E1000_PTC1522 = 0x040EC, /* Packets TX (1024-1522 Bytes) - R/clr */
5810 + E1000_MPTC = 0x040F0, /* Multicast Packets TX Count - R/clr */
5811 + E1000_BPTC = 0x040F4, /* Broadcast Packets TX Count - R/clr */
5812 + E1000_TSCTC = 0x040F8, /* TCP Segmentation Context TX - R/clr */
5813 + E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context TX Fail - R/clr */
5814 + E1000_IAC = 0x04100, /* Interrupt Assertion Count */
5815 + E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
5816 + E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
5817 + E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
5818 + E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
5819 + E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
5820 + E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
5821 + E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
5822 + E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
5823 + E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */
5824 + E1000_RFCTL = 0x05008, /* Receive Filter Control*/
5825 + E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
5826 + E1000_RA = 0x05400, /* Receive Address - RW Array */
5827 + E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
5828 + E1000_WUC = 0x05800, /* Wakeup Control - RW */
5829 + E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
5830 + E1000_WUS = 0x05810, /* Wakeup Status - RO */
5831 + E1000_MANC = 0x05820, /* Management Control - RW */
5832 + E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
5833 + E1000_HOST_IF = 0x08800, /* Host Interface */
5835 + E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
5836 + E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
5837 + E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
5838 + E1000_GCR = 0x05B00, /* PCI-Ex Control */
5839 + E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
5840 + E1000_SWSM = 0x05B50, /* SW Semaphore */
5841 + E1000_FWSM = 0x05B54, /* FW Semaphore */
5842 + E1000_HICR = 0x08F00, /* Host Inteface Control */
5845 +/* RSS registers */
5847 +/* IGP01E1000 Specific Registers */
5848 +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
5849 +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
5850 +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
5851 +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
5852 +#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
5853 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
5855 +#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
5856 +#define IGP01E1000_PHY_POLARITY_MASK 0x0078
5858 +#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
5859 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
5861 +#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
5863 +#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
5864 +#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
5865 +#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
5867 +#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
5869 +#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
5870 +#define IGP01E1000_PSSR_MDIX 0x0008
5871 +#define IGP01E1000_PSSR_SPEED_MASK 0xC000
5872 +#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
5874 +#define IGP02E1000_PHY_CHANNEL_NUM 4
5875 +#define IGP02E1000_PHY_AGC_A 0x11B1
5876 +#define IGP02E1000_PHY_AGC_B 0x12B1
5877 +#define IGP02E1000_PHY_AGC_C 0x14B1
5878 +#define IGP02E1000_PHY_AGC_D 0x18B1
5880 +#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
5881 +#define IGP02E1000_AGC_LENGTH_MASK 0x7F
5882 +#define IGP02E1000_AGC_RANGE 15
5885 +#define E1000_VFTA_ENTRY_SHIFT 5
5886 +#define E1000_VFTA_ENTRY_MASK 0x7F
5887 +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
5889 +#define E1000_HICR_EN 0x01 /* Enable bit - RO */
5890 +#define E1000_HICR_C 0x02 /* Driver sets this bit when done
5891 + * to put command in RAM */
5892 +#define E1000_HICR_FW_RESET_ENABLE 0x40
5893 +#define E1000_HICR_FW_RESET 0x80
5895 +#define E1000_FWSM_MODE_MASK 0xE
5896 +#define E1000_FWSM_MODE_SHIFT 1
5898 +#define E1000_MNG_IAMT_MODE 0x3
5899 +#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
5900 +#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
5901 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
5902 +#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
5903 +#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
5904 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
5907 +#define E1000_STM_OPCODE 0xDB00
5909 +#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
5910 +#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
5911 +#define E1000_KMRNCTRLSTA_REN 0x00200000
5912 +#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
5913 +#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
5915 +#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
5916 +#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
5917 +#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
5918 +#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
5920 +/* IFE PHY Extended Status Control */
5921 +#define IFE_PESC_POLARITY_REVERSED 0x0100
5923 +/* IFE PHY Special Control */
5924 +#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
5925 +#define IFE_PSC_FORCE_POLARITY 0x0020
5927 +/* IFE PHY Special Control and LED Control */
5928 +#define IFE_PSCL_PROBE_MODE 0x0020
5929 +#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
5930 +#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
5932 +/* IFE PHY MDIX Control */
5933 +#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
5934 +#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
5935 +#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
5937 +#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
5939 +#define E1000_DEV_ID_82571EB_COPPER 0x105E
5940 +#define E1000_DEV_ID_82571EB_FIBER 0x105F
5941 +#define E1000_DEV_ID_82571EB_SERDES 0x1060
5942 +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
5943 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
5944 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
5945 +#define E1000_DEV_ID_82572EI_COPPER 0x107D
5946 +#define E1000_DEV_ID_82572EI_FIBER 0x107E
5947 +#define E1000_DEV_ID_82572EI_SERDES 0x107F
5948 +#define E1000_DEV_ID_82572EI 0x10B9
5949 +#define E1000_DEV_ID_82573E 0x108B
5950 +#define E1000_DEV_ID_82573E_IAMT 0x108C
5951 +#define E1000_DEV_ID_82573L 0x109A
5953 +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
5954 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
5955 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
5956 +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
5958 +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
5959 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
5960 +#define E1000_DEV_ID_ICH8_IGP_C 0x104B
5961 +#define E1000_DEV_ID_ICH8_IFE 0x104C
5962 +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
5963 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
5964 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D
5965 +#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
5966 +#define E1000_DEV_ID_ICH9_IGP_C 0x294C
5967 +#define E1000_DEV_ID_ICH9_IFE 0x10C0
5968 +#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
5969 +#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
5971 +#define E1000_FUNC_1 1
5973 +enum e1000_mac_type {
5977 + e1000_80003es2lan,
5982 +enum e1000_media_type {
5983 + e1000_media_type_unknown = 0,
5984 + e1000_media_type_copper = 1,
5985 + e1000_media_type_fiber = 2,
5986 + e1000_media_type_internal_serdes = 3,
5987 + e1000_num_media_types
5990 +enum e1000_nvm_type {
5991 + e1000_nvm_unknown = 0,
5993 + e1000_nvm_eeprom_spi,
5994 + e1000_nvm_flash_hw,
5995 + e1000_nvm_flash_sw
5998 +enum e1000_nvm_override {
5999 + e1000_nvm_override_none = 0,
6000 + e1000_nvm_override_spi_small,
6001 + e1000_nvm_override_spi_large
6004 +enum e1000_phy_type {
6005 + e1000_phy_unknown = 0,
6010 + e1000_phy_gg82563,
6015 +enum e1000_bus_width {
6016 + e1000_bus_width_unknown = 0,
6017 + e1000_bus_width_pcie_x1,
6018 + e1000_bus_width_pcie_x2,
6019 + e1000_bus_width_pcie_x4 = 4,
6020 + e1000_bus_width_32,
6021 + e1000_bus_width_64,
6022 + e1000_bus_width_reserved
6025 +enum e1000_1000t_rx_status {
6026 + e1000_1000t_rx_status_not_ok = 0,
6027 + e1000_1000t_rx_status_ok,
6028 + e1000_1000t_rx_status_undefined = 0xFF
6031 +enum e1000_rev_polarity{
6032 + e1000_rev_polarity_normal = 0,
6033 + e1000_rev_polarity_reversed,
6034 + e1000_rev_polarity_undefined = 0xFF
6037 +enum e1000_fc_mode {
6038 + e1000_fc_none = 0,
6039 + e1000_fc_rx_pause,
6040 + e1000_fc_tx_pause,
6042 + e1000_fc_default = 0xFF
6045 +enum e1000_ms_type {
6046 + e1000_ms_hw_default = 0,
6047 + e1000_ms_force_master,
6048 + e1000_ms_force_slave,
6052 +enum e1000_smart_speed {
6053 + e1000_smart_speed_default = 0,
6054 + e1000_smart_speed_on,
6055 + e1000_smart_speed_off
6058 +/* Receive Descriptor */
6059 +struct e1000_rx_desc {
6060 + u64 buffer_addr; /* Address of the descriptor's data buffer */
6061 + u16 length; /* Length of data DMAed into data buffer */
6062 + u16 csum; /* Packet checksum */
6063 + u8 status; /* Descriptor status */
6064 + u8 errors; /* Descriptor Errors */
6068 +/* Receive Descriptor - Extended */
6069 +union e1000_rx_desc_extended {
6076 + u32 mrq; /* Multiple Rx Queues */
6078 + u32 rss; /* RSS Hash */
6080 + u16 ip_id; /* IP id */
6081 + u16 csum; /* Packet Checksum */
6086 + u32 status_error; /* ext status/error */
6088 + u16 vlan; /* VLAN tag */
6090 + } wb; /* writeback */
6093 +#define MAX_PS_BUFFERS 4
6094 +/* Receive Descriptor - Packet Split */
6095 +union e1000_rx_desc_packet_split {
6097 + /* one buffer for protocol header(s), three data buffers */
6098 + u64 buffer_addr[MAX_PS_BUFFERS];
6102 + u32 mrq; /* Multiple Rx Queues */
6104 + u32 rss; /* RSS Hash */
6106 + u16 ip_id; /* IP id */
6107 + u16 csum; /* Packet Checksum */
6112 + u32 status_error; /* ext status/error */
6113 + u16 length0; /* length of buffer 0 */
6114 + u16 vlan; /* VLAN tag */
6117 + u16 header_status;
6118 + u16 length[3]; /* length of buffers 1-3 */
6121 + } wb; /* writeback */
6124 +/* Transmit Descriptor */
6125 +struct e1000_tx_desc {
6126 + u64 buffer_addr; /* Address of the descriptor's data buffer */
6130 + u16 length; /* Data buffer length */
6131 + u8 cso; /* Checksum offset */
6132 + u8 cmd; /* Descriptor control */
6138 + u8 status; /* Descriptor status */
6139 + u8 css; /* Checksum start */
6145 +/* Offload Context Descriptor */
6146 +struct e1000_context_desc {
6150 + u8 ipcss; /* IP checksum start */
6151 + u8 ipcso; /* IP checksum offset */
6152 + u16 ipcse; /* IP checksum end */
6158 + u8 tucss; /* TCP checksum start */
6159 + u8 tucso; /* TCP checksum offset */
6160 + u16 tucse; /* TCP checksum end */
6163 + u32 cmd_and_length;
6167 + u8 status; /* Descriptor status */
6168 + u8 hdr_len; /* Header length */
6169 + u16 mss; /* Maximum segment size */
6174 +/* Offload data descriptor */
6175 +struct e1000_data_desc {
6176 + u64 buffer_addr; /* Address of the descriptor's buffer address */
6180 + u16 length; /* Data buffer length */
6188 + u8 status; /* Descriptor status */
6189 + u8 popts; /* Packet Options */
6190 + u16 special; /* */
6195 +/* Statistics counters collected by the MAC */
6196 +struct e1000_hw_stats {
6266 +struct e1000_phy_stats {
6268 + u32 receive_errors;
6271 +struct e1000_host_mng_dhcp_cookie {
6282 +/* Host Interface "Rev 1" */
6283 +struct e1000_host_command_header {
6285 + u8 command_length;
6286 + u8 command_options;
6290 +#define E1000_HI_MAX_DATA_LENGTH 252
6291 +struct e1000_host_command_info {
6292 + struct e1000_host_command_header command_header;
6293 + u8 command_data[E1000_HI_MAX_DATA_LENGTH];
6296 +/* Host Interface "Rev 2" */
6297 +struct e1000_host_mng_command_header {
6302 + u16 command_length;
6305 +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
6306 +struct e1000_host_mng_command_info {
6307 + struct e1000_host_mng_command_header command_header;
6308 + u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
6311 +/* Function pointers and static data for the MAC. */
6312 +struct e1000_mac_operations {
6313 + u32 mng_mode_enab;
6315 + s32 (*check_for_link)(struct e1000_hw *);
6316 + s32 (*cleanup_led)(struct e1000_hw *);
6317 + void (*clear_hw_cntrs)(struct e1000_hw *);
6318 + s32 (*get_bus_info)(struct e1000_hw *);
6319 + s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
6320 + s32 (*led_on)(struct e1000_hw *);
6321 + s32 (*led_off)(struct e1000_hw *);
6322 + void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32,
6324 + s32 (*reset_hw)(struct e1000_hw *);
6325 + s32 (*init_hw)(struct e1000_hw *);
6326 + s32 (*setup_link)(struct e1000_hw *);
6327 + s32 (*setup_physical_interface)(struct e1000_hw *);
6330 +/* Function pointers for the PHY. */
6331 +struct e1000_phy_operations {
6332 + s32 (*acquire_phy)(struct e1000_hw *);
6333 + s32 (*check_reset_block)(struct e1000_hw *);
6334 + s32 (*commit_phy)(struct e1000_hw *);
6335 + s32 (*force_speed_duplex)(struct e1000_hw *);
6336 + s32 (*get_cfg_done)(struct e1000_hw *hw);
6337 + s32 (*get_cable_length)(struct e1000_hw *);
6338 + s32 (*get_phy_info)(struct e1000_hw *);
6339 + s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
6340 + void (*release_phy)(struct e1000_hw *);
6341 + s32 (*reset_phy)(struct e1000_hw *);
6342 + s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
6343 + s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
6344 + s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
6347 +/* Function pointers for the NVM. */
6348 +struct e1000_nvm_operations {
6349 + s32 (*acquire_nvm)(struct e1000_hw *);
6350 + s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
6351 + void (*release_nvm)(struct e1000_hw *);
6352 + s32 (*update_nvm)(struct e1000_hw *);
6353 + s32 (*valid_led_default)(struct e1000_hw *, u16 *);
6354 + s32 (*validate_nvm)(struct e1000_hw *);
6355 + s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
6358 +struct e1000_mac_info {
6359 + struct e1000_mac_operations ops;
6364 + enum e1000_mac_type type;
6365 + enum e1000_fc_mode fc;
6366 + enum e1000_fc_mode original_fc;
6368 + u32 collision_delta;
6369 + u32 ledctl_default;
6372 + u32 max_frame_size;
6373 + u32 mc_filter_type;
6374 + u32 min_frame_size;
6375 + u32 tx_packet_delta;
6378 + u16 current_ifs_val;
6382 + u16 ifs_step_size;
6383 + u16 mta_reg_count;
6384 + u16 rar_entry_count;
6385 + u16 fc_high_water;
6387 + u16 fc_pause_time;
6389 + u8 forced_speed_duplex;
6391 + bool arc_subsystem_valid;
6393 + bool autoneg_failed;
6394 + bool get_link_status;
6396 + bool serdes_has_link;
6397 + bool tx_pkt_filtering;
6400 +struct e1000_phy_info {
6401 + struct e1000_phy_operations ops;
6403 + enum e1000_phy_type type;
6405 + enum e1000_1000t_rx_status local_rx;
6406 + enum e1000_1000t_rx_status remote_rx;
6407 + enum e1000_ms_type ms_type;
6408 + enum e1000_ms_type original_ms_type;
6409 + enum e1000_rev_polarity cable_polarity;
6410 + enum e1000_smart_speed smart_speed;
6414 + u32 reset_delay_us; /* in usec */
6417 + u16 autoneg_advertised;
6420 + u16 max_cable_length;
6421 + u16 min_cable_length;
6425 + bool disable_polarity_correction;
6427 + bool polarity_correction;
6428 + bool speed_downgraded;
6429 + bool wait_for_link;
6432 +struct e1000_nvm_info {
6433 + struct e1000_nvm_operations ops;
6435 + enum e1000_nvm_type type;
6436 + enum e1000_nvm_override override;
6438 + u32 flash_bank_size;
6439 + u32 flash_base_addr;
6448 +struct e1000_bus_info {
6449 + enum e1000_bus_width width;
6454 +struct e1000_dev_spec_82571 {
6455 + bool laa_is_present;
6458 +struct e1000_shadow_ram {
6463 +#define E1000_ICH8_SHADOW_RAM_WORDS 2048
6465 +struct e1000_dev_spec_ich8lan {
6466 + bool kmrn_lock_loss_workaround_enabled;
6467 + struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
6471 + struct e1000_adapter *adapter;
6473 + u8 __iomem *hw_addr;
6474 + u8 __iomem *flash_address;
6476 + struct e1000_mac_info mac;
6477 + struct e1000_phy_info phy;
6478 + struct e1000_nvm_info nvm;
6479 + struct e1000_bus_info bus;
6480 + struct e1000_host_mng_dhcp_cookie mng_cookie;
6483 + struct e1000_dev_spec_82571 e82571;
6484 + struct e1000_dev_spec_ich8lan ich8lan;
6487 + enum e1000_media_type media_type;
6491 +#define hw_dbg(hw, format, arg...) \
6492 + printk(KERN_DEBUG, "%s: " format, e1000_get_hw_dev_name(hw), ##arg);
6494 +static inline int __attribute__ ((format (printf, 2, 3)))
6495 +hw_dbg(struct e1000_hw *hw, const char *format, ...)
6502 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/ich8lan.c linux-2.6.22-10/drivers/net/e1000e/ich8lan.c
6503 --- linux-2.6.22-0/drivers/net/e1000e/ich8lan.c 1969-12-31 19:00:00.000000000 -0500
6504 +++ linux-2.6.22-10/drivers/net/e1000e/ich8lan.c 2007-11-21 13:55:28.000000000 -0500
6506 +/*******************************************************************************
6508 + Intel PRO/1000 Linux driver
6509 + Copyright(c) 1999 - 2007 Intel Corporation.
6511 + This program is free software; you can redistribute it and/or modify it
6512 + under the terms and conditions of the GNU General Public License,
6513 + version 2, as published by the Free Software Foundation.
6515 + This program is distributed in the hope it will be useful, but WITHOUT
6516 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6517 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6520 + You should have received a copy of the GNU General Public License along with
6521 + this program; if not, write to the Free Software Foundation, Inc.,
6522 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6524 + The full GNU General Public License is included in this distribution in
6525 + the file called "COPYING".
6527 + Contact Information:
6528 + Linux NICS <linux.nics@intel.com>
6529 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
6530 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
6532 +*******************************************************************************/
6535 + * 82562G-2 10/100 Network Connection
6536 + * 82562GT 10/100 Network Connection
6537 + * 82562GT-2 10/100 Network Connection
6538 + * 82562V 10/100 Network Connection
6539 + * 82562V-2 10/100 Network Connection
6540 + * 82566DC-2 Gigabit Network Connection
6541 + * 82566DC Gigabit Network Connection
6542 + * 82566DM-2 Gigabit Network Connection
6543 + * 82566DM Gigabit Network Connection
6544 + * 82566MC Gigabit Network Connection
6545 + * 82566MM Gigabit Network Connection
6548 +#include <linux/netdevice.h>
6549 +#include <linux/ethtool.h>
6550 +#include <linux/delay.h>
6551 +#include <linux/pci.h>
6555 +#define ICH_FLASH_GFPREG 0x0000
6556 +#define ICH_FLASH_HSFSTS 0x0004
6557 +#define ICH_FLASH_HSFCTL 0x0006
6558 +#define ICH_FLASH_FADDR 0x0008
6559 +#define ICH_FLASH_FDATA0 0x0010
6561 +#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
6562 +#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
6563 +#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
6564 +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
6565 +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
6567 +#define ICH_CYCLE_READ 0
6568 +#define ICH_CYCLE_WRITE 2
6569 +#define ICH_CYCLE_ERASE 3
6571 +#define FLASH_GFPREG_BASE_MASK 0x1FFF
6572 +#define FLASH_SECTOR_ADDR_SHIFT 12
6574 +#define ICH_FLASH_SEG_SIZE_256 256
6575 +#define ICH_FLASH_SEG_SIZE_4K 4096
6576 +#define ICH_FLASH_SEG_SIZE_8K 8192
6577 +#define ICH_FLASH_SEG_SIZE_64K 65536
6580 +#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6582 +#define E1000_ICH_MNG_IAMT_MODE 0x2
6584 +#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
6585 + (ID_LED_DEF1_OFF2 << 8) | \
6586 + (ID_LED_DEF1_ON2 << 4) | \
6587 + (ID_LED_DEF1_DEF2))
6589 +#define E1000_ICH_NVM_SIG_WORD 0x13
6590 +#define E1000_ICH_NVM_SIG_MASK 0xC000
6592 +#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
6594 +#define E1000_FEXTNVM_SW_CONFIG 1
6595 +#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
6597 +#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
6599 +#define E1000_ICH_RAR_ENTRIES 7
6601 +#define PHY_PAGE_SHIFT 5
6602 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
6603 + ((reg) & MAX_PHY_REG_ADDRESS))
6604 +#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
6605 +#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
6607 +#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
6608 +#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
6609 +#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
6611 +/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
6612 +/* Offset 04h HSFSTS */
6613 +union ich8_hws_flash_status {
6614 + struct ich8_hsfsts {
6615 + u16 flcdone :1; /* bit 0 Flash Cycle Done */
6616 + u16 flcerr :1; /* bit 1 Flash Cycle Error */
6617 + u16 dael :1; /* bit 2 Direct Access error Log */
6618 + u16 berasesz :2; /* bit 4:3 Sector Erase Size */
6619 + u16 flcinprog :1; /* bit 5 flash cycle in Progress */
6620 + u16 reserved1 :2; /* bit 13:6 Reserved */
6621 + u16 reserved2 :6; /* bit 13:6 Reserved */
6622 + u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
6623 + u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
6628 +/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
6629 +/* Offset 06h FLCTL */
6630 +union ich8_hws_flash_ctrl {
6631 + struct ich8_hsflctl {
6632 + u16 flcgo :1; /* 0 Flash Cycle Go */
6633 + u16 flcycle :2; /* 2:1 Flash Cycle */
6634 + u16 reserved :5; /* 7:3 Reserved */
6635 + u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
6636 + u16 flockdn :6; /* 15:10 Reserved */
6641 +/* ICH Flash Region Access Permissions */
6642 +union ich8_hws_flash_regacc {
6643 + struct ich8_flracc {
6644 + u32 grra :8; /* 0:7 GbE region Read Access */
6645 + u32 grwa :8; /* 8:15 GbE region Write Access */
6646 + u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
6647 + u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
6652 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
6653 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
6654 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
6655 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
6656 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
6657 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
6658 + u32 offset, u8 byte);
6659 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
6661 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
6662 + u8 size, u16 *data);
6663 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
6664 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
6666 +static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
6668 + return readw(hw->flash_address + reg);
6671 +static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
6673 + return readl(hw->flash_address + reg);
6676 +static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
6678 + writew(val, hw->flash_address + reg);
6681 +static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
6683 + writel(val, hw->flash_address + reg);
6686 +#define er16flash(reg) __er16flash(hw, (reg))
6687 +#define er32flash(reg) __er32flash(hw, (reg))
6688 +#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
6689 +#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
6692 + * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
6693 + * @hw: pointer to the HW structure
6695 + * Initialize family-specific PHY parameters and function pointers.
6697 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
6699 + struct e1000_phy_info *phy = &hw->phy;
6704 + phy->reset_delay_us = 100;
6707 + while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
6710 + ret_val = e1000e_get_phy_id(hw);
6715 + /* Verify phy id */
6716 + switch (phy->id) {
6717 + case IGP03E1000_E_PHY_ID:
6718 + phy->type = e1000_phy_igp_3;
6719 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
6721 + case IFE_E_PHY_ID:
6722 + case IFE_PLUS_E_PHY_ID:
6723 + case IFE_C_E_PHY_ID:
6724 + phy->type = e1000_phy_ife;
6725 + phy->autoneg_mask = E1000_ALL_NOT_GIG;
6728 + return -E1000_ERR_PHY;
6736 + * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
6737 + * @hw: pointer to the HW structure
6739 + * Initialize family-specific NVM parameters and function
6742 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
6744 + struct e1000_nvm_info *nvm = &hw->nvm;
6745 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
6747 + u32 sector_base_addr;
6748 + u32 sector_end_addr;
6751 + /* Can't read flash registers if the register set isn't mapped.
6753 + if (!hw->flash_address) {
6754 + hw_dbg(hw, "ERROR: Flash registers not mapped\n");
6755 + return -E1000_ERR_CONFIG;
6758 + nvm->type = e1000_nvm_flash_sw;
6760 + gfpreg = er32flash(ICH_FLASH_GFPREG);
6762 + /* sector_X_addr is a "sector"-aligned address (4096 bytes)
6763 + * Add 1 to sector_end_addr since this sector is included in
6764 + * the overall size. */
6765 + sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
6766 + sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
6768 + /* flash_base_addr is byte-aligned */
6769 + nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
6771 + /* find total size of the NVM, then cut in half since the total
6772 + * size represents two separate NVM banks. */
6773 + nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
6774 + << FLASH_SECTOR_ADDR_SHIFT;
6775 + nvm->flash_bank_size /= 2;
6776 + /* Adjust to word count */
6777 + nvm->flash_bank_size /= sizeof(u16);
6779 + nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
6781 + /* Clear shadow ram */
6782 + for (i = 0; i < nvm->word_size; i++) {
6783 + dev_spec->shadow_ram[i].modified = 0;
6784 + dev_spec->shadow_ram[i].value = 0xFFFF;
6791 + * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
6792 + * @hw: pointer to the HW structure
6794 + * Initialize family-specific MAC parameters and function
6797 +static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
6799 + struct e1000_hw *hw = &adapter->hw;
6800 + struct e1000_mac_info *mac = &hw->mac;
6802 + /* Set media type function pointer */
6803 + hw->media_type = e1000_media_type_copper;
6805 + /* Set mta register count */
6806 + mac->mta_reg_count = 32;
6807 + /* Set rar entry count */
6808 + mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
6809 + if (mac->type == e1000_ich8lan)
6810 + mac->rar_entry_count--;
6811 + /* Set if manageability features are enabled. */
6812 + mac->arc_subsystem_valid = 1;
6814 + /* Enable PCS Lock-loss workaround for ICH8 */
6815 + if (mac->type == e1000_ich8lan)
6816 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
6821 +static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter)
6823 + struct e1000_hw *hw = &adapter->hw;
6826 + rc = e1000_init_mac_params_ich8lan(adapter);
6830 + rc = e1000_init_nvm_params_ich8lan(hw);
6834 + rc = e1000_init_phy_params_ich8lan(hw);
6838 + if ((adapter->hw.mac.type == e1000_ich8lan) &&
6839 + (adapter->hw.phy.type == e1000_phy_igp_3))
6840 + adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
6846 + * e1000_acquire_swflag_ich8lan - Acquire software control flag
6847 + * @hw: pointer to the HW structure
6849 + * Acquires the software control flag for performing NVM and PHY
6850 + * operations. This is a function pointer entry point only called by
6851 + * read/write routines for the PHY and NVM parts.
6853 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
6856 + u32 timeout = PHY_CFG_TIMEOUT;
6859 + extcnf_ctrl = er32(EXTCNF_CTRL);
6860 + extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
6861 + ew32(EXTCNF_CTRL, extcnf_ctrl);
6863 + extcnf_ctrl = er32(EXTCNF_CTRL);
6864 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
6871 + hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
6872 + return -E1000_ERR_CONFIG;
6879 + * e1000_release_swflag_ich8lan - Release software control flag
6880 + * @hw: pointer to the HW structure
6882 + * Releases the software control flag for performing NVM and PHY operations.
6883 + * This is a function pointer entry point only called by read/write
6884 + * routines for the PHY and NVM parts.
6886 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
6890 + extcnf_ctrl = er32(EXTCNF_CTRL);
6891 + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
6892 + ew32(EXTCNF_CTRL, extcnf_ctrl);
6896 + * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
6897 + * @hw: pointer to the HW structure
6899 + * Checks if firmware is blocking the reset of the PHY.
6900 + * This is a function pointer entry point only called by
6903 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
6907 + fwsm = er32(FWSM);
6909 + return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
6913 + * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
6914 + * @hw: pointer to the HW structure
6916 + * Forces the speed and duplex settings of the PHY.
6917 + * This is a function pointer entry point only called by
6918 + * PHY setup routines.
6920 +static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
6922 + struct e1000_phy_info *phy = &hw->phy;
6927 + if (phy->type != e1000_phy_ife) {
6928 + ret_val = e1000e_phy_force_speed_duplex_igp(hw);
6932 + ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
6936 + e1000e_phy_force_speed_duplex_setup(hw, &data);
6938 + ret_val = e1e_wphy(hw, PHY_CONTROL, data);
6942 + /* Disable MDI-X support for 10/100 */
6943 + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
6947 + data &= ~IFE_PMC_AUTO_MDIX;
6948 + data &= ~IFE_PMC_FORCE_MDIX;
6950 + ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
6954 + hw_dbg(hw, "IFE PMC: %X\n", data);
6958 + if (phy->wait_for_link) {
6959 + hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
6961 + ret_val = e1000e_phy_has_link_generic(hw,
6969 + hw_dbg(hw, "Link taking longer than expected.\n");
6971 + /* Try once more */
6972 + ret_val = e1000e_phy_has_link_generic(hw,
6984 + * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
6985 + * @hw: pointer to the HW structure
6988 + * This is a function pointer entry point called by drivers
6989 + * or other shared routines.
6991 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
6993 + struct e1000_phy_info *phy = &hw->phy;
6995 + u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
6997 + u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
6998 + u16 word_addr, reg_data, reg_addr, phy_page = 0;
7000 + ret_val = e1000e_phy_hw_reset_generic(hw);
7004 + /* Initialize the PHY from the NVM on ICH platforms. This
7005 + * is needed due to an issue where the NVM configuration is
7006 + * not properly autoloaded after power transitions.
7007 + * Therefore, after each PHY reset, we will load the
7008 + * configuration data out of the NVM manually.
7010 + if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
7011 + struct e1000_adapter *adapter = hw->adapter;
7013 + /* Check if SW needs configure the PHY */
7014 + if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
7015 + (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
7016 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
7018 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
7020 + data = er32(FEXTNVM);
7021 + if (!(data & sw_cfg_mask))
7024 + /* Wait for basic configuration completes before proceeding*/
7026 + data = er32(STATUS);
7027 + data &= E1000_STATUS_LAN_INIT_DONE;
7029 + } while ((!data) && --loop);
7031 + /* If basic configuration is incomplete before the above loop
7032 + * count reaches 0, loading the configuration from NVM will
7033 + * leave the PHY in a bad state possibly resulting in no link.
7036 + hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
7039 + /* Clear the Init Done bit for the next init event */
7040 + data = er32(STATUS);
7041 + data &= ~E1000_STATUS_LAN_INIT_DONE;
7042 + ew32(STATUS, data);
7044 + /* Make sure HW does not configure LCD from PHY
7045 + * extended configuration before SW configuration */
7046 + data = er32(EXTCNF_CTRL);
7047 + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
7050 + cnf_size = er32(EXTCNF_SIZE);
7051 + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
7052 + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
7056 + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
7057 + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
7059 + /* Configure LCD from extended configuration
7062 + /* cnf_base_addr is in DWORD */
7063 + word_addr = (u16)(cnf_base_addr << 1);
7065 + for (i = 0; i < cnf_size; i++) {
7066 + ret_val = e1000_read_nvm(hw,
7067 + (word_addr + i * 2),
7073 + ret_val = e1000_read_nvm(hw,
7074 + (word_addr + i * 2 + 1),
7080 + /* Save off the PHY page for future writes. */
7081 + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
7082 + phy_page = reg_data;
7086 + reg_addr |= phy_page;
7088 + ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
7098 + * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
7099 + * @hw: pointer to the HW structure
7101 + * Populates "phy" structure with various feature states.
7102 + * This function is only called by other family-specific
7105 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
7107 + struct e1000_phy_info *phy = &hw->phy;
7112 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
7117 + hw_dbg(hw, "Phy info is only valid if link is up\n");
7118 + return -E1000_ERR_CONFIG;
7121 + ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
7124 + phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
7126 + if (phy->polarity_correction) {
7127 + ret_val = e1000_check_polarity_ife_ich8lan(hw);
7131 + /* Polarity is forced */
7132 + phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
7133 + ? e1000_rev_polarity_reversed
7134 + : e1000_rev_polarity_normal;
7137 + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
7141 + phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
7143 + /* The following parameters are undefined for 10/100 operation. */
7144 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
7145 + phy->local_rx = e1000_1000t_rx_status_undefined;
7146 + phy->remote_rx = e1000_1000t_rx_status_undefined;
7152 + * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
7153 + * @hw: pointer to the HW structure
7155 + * Wrapper for calling the get_phy_info routines for the appropriate phy type.
7156 + * This is a function pointer entry point called by drivers
7157 + * or other shared routines.
7159 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
7161 + switch (hw->phy.type) {
7162 + case e1000_phy_ife:
7163 + return e1000_get_phy_info_ife_ich8lan(hw);
7165 + case e1000_phy_igp_3:
7166 + return e1000e_get_phy_info_igp(hw);
7172 + return -E1000_ERR_PHY_TYPE;
7176 + * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
7177 + * @hw: pointer to the HW structure
7179 + * Polarity is determined on the polarity reveral feature being enabled.
7180 + * This function is only called by other family-specific
7183 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
7185 + struct e1000_phy_info *phy = &hw->phy;
7187 + u16 phy_data, offset, mask;
7189 + /* Polarity is determined based on the reversal feature
7192 + if (phy->polarity_correction) {
7193 + offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
7194 + mask = IFE_PESC_POLARITY_REVERSED;
7196 + offset = IFE_PHY_SPECIAL_CONTROL;
7197 + mask = IFE_PSC_FORCE_POLARITY;
7200 + ret_val = e1e_rphy(hw, offset, &phy_data);
7203 + phy->cable_polarity = (phy_data & mask)
7204 + ? e1000_rev_polarity_reversed
7205 + : e1000_rev_polarity_normal;
7211 + * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
7212 + * @hw: pointer to the HW structure
7213 + * @active: TRUE to enable LPLU, FALSE to disable
7215 + * Sets the LPLU D0 state according to the active flag. When
7216 + * activating LPLU this function also disables smart speed
7217 + * and vice versa. LPLU will not be activated unless the
7218 + * device autonegotiation advertisement meets standards of
7219 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
7220 + * This is a function pointer entry point only called by
7221 + * PHY setup routines.
7223 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
7225 + struct e1000_phy_info *phy = &hw->phy;
7230 + if (phy->type != e1000_phy_igp_3)
7233 + phy_ctrl = er32(PHY_CTRL);
7236 + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7237 + ew32(PHY_CTRL, phy_ctrl);
7239 + /* Call gig speed drop workaround on LPLU before accessing
7240 + * any PHY registers */
7241 + if ((hw->mac.type == e1000_ich8lan) &&
7242 + (hw->phy.type == e1000_phy_igp_3))
7243 + e1000e_gig_downshift_workaround_ich8lan(hw);
7245 + /* When LPLU is enabled, we should disable SmartSpeed */
7246 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
7247 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7248 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
7252 + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7253 + ew32(PHY_CTRL, phy_ctrl);
7255 + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
7256 + * during Dx states where the power conservation is most
7257 + * important. During driver activity we should enable
7258 + * SmartSpeed, so performance is maintained. */
7259 + if (phy->smart_speed == e1000_smart_speed_on) {
7260 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
7265 + data |= IGP01E1000_PSCFR_SMART_SPEED;
7266 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
7270 + } else if (phy->smart_speed == e1000_smart_speed_off) {
7271 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
7276 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7277 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
7288 + * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
7289 + * @hw: pointer to the HW structure
7290 + * @active: TRUE to enable LPLU, FALSE to disable
7292 + * Sets the LPLU D3 state according to the active flag. When
7293 + * activating LPLU this function also disables smart speed
7294 + * and vice versa. LPLU will not be activated unless the
7295 + * device autonegotiation advertisement meets standards of
7296 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
7297 + * This is a function pointer entry point only called by
7298 + * PHY setup routines.
7300 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
7302 + struct e1000_phy_info *phy = &hw->phy;
7307 + phy_ctrl = er32(PHY_CTRL);
7310 + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7311 + ew32(PHY_CTRL, phy_ctrl);
7312 + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
7313 + * during Dx states where the power conservation is most
7314 + * important. During driver activity we should enable
7315 + * SmartSpeed, so performance is maintained. */
7316 + if (phy->smart_speed == e1000_smart_speed_on) {
7317 + ret_val = e1e_rphy(hw,
7318 + IGP01E1000_PHY_PORT_CONFIG,
7323 + data |= IGP01E1000_PSCFR_SMART_SPEED;
7324 + ret_val = e1e_wphy(hw,
7325 + IGP01E1000_PHY_PORT_CONFIG,
7329 + } else if (phy->smart_speed == e1000_smart_speed_off) {
7330 + ret_val = e1e_rphy(hw,
7331 + IGP01E1000_PHY_PORT_CONFIG,
7336 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7337 + ret_val = e1e_wphy(hw,
7338 + IGP01E1000_PHY_PORT_CONFIG,
7343 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
7344 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
7345 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
7346 + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7347 + ew32(PHY_CTRL, phy_ctrl);
7349 + /* Call gig speed drop workaround on LPLU before accessing
7350 + * any PHY registers */
7351 + if ((hw->mac.type == e1000_ich8lan) &&
7352 + (hw->phy.type == e1000_phy_igp_3))
7353 + e1000e_gig_downshift_workaround_ich8lan(hw);
7355 + /* When LPLU is enabled, we should disable SmartSpeed */
7356 + ret_val = e1e_rphy(hw,
7357 + IGP01E1000_PHY_PORT_CONFIG,
7362 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7363 + ret_val = e1e_wphy(hw,
7364 + IGP01E1000_PHY_PORT_CONFIG,
7372 + * e1000_read_nvm_ich8lan - Read word(s) from the NVM
7373 + * @hw: pointer to the HW structure
7374 + * @offset: The offset (in bytes) of the word(s) to read.
7375 + * @words: Size of data to read in words
7376 + * @data: Pointer to the word(s) to read at offset.
7378 + * Reads a word(s) from the NVM using the flash access registers.
7380 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
7383 + struct e1000_nvm_info *nvm = &hw->nvm;
7384 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
7389 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
7391 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
7392 + return -E1000_ERR_NVM;
7395 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7399 + /* Start with the bank offset, then add the relative offset. */
7400 + act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
7401 + ? nvm->flash_bank_size
7403 + act_offset += offset;
7405 + for (i = 0; i < words; i++) {
7406 + if ((dev_spec->shadow_ram) &&
7407 + (dev_spec->shadow_ram[offset+i].modified)) {
7408 + data[i] = dev_spec->shadow_ram[offset+i].value;
7410 + ret_val = e1000_read_flash_word_ich8lan(hw,
7419 + e1000_release_swflag_ich8lan(hw);
7425 + * e1000_flash_cycle_init_ich8lan - Initialize flash
7426 + * @hw: pointer to the HW structure
7428 + * This function does initial flash setup so that a new read/write/erase cycle
7431 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
7433 + union ich8_hws_flash_status hsfsts;
7434 + s32 ret_val = -E1000_ERR_NVM;
7437 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7439 + /* Check if the flash descriptor is valid */
7440 + if (hsfsts.hsf_status.fldesvalid == 0) {
7441 + hw_dbg(hw, "Flash descriptor invalid. "
7442 + "SW Sequencing must be used.");
7443 + return -E1000_ERR_NVM;
7446 + /* Clear FCERR and DAEL in hw status by writing 1 */
7447 + hsfsts.hsf_status.flcerr = 1;
7448 + hsfsts.hsf_status.dael = 1;
7450 + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
7452 + /* Either we should have a hardware SPI cycle in progress
7453 + * bit to check against, in order to start a new cycle or
7454 + * FDONE bit should be changed in the hardware so that it
7455 + * is 1 after harware reset, which can then be used as an
7456 + * indication whether a cycle is in progress or has been
7460 + if (hsfsts.hsf_status.flcinprog == 0) {
7461 + /* There is no cycle running at present,
7462 + * so we can start a cycle */
7463 + /* Begin by setting Flash Cycle Done. */
7464 + hsfsts.hsf_status.flcdone = 1;
7465 + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
7468 + /* otherwise poll for sometime so the current
7469 + * cycle has a chance to end before giving up. */
7470 + for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
7471 + hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
7472 + if (hsfsts.hsf_status.flcinprog == 0) {
7478 + if (ret_val == 0) {
7479 + /* Successful in waiting for previous cycle to timeout,
7480 + * now set the Flash Cycle Done. */
7481 + hsfsts.hsf_status.flcdone = 1;
7482 + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
7484 + hw_dbg(hw, "Flash controller busy, cannot get access");
7492 + * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
7493 + * @hw: pointer to the HW structure
7494 + * @timeout: maximum time to wait for completion
7496 + * This function starts a flash cycle and waits for its completion.
7498 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
7500 + union ich8_hws_flash_ctrl hsflctl;
7501 + union ich8_hws_flash_status hsfsts;
7502 + s32 ret_val = -E1000_ERR_NVM;
7505 + /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
7506 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
7507 + hsflctl.hsf_ctrl.flcgo = 1;
7508 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
7510 + /* wait till FDONE bit is set to 1 */
7512 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7513 + if (hsfsts.hsf_status.flcdone == 1)
7516 + } while (i++ < timeout);
7518 + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
7525 + * e1000_read_flash_word_ich8lan - Read word from flash
7526 + * @hw: pointer to the HW structure
7527 + * @offset: offset to data location
7528 + * @data: pointer to the location for storing the data
7530 + * Reads the flash word at offset into data. Offset is converted
7531 + * to bytes before read.
7533 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
7536 + /* Must convert offset into bytes. */
7539 + return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
7543 + * e1000_read_flash_data_ich8lan - Read byte or word from NVM
7544 + * @hw: pointer to the HW structure
7545 + * @offset: The offset (in bytes) of the byte or word to read.
7546 + * @size: Size of data to read, 1=byte 2=word
7547 + * @data: Pointer to the word to store the value read.
7549 + * Reads a byte or word from the NVM using the flash access registers.
7551 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
7552 + u8 size, u16 *data)
7554 + union ich8_hws_flash_status hsfsts;
7555 + union ich8_hws_flash_ctrl hsflctl;
7556 + u32 flash_linear_addr;
7557 + u32 flash_data = 0;
7558 + s32 ret_val = -E1000_ERR_NVM;
7561 + if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
7562 + return -E1000_ERR_NVM;
7564 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7565 + hw->nvm.flash_base_addr;
7570 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7574 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
7575 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7576 + hsflctl.hsf_ctrl.fldbcount = size - 1;
7577 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
7578 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
7580 + ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
7582 + ret_val = e1000_flash_cycle_ich8lan(hw,
7583 + ICH_FLASH_READ_COMMAND_TIMEOUT);
7585 + /* Check if FCERR is set to 1, if set to 1, clear it
7586 + * and try the whole sequence a few more times, else
7587 + * read in (shift in) the Flash Data0, the order is
7588 + * least significant byte first msb to lsb */
7589 + if (ret_val == 0) {
7590 + flash_data = er32flash(ICH_FLASH_FDATA0);
7592 + *data = (u8)(flash_data & 0x000000FF);
7593 + } else if (size == 2) {
7594 + *data = (u16)(flash_data & 0x0000FFFF);
7598 + /* If we've gotten here, then things are probably
7599 + * completely hosed, but if the error condition is
7600 + * detected, it won't hurt to give it another try...
7601 + * ICH_FLASH_CYCLE_REPEAT_COUNT times.
7603 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7604 + if (hsfsts.hsf_status.flcerr == 1) {
7605 + /* Repeat for some time before giving up. */
7607 + } else if (hsfsts.hsf_status.flcdone == 0) {
7608 + hw_dbg(hw, "Timeout error - flash cycle "
7609 + "did not complete.");
7613 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7619 + * e1000_write_nvm_ich8lan - Write word(s) to the NVM
7620 + * @hw: pointer to the HW structure
7621 + * @offset: The offset (in bytes) of the word(s) to write.
7622 + * @words: Size of data to write in words
7623 + * @data: Pointer to the word(s) to write at offset.
7625 + * Writes a byte or word to the NVM using the flash access registers.
7627 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
7630 + struct e1000_nvm_info *nvm = &hw->nvm;
7631 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
7635 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
7637 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
7638 + return -E1000_ERR_NVM;
7641 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7645 + for (i = 0; i < words; i++) {
7646 + dev_spec->shadow_ram[offset+i].modified = 1;
7647 + dev_spec->shadow_ram[offset+i].value = data[i];
7650 + e1000_release_swflag_ich8lan(hw);
7656 + * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
7657 + * @hw: pointer to the HW structure
7659 + * The NVM checksum is updated by calling the generic update_nvm_checksum,
7660 + * which writes the checksum to the shadow ram. The changes in the shadow
7661 + * ram are then committed to the EEPROM by processing each bank at a time
7662 + * checking for the modified bit and writing only the pending changes.
7663 + * After a succesful commit, the shadow ram is cleared and is ready for
7666 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
7668 + struct e1000_nvm_info *nvm = &hw->nvm;
7669 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
7670 + u32 i, act_offset, new_bank_offset, old_bank_offset;
7674 + ret_val = e1000e_update_nvm_checksum_generic(hw);
7678 + if (nvm->type != e1000_nvm_flash_sw)
7681 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7685 + /* We're writing to the opposite bank so if we're on bank 1,
7686 + * write to bank 0 etc. We also need to erase the segment that
7687 + * is going to be written */
7688 + if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
7689 + new_bank_offset = nvm->flash_bank_size;
7690 + old_bank_offset = 0;
7691 + e1000_erase_flash_bank_ich8lan(hw, 1);
7693 + old_bank_offset = nvm->flash_bank_size;
7694 + new_bank_offset = 0;
7695 + e1000_erase_flash_bank_ich8lan(hw, 0);
7698 + for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
7699 + /* Determine whether to write the value stored
7700 + * in the other NVM bank or a modified value stored
7701 + * in the shadow RAM */
7702 + if (dev_spec->shadow_ram[i].modified) {
7703 + data = dev_spec->shadow_ram[i].value;
7705 + e1000_read_flash_word_ich8lan(hw,
7706 + i + old_bank_offset,
7710 + /* If the word is 0x13, then make sure the signature bits
7711 + * (15:14) are 11b until the commit has completed.
7712 + * This will allow us to write 10b which indicates the
7713 + * signature is valid. We want to do this after the write
7714 + * has completed so that we don't mark the segment valid
7715 + * while the write is still in progress */
7716 + if (i == E1000_ICH_NVM_SIG_WORD)
7717 + data |= E1000_ICH_NVM_SIG_MASK;
7719 + /* Convert offset to bytes. */
7720 + act_offset = (i + new_bank_offset) << 1;
7723 + /* Write the bytes to the new bank. */
7724 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7731 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7738 + /* Don't bother writing the segment valid bits if sector
7739 + * programming failed. */
7741 + hw_dbg(hw, "Flash commit failed.\n");
7742 + e1000_release_swflag_ich8lan(hw);
7746 + /* Finally validate the new segment by setting bit 15:14
7747 + * to 10b in word 0x13 , this can be done without an
7748 + * erase as well since these bits are 11 to start with
7749 + * and we need to change bit 14 to 0b */
7750 + act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
7751 + e1000_read_flash_word_ich8lan(hw, act_offset, &data);
7753 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7754 + act_offset * 2 + 1,
7757 + e1000_release_swflag_ich8lan(hw);
7761 + /* And invalidate the previously valid segment by setting
7762 + * its signature word (0x13) high_byte to 0b. This can be
7763 + * done without an erase because flash erase sets all bits
7764 + * to 1's. We can write 1's to 0's without an erase */
7765 + act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
7766 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
7768 + e1000_release_swflag_ich8lan(hw);
7772 + /* Great! Everything worked, we can now clear the cached entries. */
7773 + for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
7774 + dev_spec->shadow_ram[i].modified = 0;
7775 + dev_spec->shadow_ram[i].value = 0xFFFF;
7778 + e1000_release_swflag_ich8lan(hw);
7780 + /* Reload the EEPROM, or else modifications will not appear
7781 + * until after the next adapter reset.
7783 + e1000e_reload_nvm(hw);
7790 + * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
7791 + * @hw: pointer to the HW structure
7793 + * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
7794 + * If the bit is 0, that the EEPROM had been modified, but the checksum was not
7795 + * calculated, in which case we need to calculate the checksum and set bit 6.
7797 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
7802 + /* Read 0x19 and check bit 6. If this bit is 0, the checksum
7803 + * needs to be fixed. This bit is an indication that the NVM
7804 + * was prepared by OEM software and did not calculate the
7805 + * checksum...a likely scenario.
7807 + ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
7811 + if ((data & 0x40) == 0) {
7813 + ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
7816 + ret_val = e1000e_update_nvm_checksum(hw);
7821 + return e1000e_validate_nvm_checksum_generic(hw);
7825 + * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
7826 + * @hw: pointer to the HW structure
7827 + * @offset: The offset (in bytes) of the byte/word to read.
7828 + * @size: Size of data to read, 1=byte 2=word
7829 + * @data: The byte(s) to write to the NVM.
7831 + * Writes one/two bytes to the NVM using the flash access registers.
7833 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
7834 + u8 size, u16 data)
7836 + union ich8_hws_flash_status hsfsts;
7837 + union ich8_hws_flash_ctrl hsflctl;
7838 + u32 flash_linear_addr;
7839 + u32 flash_data = 0;
7843 + if (size < 1 || size > 2 || data > size * 0xff ||
7844 + offset > ICH_FLASH_LINEAR_ADDR_MASK)
7845 + return -E1000_ERR_NVM;
7847 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7848 + hw->nvm.flash_base_addr;
7853 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7857 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
7858 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7859 + hsflctl.hsf_ctrl.fldbcount = size -1;
7860 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
7861 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
7863 + ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
7866 + flash_data = (u32)data & 0x00FF;
7868 + flash_data = (u32)data;
7870 + ew32flash(ICH_FLASH_FDATA0, flash_data);
7872 + /* check if FCERR is set to 1 , if set to 1, clear it
7873 + * and try the whole sequence a few more times else done */
7874 + ret_val = e1000_flash_cycle_ich8lan(hw,
7875 + ICH_FLASH_WRITE_COMMAND_TIMEOUT);
7879 + /* If we're here, then things are most likely
7880 + * completely hosed, but if the error condition
7881 + * is detected, it won't hurt to give it another
7882 + * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
7884 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7885 + if (hsfsts.hsf_status.flcerr == 1)
7886 + /* Repeat for some time before giving up. */
7888 + if (hsfsts.hsf_status.flcdone == 0) {
7889 + hw_dbg(hw, "Timeout error - flash cycle "
7890 + "did not complete.");
7893 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7899 + * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
7900 + * @hw: pointer to the HW structure
7901 + * @offset: The index of the byte to read.
7902 + * @data: The byte to write to the NVM.
7904 + * Writes a single byte to the NVM using the flash access registers.
7906 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
7909 + u16 word = (u16)data;
7911 + return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
7915 + * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
7916 + * @hw: pointer to the HW structure
7917 + * @offset: The offset of the byte to write.
7918 + * @byte: The byte to write to the NVM.
7920 + * Writes a single byte to the NVM using the flash access registers.
7921 + * Goes through a retry algorithm before giving up.
7923 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
7924 + u32 offset, u8 byte)
7927 + u16 program_retries;
7929 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7933 + for (program_retries = 0; program_retries < 100; program_retries++) {
7934 + hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
7936 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7940 + if (program_retries == 100)
7941 + return -E1000_ERR_NVM;
7947 + * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
7948 + * @hw: pointer to the HW structure
7949 + * @bank: 0 for first bank, 1 for second bank, etc.
7951 + * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
7952 + * bank N is 4096 * N + flash_reg_addr.
7954 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
7956 + struct e1000_nvm_info *nvm = &hw->nvm;
7957 + union ich8_hws_flash_status hsfsts;
7958 + union ich8_hws_flash_ctrl hsflctl;
7959 + u32 flash_linear_addr;
7960 + /* bank size is in 16bit words - adjust to bytes */
7961 + u32 flash_bank_size = nvm->flash_bank_size * 2;
7968 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7970 + /* Determine HW Sector size: Read BERASE bits of hw flash status
7972 + /* 00: The Hw sector is 256 bytes, hence we need to erase 16
7973 + * consecutive sectors. The start index for the nth Hw sector
7974 + * can be calculated as = bank * 4096 + n * 256
7975 + * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
7976 + * The start index for the nth Hw sector can be calculated
7977 + * as = bank * 4096
7978 + * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
7979 + * (ich9 only, otherwise error condition)
7980 + * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
7982 + switch (hsfsts.hsf_status.berasesz) {
7984 + /* Hw sector size 256 */
7985 + sector_size = ICH_FLASH_SEG_SIZE_256;
7986 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
7989 + sector_size = ICH_FLASH_SEG_SIZE_4K;
7990 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
7993 + if (hw->mac.type == e1000_ich9lan) {
7994 + sector_size = ICH_FLASH_SEG_SIZE_8K;
7995 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
7997 + return -E1000_ERR_NVM;
8001 + sector_size = ICH_FLASH_SEG_SIZE_64K;
8002 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
8005 + return -E1000_ERR_NVM;
8008 + /* Start with the base address, then add the sector offset. */
8009 + flash_linear_addr = hw->nvm.flash_base_addr;
8010 + flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
8012 + for (j = 0; j < iteration ; j++) {
8015 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
8019 + /* Write a value 11 (block Erase) in Flash
8020 + * Cycle field in hw flash control */
8021 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
8022 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8023 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
8025 + /* Write the last 24 bits of an index within the
8026 + * block into Flash Linear address field in Flash
8029 + flash_linear_addr += (j * sector_size);
8030 + ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
8032 + ret_val = e1000_flash_cycle_ich8lan(hw,
8033 + ICH_FLASH_ERASE_COMMAND_TIMEOUT);
8037 + /* Check if FCERR is set to 1. If 1,
8038 + * clear it and try the whole sequence
8039 + * a few more times else Done */
8040 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
8041 + if (hsfsts.hsf_status.flcerr == 1)
8042 + /* repeat for some time before
8045 + else if (hsfsts.hsf_status.flcdone == 0)
8047 + } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
8054 + * e1000_valid_led_default_ich8lan - Set the default LED settings
8055 + * @hw: pointer to the HW structure
8056 + * @data: Pointer to the LED settings
8058 + * Reads the LED default settings from the NVM to data. If the NVM LED
8059 + * settings is all 0's or F's, set the LED default to a valid LED default
8062 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
8066 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
8068 + hw_dbg(hw, "NVM Read Error\n");
8072 + if (*data == ID_LED_RESERVED_0000 ||
8073 + *data == ID_LED_RESERVED_FFFF)
8074 + *data = ID_LED_DEFAULT_ICH8LAN;
8080 + * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
8081 + * @hw: pointer to the HW structure
8083 + * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
8084 + * register, so the the bus width is hard coded.
8086 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
8088 + struct e1000_bus_info *bus = &hw->bus;
8091 + ret_val = e1000e_get_bus_info_pcie(hw);
8093 + /* ICH devices are "PCI Express"-ish. They have
8094 + * a configuration space, but do not contain
8095 + * PCI Express Capability registers, so bus width
8096 + * must be hardcoded.
8098 + if (bus->width == e1000_bus_width_unknown)
8099 + bus->width = e1000_bus_width_pcie_x1;
8105 + * e1000_reset_hw_ich8lan - Reset the hardware
8106 + * @hw: pointer to the HW structure
8108 + * Does a full reset of the hardware which includes a reset of the PHY and
8111 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
8113 + u32 ctrl, icr, kab;
8116 + /* Prevent the PCI-E bus from sticking if there is no TLP connection
8117 + * on the last TLP read/write transaction when MAC is reset.
8119 + ret_val = e1000e_disable_pcie_master(hw);
8121 + hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
8124 + hw_dbg(hw, "Masking off all interrupts\n");
8125 + ew32(IMC, 0xffffffff);
8127 + /* Disable the Transmit and Receive units. Then delay to allow
8128 + * any pending transactions to complete before we hit the MAC
8129 + * with the global reset.
8132 + ew32(TCTL, E1000_TCTL_PSP);
8137 + /* Workaround for ICH8 bit corruption issue in FIFO memory */
8138 + if (hw->mac.type == e1000_ich8lan) {
8139 + /* Set Tx and Rx buffer allocation to 8k apiece. */
8140 + ew32(PBA, E1000_PBA_8K);
8141 + /* Set Packet Buffer Size to 16k. */
8142 + ew32(PBS, E1000_PBS_16K);
8145 + ctrl = er32(CTRL);
8147 + if (!e1000_check_reset_block(hw)) {
8148 + /* PHY HW reset requires MAC CORE reset at the same
8149 + * time to make sure the interface between MAC and the
8150 + * external PHY is reset.
8152 + ctrl |= E1000_CTRL_PHY_RST;
8154 + ret_val = e1000_acquire_swflag_ich8lan(hw);
8155 + hw_dbg(hw, "Issuing a global reset to ich8lan");
8156 + ew32(CTRL, (ctrl | E1000_CTRL_RST));
8159 + ret_val = e1000e_get_auto_rd_done(hw);
8162 + * When auto config read does not complete, do not
8163 + * return with an error. This can happen in situations
8164 + * where there is no eeprom and prevents getting link.
8166 + hw_dbg(hw, "Auto Read Done did not complete\n");
8169 + ew32(IMC, 0xffffffff);
8172 + kab = er32(KABGTXD);
8173 + kab |= E1000_KABGTXD_BGSQLBIAS;
8174 + ew32(KABGTXD, kab);
8180 + * e1000_init_hw_ich8lan - Initialize the hardware
8181 + * @hw: pointer to the HW structure
8183 + * Prepares the hardware for transmit and receive by doing the following:
8184 + * - initialize hardware bits
8185 + * - initialize LED identification
8186 + * - setup receive address registers
8187 + * - setup flow control
8188 + * - setup transmit discriptors
8189 + * - clear statistics
8191 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
8193 + struct e1000_mac_info *mac = &hw->mac;
8194 + u32 ctrl_ext, txdctl, snoop;
8198 + e1000_initialize_hw_bits_ich8lan(hw);
8200 + /* Initialize identification LED */
8201 + ret_val = e1000e_id_led_init(hw);
8203 + hw_dbg(hw, "Error initializing identification LED\n");
8207 + /* Setup the receive address. */
8208 + e1000e_init_rx_addrs(hw, mac->rar_entry_count);
8210 + /* Zero out the Multicast HASH table */
8211 + hw_dbg(hw, "Zeroing the MTA\n");
8212 + for (i = 0; i < mac->mta_reg_count; i++)
8213 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
8215 + /* Setup link and flow control */
8216 + ret_val = e1000_setup_link_ich8lan(hw);
8218 + /* Set the transmit descriptor write-back policy for both queues */
8219 + txdctl = er32(TXDCTL);
8220 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
8221 + E1000_TXDCTL_FULL_TX_DESC_WB;
8222 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
8223 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
8224 + ew32(TXDCTL, txdctl);
8225 + txdctl = er32(TXDCTL1);
8226 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
8227 + E1000_TXDCTL_FULL_TX_DESC_WB;
8228 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
8229 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
8230 + ew32(TXDCTL1, txdctl);
8232 + /* ICH8 has opposite polarity of no_snoop bits.
8233 + * By default, we should use snoop behavior. */
8234 + if (mac->type == e1000_ich8lan)
8235 + snoop = PCIE_ICH8_SNOOP_ALL;
8237 + snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
8238 + e1000e_set_pcie_no_snoop(hw, snoop);
8240 + ctrl_ext = er32(CTRL_EXT);
8241 + ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8242 + ew32(CTRL_EXT, ctrl_ext);
8244 + /* Clear all of the statistics registers (clear on read). It is
8245 + * important that we do this after we have tried to establish link
8246 + * because the symbol error count will increment wildly if there
8249 + e1000_clear_hw_cntrs_ich8lan(hw);
8254 + * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
8255 + * @hw: pointer to the HW structure
8257 + * Sets/Clears required hardware bits necessary for correctly setting up the
8258 + * hardware for transmit and receive.
8260 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
8264 + /* Extended Device Control */
8265 + reg = er32(CTRL_EXT);
8267 + ew32(CTRL_EXT, reg);
8269 + /* Transmit Descriptor Control 0 */
8270 + reg = er32(TXDCTL);
8272 + ew32(TXDCTL, reg);
8274 + /* Transmit Descriptor Control 1 */
8275 + reg = er32(TXDCTL1);
8277 + ew32(TXDCTL1, reg);
8279 + /* Transmit Arbitration Control 0 */
8280 + reg = er32(TARC0);
8281 + if (hw->mac.type == e1000_ich8lan)
8282 + reg |= (1 << 28) | (1 << 29);
8283 + reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
8286 + /* Transmit Arbitration Control 1 */
8287 + reg = er32(TARC1);
8288 + if (er32(TCTL) & E1000_TCTL_MULR)
8289 + reg &= ~(1 << 28);
8292 + reg |= (1 << 24) | (1 << 26) | (1 << 30);
8295 + /* Device Status */
8296 + if (hw->mac.type == e1000_ich8lan) {
8297 + reg = er32(STATUS);
8298 + reg &= ~(1 << 31);
8299 + ew32(STATUS, reg);
8304 + * e1000_setup_link_ich8lan - Setup flow control and link settings
8305 + * @hw: pointer to the HW structure
8307 + * Determines which flow control settings to use, then configures flow
8308 + * control. Calls the appropriate media-specific link configuration
8309 + * function. Assuming the adapter has a valid link partner, a valid link
8310 + * should be established. Assumes the hardware has previously been reset
8311 + * and the transmitter and receiver are not enabled.
8313 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
8315 + struct e1000_mac_info *mac = &hw->mac;
8318 + if (e1000_check_reset_block(hw))
8321 + /* ICH parts do not have a word in the NVM to determine
8322 + * the default flow control setting, so we explicitly
8325 + if (mac->fc == e1000_fc_default)
8326 + mac->fc = e1000_fc_full;
8328 + mac->original_fc = mac->fc;
8330 + hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc);
8332 + /* Continue to configure the copper link. */
8333 + ret_val = e1000_setup_copper_link_ich8lan(hw);
8337 + ew32(FCTTV, mac->fc_pause_time);
8339 + return e1000e_set_fc_watermarks(hw);
8343 + * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
8344 + * @hw: pointer to the HW structure
8346 + * Configures the kumeran interface to the PHY to wait the appropriate time
8347 + * when polling the PHY, then call the generic setup_copper_link to finish
8348 + * configuring the copper link.
8350 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
8356 + ctrl = er32(CTRL);
8357 + ctrl |= E1000_CTRL_SLU;
8358 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
8361 + /* Set the mac to wait the maximum time between each iteration
8362 + * and increase the max iterations when polling the phy;
8363 + * this fixes erroneous timeouts at 10Mbps. */
8364 + ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
8367 + ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
8371 + ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
8375 + if (hw->phy.type == e1000_phy_igp_3) {
8376 + ret_val = e1000e_copper_link_setup_igp(hw);
8381 + return e1000e_setup_copper_link(hw);
8385 + * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
8386 + * @hw: pointer to the HW structure
8387 + * @speed: pointer to store current link speed
8388 + * @duplex: pointer to store the current link duplex
8390 + * Calls the generic get_speed_and_duplex to retreive the current link
8391 + * information and then calls the Kumeran lock loss workaround for links at
8394 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
8399 + ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
8403 + if ((hw->mac.type == e1000_ich8lan) &&
8404 + (hw->phy.type == e1000_phy_igp_3) &&
8405 + (*speed == SPEED_1000)) {
8406 + ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
8413 + * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
8414 + * @hw: pointer to the HW structure
8416 + * Work-around for 82566 Kumeran PCS lock loss:
8417 + * On link status change (i.e. PCI reset, speed change) and link is up and
8418 + * speed is gigabit-
8419 + * 0) if workaround is optionally disabled do nothing
8420 + * 1) wait 1ms for Kumeran link to come up
8421 + * 2) check Kumeran Diagnostic register PCS lock loss bit
8422 + * 3) if not set the link is locked (all is good), otherwise...
8423 + * 4) reset the PHY
8424 + * 5) repeat up to 10 times
8425 + * Note: this is only called for IGP3 copper when speed is 1gb.
8427 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
8429 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
8435 + if (!dev_spec->kmrn_lock_loss_workaround_enabled)
8438 + /* Make sure link is up before proceeding. If not just return.
8439 + * Attempting this while link is negotiating fouled up link
8441 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
8445 + for (i = 0; i < 10; i++) {
8446 + /* read once to clear */
8447 + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
8450 + /* and again to get new status */
8451 + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
8455 + /* check for PCS lock */
8456 + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
8459 + /* Issue PHY reset */
8460 + e1000_phy_hw_reset(hw);
8463 + /* Disable GigE link negotiation */
8464 + phy_ctrl = er32(PHY_CTRL);
8465 + phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
8466 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8467 + ew32(PHY_CTRL, phy_ctrl);
8469 + /* Call gig speed drop workaround on Giga disable before accessing
8470 + * any PHY registers */
8471 + e1000e_gig_downshift_workaround_ich8lan(hw);
8473 + /* unable to acquire PCS lock */
8474 + return -E1000_ERR_PHY;
8478 + * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
8479 + * @hw: pointer to the HW structure
8480 + * @state: boolean value used to set the current Kumaran workaround state
8482 + * If ICH8, set the current Kumeran workaround state (enabled - TRUE
8483 + * /disabled - FALSE).
8485 +void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
8488 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
8490 + if (hw->mac.type != e1000_ich8lan) {
8491 + hw_dbg(hw, "Workaround applies to ICH8 only.\n");
8495 + dev_spec->kmrn_lock_loss_workaround_enabled = state;
8499 + * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
8500 + * @hw: pointer to the HW structure
8502 + * Workaround for 82566 power-down on D3 entry:
8503 + * 1) disable gigabit link
8504 + * 2) write VR power-down enable
8506 + * Continue if successful, else issue LCD reset and repeat
8508 +void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
8514 + if (hw->phy.type != e1000_phy_igp_3)
8517 + /* Try the workaround twice (if needed) */
8519 + /* Disable link */
8520 + reg = er32(PHY_CTRL);
8521 + reg |= (E1000_PHY_CTRL_GBE_DISABLE |
8522 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8523 + ew32(PHY_CTRL, reg);
8525 + /* Call gig speed drop workaround on Giga disable before
8526 + * accessing any PHY registers */
8527 + if (hw->mac.type == e1000_ich8lan)
8528 + e1000e_gig_downshift_workaround_ich8lan(hw);
8530 + /* Write VR power-down enable */
8531 + e1e_rphy(hw, IGP3_VR_CTRL, &data);
8532 + data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8533 + e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
8535 + /* Read it back and test */
8536 + e1e_rphy(hw, IGP3_VR_CTRL, &data);
8537 + data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8538 + if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
8541 + /* Issue PHY reset and repeat at most one more time */
8543 + ew32(CTRL, reg | E1000_CTRL_PHY_RST);
8549 + * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
8550 + * @hw: pointer to the HW structure
8552 + * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
8553 + * LPLU, Giga disable, MDIC PHY reset):
8554 + * 1) Set Kumeran Near-end loopback
8555 + * 2) Clear Kumeran Near-end loopback
8556 + * Should only be called for ICH8[m] devices with IGP_3 Phy.
8558 +void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
8563 + if ((hw->mac.type != e1000_ich8lan) ||
8564 + (hw->phy.type != e1000_phy_igp_3))
8567 + ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
8571 + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
8572 + ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
8576 + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
8577 + ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
8582 + * e1000_cleanup_led_ich8lan - Restore the default LED operation
8583 + * @hw: pointer to the HW structure
8585 + * Return the LED back to the default configuration.
8587 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
8589 + if (hw->phy.type == e1000_phy_ife)
8590 + return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
8592 + ew32(LEDCTL, hw->mac.ledctl_default);
8597 + * e1000_led_on_ich8lan - Turn LED's on
8598 + * @hw: pointer to the HW structure
8600 + * Turn on the LED's.
8602 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
8604 + if (hw->phy.type == e1000_phy_ife)
8605 + return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
8606 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
8608 + ew32(LEDCTL, hw->mac.ledctl_mode2);
8613 + * e1000_led_off_ich8lan - Turn LED's off
8614 + * @hw: pointer to the HW structure
8616 + * Turn off the LED's.
8618 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
8620 + if (hw->phy.type == e1000_phy_ife)
8621 + return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
8622 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
8624 + ew32(LEDCTL, hw->mac.ledctl_mode1);
8629 + * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
8630 + * @hw: pointer to the HW structure
8632 + * Clears hardware counters specific to the silicon family and calls
8633 + * clear_hw_cntrs_generic to clear all general purpose counters.
8635 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
8639 + e1000e_clear_hw_cntrs_base(hw);
8641 + temp = er32(ALGNERRC);
8642 + temp = er32(RXERRC);
8643 + temp = er32(TNCRS);
8644 + temp = er32(CEXTERR);
8645 + temp = er32(TSCTC);
8646 + temp = er32(TSCTFC);
8648 + temp = er32(MGTPRC);
8649 + temp = er32(MGTPDC);
8650 + temp = er32(MGTPTC);
8653 + temp = er32(ICRXOC);
8657 +static struct e1000_mac_operations ich8_mac_ops = {
8658 + .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
8659 + .check_for_link = e1000e_check_for_copper_link,
8660 + .cleanup_led = e1000_cleanup_led_ich8lan,
8661 + .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
8662 + .get_bus_info = e1000_get_bus_info_ich8lan,
8663 + .get_link_up_info = e1000_get_link_up_info_ich8lan,
8664 + .led_on = e1000_led_on_ich8lan,
8665 + .led_off = e1000_led_off_ich8lan,
8666 + .mc_addr_list_update = e1000e_mc_addr_list_update_generic,
8667 + .reset_hw = e1000_reset_hw_ich8lan,
8668 + .init_hw = e1000_init_hw_ich8lan,
8669 + .setup_link = e1000_setup_link_ich8lan,
8670 + .setup_physical_interface= e1000_setup_copper_link_ich8lan,
8673 +static struct e1000_phy_operations ich8_phy_ops = {
8674 + .acquire_phy = e1000_acquire_swflag_ich8lan,
8675 + .check_reset_block = e1000_check_reset_block_ich8lan,
8676 + .commit_phy = NULL,
8677 + .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
8678 + .get_cfg_done = e1000e_get_cfg_done,
8679 + .get_cable_length = e1000e_get_cable_length_igp_2,
8680 + .get_phy_info = e1000_get_phy_info_ich8lan,
8681 + .read_phy_reg = e1000e_read_phy_reg_igp,
8682 + .release_phy = e1000_release_swflag_ich8lan,
8683 + .reset_phy = e1000_phy_hw_reset_ich8lan,
8684 + .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
8685 + .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
8686 + .write_phy_reg = e1000e_write_phy_reg_igp,
8689 +static struct e1000_nvm_operations ich8_nvm_ops = {
8690 + .acquire_nvm = e1000_acquire_swflag_ich8lan,
8691 + .read_nvm = e1000_read_nvm_ich8lan,
8692 + .release_nvm = e1000_release_swflag_ich8lan,
8693 + .update_nvm = e1000_update_nvm_checksum_ich8lan,
8694 + .valid_led_default = e1000_valid_led_default_ich8lan,
8695 + .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
8696 + .write_nvm = e1000_write_nvm_ich8lan,
8699 +struct e1000_info e1000_ich8_info = {
8700 + .mac = e1000_ich8lan,
8701 + .flags = FLAG_HAS_WOL
8702 + | FLAG_RX_CSUM_ENABLED
8703 + | FLAG_HAS_CTRLEXT_ON_LOAD
8706 + | FLAG_APME_IN_WUC,
8708 + .get_invariants = e1000_get_invariants_ich8lan,
8709 + .mac_ops = &ich8_mac_ops,
8710 + .phy_ops = &ich8_phy_ops,
8711 + .nvm_ops = &ich8_nvm_ops,
8714 +struct e1000_info e1000_ich9_info = {
8715 + .mac = e1000_ich9lan,
8716 + .flags = FLAG_HAS_JUMBO_FRAMES
8718 + | FLAG_RX_CSUM_ENABLED
8719 + | FLAG_HAS_CTRLEXT_ON_LOAD
8723 + | FLAG_APME_IN_WUC,
8725 + .get_invariants = e1000_get_invariants_ich8lan,
8726 + .mac_ops = &ich8_mac_ops,
8727 + .phy_ops = &ich8_phy_ops,
8728 + .nvm_ops = &ich8_nvm_ops,
8731 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/lib.c linux-2.6.22-10/drivers/net/e1000e/lib.c
8732 --- linux-2.6.22-0/drivers/net/e1000e/lib.c 1969-12-31 19:00:00.000000000 -0500
8733 +++ linux-2.6.22-10/drivers/net/e1000e/lib.c 2007-11-21 13:55:36.000000000 -0500
8735 +/*******************************************************************************
8737 + Intel PRO/1000 Linux driver
8738 + Copyright(c) 1999 - 2007 Intel Corporation.
8740 + This program is free software; you can redistribute it and/or modify it
8741 + under the terms and conditions of the GNU General Public License,
8742 + version 2, as published by the Free Software Foundation.
8744 + This program is distributed in the hope it will be useful, but WITHOUT
8745 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8746 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8749 + You should have received a copy of the GNU General Public License along with
8750 + this program; if not, write to the Free Software Foundation, Inc.,
8751 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8753 + The full GNU General Public License is included in this distribution in
8754 + the file called "COPYING".
8756 + Contact Information:
8757 + Linux NICS <linux.nics@intel.com>
8758 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
8759 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
8761 +*******************************************************************************/
8763 +#include <linux/netdevice.h>
8764 +#include <linux/ethtool.h>
8765 +#include <linux/delay.h>
8766 +#include <linux/pci.h>
8770 +enum e1000_mng_mode {
8771 + e1000_mng_mode_none = 0,
8772 + e1000_mng_mode_asf,
8773 + e1000_mng_mode_pt,
8774 + e1000_mng_mode_ipmi,
8775 + e1000_mng_mode_host_if_only
8778 +#define E1000_FACTPS_MNGCG 0x20000000
8780 +#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management
8781 + * Technology signature */
8784 + * e1000e_get_bus_info_pcie - Get PCIe bus information
8785 + * @hw: pointer to the HW structure
8787 + * Determines and stores the system bus information for a particular
8788 + * network interface. The following bus information is determined and stored:
8789 + * bus speed, bus width, type (PCIe), and PCIe function.
8791 +s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
8793 + struct e1000_bus_info *bus = &hw->bus;
8794 + struct e1000_adapter *adapter = hw->adapter;
8796 + u16 pcie_link_status, pci_header_type, cap_offset;
8798 + cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8799 + if (!cap_offset) {
8800 + bus->width = e1000_bus_width_unknown;
8802 + pci_read_config_word(adapter->pdev,
8803 + cap_offset + PCIE_LINK_STATUS,
8804 + &pcie_link_status);
8805 + bus->width = (enum e1000_bus_width)((pcie_link_status &
8806 + PCIE_LINK_WIDTH_MASK) >>
8807 + PCIE_LINK_WIDTH_SHIFT);
8810 + pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
8811 + &pci_header_type);
8812 + if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
8813 + status = er32(STATUS);
8814 + bus->func = (status & E1000_STATUS_FUNC_MASK)
8815 + >> E1000_STATUS_FUNC_SHIFT;
8824 + * e1000e_write_vfta - Write value to VLAN filter table
8825 + * @hw: pointer to the HW structure
8826 + * @offset: register offset in VLAN filter table
8827 + * @value: register value written to VLAN filter table
8829 + * Writes value at the given offset in the register array which stores
8830 + * the VLAN filter table.
8832 +void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
8834 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
8839 + * e1000e_init_rx_addrs - Initialize receive address's
8840 + * @hw: pointer to the HW structure
8841 + * @rar_count: receive address registers
8843 + * Setups the receive address registers by setting the base receive address
8844 + * register to the devices MAC address and clearing all the other receive
8845 + * address registers to 0.
8847 +void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
8851 + /* Setup the receive address */
8852 + hw_dbg(hw, "Programming MAC Address into RAR[0]\n");
8854 + e1000e_rar_set(hw, hw->mac.addr, 0);
8856 + /* Zero out the other (rar_entry_count - 1) receive addresses */
8857 + hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);
8858 + for (i = 1; i < rar_count; i++) {
8859 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
8861 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
8867 + * e1000e_rar_set - Set receive address register
8868 + * @hw: pointer to the HW structure
8869 + * @addr: pointer to the receive address
8870 + * @index: receive address array register
8872 + * Sets the receive address array register at index to the address passed
8875 +void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
8877 + u32 rar_low, rar_high;
8879 + /* HW expects these in little endian so we reverse the byte order
8880 + * from network order (big endian) to little endian
8882 + rar_low = ((u32) addr[0] |
8883 + ((u32) addr[1] << 8) |
8884 + ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
8886 + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
8888 + rar_high |= E1000_RAH_AV;
8890 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
8891 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
8895 + * e1000_mta_set - Set multicast filter table address
8896 + * @hw: pointer to the HW structure
8897 + * @hash_value: determines the MTA register and bit to set
8899 + * The multicast table address is a register array of 32-bit registers.
8900 + * The hash_value is used to determine what register the bit is in, the
8901 + * current value is read, the new bit is OR'd in and the new value is
8902 + * written back into the register.
8904 +static void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
8906 + u32 hash_bit, hash_reg, mta;
8908 + /* The MTA is a register array of 32-bit registers. It is
8909 + * treated like an array of (32*mta_reg_count) bits. We want to
8910 + * set bit BitArray[hash_value]. So we figure out what register
8911 + * the bit is in, read it, OR in the new bit, then write
8912 + * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
8913 + * mask to bits 31:5 of the hash value which gives us the
8914 + * register we're modifying. The hash bit within that register
8915 + * is determined by the lower 5 bits of the hash value.
8917 + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
8918 + hash_bit = hash_value & 0x1F;
8920 + mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
8922 + mta |= (1 << hash_bit);
8924 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
8929 + * e1000_hash_mc_addr - Generate a multicast hash value
8930 + * @hw: pointer to the HW structure
8931 + * @mc_addr: pointer to a multicast address
8933 + * Generates a multicast address hash value which is used to determine
8934 + * the multicast filter table array address and new table value. See
8935 + * e1000_mta_set_generic()
8937 +static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
8939 + u32 hash_value, hash_mask;
8942 + /* Register count multiplied by bits per register */
8943 + hash_mask = (hw->mac.mta_reg_count * 32) - 1;
8945 + /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
8946 + * where 0xFF would still fall within the hash mask. */
8947 + while (hash_mask >> bit_shift != 0xFF)
8950 + /* The portion of the address that is used for the hash table
8951 + * is determined by the mc_filter_type setting.
8952 + * The algorithm is such that there is a total of 8 bits of shifting.
8953 + * The bit_shift for a mc_filter_type of 0 represents the number of
8954 + * left-shifts where the MSB of mc_addr[5] would still fall within
8955 + * the hash_mask. Case 0 does this exactly. Since there are a total
8956 + * of 8 bits of shifting, then mc_addr[4] will shift right the
8957 + * remaining number of bits. Thus 8 - bit_shift. The rest of the
8958 + * cases are a variation of this algorithm...essentially raising the
8959 + * number of bits to shift mc_addr[5] left, while still keeping the
8960 + * 8-bit shifting total.
8962 + /* For example, given the following Destination MAC Address and an
8963 + * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
8964 + * we can see that the bit_shift for case 0 is 4. These are the hash
8965 + * values resulting from each mc_filter_type...
8966 + * [0] [1] [2] [3] [4] [5]
8967 + * 01 AA 00 12 34 56
8970 + * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
8971 + * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
8972 + * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
8973 + * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
8975 + switch (hw->mac.mc_filter_type) {
8990 + hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
8991 + (((u16) mc_addr[5]) << bit_shift)));
8993 + return hash_value;
8997 + * e1000e_mc_addr_list_update_generic - Update Multicast addresses
8998 + * @hw: pointer to the HW structure
8999 + * @mc_addr_list: array of multicast addresses to program
9000 + * @mc_addr_count: number of multicast addresses to program
9001 + * @rar_used_count: the first RAR register free to program
9002 + * @rar_count: total number of supported Receive Address Registers
9004 + * Updates the Receive Address Registers and Multicast Table Array.
9005 + * The caller must have a packed mc_addr_list of multicast addresses.
9006 + * The parameter rar_count will usually be hw->mac.rar_entry_count
9007 + * unless there are workarounds that change this.
9009 +void e1000e_mc_addr_list_update_generic(struct e1000_hw *hw,
9010 + u8 *mc_addr_list, u32 mc_addr_count,
9011 + u32 rar_used_count, u32 rar_count)
9016 + /* Load the first set of multicast addresses into the exact
9017 + * filters (RAR). If there are not enough to fill the RAR
9018 + * array, clear the filters.
9020 + for (i = rar_used_count; i < rar_count; i++) {
9021 + if (mc_addr_count) {
9022 + e1000e_rar_set(hw, mc_addr_list, i);
9024 + mc_addr_list += ETH_ALEN;
9026 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
9028 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
9033 + /* Clear the old settings from the MTA */
9034 + hw_dbg(hw, "Clearing MTA\n");
9035 + for (i = 0; i < hw->mac.mta_reg_count; i++) {
9036 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
9040 + /* Load any remaining multicast addresses into the hash table. */
9041 + for (; mc_addr_count > 0; mc_addr_count--) {
9042 + hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
9043 + hw_dbg(hw, "Hash value = 0x%03X\n", hash_value);
9044 + e1000_mta_set(hw, hash_value);
9045 + mc_addr_list += ETH_ALEN;
9050 + * e1000e_clear_hw_cntrs_base - Clear base hardware counters
9051 + * @hw: pointer to the HW structure
9053 + * Clears the base hardware counters by reading the counter registers.
9055 +void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
9059 + temp = er32(CRCERRS);
9060 + temp = er32(SYMERRS);
9063 + temp = er32(ECOL);
9065 + temp = er32(LATECOL);
9066 + temp = er32(COLC);
9069 + temp = er32(RLEC);
9070 + temp = er32(XONRXC);
9071 + temp = er32(XONTXC);
9072 + temp = er32(XOFFRXC);
9073 + temp = er32(XOFFTXC);
9074 + temp = er32(FCRUC);
9075 + temp = er32(GPRC);
9076 + temp = er32(BPRC);
9077 + temp = er32(MPRC);
9078 + temp = er32(GPTC);
9079 + temp = er32(GORCL);
9080 + temp = er32(GORCH);
9081 + temp = er32(GOTCL);
9082 + temp = er32(GOTCH);
9083 + temp = er32(RNBC);
9088 + temp = er32(TORL);
9089 + temp = er32(TORH);
9090 + temp = er32(TOTL);
9091 + temp = er32(TOTH);
9094 + temp = er32(MPTC);
9095 + temp = er32(BPTC);
9099 + * e1000e_check_for_copper_link - Check for link (Copper)
9100 + * @hw: pointer to the HW structure
9102 + * Checks to see of the link status of the hardware has changed. If a
9103 + * change in link status has been detected, then we read the PHY registers
9104 + * to get the current speed/duplex if link exists.
9106 +s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
9108 + struct e1000_mac_info *mac = &hw->mac;
9112 + /* We only want to go out to the PHY registers to see if Auto-Neg
9113 + * has completed and/or if our link status has changed. The
9114 + * get_link_status flag is set upon receiving a Link Status
9115 + * Change or Rx Sequence Error interrupt.
9117 + if (!mac->get_link_status)
9120 + /* First we want to see if the MII Status Register reports
9121 + * link. If so, then we want to get the current speed/duplex
9124 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
9129 + return ret_val; /* No link detected */
9131 + mac->get_link_status = 0;
9133 + /* Check if there was DownShift, must be checked
9134 + * immediately after link-up */
9135 + e1000e_check_downshift(hw);
9137 + /* If we are forcing speed/duplex, then we simply return since
9138 + * we have already determined whether we have link or not.
9140 + if (!mac->autoneg) {
9141 + ret_val = -E1000_ERR_CONFIG;
9145 + /* Auto-Neg is enabled. Auto Speed Detection takes care
9146 + * of MAC speed/duplex configuration. So we only need to
9147 + * configure Collision Distance in the MAC.
9149 + e1000e_config_collision_dist(hw);
9151 + /* Configure Flow Control now that Auto-Neg has completed.
9152 + * First, we need to restore the desired flow control
9153 + * settings because we may have had to re-autoneg with a
9154 + * different link partner.
9156 + ret_val = e1000e_config_fc_after_link_up(hw);
9158 + hw_dbg(hw, "Error configuring flow control\n");
9165 + * e1000e_check_for_fiber_link - Check for link (Fiber)
9166 + * @hw: pointer to the HW structure
9168 + * Checks for link up on the hardware. If link is not up and we have
9169 + * a signal, then we need to force link up.
9171 +s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
9173 + struct e1000_mac_info *mac = &hw->mac;
9179 + ctrl = er32(CTRL);
9180 + status = er32(STATUS);
9181 + rxcw = er32(RXCW);
9183 + /* If we don't have link (auto-negotiation failed or link partner
9184 + * cannot auto-negotiate), the cable is plugged in (we have signal),
9185 + * and our link partner is not trying to auto-negotiate with us (we
9186 + * are receiving idles or data), we need to force link up. We also
9187 + * need to give auto-negotiation time to complete, in case the cable
9188 + * was just plugged in. The autoneg_failed flag does this.
9190 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9191 + if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
9192 + (!(rxcw & E1000_RXCW_C))) {
9193 + if (mac->autoneg_failed == 0) {
9194 + mac->autoneg_failed = 1;
9197 + hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
9199 + /* Disable auto-negotiation in the TXCW register */
9200 + ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9202 + /* Force link-up and also force full-duplex. */
9203 + ctrl = er32(CTRL);
9204 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9207 + /* Configure Flow Control after forcing link up. */
9208 + ret_val = e1000e_config_fc_after_link_up(hw);
9210 + hw_dbg(hw, "Error configuring flow control\n");
9213 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9214 + /* If we are forcing link and we are receiving /C/ ordered
9215 + * sets, re-enable auto-negotiation in the TXCW register
9216 + * and disable forced link in the Device Control register
9217 + * in an attempt to auto-negotiate with our link partner.
9219 + hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
9220 + ew32(TXCW, mac->txcw);
9221 + ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
9223 + mac->serdes_has_link = 1;
9230 + * e1000e_check_for_serdes_link - Check for link (Serdes)
9231 + * @hw: pointer to the HW structure
9233 + * Checks for link up on the hardware. If link is not up and we have
9234 + * a signal, then we need to force link up.
9236 +s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
9238 + struct e1000_mac_info *mac = &hw->mac;
9244 + ctrl = er32(CTRL);
9245 + status = er32(STATUS);
9246 + rxcw = er32(RXCW);
9248 + /* If we don't have link (auto-negotiation failed or link partner
9249 + * cannot auto-negotiate), and our link partner is not trying to
9250 + * auto-negotiate with us (we are receiving idles or data),
9251 + * we need to force link up. We also need to give auto-negotiation
9252 + * time to complete.
9254 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9255 + if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
9256 + if (mac->autoneg_failed == 0) {
9257 + mac->autoneg_failed = 1;
9260 + hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
9262 + /* Disable auto-negotiation in the TXCW register */
9263 + ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9265 + /* Force link-up and also force full-duplex. */
9266 + ctrl = er32(CTRL);
9267 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9270 + /* Configure Flow Control after forcing link up. */
9271 + ret_val = e1000e_config_fc_after_link_up(hw);
9273 + hw_dbg(hw, "Error configuring flow control\n");
9276 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9277 + /* If we are forcing link and we are receiving /C/ ordered
9278 + * sets, re-enable auto-negotiation in the TXCW register
9279 + * and disable forced link in the Device Control register
9280 + * in an attempt to auto-negotiate with our link partner.
9282 + hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
9283 + ew32(TXCW, mac->txcw);
9284 + ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
9286 + mac->serdes_has_link = 1;
9287 + } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
9288 + /* If we force link for non-auto-negotiation switch, check
9289 + * link status based on MAC synchronization for internal
9290 + * serdes media type.
9292 + /* SYNCH bit and IV bit are sticky. */
9294 + if (E1000_RXCW_SYNCH & er32(RXCW)) {
9295 + if (!(rxcw & E1000_RXCW_IV)) {
9296 + mac->serdes_has_link = 1;
9297 + hw_dbg(hw, "SERDES: Link is up.\n");
9300 + mac->serdes_has_link = 0;
9301 + hw_dbg(hw, "SERDES: Link is down.\n");
9305 + if (E1000_TXCW_ANE & er32(TXCW)) {
9306 + status = er32(STATUS);
9307 + mac->serdes_has_link = (status & E1000_STATUS_LU);
9314 + * e1000_set_default_fc_generic - Set flow control default values
9315 + * @hw: pointer to the HW structure
9317 + * Read the EEPROM for the default values for flow control and store the
9320 +static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
9322 + struct e1000_mac_info *mac = &hw->mac;
9326 + if (mac->fc != e1000_fc_default)
9329 + /* Read and store word 0x0F of the EEPROM. This word contains bits
9330 + * that determine the hardware's default PAUSE (flow control) mode,
9331 + * a bit that determines whether the HW defaults to enabling or
9332 + * disabling auto-negotiation, and the direction of the
9333 + * SW defined pins. If there is no SW over-ride of the flow
9334 + * control setting, then the variable hw->fc will
9335 + * be initialized based on a value in the EEPROM.
9337 + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
9340 + hw_dbg(hw, "NVM Read Error\n");
9344 + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
9345 + mac->fc = e1000_fc_none;
9346 + else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
9347 + NVM_WORD0F_ASM_DIR)
9348 + mac->fc = e1000_fc_tx_pause;
9350 + mac->fc = e1000_fc_full;
9356 + * e1000e_setup_link - Setup flow control and link settings
9357 + * @hw: pointer to the HW structure
9359 + * Determines which flow control settings to use, then configures flow
9360 + * control. Calls the appropriate media-specific link configuration
9361 + * function. Assuming the adapter has a valid link partner, a valid link
9362 + * should be established. Assumes the hardware has previously been reset
9363 + * and the transmitter and receiver are not enabled.
9365 +s32 e1000e_setup_link(struct e1000_hw *hw)
9367 + struct e1000_mac_info *mac = &hw->mac;
9370 + /* In the case of the phy reset being blocked, we already have a link.
9371 + * We do not need to set it up again.
9373 + if (e1000_check_reset_block(hw))
9376 + ret_val = e1000_set_default_fc_generic(hw);
9380 + /* We want to save off the original Flow Control configuration just
9381 + * in case we get disconnected and then reconnected into a different
9382 + * hub or switch with different Flow Control capabilities.
9384 + mac->original_fc = mac->fc;
9386 + hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc);
9388 + /* Call the necessary media_type subroutine to configure the link. */
9389 + ret_val = mac->ops.setup_physical_interface(hw);
9393 + /* Initialize the flow control address, type, and PAUSE timer
9394 + * registers to their default values. This is done even if flow
9395 + * control is disabled, because it does not hurt anything to
9396 + * initialize these registers.
9398 + hw_dbg(hw, "Initializing the Flow Control address, type and timer regs\n");
9399 + ew32(FCT, FLOW_CONTROL_TYPE);
9400 + ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
9401 + ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
9403 + ew32(FCTTV, mac->fc_pause_time);
9405 + return e1000e_set_fc_watermarks(hw);
9409 + * e1000_commit_fc_settings_generic - Configure flow control
9410 + * @hw: pointer to the HW structure
9412 + * Write the flow control settings to the Transmit Config Word Register (TXCW)
9413 + * base on the flow control settings in e1000_mac_info.
9415 +static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
9417 + struct e1000_mac_info *mac = &hw->mac;
9420 + /* Check for a software override of the flow control settings, and
9421 + * setup the device accordingly. If auto-negotiation is enabled, then
9422 + * software will have to set the "PAUSE" bits to the correct value in
9423 + * the Transmit Config Word Register (TXCW) and re-start auto-
9424 + * negotiation. However, if auto-negotiation is disabled, then
9425 + * software will have to manually configure the two flow control enable
9426 + * bits in the CTRL register.
9428 + * The possible values of the "fc" parameter are:
9429 + * 0: Flow control is completely disabled
9430 + * 1: Rx flow control is enabled (we can receive pause frames,
9431 + * but not send pause frames).
9432 + * 2: Tx flow control is enabled (we can send pause frames but we
9433 + * do not support receiving pause frames).
9434 + * 3: Both Rx and TX flow control (symmetric) are enabled.
9436 + switch (mac->fc) {
9437 + case e1000_fc_none:
9438 + /* Flow control completely disabled by a software over-ride. */
9439 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
9441 + case e1000_fc_rx_pause:
9442 + /* RX Flow control is enabled and TX Flow control is disabled
9443 + * by a software over-ride. Since there really isn't a way to
9444 + * advertise that we are capable of RX Pause ONLY, we will
9445 + * advertise that we support both symmetric and asymmetric RX
9446 + * PAUSE. Later, we will disable the adapter's ability to send
9449 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9451 + case e1000_fc_tx_pause:
9452 + /* TX Flow control is enabled, and RX Flow control is disabled,
9453 + * by a software over-ride.
9455 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
9457 + case e1000_fc_full:
9458 + /* Flow control (both RX and TX) is enabled by a software
9461 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9464 + hw_dbg(hw, "Flow control param set incorrectly\n");
9465 + return -E1000_ERR_CONFIG;
9476 + * e1000_poll_fiber_serdes_link_generic - Poll for link up
9477 + * @hw: pointer to the HW structure
9479 + * Polls for link up by reading the status register, if link fails to come
9480 + * up with auto-negotiation, then the link is forced if a signal is detected.
9482 +static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
9484 + struct e1000_mac_info *mac = &hw->mac;
9488 + /* If we have a signal (the cable is plugged in, or assumed true for
9489 + * serdes media) then poll for a "Link-Up" indication in the Device
9490 + * Status Register. Time-out if a link isn't seen in 500 milliseconds
9491 + * seconds (Auto-negotiation should complete in less than 500
9492 + * milliseconds even if the other end is doing it in SW).
9494 + for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
9496 + status = er32(STATUS);
9497 + if (status & E1000_STATUS_LU)
9500 + if (i == FIBER_LINK_UP_LIMIT) {
9501 + hw_dbg(hw, "Never got a valid link from auto-neg!!!\n");
9502 + mac->autoneg_failed = 1;
9503 + /* AutoNeg failed to achieve a link, so we'll call
9504 + * mac->check_for_link. This routine will force the
9505 + * link up if we detect a signal. This will allow us to
9506 + * communicate with non-autonegotiating link partners.
9508 + ret_val = mac->ops.check_for_link(hw);
9510 + hw_dbg(hw, "Error while checking for link\n");
9513 + mac->autoneg_failed = 0;
9515 + mac->autoneg_failed = 0;
9516 + hw_dbg(hw, "Valid Link Found\n");
9523 + * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
9524 + * @hw: pointer to the HW structure
9526 + * Configures collision distance and flow control for fiber and serdes
9527 + * links. Upon successful setup, poll for link.
9529 +s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
9534 + ctrl = er32(CTRL);
9536 + /* Take the link out of reset */
9537 + ctrl &= ~E1000_CTRL_LRST;
9539 + e1000e_config_collision_dist(hw);
9541 + ret_val = e1000_commit_fc_settings_generic(hw);
9545 + /* Since auto-negotiation is enabled, take the link out of reset (the
9546 + * link will be in reset, because we previously reset the chip). This
9547 + * will restart auto-negotiation. If auto-negotiation is successful
9548 + * then the link-up status bit will be set and the flow control enable
9549 + * bits (RFCE and TFCE) will be set according to their negotiated value.
9551 + hw_dbg(hw, "Auto-negotiation enabled\n");
9557 + /* For these adapters, the SW defineable pin 1 is set when the optics
9558 + * detect a signal. If we have a signal, then poll for a "Link-Up"
9561 + if (hw->media_type == e1000_media_type_internal_serdes ||
9562 + (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
9563 + ret_val = e1000_poll_fiber_serdes_link_generic(hw);
9565 + hw_dbg(hw, "No signal detected\n");
9572 + * e1000e_config_collision_dist - Configure collision distance
9573 + * @hw: pointer to the HW structure
9575 + * Configures the collision distance to the default value and is used
9576 + * during link setup. Currently no func pointer exists and all
9577 + * implementations are handled in the generic version of this function.
9579 +void e1000e_config_collision_dist(struct e1000_hw *hw)
9583 + tctl = er32(TCTL);
9585 + tctl &= ~E1000_TCTL_COLD;
9586 + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
9593 + * e1000e_set_fc_watermarks - Set flow control high/low watermarks
9594 + * @hw: pointer to the HW structure
9596 + * Sets the flow control high/low threshold (watermark) registers. If
9597 + * flow control XON frame transmission is enabled, then set XON frame
9598 + * tansmission as well.
9600 +s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
9602 + struct e1000_mac_info *mac = &hw->mac;
9603 + u32 fcrtl = 0, fcrth = 0;
9605 + /* Set the flow control receive threshold registers. Normally,
9606 + * these registers will be set to a default threshold that may be
9607 + * adjusted later by the driver's runtime code. However, if the
9608 + * ability to transmit pause frames is not enabled, then these
9609 + * registers will be set to 0.
9611 + if (mac->fc & e1000_fc_tx_pause) {
9612 + /* We need to set up the Receive Threshold high and low water
9613 + * marks as well as (optionally) enabling the transmission of
9616 + fcrtl = mac->fc_low_water;
9617 + fcrtl |= E1000_FCRTL_XONE;
9618 + fcrth = mac->fc_high_water;
9620 + ew32(FCRTL, fcrtl);
9621 + ew32(FCRTH, fcrth);
9627 + * e1000e_force_mac_fc - Force the MAC's flow control settings
9628 + * @hw: pointer to the HW structure
9630 + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
9631 + * device control register to reflect the adapter settings. TFCE and RFCE
9632 + * need to be explicitly set by software when a copper PHY is used because
9633 + * autonegotiation is managed by the PHY rather than the MAC. Software must
9634 + * also configure these bits when link is forced on a fiber connection.
9636 +s32 e1000e_force_mac_fc(struct e1000_hw *hw)
9638 + struct e1000_mac_info *mac = &hw->mac;
9641 + ctrl = er32(CTRL);
9643 + /* Because we didn't get link via the internal auto-negotiation
9644 + * mechanism (we either forced link or we got link via PHY
9645 + * auto-neg), we have to manually enable/disable transmit an
9646 + * receive flow control.
9648 + * The "Case" statement below enables/disable flow control
9649 + * according to the "mac->fc" parameter.
9651 + * The possible values of the "fc" parameter are:
9652 + * 0: Flow control is completely disabled
9653 + * 1: Rx flow control is enabled (we can receive pause
9654 + * frames but not send pause frames).
9655 + * 2: Tx flow control is enabled (we can send pause frames
9656 + * frames but we do not receive pause frames).
9657 + * 3: Both Rx and TX flow control (symmetric) is enabled.
9658 + * other: No other values should be possible at this point.
9660 + hw_dbg(hw, "mac->fc = %u\n", mac->fc);
9662 + switch (mac->fc) {
9663 + case e1000_fc_none:
9664 + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
9666 + case e1000_fc_rx_pause:
9667 + ctrl &= (~E1000_CTRL_TFCE);
9668 + ctrl |= E1000_CTRL_RFCE;
9670 + case e1000_fc_tx_pause:
9671 + ctrl &= (~E1000_CTRL_RFCE);
9672 + ctrl |= E1000_CTRL_TFCE;
9674 + case e1000_fc_full:
9675 + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
9678 + hw_dbg(hw, "Flow control param set incorrectly\n");
9679 + return -E1000_ERR_CONFIG;
9688 + * e1000e_config_fc_after_link_up - Configures flow control after link
9689 + * @hw: pointer to the HW structure
9691 + * Checks the status of auto-negotiation after link up to ensure that the
9692 + * speed and duplex were not forced. If the link needed to be forced, then
9693 + * flow control needs to be forced also. If auto-negotiation is enabled
9694 + * and did not fail, then we configure flow control based on our link
9697 +s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
9699 + struct e1000_mac_info *mac = &hw->mac;
9701 + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
9702 + u16 speed, duplex;
9704 + /* Check for the case where we have fiber media and auto-neg failed
9705 + * so we had to force link. In this case, we need to force the
9706 + * configuration of the MAC to match the "fc" parameter.
9708 + if (mac->autoneg_failed) {
9709 + if (hw->media_type == e1000_media_type_fiber ||
9710 + hw->media_type == e1000_media_type_internal_serdes)
9711 + ret_val = e1000e_force_mac_fc(hw);
9713 + if (hw->media_type == e1000_media_type_copper)
9714 + ret_val = e1000e_force_mac_fc(hw);
9718 + hw_dbg(hw, "Error forcing flow control settings\n");
9722 + /* Check for the case where we have copper media and auto-neg is
9723 + * enabled. In this case, we need to check and see if Auto-Neg
9724 + * has completed, and if so, how the PHY and link partner has
9725 + * flow control configured.
9727 + if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) {
9728 + /* Read the MII Status Register and check to see if AutoNeg
9729 + * has completed. We read this twice because this reg has
9730 + * some "sticky" (latched) bits.
9732 + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
9735 + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
9739 + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
9740 + hw_dbg(hw, "Copper PHY and Auto Neg "
9741 + "has not completed.\n");
9745 + /* The AutoNeg process has completed, so we now need to
9746 + * read both the Auto Negotiation Advertisement
9747 + * Register (Address 4) and the Auto_Negotiation Base
9748 + * Page Ability Register (Address 5) to determine how
9749 + * flow control was negotiated.
9751 + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
9754 + ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
9758 + /* Two bits in the Auto Negotiation Advertisement Register
9759 + * (Address 4) and two bits in the Auto Negotiation Base
9760 + * Page Ability Register (Address 5) determine flow control
9761 + * for both the PHY and the link partner. The following
9762 + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
9763 + * 1999, describes these PAUSE resolution bits and how flow
9764 + * control is determined based upon these settings.
9765 + * NOTE: DC = Don't Care
9767 + * LOCAL DEVICE | LINK PARTNER
9768 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
9769 + *-------|---------|-------|---------|--------------------
9770 + * 0 | 0 | DC | DC | e1000_fc_none
9771 + * 0 | 1 | 0 | DC | e1000_fc_none
9772 + * 0 | 1 | 1 | 0 | e1000_fc_none
9773 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
9774 + * 1 | 0 | 0 | DC | e1000_fc_none
9775 + * 1 | DC | 1 | DC | e1000_fc_full
9776 + * 1 | 1 | 0 | 0 | e1000_fc_none
9777 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
9780 + /* Are both PAUSE bits set to 1? If so, this implies
9781 + * Symmetric Flow Control is enabled at both ends. The
9782 + * ASM_DIR bits are irrelevant per the spec.
9784 + * For Symmetric Flow Control:
9786 + * LOCAL DEVICE | LINK PARTNER
9787 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
9788 + *-------|---------|-------|---------|--------------------
9789 + * 1 | DC | 1 | DC | E1000_fc_full
9792 + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
9793 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
9794 + /* Now we need to check if the user selected RX ONLY
9795 + * of pause frames. In this case, we had to advertise
9796 + * FULL flow control because we could not advertise RX
9797 + * ONLY. Hence, we must now check to see if we need to
9798 + * turn OFF the TRANSMISSION of PAUSE frames.
9800 + if (mac->original_fc == e1000_fc_full) {
9801 + mac->fc = e1000_fc_full;
9802 + hw_dbg(hw, "Flow Control = FULL.\r\n");
9804 + mac->fc = e1000_fc_rx_pause;
9805 + hw_dbg(hw, "Flow Control = "
9806 + "RX PAUSE frames only.\r\n");
9809 + /* For receiving PAUSE frames ONLY.
9811 + * LOCAL DEVICE | LINK PARTNER
9812 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
9813 + *-------|---------|-------|---------|--------------------
9814 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
9817 + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
9818 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
9819 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
9820 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
9821 + mac->fc = e1000_fc_tx_pause;
9822 + hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n");
9824 + /* For transmitting PAUSE frames ONLY.
9826 + * LOCAL DEVICE | LINK PARTNER
9827 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
9828 + *-------|---------|-------|---------|--------------------
9829 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
9832 + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
9833 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
9834 + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
9835 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
9836 + mac->fc = e1000_fc_rx_pause;
9837 + hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n");
9839 + /* Per the IEEE spec, at this point flow control should be
9840 + * disabled. However, we want to consider that we could
9841 + * be connected to a legacy switch that doesn't advertise
9842 + * desired flow control, but can be forced on the link
9843 + * partner. So if we advertised no flow control, that is
9844 + * what we will resolve to. If we advertised some kind of
9845 + * receive capability (Rx Pause Only or Full Flow Control)
9846 + * and the link partner advertised none, we will configure
9847 + * ourselves to enable Rx Flow Control only. We can do
9848 + * this safely for two reasons: If the link partner really
9849 + * didn't want flow control enabled, and we enable Rx, no
9850 + * harm done since we won't be receiving any PAUSE frames
9851 + * anyway. If the intent on the link partner was to have
9852 + * flow control enabled, then by us enabling RX only, we
9853 + * can at least receive pause frames and process them.
9854 + * This is a good idea because in most cases, since we are
9855 + * predominantly a server NIC, more times than not we will
9856 + * be asked to delay transmission of packets than asking
9857 + * our link partner to pause transmission of frames.
9859 + else if ((mac->original_fc == e1000_fc_none) ||
9860 + (mac->original_fc == e1000_fc_tx_pause)) {
9861 + mac->fc = e1000_fc_none;
9862 + hw_dbg(hw, "Flow Control = NONE.\r\n");
9864 + mac->fc = e1000_fc_rx_pause;
9865 + hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n");
9868 + /* Now we need to do one last check... If we auto-
9869 + * negotiated to HALF DUPLEX, flow control should not be
9870 + * enabled per IEEE 802.3 spec.
9872 + ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
9874 + hw_dbg(hw, "Error getting link speed and duplex\n");
9878 + if (duplex == HALF_DUPLEX)
9879 + mac->fc = e1000_fc_none;
9881 + /* Now we call a subroutine to actually force the MAC
9882 + * controller to use the correct flow control settings.
9884 + ret_val = e1000e_force_mac_fc(hw);
9886 + hw_dbg(hw, "Error forcing flow control settings\n");
9895 + * e1000e_get_speed_and_duplex_copper - Retreive current speed/duplex
9896 + * @hw: pointer to the HW structure
9897 + * @speed: stores the current speed
9898 + * @duplex: stores the current duplex
9900 + * Read the status register for the current speed/duplex and store the current
9901 + * speed and duplex for copper connections.
9903 +s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
9907 + status = er32(STATUS);
9908 + if (status & E1000_STATUS_SPEED_1000) {
9909 + *speed = SPEED_1000;
9910 + hw_dbg(hw, "1000 Mbs, ");
9911 + } else if (status & E1000_STATUS_SPEED_100) {
9912 + *speed = SPEED_100;
9913 + hw_dbg(hw, "100 Mbs, ");
9915 + *speed = SPEED_10;
9916 + hw_dbg(hw, "10 Mbs, ");
9919 + if (status & E1000_STATUS_FD) {
9920 + *duplex = FULL_DUPLEX;
9921 + hw_dbg(hw, "Full Duplex\n");
9923 + *duplex = HALF_DUPLEX;
9924 + hw_dbg(hw, "Half Duplex\n");
9931 + * e1000e_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex
9932 + * @hw: pointer to the HW structure
9933 + * @speed: stores the current speed
9934 + * @duplex: stores the current duplex
9936 + * Sets the speed and duplex to gigabit full duplex (the only possible option)
9937 + * for fiber/serdes links.
9939 +s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
9941 + *speed = SPEED_1000;
9942 + *duplex = FULL_DUPLEX;
9948 + * e1000e_get_hw_semaphore - Acquire hardware semaphore
9949 + * @hw: pointer to the HW structure
9951 + * Acquire the HW semaphore to access the PHY or NVM
9953 +s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
9956 + s32 timeout = hw->nvm.word_size + 1;
9959 + /* Get the SW semaphore */
9960 + while (i < timeout) {
9961 + swsm = er32(SWSM);
9962 + if (!(swsm & E1000_SWSM_SMBI))
9969 + if (i == timeout) {
9970 + hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n");
9971 + return -E1000_ERR_NVM;
9974 + /* Get the FW semaphore. */
9975 + for (i = 0; i < timeout; i++) {
9976 + swsm = er32(SWSM);
9977 + ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
9979 + /* Semaphore acquired if bit latched */
9980 + if (er32(SWSM) & E1000_SWSM_SWESMBI)
9986 + if (i == timeout) {
9987 + /* Release semaphores */
9988 + e1000e_put_hw_semaphore(hw);
9989 + hw_dbg(hw, "Driver can't access the NVM\n");
9990 + return -E1000_ERR_NVM;
9997 + * e1000e_put_hw_semaphore - Release hardware semaphore
9998 + * @hw: pointer to the HW structure
10000 + * Release hardware semaphore used to access the PHY or NVM
10002 +void e1000e_put_hw_semaphore(struct e1000_hw *hw)
10006 + swsm = er32(SWSM);
10007 + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
10008 + ew32(SWSM, swsm);
10012 + * e1000e_get_auto_rd_done - Check for auto read completion
10013 + * @hw: pointer to the HW structure
10015 + * Check EEPROM for Auto Read done bit.
10017 +s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
10021 + while (i < AUTO_READ_DONE_TIMEOUT) {
10022 + if (er32(EECD) & E1000_EECD_AUTO_RD)
10028 + if (i == AUTO_READ_DONE_TIMEOUT) {
10029 + hw_dbg(hw, "Auto read by HW from NVM has not completed.\n");
10030 + return -E1000_ERR_RESET;
10037 + * e1000e_valid_led_default - Verify a valid default LED config
10038 + * @hw: pointer to the HW structure
10039 + * @data: pointer to the NVM (EEPROM)
10041 + * Read the EEPROM for the current default LED configuration. If the
10042 + * LED configuration is not valid, set to a valid LED configuration.
10044 +s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
10048 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
10050 + hw_dbg(hw, "NVM Read Error\n");
10054 + if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
10055 + *data = ID_LED_DEFAULT;
10061 + * e1000e_id_led_init -
10062 + * @hw: pointer to the HW structure
10065 +s32 e1000e_id_led_init(struct e1000_hw *hw)
10067 + struct e1000_mac_info *mac = &hw->mac;
10069 + const u32 ledctl_mask = 0x000000FF;
10070 + const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
10071 + const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
10072 + u16 data, i, temp;
10073 + const u16 led_mask = 0x0F;
10075 + ret_val = hw->nvm.ops.valid_led_default(hw, &data);
10079 + mac->ledctl_default = er32(LEDCTL);
10080 + mac->ledctl_mode1 = mac->ledctl_default;
10081 + mac->ledctl_mode2 = mac->ledctl_default;
10083 + for (i = 0; i < 4; i++) {
10084 + temp = (data >> (i << 2)) & led_mask;
10086 + case ID_LED_ON1_DEF2:
10087 + case ID_LED_ON1_ON2:
10088 + case ID_LED_ON1_OFF2:
10089 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10090 + mac->ledctl_mode1 |= ledctl_on << (i << 3);
10092 + case ID_LED_OFF1_DEF2:
10093 + case ID_LED_OFF1_ON2:
10094 + case ID_LED_OFF1_OFF2:
10095 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10096 + mac->ledctl_mode1 |= ledctl_off << (i << 3);
10103 + case ID_LED_DEF1_ON2:
10104 + case ID_LED_ON1_ON2:
10105 + case ID_LED_OFF1_ON2:
10106 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10107 + mac->ledctl_mode2 |= ledctl_on << (i << 3);
10109 + case ID_LED_DEF1_OFF2:
10110 + case ID_LED_ON1_OFF2:
10111 + case ID_LED_OFF1_OFF2:
10112 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10113 + mac->ledctl_mode2 |= ledctl_off << (i << 3);
10125 + * e1000e_cleanup_led_generic - Set LED config to default operation
10126 + * @hw: pointer to the HW structure
10128 + * Remove the current LED configuration and set the LED configuration
10129 + * to the default value, saved from the EEPROM.
10131 +s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
10133 + ew32(LEDCTL, hw->mac.ledctl_default);
10138 + * e1000e_blink_led - Blink LED
10139 + * @hw: pointer to the HW structure
10141 + * Blink the led's which are set to be on.
10143 +s32 e1000e_blink_led(struct e1000_hw *hw)
10145 + u32 ledctl_blink = 0;
10148 + if (hw->media_type == e1000_media_type_fiber) {
10149 + /* always blink LED0 for PCI-E fiber */
10150 + ledctl_blink = E1000_LEDCTL_LED0_BLINK |
10151 + (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
10153 + /* set the blink bit for each LED that's "on" (0x0E)
10154 + * in ledctl_mode2 */
10155 + ledctl_blink = hw->mac.ledctl_mode2;
10156 + for (i = 0; i < 4; i++)
10157 + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
10158 + E1000_LEDCTL_MODE_LED_ON)
10159 + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
10163 + ew32(LEDCTL, ledctl_blink);
10169 + * e1000e_led_on_generic - Turn LED on
10170 + * @hw: pointer to the HW structure
10174 +s32 e1000e_led_on_generic(struct e1000_hw *hw)
10178 + switch (hw->media_type) {
10179 + case e1000_media_type_fiber:
10180 + ctrl = er32(CTRL);
10181 + ctrl &= ~E1000_CTRL_SWDPIN0;
10182 + ctrl |= E1000_CTRL_SWDPIO0;
10183 + ew32(CTRL, ctrl);
10185 + case e1000_media_type_copper:
10186 + ew32(LEDCTL, hw->mac.ledctl_mode2);
10196 + * e1000e_led_off_generic - Turn LED off
10197 + * @hw: pointer to the HW structure
10201 +s32 e1000e_led_off_generic(struct e1000_hw *hw)
10205 + switch (hw->media_type) {
10206 + case e1000_media_type_fiber:
10207 + ctrl = er32(CTRL);
10208 + ctrl |= E1000_CTRL_SWDPIN0;
10209 + ctrl |= E1000_CTRL_SWDPIO0;
10210 + ew32(CTRL, ctrl);
10212 + case e1000_media_type_copper:
10213 + ew32(LEDCTL, hw->mac.ledctl_mode1);
10223 + * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
10224 + * @hw: pointer to the HW structure
10225 + * @no_snoop: bitmap of snoop events
10227 + * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
10229 +void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
10235 + gcr &= ~(PCIE_NO_SNOOP_ALL);
10242 + * e1000e_disable_pcie_master - Disables PCI-express master access
10243 + * @hw: pointer to the HW structure
10245 + * Returns 0 if successful, else returns -10
10246 + * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
10247 + * the master requests to be disabled.
10249 + * Disables PCI-Express master access and verifies there are no pending
10252 +s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
10255 + s32 timeout = MASTER_DISABLE_TIMEOUT;
10257 + ctrl = er32(CTRL);
10258 + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
10259 + ew32(CTRL, ctrl);
10261 + while (timeout) {
10262 + if (!(er32(STATUS) &
10263 + E1000_STATUS_GIO_MASTER_ENABLE))
10270 + hw_dbg(hw, "Master requests are pending.\n");
10271 + return -E1000_ERR_MASTER_REQUESTS_PENDING;
10278 + * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
10279 + * @hw: pointer to the HW structure
10281 + * Reset the Adaptive Interframe Spacing throttle to default values.
10283 +void e1000e_reset_adaptive(struct e1000_hw *hw)
10285 + struct e1000_mac_info *mac = &hw->mac;
10287 + mac->current_ifs_val = 0;
10288 + mac->ifs_min_val = IFS_MIN;
10289 + mac->ifs_max_val = IFS_MAX;
10290 + mac->ifs_step_size = IFS_STEP;
10291 + mac->ifs_ratio = IFS_RATIO;
10293 + mac->in_ifs_mode = 0;
10298 + * e1000e_update_adaptive - Update Adaptive Interframe Spacing
10299 + * @hw: pointer to the HW structure
10301 + * Update the Adaptive Interframe Spacing Throttle value based on the
10302 + * time between transmitted packets and time between collisions.
10304 +void e1000e_update_adaptive(struct e1000_hw *hw)
10306 + struct e1000_mac_info *mac = &hw->mac;
10308 + if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
10309 + if (mac->tx_packet_delta > MIN_NUM_XMITS) {
10310 + mac->in_ifs_mode = 1;
10311 + if (mac->current_ifs_val < mac->ifs_max_val) {
10312 + if (!mac->current_ifs_val)
10313 + mac->current_ifs_val = mac->ifs_min_val;
10315 + mac->current_ifs_val +=
10316 + mac->ifs_step_size;
10318 + mac->current_ifs_val);
10322 + if (mac->in_ifs_mode &&
10323 + (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
10324 + mac->current_ifs_val = 0;
10325 + mac->in_ifs_mode = 0;
10332 + * e1000_raise_eec_clk - Raise EEPROM clock
10333 + * @hw: pointer to the HW structure
10334 + * @eecd: pointer to the EEPROM
10336 + * Enable/Raise the EEPROM clock bit.
10338 +static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
10340 + *eecd = *eecd | E1000_EECD_SK;
10341 + ew32(EECD, *eecd);
10343 + udelay(hw->nvm.delay_usec);
10347 + * e1000_lower_eec_clk - Lower EEPROM clock
10348 + * @hw: pointer to the HW structure
10349 + * @eecd: pointer to the EEPROM
10351 + * Clear/Lower the EEPROM clock bit.
10353 +static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
10355 + *eecd = *eecd & ~E1000_EECD_SK;
10356 + ew32(EECD, *eecd);
10358 + udelay(hw->nvm.delay_usec);
10362 + * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
10363 + * @hw: pointer to the HW structure
10364 + * @data: data to send to the EEPROM
10365 + * @count: number of bits to shift out
10367 + * We need to shift 'count' bits out to the EEPROM. So, the value in the
10368 + * "data" parameter will be shifted out to the EEPROM one bit at a time.
10369 + * In order to do this, "data" must be broken down into bits.
10371 +static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
10373 + struct e1000_nvm_info *nvm = &hw->nvm;
10374 + u32 eecd = er32(EECD);
10377 + mask = 0x01 << (count - 1);
10378 + if (nvm->type == e1000_nvm_eeprom_spi)
10379 + eecd |= E1000_EECD_DO;
10382 + eecd &= ~E1000_EECD_DI;
10385 + eecd |= E1000_EECD_DI;
10387 + ew32(EECD, eecd);
10390 + udelay(nvm->delay_usec);
10392 + e1000_raise_eec_clk(hw, &eecd);
10393 + e1000_lower_eec_clk(hw, &eecd);
10398 + eecd &= ~E1000_EECD_DI;
10399 + ew32(EECD, eecd);
10403 + * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
10404 + * @hw: pointer to the HW structure
10405 + * @count: number of bits to shift in
10407 + * In order to read a register from the EEPROM, we need to shift 'count' bits
10408 + * in from the EEPROM. Bits are "shifted in" by raising the clock input to
10409 + * the EEPROM (setting the SK bit), and then reading the value of the data out
10410 + * "DO" bit. During this "shifting in" process the data in "DI" bit should
10411 + * always be clear.
10413 +static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
10419 + eecd = er32(EECD);
10421 + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
10424 + for (i = 0; i < count; i++) {
10426 + e1000_raise_eec_clk(hw, &eecd);
10428 + eecd = er32(EECD);
10430 + eecd &= ~E1000_EECD_DI;
10431 + if (eecd & E1000_EECD_DO)
10434 + e1000_lower_eec_clk(hw, &eecd);
10441 + * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
10442 + * @hw: pointer to the HW structure
10443 + * @ee_reg: EEPROM flag for polling
10445 + * Polls the EEPROM status bit for either read or write completion based
10446 + * upon the value of 'ee_reg'.
10448 +s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
10450 + u32 attempts = 100000;
10453 + for (i = 0; i < attempts; i++) {
10454 + if (ee_reg == E1000_NVM_POLL_READ)
10455 + reg = er32(EERD);
10457 + reg = er32(EEWR);
10459 + if (reg & E1000_NVM_RW_REG_DONE)
10465 + return -E1000_ERR_NVM;
10469 + * e1000e_acquire_nvm - Generic request for access to EEPROM
10470 + * @hw: pointer to the HW structure
10472 + * Set the EEPROM access request bit and wait for EEPROM access grant bit.
10473 + * Return successful if access grant bit set, else clear the request for
10474 + * EEPROM access and return -E1000_ERR_NVM (-1).
10476 +s32 e1000e_acquire_nvm(struct e1000_hw *hw)
10478 + u32 eecd = er32(EECD);
10479 + s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
10481 + ew32(EECD, eecd | E1000_EECD_REQ);
10482 + eecd = er32(EECD);
10484 + while (timeout) {
10485 + if (eecd & E1000_EECD_GNT)
10488 + eecd = er32(EECD);
10493 + eecd &= ~E1000_EECD_REQ;
10494 + ew32(EECD, eecd);
10495 + hw_dbg(hw, "Could not acquire NVM grant\n");
10496 + return -E1000_ERR_NVM;
10503 + * e1000_standby_nvm - Return EEPROM to standby state
10504 + * @hw: pointer to the HW structure
10506 + * Return the EEPROM to a standby state.
10508 +static void e1000_standby_nvm(struct e1000_hw *hw)
10510 + struct e1000_nvm_info *nvm = &hw->nvm;
10511 + u32 eecd = er32(EECD);
10513 + if (nvm->type == e1000_nvm_eeprom_spi) {
10514 + /* Toggle CS to flush commands */
10515 + eecd |= E1000_EECD_CS;
10516 + ew32(EECD, eecd);
10518 + udelay(nvm->delay_usec);
10519 + eecd &= ~E1000_EECD_CS;
10520 + ew32(EECD, eecd);
10522 + udelay(nvm->delay_usec);
10527 + * e1000_stop_nvm - Terminate EEPROM command
10528 + * @hw: pointer to the HW structure
10530 + * Terminates the current command by inverting the EEPROM's chip select pin.
10532 +static void e1000_stop_nvm(struct e1000_hw *hw)
10536 + eecd = er32(EECD);
10537 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
10538 + /* Pull CS high */
10539 + eecd |= E1000_EECD_CS;
10540 + e1000_lower_eec_clk(hw, &eecd);
10545 + * e1000e_release_nvm - Release exclusive access to EEPROM
10546 + * @hw: pointer to the HW structure
10548 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
10550 +void e1000e_release_nvm(struct e1000_hw *hw)
10554 + e1000_stop_nvm(hw);
10556 + eecd = er32(EECD);
10557 + eecd &= ~E1000_EECD_REQ;
10558 + ew32(EECD, eecd);
10562 + * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
10563 + * @hw: pointer to the HW structure
10565 + * Setups the EEPROM for reading and writing.
10567 +static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
10569 + struct e1000_nvm_info *nvm = &hw->nvm;
10570 + u32 eecd = er32(EECD);
10574 + if (nvm->type == e1000_nvm_eeprom_spi) {
10575 + /* Clear SK and CS */
10576 + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
10577 + ew32(EECD, eecd);
10579 + timeout = NVM_MAX_RETRY_SPI;
10581 + /* Read "Status Register" repeatedly until the LSB is cleared.
10582 + * The EEPROM will signal that the command has been completed
10583 + * by clearing bit 0 of the internal status register. If it's
10584 + * not cleared within 'timeout', then error out. */
10585 + while (timeout) {
10586 + e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
10587 + hw->nvm.opcode_bits);
10588 + spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
10589 + if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
10593 + e1000_standby_nvm(hw);
10598 + hw_dbg(hw, "SPI NVM Status error\n");
10599 + return -E1000_ERR_NVM;
10607 + * e1000e_read_nvm_spi - Read EEPROM's using SPI
10608 + * @hw: pointer to the HW structure
10609 + * @offset: offset of word in the EEPROM to read
10610 + * @words: number of words to read
10611 + * @data: word read from the EEPROM
10613 + * Reads a 16 bit word from the EEPROM.
10615 +s32 e1000e_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
10617 + struct e1000_nvm_info *nvm = &hw->nvm;
10621 + u8 read_opcode = NVM_READ_OPCODE_SPI;
10623 + /* A check for invalid values: offset too large, too many words,
10624 + * and not enough words. */
10625 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
10627 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
10628 + return -E1000_ERR_NVM;
10631 + ret_val = nvm->ops.acquire_nvm(hw);
10635 + ret_val = e1000_ready_nvm_eeprom(hw);
10637 + nvm->ops.release_nvm(hw);
10641 + e1000_standby_nvm(hw);
10643 + if ((nvm->address_bits == 8) && (offset >= 128))
10644 + read_opcode |= NVM_A8_OPCODE_SPI;
10646 + /* Send the READ command (opcode + addr) */
10647 + e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
10648 + e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
10650 + /* Read the data. SPI NVMs increment the address with each byte
10651 + * read and will roll over if reading beyond the end. This allows
10652 + * us to read the whole NVM from any offset */
10653 + for (i = 0; i < words; i++) {
10654 + word_in = e1000_shift_in_eec_bits(hw, 16);
10655 + data[i] = (word_in >> 8) | (word_in << 8);
10658 + nvm->ops.release_nvm(hw);
10663 + * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
10664 + * @hw: pointer to the HW structure
10665 + * @offset: offset of word in the EEPROM to read
10666 + * @words: number of words to read
10667 + * @data: word read from the EEPROM
10669 + * Reads a 16 bit word from the EEPROM using the EERD register.
10671 +s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
10673 + struct e1000_nvm_info *nvm = &hw->nvm;
10677 + /* A check for invalid values: offset too large, too many words,
10678 + * and not enough words. */
10679 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
10681 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
10682 + return -E1000_ERR_NVM;
10685 + for (i = 0; i < words; i++) {
10686 + eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
10687 + E1000_NVM_RW_REG_START;
10689 + ew32(EERD, eerd);
10690 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
10694 + data[i] = (er32(EERD) >>
10695 + E1000_NVM_RW_REG_DATA);
10702 + * e1000e_write_nvm_spi - Write to EEPROM using SPI
10703 + * @hw: pointer to the HW structure
10704 + * @offset: offset within the EEPROM to be written to
10705 + * @words: number of words to write
10706 + * @data: 16 bit word(s) to be written to the EEPROM
10708 + * Writes data to EEPROM at offset using SPI interface.
10710 + * If e1000e_update_nvm_checksum is not called after this function , the
10711 + * EEPROM will most likley contain an invalid checksum.
10713 +s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
10715 + struct e1000_nvm_info *nvm = &hw->nvm;
10719 + /* A check for invalid values: offset too large, too many words,
10720 + * and not enough words. */
10721 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
10723 + hw_dbg(hw, "nvm parameter(s) out of bounds\n");
10724 + return -E1000_ERR_NVM;
10727 + ret_val = nvm->ops.acquire_nvm(hw);
10733 + while (widx < words) {
10734 + u8 write_opcode = NVM_WRITE_OPCODE_SPI;
10736 + ret_val = e1000_ready_nvm_eeprom(hw);
10738 + nvm->ops.release_nvm(hw);
10742 + e1000_standby_nvm(hw);
10744 + /* Send the WRITE ENABLE command (8 bit opcode) */
10745 + e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
10746 + nvm->opcode_bits);
10748 + e1000_standby_nvm(hw);
10750 + /* Some SPI eeproms use the 8th address bit embedded in the
10752 + if ((nvm->address_bits == 8) && (offset >= 128))
10753 + write_opcode |= NVM_A8_OPCODE_SPI;
10755 + /* Send the Write command (8-bit opcode + addr) */
10756 + e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
10757 + e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
10758 + nvm->address_bits);
10760 + /* Loop to allow for up to whole page write of eeprom */
10761 + while (widx < words) {
10762 + u16 word_out = data[widx];
10763 + word_out = (word_out >> 8) | (word_out << 8);
10764 + e1000_shift_out_eec_bits(hw, word_out, 16);
10767 + if ((((offset + widx) * 2) % nvm->page_size) == 0) {
10768 + e1000_standby_nvm(hw);
10779 + * e1000e_read_mac_addr - Read device MAC address
10780 + * @hw: pointer to the HW structure
10782 + * Reads the device MAC address from the EEPROM and stores the value.
10783 + * Since devices with two ports use the same EEPROM, we increment the
10784 + * last bit in the MAC address for the second port.
10786 +s32 e1000e_read_mac_addr(struct e1000_hw *hw)
10789 + u16 offset, nvm_data, i;
10791 + for (i = 0; i < ETH_ALEN; i += 2) {
10793 + ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
10795 + hw_dbg(hw, "NVM Read Error\n");
10798 + hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
10799 + hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
10802 + /* Flip last bit of mac address if we're on second port */
10803 + if (hw->bus.func == E1000_FUNC_1)
10804 + hw->mac.perm_addr[5] ^= 1;
10806 + for (i = 0; i < ETH_ALEN; i++)
10807 + hw->mac.addr[i] = hw->mac.perm_addr[i];
10813 + * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
10814 + * @hw: pointer to the HW structure
10816 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
10817 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
10819 +s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
10822 + u16 checksum = 0;
10825 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
10826 + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
10828 + hw_dbg(hw, "NVM Read Error\n");
10831 + checksum += nvm_data;
10834 + if (checksum != (u16) NVM_SUM) {
10835 + hw_dbg(hw, "NVM Checksum Invalid\n");
10836 + return -E1000_ERR_NVM;
10843 + * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
10844 + * @hw: pointer to the HW structure
10846 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
10847 + * up to the checksum. Then calculates the EEPROM checksum and writes the
10848 + * value to the EEPROM.
10850 +s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
10853 + u16 checksum = 0;
10856 + for (i = 0; i < NVM_CHECKSUM_REG; i++) {
10857 + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
10859 + hw_dbg(hw, "NVM Read Error while updating checksum.\n");
10862 + checksum += nvm_data;
10864 + checksum = (u16) NVM_SUM - checksum;
10865 + ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
10867 + hw_dbg(hw, "NVM Write Error while updating checksum.\n");
10873 + * e1000e_reload_nvm - Reloads EEPROM
10874 + * @hw: pointer to the HW structure
10876 + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
10877 + * extended control register.
10879 +void e1000e_reload_nvm(struct e1000_hw *hw)
10884 + ctrl_ext = er32(CTRL_EXT);
10885 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
10886 + ew32(CTRL_EXT, ctrl_ext);
10891 + * e1000_calculate_checksum - Calculate checksum for buffer
10892 + * @buffer: pointer to EEPROM
10893 + * @length: size of EEPROM to calculate a checksum for
10895 + * Calculates the checksum for some buffer on a specified length. The
10896 + * checksum calculated is returned.
10898 +static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
10906 + for (i = 0; i < length; i++)
10907 + sum += buffer[i];
10909 + return (u8) (0 - sum);
10913 + * e1000_mng_enable_host_if - Checks host interface is enabled
10914 + * @hw: pointer to the HW structure
10916 + * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
10918 + * This function checks whether the HOST IF is enabled for command operaton
10919 + * and also checks whether the previous command is completed. It busy waits
10920 + * in case of previous command is not completed.
10922 +static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
10927 + /* Check that the host interface is enabled. */
10928 + hicr = er32(HICR);
10929 + if ((hicr & E1000_HICR_EN) == 0) {
10930 + hw_dbg(hw, "E1000_HOST_EN bit disabled.\n");
10931 + return -E1000_ERR_HOST_INTERFACE_COMMAND;
10933 + /* check the previous command is completed */
10934 + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
10935 + hicr = er32(HICR);
10936 + if (!(hicr & E1000_HICR_C))
10941 + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
10942 + hw_dbg(hw, "Previous command timeout failed .\n");
10943 + return -E1000_ERR_HOST_INTERFACE_COMMAND;
10950 + * e1000e_check_mng_mode - check managament mode
10951 + * @hw: pointer to the HW structure
10953 + * Reads the firmware semaphore register and returns true (>0) if
10954 + * manageability is enabled, else false (0).
10956 +bool e1000e_check_mng_mode(struct e1000_hw *hw)
10958 + u32 fwsm = er32(FWSM);
10960 + return (fwsm & E1000_FWSM_MODE_MASK) == hw->mac.ops.mng_mode_enab;
10964 + * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
10965 + * @hw: pointer to the HW structure
10967 + * Enables packet filtering on transmit packets if manageability is enabled
10968 + * and host interface is enabled.
10970 +bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
10972 + struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
10973 + u32 *buffer = (u32 *)&hw->mng_cookie;
10975 + s32 ret_val, hdr_csum, csum;
10978 + /* No manageability, no filtering */
10979 + if (!e1000e_check_mng_mode(hw)) {
10980 + hw->mac.tx_pkt_filtering = 0;
10984 + /* If we can't read from the host interface for whatever
10985 + * reason, disable filtering.
10987 + ret_val = e1000_mng_enable_host_if(hw);
10988 + if (ret_val != 0) {
10989 + hw->mac.tx_pkt_filtering = 0;
10993 + /* Read in the header. Length and offset are in dwords. */
10994 + len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
10995 + offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
10996 + for (i = 0; i < len; i++)
10997 + *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
10998 + hdr_csum = hdr->checksum;
10999 + hdr->checksum = 0;
11000 + csum = e1000_calculate_checksum((u8 *)hdr,
11001 + E1000_MNG_DHCP_COOKIE_LENGTH);
11002 + /* If either the checksums or signature don't match, then
11003 + * the cookie area isn't considered valid, in which case we
11004 + * take the safe route of assuming Tx filtering is enabled.
11006 + if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
11007 + hw->mac.tx_pkt_filtering = 1;
11011 + /* Cookie area is valid, make the final check for filtering. */
11012 + if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
11013 + hw->mac.tx_pkt_filtering = 0;
11017 + hw->mac.tx_pkt_filtering = 1;
11022 + * e1000_mng_write_cmd_header - Writes manageability command header
11023 + * @hw: pointer to the HW structure
11024 + * @hdr: pointer to the host interface command header
11026 + * Writes the command header after does the checksum calculation.
11028 +static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
11029 + struct e1000_host_mng_command_header *hdr)
11031 + u16 i, length = sizeof(struct e1000_host_mng_command_header);
11033 + /* Write the whole command header structure with new checksum. */
11035 + hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
11038 + /* Write the relevant command block into the ram area. */
11039 + for (i = 0; i < length; i++) {
11040 + E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
11041 + *((u32 *) hdr + i));
11049 + * e1000_mng_host_if_write - Writes to the manageability host interface
11050 + * @hw: pointer to the HW structure
11051 + * @buffer: pointer to the host interface buffer
11052 + * @length: size of the buffer
11053 + * @offset: location in the buffer to write to
11054 + * @sum: sum of the data (not checksum)
11056 + * This function writes the buffer content at the offset given on the host if.
11057 + * It also does alignment considerations to do the writes in most efficient
11058 + * way. Also fills up the sum of the buffer in *buffer parameter.
11060 +static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
11061 + u16 length, u16 offset, u8 *sum)
11064 + u8 *bufptr = buffer;
11066 + u16 remaining, i, j, prev_bytes;
11068 + /* sum = only sum of the data and it is not checksum */
11070 + if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
11071 + return -E1000_ERR_PARAM;
11073 + tmp = (u8 *)&data;
11074 + prev_bytes = offset & 0x3;
11077 + if (prev_bytes) {
11078 + data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
11079 + for (j = prev_bytes; j < sizeof(u32); j++) {
11080 + *(tmp + j) = *bufptr++;
11081 + *sum += *(tmp + j);
11083 + E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
11084 + length -= j - prev_bytes;
11088 + remaining = length & 0x3;
11089 + length -= remaining;
11091 + /* Calculate length in DWORDs */
11094 + /* The device driver writes the relevant command block into the
11096 + for (i = 0; i < length; i++) {
11097 + for (j = 0; j < sizeof(u32); j++) {
11098 + *(tmp + j) = *bufptr++;
11099 + *sum += *(tmp + j);
11102 + E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
11105 + for (j = 0; j < sizeof(u32); j++) {
11106 + if (j < remaining)
11107 + *(tmp + j) = *bufptr++;
11111 + *sum += *(tmp + j);
11113 + E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
11120 + * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
11121 + * @hw: pointer to the HW structure
11122 + * @buffer: pointer to the host interface
11123 + * @length: size of the buffer
11125 + * Writes the DHCP information to the host interface.
11127 +s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
11129 + struct e1000_host_mng_command_header hdr;
11133 + hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
11134 + hdr.command_length = length;
11135 + hdr.reserved1 = 0;
11136 + hdr.reserved2 = 0;
11137 + hdr.checksum = 0;
11139 + /* Enable the host interface */
11140 + ret_val = e1000_mng_enable_host_if(hw);
11144 + /* Populate the host interface with the contents of "buffer". */
11145 + ret_val = e1000_mng_host_if_write(hw, buffer, length,
11146 + sizeof(hdr), &(hdr.checksum));
11150 + /* Write the manageability command header */
11151 + ret_val = e1000_mng_write_cmd_header(hw, &hdr);
11155 + /* Tell the ARC a new command is pending. */
11156 + hicr = er32(HICR);
11157 + ew32(HICR, hicr | E1000_HICR_C);
11163 + * e1000e_enable_mng_pass_thru - Enable processing of ARP's
11164 + * @hw: pointer to the HW structure
11166 + * Verifies the hardware needs to allow ARPs to be processed by the host.
11168 +bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
11171 + u32 fwsm, factps;
11172 + bool ret_val = 0;
11174 + manc = er32(MANC);
11176 + if (!(manc & E1000_MANC_RCV_TCO_EN) ||
11177 + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
11180 + if (hw->mac.arc_subsystem_valid) {
11181 + fwsm = er32(FWSM);
11182 + factps = er32(FACTPS);
11184 + if (!(factps & E1000_FACTPS_MNGCG) &&
11185 + ((fwsm & E1000_FWSM_MODE_MASK) ==
11186 + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
11191 + if ((manc & E1000_MANC_SMBUS_EN) &&
11192 + !(manc & E1000_MANC_ASF_EN)) {
11201 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/Makefile linux-2.6.22-10/drivers/net/e1000e/Makefile
11202 --- linux-2.6.22-0/drivers/net/e1000e/Makefile 1969-12-31 19:00:00.000000000 -0500
11203 +++ linux-2.6.22-10/drivers/net/e1000e/Makefile 2007-11-21 13:55:13.000000000 -0500
11205 +################################################################################
11207 +# Intel PRO/1000 Linux driver
11208 +# Copyright(c) 1999 - 2007 Intel Corporation.
11210 +# This program is free software; you can redistribute it and/or modify it
11211 +# under the terms and conditions of the GNU General Public License,
11212 +# version 2, as published by the Free Software Foundation.
11214 +# This program is distributed in the hope it will be useful, but WITHOUT
11215 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11216 +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11219 +# You should have received a copy of the GNU General Public License along with
11220 +# this program; if not, write to the Free Software Foundation, Inc.,
11221 +# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11223 +# The full GNU General Public License is included in this distribution in
11224 +# the file called "COPYING".
11226 +# Contact Information:
11227 +# Linux NICS <linux.nics@intel.com>
11228 +# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11229 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11231 +################################################################################
11234 +# Makefile for the Intel(R) PRO/1000 ethernet driver
11237 +obj-$(CONFIG_E1000E) += e1000e.o
11239 +e1000e-objs := 82571.o ich8lan.o es2lan.o \
11240 + lib.o phy.o param.o ethtool.o netdev.o
11242 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/netdev.c linux-2.6.22-10/drivers/net/e1000e/netdev.c
11243 --- linux-2.6.22-0/drivers/net/e1000e/netdev.c 1969-12-31 19:00:00.000000000 -0500
11244 +++ linux-2.6.22-10/drivers/net/e1000e/netdev.c 2007-11-21 13:55:34.000000000 -0500
11246 +/*******************************************************************************
11248 + Intel PRO/1000 Linux driver
11249 + Copyright(c) 1999 - 2007 Intel Corporation.
11251 + This program is free software; you can redistribute it and/or modify it
11252 + under the terms and conditions of the GNU General Public License,
11253 + version 2, as published by the Free Software Foundation.
11255 + This program is distributed in the hope it will be useful, but WITHOUT
11256 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11257 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11260 + You should have received a copy of the GNU General Public License along with
11261 + this program; if not, write to the Free Software Foundation, Inc.,
11262 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11264 + The full GNU General Public License is included in this distribution in
11265 + the file called "COPYING".
11267 + Contact Information:
11268 + Linux NICS <linux.nics@intel.com>
11269 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11270 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11272 +*******************************************************************************/
11274 +#include <linux/module.h>
11275 +#include <linux/types.h>
11276 +#include <linux/init.h>
11277 +#include <linux/pci.h>
11278 +#include <linux/vmalloc.h>
11279 +#include <linux/pagemap.h>
11280 +#include <linux/delay.h>
11281 +#include <linux/netdevice.h>
11282 +#include <linux/tcp.h>
11283 +#include <linux/ipv6.h>
11284 +#include <net/checksum.h>
11285 +#include <net/ip6_checksum.h>
11286 +#include <linux/mii.h>
11287 +#include <linux/ethtool.h>
11288 +#include <linux/if_vlan.h>
11289 +#include <linux/cpu.h>
11290 +#include <linux/smp.h>
11292 +#include "e1000.h"
11294 +#define DRV_VERSION "0.2.0"
11295 +char e1000e_driver_name[] = "e1000e";
11296 +const char e1000e_driver_version[] = DRV_VERSION;
11298 +static const struct e1000_info *e1000_info_tbl[] = {
11299 + [board_82571] = &e1000_82571_info,
11300 + [board_82572] = &e1000_82572_info,
11301 + [board_82573] = &e1000_82573_info,
11302 + [board_80003es2lan] = &e1000_es2_info,
11303 + [board_ich8lan] = &e1000_ich8_info,
11304 + [board_ich9lan] = &e1000_ich9_info,
11309 + * e1000_get_hw_dev_name - return device name string
11310 + * used by hardware layer to print debugging information
11312 +char *e1000e_get_hw_dev_name(struct e1000_hw *hw)
11314 + struct e1000_adapter *adapter = hw->back;
11315 + struct net_device *netdev = adapter->netdev;
11316 + return netdev->name;
11321 + * e1000_desc_unused - calculate if we have unused descriptors
11323 +static int e1000_desc_unused(struct e1000_ring *ring)
11325 + if (ring->next_to_clean > ring->next_to_use)
11326 + return ring->next_to_clean - ring->next_to_use - 1;
11328 + return ring->count + ring->next_to_clean - ring->next_to_use - 1;
11332 + * e1000_receive_skb - helper function to handle rx indications
11333 + * @adapter: board private structure
11334 + * @status: descriptor status field as written by hardware
11335 + * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
11336 + * @skb: pointer to sk_buff to be indicated to stack
11338 +static void e1000_receive_skb(struct e1000_adapter *adapter,
11339 + struct net_device *netdev,
11340 + struct sk_buff *skb,
11341 + u8 status, u16 vlan)
11343 + skb->protocol = eth_type_trans(skb, netdev);
11345 + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
11346 + vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
11347 + le16_to_cpu(vlan) &
11348 + E1000_RXD_SPC_VLAN_MASK);
11350 + netif_receive_skb(skb);
11352 + netdev->last_rx = jiffies;
11356 + * e1000_rx_checksum - Receive Checksum Offload for 82543
11357 + * @adapter: board private structure
11358 + * @status_err: receive descriptor status and error fields
11359 + * @csum: receive descriptor csum field
11360 + * @sk_buff: socket buffer with received data
11362 +static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
11363 + u32 csum, struct sk_buff *skb)
11365 + u16 status = (u16)status_err;
11366 + u8 errors = (u8)(status_err >> 24);
11367 + skb->ip_summed = CHECKSUM_NONE;
11369 + /* Ignore Checksum bit is set */
11370 + if (status & E1000_RXD_STAT_IXSM)
11372 + /* TCP/UDP checksum error bit is set */
11373 + if (errors & E1000_RXD_ERR_TCPE) {
11374 + /* let the stack verify checksum errors */
11375 + adapter->hw_csum_err++;
11379 + /* TCP/UDP Checksum has not been calculated */
11380 + if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
11383 + /* It must be a TCP or UDP packet with a valid checksum */
11384 + if (status & E1000_RXD_STAT_TCPCS) {
11385 + /* TCP checksum is good */
11386 + skb->ip_summed = CHECKSUM_UNNECESSARY;
11388 + /* IP fragment with UDP payload */
11389 + /* Hardware complements the payload checksum, so we undo it
11390 + * and then put the value in host order for further stack use.
11392 + csum = ntohl(csum ^ 0xFFFF);
11393 + skb->csum = csum;
11394 + skb->ip_summed = CHECKSUM_COMPLETE;
11396 + adapter->hw_csum_good++;
11400 + * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
11401 + * @adapter: address of board private structure
11403 +static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
11404 + int cleaned_count)
11406 + struct net_device *netdev = adapter->netdev;
11407 + struct pci_dev *pdev = adapter->pdev;
11408 + struct e1000_ring *rx_ring = adapter->rx_ring;
11409 + struct e1000_rx_desc *rx_desc;
11410 + struct e1000_buffer *buffer_info;
11411 + struct sk_buff *skb;
11413 + unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
11415 + i = rx_ring->next_to_use;
11416 + buffer_info = &rx_ring->buffer_info[i];
11418 + while (cleaned_count--) {
11419 + skb = buffer_info->skb;
11421 + skb_trim(skb, 0);
11425 + skb = netdev_alloc_skb(netdev, bufsz);
11427 + /* Better luck next round */
11428 + adapter->alloc_rx_buff_failed++;
11432 + /* Make buffer alignment 2 beyond a 16 byte boundary
11433 + * this will result in a 16 byte aligned IP header after
11434 + * the 14 byte MAC header is removed
11436 + skb_reserve(skb, NET_IP_ALIGN);
11438 + buffer_info->skb = skb;
11440 + buffer_info->dma = pci_map_single(pdev, skb->data,
11441 + adapter->rx_buffer_len,
11442 + PCI_DMA_FROMDEVICE);
11443 + if (pci_dma_mapping_error(buffer_info->dma)) {
11444 + dev_err(&pdev->dev, "RX DMA map failed\n");
11445 + adapter->rx_dma_failed++;
11449 + rx_desc = E1000_RX_DESC(*rx_ring, i);
11450 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
11453 + if (i == rx_ring->count)
11455 + buffer_info = &rx_ring->buffer_info[i];
11458 + if (rx_ring->next_to_use != i) {
11459 + rx_ring->next_to_use = i;
11461 + i = (rx_ring->count - 1);
11463 + /* Force memory writes to complete before letting h/w
11464 + * know there are new descriptors to fetch. (Only
11465 + * applicable for weak-ordered memory model archs,
11466 + * such as IA-64). */
11468 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
11473 + * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
11474 + * @adapter: address of board private structure
11476 +static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
11477 + int cleaned_count)
11479 + struct net_device *netdev = adapter->netdev;
11480 + struct pci_dev *pdev = adapter->pdev;
11481 + union e1000_rx_desc_packet_split *rx_desc;
11482 + struct e1000_ring *rx_ring = adapter->rx_ring;
11483 + struct e1000_buffer *buffer_info;
11484 + struct e1000_ps_page *ps_page;
11485 + struct sk_buff *skb;
11486 + unsigned int i, j;
11488 + i = rx_ring->next_to_use;
11489 + buffer_info = &rx_ring->buffer_info[i];
11491 + while (cleaned_count--) {
11492 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
11494 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
11495 + ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS)
11497 + if (j < adapter->rx_ps_pages) {
11498 + if (!ps_page->page) {
11499 + ps_page->page = alloc_page(GFP_ATOMIC);
11500 + if (!ps_page->page) {
11501 + adapter->alloc_rx_buff_failed++;
11504 + ps_page->dma = pci_map_page(pdev,
11507 + PCI_DMA_FROMDEVICE);
11508 + if (pci_dma_mapping_error(
11510 + dev_err(&adapter->pdev->dev,
11511 + "RX DMA page map failed\n");
11512 + adapter->rx_dma_failed++;
11517 + * Refresh the desc even if buffer_addrs
11518 + * didn't change because each write-back
11519 + * erases this info.
11521 + rx_desc->read.buffer_addr[j+1] =
11522 + cpu_to_le64(ps_page->dma);
11524 + rx_desc->read.buffer_addr[j+1] = ~0;
11528 + skb = netdev_alloc_skb(netdev,
11529 + adapter->rx_ps_bsize0 + NET_IP_ALIGN);
11532 + adapter->alloc_rx_buff_failed++;
11536 + /* Make buffer alignment 2 beyond a 16 byte boundary
11537 + * this will result in a 16 byte aligned IP header after
11538 + * the 14 byte MAC header is removed
11540 + skb_reserve(skb, NET_IP_ALIGN);
11542 + buffer_info->skb = skb;
11543 + buffer_info->dma = pci_map_single(pdev, skb->data,
11544 + adapter->rx_ps_bsize0,
11545 + PCI_DMA_FROMDEVICE);
11546 + if (pci_dma_mapping_error(buffer_info->dma)) {
11547 + dev_err(&pdev->dev, "RX DMA map failed\n");
11548 + adapter->rx_dma_failed++;
11549 + /* cleanup skb */
11550 + dev_kfree_skb_any(skb);
11551 + buffer_info->skb = NULL;
11555 + rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
11558 + if (i == rx_ring->count)
11560 + buffer_info = &rx_ring->buffer_info[i];
11564 + if (rx_ring->next_to_use != i) {
11565 + rx_ring->next_to_use = i;
11568 + i = (rx_ring->count - 1);
11570 + /* Force memory writes to complete before letting h/w
11571 + * know there are new descriptors to fetch. (Only
11572 + * applicable for weak-ordered memory model archs,
11573 + * such as IA-64). */
11575 + /* Hardware increments by 16 bytes, but packet split
11576 + * descriptors are 32 bytes...so we increment tail
11579 + writel(i<<1, adapter->hw.hw_addr + rx_ring->tail);
11584 + * e1000_alloc_rx_buffers_jumbo - Replace used jumbo receive buffers
11586 + * @adapter: address of board private structure
11587 + * @cleaned_count: number of buffers to allocate this pass
11589 +static void e1000_alloc_rx_buffers_jumbo(struct e1000_adapter *adapter,
11590 + int cleaned_count)
11592 + struct net_device *netdev = adapter->netdev;
11593 + struct pci_dev *pdev = adapter->pdev;
11594 + struct e1000_ring *rx_ring = adapter->rx_ring;
11595 + struct e1000_rx_desc *rx_desc;
11596 + struct e1000_buffer *buffer_info;
11597 + struct sk_buff *skb;
11599 + unsigned int bufsz = 256 -
11600 + 16 /*for skb_reserve */ -
11603 + i = rx_ring->next_to_use;
11604 + buffer_info = &rx_ring->buffer_info[i];
11606 + while (cleaned_count--) {
11607 + skb = buffer_info->skb;
11609 + skb_trim(skb, 0);
11613 + skb = netdev_alloc_skb(netdev, bufsz);
11615 + /* Better luck next round */
11616 + adapter->alloc_rx_buff_failed++;
11620 + /* Make buffer alignment 2 beyond a 16 byte boundary
11621 + * this will result in a 16 byte aligned IP header after
11622 + * the 14 byte MAC header is removed
11624 + skb_reserve(skb, NET_IP_ALIGN);
11626 + buffer_info->skb = skb;
11628 + /* allocate a new page if necessary */
11629 + if (!buffer_info->page) {
11630 + buffer_info->page = alloc_page(GFP_ATOMIC);
11631 + if (!buffer_info->page) {
11632 + adapter->alloc_rx_buff_failed++;
11637 + if (!buffer_info->dma)
11638 + buffer_info->dma = pci_map_page(pdev,
11639 + buffer_info->page, 0,
11641 + PCI_DMA_FROMDEVICE);
11642 + if (pci_dma_mapping_error(buffer_info->dma)) {
11643 + dev_err(&adapter->pdev->dev, "RX DMA page map failed\n");
11644 + adapter->rx_dma_failed++;
11648 + rx_desc = E1000_RX_DESC(*rx_ring, i);
11649 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
11652 + if (i == rx_ring->count)
11654 + buffer_info = &rx_ring->buffer_info[i];
11657 + if (rx_ring->next_to_use != i) {
11658 + rx_ring->next_to_use = i;
11660 + i = (rx_ring->count - 1);
11662 + /* Force memory writes to complete before letting h/w
11663 + * know there are new descriptors to fetch. (Only
11664 + * applicable for weak-ordered memory model archs,
11665 + * such as IA-64). */
11667 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
11672 + * e1000_clean_rx_irq - Send received data up the network stack; legacy
11673 + * @adapter: board private structure
11675 + * the return value indicates whether actual cleaning was done, there
11676 + * is no guarantee that everything was cleaned
11678 +static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
11679 + int *work_done, int work_to_do)
11681 + struct net_device *netdev = adapter->netdev;
11682 + struct pci_dev *pdev = adapter->pdev;
11683 + struct e1000_ring *rx_ring = adapter->rx_ring;
11684 + struct e1000_rx_desc *rx_desc, *next_rxd;
11685 + struct e1000_buffer *buffer_info, *next_buffer;
11688 + int cleaned_count = 0;
11689 + bool cleaned = 0;
11690 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
11692 + i = rx_ring->next_to_clean;
11693 + rx_desc = E1000_RX_DESC(*rx_ring, i);
11694 + buffer_info = &rx_ring->buffer_info[i];
11696 + while (rx_desc->status & E1000_RXD_STAT_DD) {
11697 + struct sk_buff *skb;
11700 + if (*work_done >= work_to_do)
11704 + status = rx_desc->status;
11705 + skb = buffer_info->skb;
11706 + buffer_info->skb = NULL;
11708 + prefetch(skb->data - NET_IP_ALIGN);
11711 + if (i == rx_ring->count)
11713 + next_rxd = E1000_RX_DESC(*rx_ring, i);
11714 + prefetch(next_rxd);
11716 + next_buffer = &rx_ring->buffer_info[i];
11720 + pci_unmap_single(pdev,
11721 + buffer_info->dma,
11722 + adapter->rx_buffer_len,
11723 + PCI_DMA_FROMDEVICE);
11724 + buffer_info->dma = 0;
11726 + length = le16_to_cpu(rx_desc->length);
11728 + /* !EOP means multiple descriptors were used to store a single
11729 + * packet, also make sure the frame isn't just CRC only */
11730 + if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) {
11731 + /* All receives must fit into a single buffer */
11732 + ndev_dbg(netdev, "%s: Receive packet consumed "
11733 + "multiple buffers\n", netdev->name);
11735 + buffer_info->skb = skb;
11739 + if (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
11741 + buffer_info->skb = skb;
11745 + /* adjust length to remove Ethernet CRC */
11748 + /* probably a little skewed due to removing CRC */
11749 + total_rx_bytes += length;
11750 + total_rx_packets++;
11752 + /* code added for copybreak, this should improve
11753 + * performance for small packets with large amounts
11754 + * of reassembly being done in the stack */
11755 + if (length < copybreak) {
11756 + struct sk_buff *new_skb =
11757 + netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
11759 + skb_reserve(new_skb, NET_IP_ALIGN);
11760 + memcpy(new_skb->data - NET_IP_ALIGN,
11761 + skb->data - NET_IP_ALIGN,
11762 + length + NET_IP_ALIGN);
11763 + /* save the skb in buffer_info as good */
11764 + buffer_info->skb = skb;
11767 + /* else just continue with the old one */
11769 + /* end copybreak code */
11770 + skb_put(skb, length);
11772 + /* Receive Checksum Offload */
11773 + e1000_rx_checksum(adapter,
11775 + ((u32)(rx_desc->errors) << 24),
11776 + le16_to_cpu(rx_desc->csum), skb);
11778 + e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special);
11781 + rx_desc->status = 0;
11783 + /* return some buffers to hardware, one at a time is too slow */
11784 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
11785 + adapter->alloc_rx_buf(adapter, cleaned_count);
11786 + cleaned_count = 0;
11789 + /* use prefetched values */
11790 + rx_desc = next_rxd;
11791 + buffer_info = next_buffer;
11793 + rx_ring->next_to_clean = i;
11795 + cleaned_count = e1000_desc_unused(rx_ring);
11796 + if (cleaned_count)
11797 + adapter->alloc_rx_buf(adapter, cleaned_count);
11799 + adapter->total_rx_packets += total_rx_packets;
11800 + adapter->total_rx_bytes += total_rx_bytes;
11804 +static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
11808 + skb->len += length;
11809 + skb->data_len += length;
11810 + skb->truesize += length;
11813 +static void e1000_put_txbuf(struct e1000_adapter *adapter,
11814 + struct e1000_buffer *buffer_info)
11816 + if (buffer_info->dma) {
11817 + pci_unmap_page(adapter->pdev, buffer_info->dma,
11818 + buffer_info->length, PCI_DMA_TODEVICE);
11819 + buffer_info->dma = 0;
11821 + if (buffer_info->skb) {
11822 + dev_kfree_skb_any(buffer_info->skb);
11823 + buffer_info->skb = NULL;
11827 +static void e1000_print_tx_hang(struct e1000_adapter *adapter)
11829 + struct e1000_ring *tx_ring = adapter->tx_ring;
11830 + unsigned int i = tx_ring->next_to_clean;
11831 + unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
11832 + struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
11833 + struct net_device *netdev = adapter->netdev;
11835 + /* detected Tx unit hang */
11837 + "Detected Tx Unit Hang:\n"
11840 + " next_to_use <%x>\n"
11841 + " next_to_clean <%x>\n"
11842 + "buffer_info[next_to_clean]:\n"
11843 + " time_stamp <%lx>\n"
11844 + " next_to_watch <%x>\n"
11845 + " jiffies <%lx>\n"
11846 + " next_to_watch.status <%x>\n",
11847 + readl(adapter->hw.hw_addr + tx_ring->head),
11848 + readl(adapter->hw.hw_addr + tx_ring->tail),
11849 + tx_ring->next_to_use,
11850 + tx_ring->next_to_clean,
11851 + tx_ring->buffer_info[eop].time_stamp,
11854 + eop_desc->upper.fields.status);
11858 + * e1000_clean_tx_irq - Reclaim resources after transmit completes
11859 + * @adapter: board private structure
11861 + * the return value indicates whether actual cleaning was done, there
11862 + * is no guarantee that everything was cleaned
11864 +static bool e1000_clean_tx_irq(struct e1000_adapter *adapter)
11866 + struct net_device *netdev = adapter->netdev;
11867 + struct e1000_hw *hw = &adapter->hw;
11868 + struct e1000_ring *tx_ring = adapter->tx_ring;
11869 + struct e1000_tx_desc *tx_desc, *eop_desc;
11870 + struct e1000_buffer *buffer_info;
11871 + unsigned int i, eop;
11872 + unsigned int count = 0;
11873 + bool cleaned = 0;
11874 + unsigned int total_tx_bytes = 0, total_tx_packets = 0;
11876 + i = tx_ring->next_to_clean;
11877 + eop = tx_ring->buffer_info[i].next_to_watch;
11878 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
11880 + while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
11881 + for (cleaned = 0; !cleaned; ) {
11882 + tx_desc = E1000_TX_DESC(*tx_ring, i);
11883 + buffer_info = &tx_ring->buffer_info[i];
11884 + cleaned = (i == eop);
11887 + struct sk_buff *skb = buffer_info->skb;
11888 + unsigned int segs, bytecount;
11889 + segs = skb_shinfo(skb)->gso_segs ?: 1;
11890 + /* multiply data chunks by size of headers */
11891 + bytecount = ((segs - 1) * skb_headlen(skb)) +
11893 + total_tx_packets += segs;
11894 + total_tx_bytes += bytecount;
11897 + e1000_put_txbuf(adapter, buffer_info);
11898 + tx_desc->upper.data = 0;
11901 + if (i == tx_ring->count)
11905 + eop = tx_ring->buffer_info[i].next_to_watch;
11906 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
11907 +#define E1000_TX_WEIGHT 64
11908 + /* weight of a sort for tx, to avoid endless transmit cleanup */
11909 + if (count++ == E1000_TX_WEIGHT)
11913 + tx_ring->next_to_clean = i;
11915 +#define TX_WAKE_THRESHOLD 32
11916 + if (cleaned && netif_carrier_ok(netdev) &&
11917 + e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
11918 + /* Make sure that anybody stopping the queue after this
11919 + * sees the new next_to_clean.
11923 + if (netif_queue_stopped(netdev) &&
11924 + !(test_bit(__E1000_DOWN, &adapter->state))) {
11925 + netif_wake_queue(netdev);
11926 + ++adapter->restart_queue;
11930 + if (adapter->detect_tx_hung) {
11931 + /* Detect a transmit hang in hardware, this serializes the
11932 + * check with the clearing of time_stamp and movement of i */
11933 + adapter->detect_tx_hung = 0;
11934 + if (tx_ring->buffer_info[eop].dma &&
11935 + time_after(jiffies, tx_ring->buffer_info[eop].time_stamp
11936 + + (adapter->tx_timeout_factor * HZ))
11937 + && !(er32(STATUS) &
11938 + E1000_STATUS_TXOFF)) {
11939 + e1000_print_tx_hang(adapter);
11940 + netif_stop_queue(netdev);
11943 + adapter->total_tx_bytes += total_tx_bytes;
11944 + adapter->total_tx_packets += total_tx_packets;
11949 + * e1000_clean_rx_irq_jumbo - Send received data up the network stack; legacy
11950 + * @adapter: board private structure
11952 + * the return value indicates whether actual cleaning was done, there
11953 + * is no guarantee that everything was cleaned
11955 +static bool e1000_clean_rx_irq_jumbo(struct e1000_adapter *adapter,
11956 + int *work_done, int work_to_do)
11958 + struct net_device *netdev = adapter->netdev;
11959 + struct pci_dev *pdev = adapter->pdev;
11960 + struct e1000_ring *rx_ring = adapter->rx_ring;
11961 + struct e1000_rx_desc *rx_desc, *next_rxd;
11962 + struct e1000_buffer *buffer_info, *next_buffer;
11965 + int cleaned_count = 0;
11966 + bool cleaned = 0;
11967 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
11969 + i = rx_ring->next_to_clean;
11970 + rx_desc = E1000_RX_DESC(*rx_ring, i);
11971 + buffer_info = &rx_ring->buffer_info[i];
11973 + while (rx_desc->status & E1000_RXD_STAT_DD) {
11974 + struct sk_buff *skb;
11977 + if (*work_done >= work_to_do)
11981 + status = rx_desc->status;
11982 + skb = buffer_info->skb;
11983 + buffer_info->skb = NULL;
11986 + if (i == rx_ring->count)
11988 + next_rxd = E1000_RX_DESC(*rx_ring, i);
11989 + prefetch(next_rxd);
11991 + next_buffer = &rx_ring->buffer_info[i];
11995 + pci_unmap_page(pdev,
11996 + buffer_info->dma,
11998 + PCI_DMA_FROMDEVICE);
11999 + buffer_info->dma = 0;
12001 + length = le16_to_cpu(rx_desc->length);
12003 + /* errors is only valid for DD + EOP descriptors */
12004 + if ((status & E1000_RXD_STAT_EOP) &&
12005 + (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
12006 + /* recycle both page and skb */
12007 + buffer_info->skb = skb;
12008 + /* an error means any chain goes out the window too */
12009 + if (rx_ring->rx_skb_top)
12010 + dev_kfree_skb(rx_ring->rx_skb_top);
12011 + rx_ring->rx_skb_top = NULL;
12015 +#define rxtop rx_ring->rx_skb_top
12016 + if (!(status & E1000_RXD_STAT_EOP)) {
12017 + /* this descriptor is only the beginning (or middle) */
12019 + /* this is the beginning of a chain */
12021 + skb_fill_page_desc(rxtop, 0, buffer_info->page,
12024 + /* this is the middle of a chain */
12025 + skb_fill_page_desc(rxtop,
12026 + skb_shinfo(rxtop)->nr_frags,
12027 + buffer_info->page, 0,
12029 + /* re-use the skb, only consumed the page */
12030 + buffer_info->skb = skb;
12032 + e1000_consume_page(buffer_info, rxtop, length);
12036 + /* end of the chain */
12037 + skb_fill_page_desc(rxtop,
12038 + skb_shinfo(rxtop)->nr_frags,
12039 + buffer_info->page, 0, length);
12040 + /* re-use the current skb, we only consumed the
12042 + buffer_info->skb = skb;
12045 + e1000_consume_page(buffer_info, skb, length);
12047 + /* no chain, got EOP, this buf is the packet
12048 + * copybreak to save the put_page/alloc_page */
12049 + if (length <= copybreak &&
12050 + skb_tailroom(skb) >= length) {
12052 + vaddr = kmap_atomic(buffer_info->page,
12053 + KM_SKB_DATA_SOFTIRQ);
12054 + memcpy(skb_tail_pointer(skb),
12056 + kunmap_atomic(vaddr,
12057 + KM_SKB_DATA_SOFTIRQ);
12058 + /* re-use the page, so don't erase
12059 + * buffer_info->page */
12060 + skb_put(skb, length);
12062 + skb_fill_page_desc(skb, 0,
12063 + buffer_info->page, 0,
12065 + e1000_consume_page(buffer_info, skb,
12071 + /* Receive Checksum Offload XXX recompute due to CRC strip? */
12072 + e1000_rx_checksum(adapter,
12074 + ((u32)(rx_desc->errors) << 24),
12075 + le16_to_cpu(rx_desc->csum), skb);
12077 + pskb_trim(skb, skb->len - 4);
12079 + /* probably a little skewed due to removing CRC */
12080 + total_rx_bytes += skb->len;
12081 + total_rx_packets++;
12083 + /* eth type trans needs skb->data to point to something */
12084 + if (!pskb_may_pull(skb, ETH_HLEN)) {
12085 + ndev_err(netdev, "__pskb_pull_tail failed.\n");
12086 + dev_kfree_skb(skb);
12090 + e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special);
12093 + rx_desc->status = 0;
12095 + /* return some buffers to hardware, one at a time is too slow */
12096 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
12097 + adapter->alloc_rx_buf(adapter, cleaned_count);
12098 + cleaned_count = 0;
12101 + /* use prefetched values */
12102 + rx_desc = next_rxd;
12103 + buffer_info = next_buffer;
12105 + rx_ring->next_to_clean = i;
12107 + cleaned_count = e1000_desc_unused(rx_ring);
12108 + if (cleaned_count)
12109 + adapter->alloc_rx_buf(adapter, cleaned_count);
12111 + adapter->total_rx_packets += total_rx_packets;
12112 + adapter->total_rx_bytes += total_rx_bytes;
12117 + * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
12118 + * @adapter: board private structure
12120 + * the return value indicates whether actual cleaning was done, there
12121 + * is no guarantee that everything was cleaned
12123 +static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
12124 + int *work_done, int work_to_do)
12126 + union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
12127 + struct net_device *netdev = adapter->netdev;
12128 + struct pci_dev *pdev = adapter->pdev;
12129 + struct e1000_ring *rx_ring = adapter->rx_ring;
12130 + struct e1000_buffer *buffer_info, *next_buffer;
12131 + struct e1000_ps_page *ps_page;
12132 + struct sk_buff *skb;
12133 + unsigned int i, j;
12134 + u32 length, staterr;
12135 + int cleaned_count = 0;
12136 + bool cleaned = 0;
12137 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
12139 + i = rx_ring->next_to_clean;
12140 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
12141 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
12142 + buffer_info = &rx_ring->buffer_info[i];
12144 + while (staterr & E1000_RXD_STAT_DD) {
12145 + if (*work_done >= work_to_do)
12148 + skb = buffer_info->skb;
12150 + /* in the packet split case this is header only */
12151 + prefetch(skb->data - NET_IP_ALIGN);
12154 + if (i == rx_ring->count)
12156 + next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
12157 + prefetch(next_rxd);
12159 + next_buffer = &rx_ring->buffer_info[i];
12163 + pci_unmap_single(pdev, buffer_info->dma,
12164 + adapter->rx_ps_bsize0,
12165 + PCI_DMA_FROMDEVICE);
12166 + buffer_info->dma = 0;
12168 + if (!(staterr & E1000_RXD_STAT_EOP)) {
12169 + ndev_dbg(netdev, "%s: Packet Split buffers didn't pick "
12170 + "up the full packet\n", netdev->name);
12171 + dev_kfree_skb_irq(skb);
12175 + if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
12176 + dev_kfree_skb_irq(skb);
12180 + length = le16_to_cpu(rx_desc->wb.middle.length0);
12183 + ndev_dbg(netdev, "%s: Last part of the packet spanning"
12184 + " multiple descriptors\n", netdev->name);
12185 + dev_kfree_skb_irq(skb);
12189 + /* Good Receive */
12190 + skb_put(skb, length);
12193 + /* this looks ugly, but it seems compiler issues make it
12194 + more efficient than reusing j */
12195 + int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
12197 + /* page alloc/put takes too long and effects small packet
12198 + * throughput, so unsplit small packets and save the alloc/put*/
12199 + if (l1 && (l1 <= copybreak) &&
12200 + ((length + l1) <= adapter->rx_ps_bsize0)) {
12203 + ps_page = &rx_ring->ps_pages[i * PS_PAGE_BUFFERS];
12205 + /* there is no documentation about how to call
12206 + * kmap_atomic, so we can't hold the mapping
12208 + pci_dma_sync_single_for_cpu(pdev, ps_page->dma,
12209 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
12210 + vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
12211 + memcpy(skb_tail_pointer(skb), vaddr, l1);
12212 + kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
12213 + pci_dma_sync_single_for_device(pdev, ps_page->dma,
12214 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
12215 + /* remove the CRC */
12217 + skb_put(skb, l1);
12222 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
12223 + length = le16_to_cpu(rx_desc->wb.upper.length[j]);
12227 + ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS) + j];
12228 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
12229 + PCI_DMA_FROMDEVICE);
12230 + ps_page->dma = 0;
12231 + skb_fill_page_desc(skb, j, ps_page->page, 0, length);
12232 + ps_page->page = NULL;
12233 + skb->len += length;
12234 + skb->data_len += length;
12235 + skb->truesize += length;
12238 + /* strip the ethernet crc, problem is we're using pages now so
12239 + * this whole operation can get a little cpu intensive */
12240 + pskb_trim(skb, skb->len - 4);
12243 + total_rx_bytes += skb->len;
12244 + total_rx_packets++;
12246 + e1000_rx_checksum(adapter, staterr, le16_to_cpu(
12247 + rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
12249 + if (rx_desc->wb.upper.header_status &
12250 + cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
12251 + adapter->rx_hdr_split++;
12253 + e1000_receive_skb(adapter, netdev, skb,
12254 + staterr, rx_desc->wb.middle.vlan);
12257 + rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
12258 + buffer_info->skb = NULL;
12260 + /* return some buffers to hardware, one at a time is too slow */
12261 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
12262 + adapter->alloc_rx_buf(adapter, cleaned_count);
12263 + cleaned_count = 0;
12266 + /* use prefetched values */
12267 + rx_desc = next_rxd;
12268 + buffer_info = next_buffer;
12270 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
12272 + rx_ring->next_to_clean = i;
12274 + cleaned_count = e1000_desc_unused(rx_ring);
12275 + if (cleaned_count)
12276 + adapter->alloc_rx_buf(adapter, cleaned_count);
12278 + adapter->total_rx_packets += total_rx_packets;
12279 + adapter->total_rx_bytes += total_rx_bytes;
12284 + * e1000_clean_rx_ring - Free Rx Buffers per Queue
12285 + * @adapter: board private structure
12287 +static void e1000_clean_rx_ring(struct e1000_adapter *adapter)
12289 + struct e1000_ring *rx_ring = adapter->rx_ring;
12290 + struct e1000_buffer *buffer_info;
12291 + struct e1000_ps_page *ps_page;
12292 + struct pci_dev *pdev = adapter->pdev;
12293 + unsigned long size;
12294 + unsigned int i, j;
12296 + /* Free all the Rx ring sk_buffs */
12297 + for (i = 0; i < rx_ring->count; i++) {
12298 + buffer_info = &rx_ring->buffer_info[i];
12299 + if (buffer_info->dma) {
12300 + if (adapter->clean_rx == e1000_clean_rx_irq)
12301 + pci_unmap_single(pdev, buffer_info->dma,
12302 + adapter->rx_buffer_len,
12303 + PCI_DMA_FROMDEVICE);
12304 + else if (adapter->clean_rx == e1000_clean_rx_irq_jumbo)
12305 + pci_unmap_page(pdev, buffer_info->dma,
12306 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
12307 + else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
12308 + pci_unmap_single(pdev, buffer_info->dma,
12309 + adapter->rx_ps_bsize0,
12310 + PCI_DMA_FROMDEVICE);
12311 + buffer_info->dma = 0;
12314 + if (buffer_info->page) {
12315 + put_page(buffer_info->page);
12316 + buffer_info->page = NULL;
12319 + if (buffer_info->skb) {
12320 + dev_kfree_skb(buffer_info->skb);
12321 + buffer_info->skb = NULL;
12324 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
12325 + ps_page = &rx_ring->ps_pages[(i * PS_PAGE_BUFFERS)
12327 + if (!ps_page->page)
12329 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
12330 + PCI_DMA_FROMDEVICE);
12331 + ps_page->dma = 0;
12332 + put_page(ps_page->page);
12333 + ps_page->page = NULL;
12337 + /* there also may be some cached data from a chained receive */
12338 + if (rx_ring->rx_skb_top) {
12339 + dev_kfree_skb(rx_ring->rx_skb_top);
12340 + rx_ring->rx_skb_top = NULL;
12343 + size = sizeof(struct e1000_buffer) * rx_ring->count;
12344 + memset(rx_ring->buffer_info, 0, size);
12345 + size = sizeof(struct e1000_ps_page)
12346 + * (rx_ring->count * PS_PAGE_BUFFERS);
12347 + memset(rx_ring->ps_pages, 0, size);
12349 + /* Zero out the descriptor ring */
12350 + memset(rx_ring->desc, 0, rx_ring->size);
12352 + rx_ring->next_to_clean = 0;
12353 + rx_ring->next_to_use = 0;
12355 + writel(0, adapter->hw.hw_addr + rx_ring->head);
12356 + writel(0, adapter->hw.hw_addr + rx_ring->tail);
12360 + * e1000_intr_msi - Interrupt Handler
12361 + * @irq: interrupt number
12362 + * @data: pointer to a network interface device structure
12364 +static irqreturn_t e1000_intr_msi(int irq, void *data)
12366 + struct net_device *netdev = data;
12367 + struct e1000_adapter *adapter = netdev_priv(netdev);
12368 + struct e1000_hw *hw = &adapter->hw;
12369 + u32 icr = er32(ICR);
12371 + /* read ICR disables interrupts using IAM, so keep up with our
12372 + * enable/disable accounting */
12373 + atomic_inc(&adapter->irq_sem);
12375 + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
12376 + hw->mac.get_link_status = 1;
12377 + /* ICH8 workaround-- Call gig speed drop workaround on cable
12378 + * disconnect (LSC) before accessing any PHY registers */
12379 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
12380 + (!(er32(STATUS) & E1000_STATUS_LU)))
12381 + e1000e_gig_downshift_workaround_ich8lan(hw);
12383 + /* 80003ES2LAN workaround-- For packet buffer work-around on
12384 + * link down event; disable receives here in the ISR and reset
12385 + * adapter in watchdog */
12386 + if (netif_carrier_ok(netdev) &&
12387 + adapter->flags & FLAG_RX_NEEDS_RESTART) {
12388 + /* disable receives */
12389 + u32 rctl = er32(RCTL);
12390 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
12392 + /* guard against interrupt when we're going down */
12393 + if (!test_bit(__E1000_DOWN, &adapter->state))
12394 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
12397 + if (netif_rx_schedule_prep(netdev)) {
12398 + adapter->total_tx_bytes = 0;
12399 + adapter->total_tx_packets = 0;
12400 + adapter->total_rx_bytes = 0;
12401 + adapter->total_rx_packets = 0;
12402 + __netif_rx_schedule(netdev);
12404 + atomic_dec(&adapter->irq_sem);
12407 + return IRQ_HANDLED;
12411 + * e1000_intr - Interrupt Handler
12412 + * @irq: interrupt number
12413 + * @data: pointer to a network interface device structure
12415 +static irqreturn_t e1000_intr(int irq, void *data)
12417 + struct net_device *netdev = data;
12418 + struct e1000_adapter *adapter = netdev_priv(netdev);
12419 + struct e1000_hw *hw = &adapter->hw;
12421 + u32 rctl, icr = er32(ICR);
12423 + return IRQ_NONE; /* Not our interrupt */
12425 + /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
12426 + * not set, then the adapter didn't send an interrupt */
12427 + if (!(icr & E1000_ICR_INT_ASSERTED))
12430 + /* Interrupt Auto-Mask...upon reading ICR,
12431 + * interrupts are masked. No need for the
12432 + * IMC write, but it does mean we should
12433 + * account for it ASAP. */
12434 + atomic_inc(&adapter->irq_sem);
12436 + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
12437 + hw->mac.get_link_status = 1;
12438 + /* ICH8 workaround-- Call gig speed drop workaround on cable
12439 + * disconnect (LSC) before accessing any PHY registers */
12440 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
12441 + (!(er32(STATUS) & E1000_STATUS_LU)))
12442 + e1000e_gig_downshift_workaround_ich8lan(hw);
12444 + /* 80003ES2LAN workaround--
12445 + * For packet buffer work-around on link down event;
12446 + * disable receives here in the ISR and
12447 + * reset adapter in watchdog
12449 + if (netif_carrier_ok(netdev) &&
12450 + (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
12451 + /* disable receives */
12452 + rctl = er32(RCTL);
12453 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
12455 + /* guard against interrupt when we're going down */
12456 + if (!test_bit(__E1000_DOWN, &adapter->state))
12457 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
12460 + if (netif_rx_schedule_prep(netdev)) {
12461 + adapter->total_tx_bytes = 0;
12462 + adapter->total_tx_packets = 0;
12463 + adapter->total_rx_bytes = 0;
12464 + adapter->total_rx_packets = 0;
12465 + __netif_rx_schedule(netdev);
12467 + atomic_dec(&adapter->irq_sem);
12470 + return IRQ_HANDLED;
12473 +static int e1000_request_irq(struct e1000_adapter *adapter)
12475 + struct net_device *netdev = adapter->netdev;
12476 + void (*handler) = &e1000_intr;
12477 + int irq_flags = IRQF_SHARED;
12480 + err = pci_enable_msi(adapter->pdev);
12482 + ndev_warn(netdev,
12483 + "Unable to allocate MSI interrupt Error: %d\n", err);
12485 + adapter->flags |= FLAG_MSI_ENABLED;
12486 + handler = &e1000_intr_msi;
12490 + err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
12493 + if (adapter->flags & FLAG_MSI_ENABLED)
12494 + pci_disable_msi(adapter->pdev);
12496 + "Unable to allocate interrupt Error: %d\n", err);
12502 +static void e1000_free_irq(struct e1000_adapter *adapter)
12504 + struct net_device *netdev = adapter->netdev;
12506 + free_irq(adapter->pdev->irq, netdev);
12507 + if (adapter->flags & FLAG_MSI_ENABLED) {
12508 + pci_disable_msi(adapter->pdev);
12509 + adapter->flags &= ~FLAG_MSI_ENABLED;
12514 + * e1000_irq_disable - Mask off interrupt generation on the NIC
12516 +static void e1000_irq_disable(struct e1000_adapter *adapter)
12518 + struct e1000_hw *hw = &adapter->hw;
12520 + atomic_inc(&adapter->irq_sem);
12523 + synchronize_irq(adapter->pdev->irq);
12527 + * e1000_irq_enable - Enable default interrupt generation settings
12529 +static void e1000_irq_enable(struct e1000_adapter *adapter)
12531 + struct e1000_hw *hw = &adapter->hw;
12533 + if (atomic_dec_and_test(&adapter->irq_sem)) {
12534 + ew32(IMS, IMS_ENABLE_MASK);
12540 + * e1000_get_hw_control - get control of the h/w from f/w
12541 + * @adapter: address of board private structure
12543 + * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
12544 + * For ASF and Pass Through versions of f/w this means that
12545 + * the driver is loaded. For AMT version (only with 82573)
12546 + * of the f/w this means that the network i/f is open.
12548 +static void e1000_get_hw_control(struct e1000_adapter *adapter)
12550 + struct e1000_hw *hw = &adapter->hw;
12554 + /* Let firmware know the driver has taken over */
12555 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
12556 + swsm = er32(SWSM);
12557 + ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
12558 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
12559 + ctrl_ext = er32(CTRL_EXT);
12561 + ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
12566 + * e1000_release_hw_control - release control of the h/w to f/w
12567 + * @adapter: address of board private structure
12569 + * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
12570 + * For ASF and Pass Through versions of f/w this means that the
12571 + * driver is no longer loaded. For AMT version (only with 82573) i
12572 + * of the f/w this means that the network i/f is closed.
12575 +static void e1000_release_hw_control(struct e1000_adapter *adapter)
12577 + struct e1000_hw *hw = &adapter->hw;
12581 + /* Let firmware taken over control of h/w */
12582 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
12583 + swsm = er32(SWSM);
12584 + ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
12585 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
12586 + ctrl_ext = er32(CTRL_EXT);
12588 + ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
12592 +static void e1000_release_manageability(struct e1000_adapter *adapter)
12594 + if (adapter->flags & FLAG_MNG_PT_ENABLED) {
12595 + struct e1000_hw *hw = &adapter->hw;
12597 + u32 manc = er32(MANC);
12599 + /* re-enable hardware interception of ARP */
12600 + manc |= E1000_MANC_ARP_EN;
12601 + manc &= ~E1000_MANC_EN_MNG2HOST;
12603 + /* don't explicitly have to mess with MANC2H since
12604 + * MANC has an enable disable that gates MANC2H */
12605 + ew32(MANC, manc);
12610 + * @e1000_alloc_ring - allocate memory for a ring structure
12612 +static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
12613 + struct e1000_ring *ring)
12615 + struct pci_dev *pdev = adapter->pdev;
12617 + ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
12626 + * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
12627 + * @adapter: board private structure
12629 + * Return 0 on success, negative on failure
12631 +int e1000e_setup_tx_resources(struct e1000_adapter *adapter)
12633 + struct e1000_ring *tx_ring = adapter->tx_ring;
12634 + int err = -ENOMEM, size;
12636 + size = sizeof(struct e1000_buffer) * tx_ring->count;
12637 + tx_ring->buffer_info = vmalloc(size);
12638 + if (!tx_ring->buffer_info)
12640 + memset(tx_ring->buffer_info, 0, size);
12642 + /* round up to nearest 4K */
12643 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
12644 + tx_ring->size = ALIGN(tx_ring->size, 4096);
12646 + err = e1000_alloc_ring_dma(adapter, tx_ring);
12650 + tx_ring->next_to_use = 0;
12651 + tx_ring->next_to_clean = 0;
12652 + spin_lock_init(&adapter->tx_queue_lock);
12656 + vfree(tx_ring->buffer_info);
12657 + ndev_err(adapter->netdev,
12658 + "Unable to allocate memory for the transmit descriptor ring\n");
12663 + * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
12664 + * @adapter: board private structure
12666 + * Returns 0 on success, negative on failure
12668 +int e1000e_setup_rx_resources(struct e1000_adapter *adapter)
12670 + struct e1000_ring *rx_ring = adapter->rx_ring;
12671 + int size, desc_len, err = -ENOMEM;
12673 + size = sizeof(struct e1000_buffer) * rx_ring->count;
12674 + rx_ring->buffer_info = vmalloc(size);
12675 + if (!rx_ring->buffer_info)
12677 + memset(rx_ring->buffer_info, 0, size);
12679 + rx_ring->ps_pages = kcalloc(rx_ring->count * PS_PAGE_BUFFERS,
12680 + sizeof(struct e1000_ps_page),
12682 + if (!rx_ring->ps_pages)
12685 + desc_len = sizeof(union e1000_rx_desc_packet_split);
12687 + /* Round up to nearest 4K */
12688 + rx_ring->size = rx_ring->count * desc_len;
12689 + rx_ring->size = ALIGN(rx_ring->size, 4096);
12691 + err = e1000_alloc_ring_dma(adapter, rx_ring);
12695 + rx_ring->next_to_clean = 0;
12696 + rx_ring->next_to_use = 0;
12697 + rx_ring->rx_skb_top = NULL;
12701 + vfree(rx_ring->buffer_info);
12702 + kfree(rx_ring->ps_pages);
12703 + ndev_err(adapter->netdev,
12704 + "Unable to allocate memory for the transmit descriptor ring\n");
12709 + * e1000_clean_tx_ring - Free Tx Buffers
12710 + * @adapter: board private structure
12712 +static void e1000_clean_tx_ring(struct e1000_adapter *adapter)
12714 + struct e1000_ring *tx_ring = adapter->tx_ring;
12715 + struct e1000_buffer *buffer_info;
12716 + unsigned long size;
12719 + for (i = 0; i < tx_ring->count; i++) {
12720 + buffer_info = &tx_ring->buffer_info[i];
12721 + e1000_put_txbuf(adapter, buffer_info);
12724 + size = sizeof(struct e1000_buffer) * tx_ring->count;
12725 + memset(tx_ring->buffer_info, 0, size);
12727 + memset(tx_ring->desc, 0, tx_ring->size);
12729 + tx_ring->next_to_use = 0;
12730 + tx_ring->next_to_clean = 0;
12731 + tx_ring->last_tx_tso = 0;
12733 + writel(0, adapter->hw.hw_addr + tx_ring->head);
12734 + writel(0, adapter->hw.hw_addr + tx_ring->tail);
12738 + * e1000e_free_tx_resources - Free Tx Resources per Queue
12739 + * @adapter: board private structure
12741 + * Free all transmit software resources
12743 +void e1000e_free_tx_resources(struct e1000_adapter *adapter)
12745 + struct pci_dev *pdev = adapter->pdev;
12746 + struct e1000_ring *tx_ring = adapter->tx_ring;
12748 + e1000_clean_tx_ring(adapter);
12750 + vfree(tx_ring->buffer_info);
12751 + tx_ring->buffer_info = NULL;
12753 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
12755 + tx_ring->desc = NULL;
12759 + * e1000e_free_rx_resources - Free Rx Resources
12760 + * @adapter: board private structure
12762 + * Free all receive software resources
12765 +void e1000e_free_rx_resources(struct e1000_adapter *adapter)
12767 + struct pci_dev *pdev = adapter->pdev;
12768 + struct e1000_ring *rx_ring = adapter->rx_ring;
12770 + e1000_clean_rx_ring(adapter);
12772 + vfree(rx_ring->buffer_info);
12773 + rx_ring->buffer_info = NULL;
12775 + kfree(rx_ring->ps_pages);
12776 + rx_ring->ps_pages = NULL;
12778 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
12780 + rx_ring->desc = NULL;
12784 + * e1000_update_itr - update the dynamic ITR value based on statistics
12785 + * Stores a new ITR value based on packets and byte
12786 + * counts during the last interrupt. The advantage of per interrupt
12787 + * computation is faster updates and more accurate ITR for the current
12788 + * traffic pattern. Constants in this function were computed
12789 + * based on theoretical maximum wire speed and thresholds were set based
12790 + * on testing data as well as attempting to minimize response time
12791 + * while increasing bulk throughput.
12792 + * this functionality is controlled by the InterruptThrottleRate module
12793 + * parameter (see e1000_param.c)
12794 + * @adapter: pointer to adapter
12795 + * @itr_setting: current adapter->itr
12796 + * @packets: the number of packets during this measurement interval
12797 + * @bytes: the number of bytes during this measurement interval
12799 +static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
12800 + u16 itr_setting, int packets,
12803 + unsigned int retval = itr_setting;
12805 + if (packets == 0)
12806 + goto update_itr_done;
12808 + switch (itr_setting) {
12809 + case lowest_latency:
12810 + /* handle TSO and jumbo frames */
12811 + if (bytes/packets > 8000)
12812 + retval = bulk_latency;
12813 + else if ((packets < 5) && (bytes > 512)) {
12814 + retval = low_latency;
12817 + case low_latency: /* 50 usec aka 20000 ints/s */
12818 + if (bytes > 10000) {
12819 + /* this if handles the TSO accounting */
12820 + if (bytes/packets > 8000) {
12821 + retval = bulk_latency;
12822 + } else if ((packets < 10) || ((bytes/packets) > 1200)) {
12823 + retval = bulk_latency;
12824 + } else if ((packets > 35)) {
12825 + retval = lowest_latency;
12827 + } else if (bytes/packets > 2000) {
12828 + retval = bulk_latency;
12829 + } else if (packets <= 2 && bytes < 512) {
12830 + retval = lowest_latency;
12833 + case bulk_latency: /* 250 usec aka 4000 ints/s */
12834 + if (bytes > 25000) {
12835 + if (packets > 35) {
12836 + retval = low_latency;
12838 + } else if (bytes < 6000) {
12839 + retval = low_latency;
12848 +static void e1000_set_itr(struct e1000_adapter *adapter)
12850 + struct e1000_hw *hw = &adapter->hw;
12852 + u32 new_itr = adapter->itr;
12854 + /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
12855 + if (adapter->link_speed != SPEED_1000) {
12858 + goto set_itr_now;
12861 + adapter->tx_itr = e1000_update_itr(adapter,
12863 + adapter->total_tx_packets,
12864 + adapter->total_tx_bytes);
12865 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
12866 + if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
12867 + adapter->tx_itr = low_latency;
12869 + adapter->rx_itr = e1000_update_itr(adapter,
12871 + adapter->total_rx_packets,
12872 + adapter->total_rx_bytes);
12873 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
12874 + if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
12875 + adapter->rx_itr = low_latency;
12877 + current_itr = max(adapter->rx_itr, adapter->tx_itr);
12879 + switch (current_itr) {
12880 + /* counts and packets in update_itr are dependent on these numbers */
12881 + case lowest_latency:
12884 + case low_latency:
12885 + new_itr = 20000; /* aka hwitr = ~200 */
12887 + case bulk_latency:
12895 + if (new_itr != adapter->itr) {
12896 + /* this attempts to bias the interrupt rate towards Bulk
12897 + * by adding intermediate steps when interrupt rate is
12899 + new_itr = new_itr > adapter->itr ?
12900 + min(adapter->itr + (new_itr >> 2), new_itr) :
12902 + adapter->itr = new_itr;
12903 + ew32(ITR, 1000000000 / (new_itr * 256));
12908 + * e1000_clean - NAPI Rx polling callback
12909 + * @adapter: board private structure
12911 +static int e1000_clean(struct net_device *poll_dev, int *budget)
12913 + struct e1000_adapter *adapter;
12914 + int work_to_do = min(*budget, poll_dev->quota);
12915 + int tx_cleaned = 0, work_done = 0;
12917 + /* Must NOT use netdev_priv macro here. */
12918 + adapter = poll_dev->priv;
12920 + /* Keep link state information with original netdev */
12921 + if (!netif_carrier_ok(poll_dev))
12922 + goto quit_polling;
12924 + /* e1000_clean is called per-cpu. This lock protects
12925 + * tx_ring from being cleaned by multiple cpus
12926 + * simultaneously. A failure obtaining the lock means
12927 + * tx_ring is currently being cleaned anyway. */
12928 + if (spin_trylock(&adapter->tx_queue_lock)) {
12929 + tx_cleaned = e1000_clean_tx_irq(adapter);
12930 + spin_unlock(&adapter->tx_queue_lock);
12933 + adapter->clean_rx(adapter, &work_done, work_to_do);
12934 + *budget -= work_done;
12935 + poll_dev->quota -= work_done;
12937 + /* If no Tx and not enough Rx work done, exit the polling mode */
12938 + if ((!tx_cleaned && (work_done == 0)) ||
12939 + !netif_running(poll_dev)) {
12941 + if (adapter->itr_setting & 3)
12942 + e1000_set_itr(adapter);
12943 + netif_rx_complete(poll_dev);
12944 + if (test_bit(__E1000_DOWN, &adapter->state))
12945 + atomic_dec(&adapter->irq_sem);
12947 + e1000_irq_enable(adapter);
12954 +static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
12956 + struct e1000_adapter *adapter = netdev_priv(netdev);
12957 + struct e1000_hw *hw = &adapter->hw;
12960 + /* don't update vlan cookie if already programmed */
12961 + if ((adapter->hw.mng_cookie.status &
12962 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
12963 + (vid == adapter->mng_vlan_id))
12965 + /* add VID to filter table */
12966 + index = (vid >> 5) & 0x7F;
12967 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
12968 + vfta |= (1 << (vid & 0x1F));
12969 + e1000e_write_vfta(hw, index, vfta);
12972 +static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
12974 + struct e1000_adapter *adapter = netdev_priv(netdev);
12975 + struct e1000_hw *hw = &adapter->hw;
12978 + e1000_irq_disable(adapter);
12979 + vlan_group_set_device(adapter->vlgrp, vid, NULL);
12980 + e1000_irq_enable(adapter);
12982 + if ((adapter->hw.mng_cookie.status &
12983 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
12984 + (vid == adapter->mng_vlan_id)) {
12985 + /* release control to f/w */
12986 + e1000_release_hw_control(adapter);
12990 + /* remove VID from filter table */
12991 + index = (vid >> 5) & 0x7F;
12992 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
12993 + vfta &= ~(1 << (vid & 0x1F));
12994 + e1000e_write_vfta(hw, index, vfta);
12997 +static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
12999 + struct net_device *netdev = adapter->netdev;
13000 + u16 vid = adapter->hw.mng_cookie.vlan_id;
13001 + u16 old_vid = adapter->mng_vlan_id;
13003 + if (!adapter->vlgrp)
13006 + if (!vlan_group_get_device(adapter->vlgrp, vid)) {
13007 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
13008 + if (adapter->hw.mng_cookie.status &
13009 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
13010 + e1000_vlan_rx_add_vid(netdev, vid);
13011 + adapter->mng_vlan_id = vid;
13014 + if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
13015 + (vid != old_vid) &&
13016 + !vlan_group_get_device(adapter->vlgrp, old_vid))
13017 + e1000_vlan_rx_kill_vid(netdev, old_vid);
13019 + adapter->mng_vlan_id = vid;
13024 +static void e1000_vlan_rx_register(struct net_device *netdev,
13025 + struct vlan_group *grp)
13027 + struct e1000_adapter *adapter = netdev_priv(netdev);
13028 + struct e1000_hw *hw = &adapter->hw;
13031 + e1000_irq_disable(adapter);
13032 + adapter->vlgrp = grp;
13035 + /* enable VLAN tag insert/strip */
13036 + ctrl = er32(CTRL);
13037 + ctrl |= E1000_CTRL_VME;
13038 + ew32(CTRL, ctrl);
13040 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
13041 + /* enable VLAN receive filtering */
13042 + rctl = er32(RCTL);
13043 + rctl |= E1000_RCTL_VFE;
13044 + rctl &= ~E1000_RCTL_CFIEN;
13045 + ew32(RCTL, rctl);
13046 + e1000_update_mng_vlan(adapter);
13049 + /* disable VLAN tag insert/strip */
13050 + ctrl = er32(CTRL);
13051 + ctrl &= ~E1000_CTRL_VME;
13052 + ew32(CTRL, ctrl);
13054 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
13055 + /* disable VLAN filtering */
13056 + rctl = er32(RCTL);
13057 + rctl &= ~E1000_RCTL_VFE;
13058 + ew32(RCTL, rctl);
13059 + if (adapter->mng_vlan_id !=
13060 + (u16)E1000_MNG_VLAN_NONE) {
13061 + e1000_vlan_rx_kill_vid(netdev,
13062 + adapter->mng_vlan_id);
13063 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
13068 + e1000_irq_enable(adapter);
13071 +static void e1000_restore_vlan(struct e1000_adapter *adapter)
13075 + e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
13077 + if (!adapter->vlgrp)
13080 + for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
13081 + if (!vlan_group_get_device(adapter->vlgrp, vid))
13083 + e1000_vlan_rx_add_vid(adapter->netdev, vid);
13087 +static void e1000_init_manageability(struct e1000_adapter *adapter)
13089 + struct e1000_hw *hw = &adapter->hw;
13090 + u32 manc, manc2h;
13092 + if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
13095 + manc = er32(MANC);
13097 + /* disable hardware interception of ARP */
13098 + manc &= ~(E1000_MANC_ARP_EN);
13100 + /* enable receiving management packets to the host. this will probably
13101 + * generate destination unreachable messages from the host OS, but
13102 + * the packets will be handled on SMBUS */
13103 + manc |= E1000_MANC_EN_MNG2HOST;
13104 + manc2h = er32(MANC2H);
13105 +#define E1000_MNG2HOST_PORT_623 (1 << 5)
13106 +#define E1000_MNG2HOST_PORT_664 (1 << 6)
13107 + manc2h |= E1000_MNG2HOST_PORT_623;
13108 + manc2h |= E1000_MNG2HOST_PORT_664;
13109 + ew32(MANC2H, manc2h);
13110 + ew32(MANC, manc);
13114 + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
13115 + * @adapter: board private structure
13117 + * Configure the Tx unit of the MAC after a reset.
13119 +static void e1000_configure_tx(struct e1000_adapter *adapter)
13121 + struct e1000_hw *hw = &adapter->hw;
13122 + struct e1000_ring *tx_ring = adapter->tx_ring;
13124 + u32 tdlen, tctl, tipg, tarc;
13125 + u32 ipgr1, ipgr2;
13127 + /* Setup the HW Tx Head and Tail descriptor pointers */
13128 + tdba = tx_ring->dma;
13129 + tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
13130 + ew32(TDBAL, (tdba & DMA_32BIT_MASK));
13131 + ew32(TDBAH, (tdba >> 32));
13132 + ew32(TDLEN, tdlen);
13135 + tx_ring->head = E1000_TDH;
13136 + tx_ring->tail = E1000_TDT;
13138 + /* Set the default values for the Tx Inter Packet Gap timer */
13139 + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
13140 + ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
13141 + ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
13143 + if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
13144 + ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
13146 + tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
13147 + tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
13148 + ew32(TIPG, tipg);
13150 + /* Set the Tx Interrupt Delay register */
13151 + ew32(TIDV, adapter->tx_int_delay);
13152 + /* tx irq moderation */
13153 + ew32(TADV, adapter->tx_abs_int_delay);
13155 + /* Program the Transmit Control Register */
13156 + tctl = er32(TCTL);
13157 + tctl &= ~E1000_TCTL_CT;
13158 + tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
13159 + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
13161 + if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
13162 + tarc = er32(TARC0);
13163 + /* set the speed mode bit, we'll clear it if we're not at
13164 + * gigabit link later */
13165 +#define SPEED_MODE_BIT (1 << 21)
13166 + tarc |= SPEED_MODE_BIT;
13167 + ew32(TARC0, tarc);
13170 + /* errata: program both queues to unweighted RR */
13171 + if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
13172 + tarc = er32(TARC0);
13174 + ew32(TARC0, tarc);
13175 + tarc = er32(TARC1);
13177 + ew32(TARC1, tarc);
13180 + e1000e_config_collision_dist(hw);
13182 + /* Setup Transmit Descriptor Settings for eop descriptor */
13183 + adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
13185 + /* only set IDE if we are delaying interrupts using the timers */
13186 + if (adapter->tx_int_delay)
13187 + adapter->txd_cmd |= E1000_TXD_CMD_IDE;
13189 + /* enable Report Status bit */
13190 + adapter->txd_cmd |= E1000_TXD_CMD_RS;
13192 + ew32(TCTL, tctl);
13194 + adapter->tx_queue_len = adapter->netdev->tx_queue_len;
13198 + * e1000_setup_rctl - configure the receive control registers
13199 + * @adapter: Board private structure
13201 +#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
13202 + (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
13203 +static void e1000_setup_rctl(struct e1000_adapter *adapter)
13205 + struct e1000_hw *hw = &adapter->hw;
13210 + /* Program MC offset vector base */
13211 + rctl = er32(RCTL);
13212 + rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
13213 + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
13214 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
13215 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
13217 + /* Do not Store bad packets */
13218 + rctl &= ~E1000_RCTL_SBP;
13220 + /* Enable Long Packet receive */
13221 + if (adapter->netdev->mtu <= ETH_DATA_LEN)
13222 + rctl &= ~E1000_RCTL_LPE;
13224 + rctl |= E1000_RCTL_LPE;
13226 + /* Setup buffer sizes */
13227 + rctl &= ~E1000_RCTL_SZ_4096;
13228 + rctl |= E1000_RCTL_BSEX;
13229 + switch (adapter->rx_buffer_len) {
13231 + rctl |= E1000_RCTL_SZ_256;
13232 + rctl &= ~E1000_RCTL_BSEX;
13235 + rctl |= E1000_RCTL_SZ_512;
13236 + rctl &= ~E1000_RCTL_BSEX;
13239 + rctl |= E1000_RCTL_SZ_1024;
13240 + rctl &= ~E1000_RCTL_BSEX;
13244 + rctl |= E1000_RCTL_SZ_2048;
13245 + rctl &= ~E1000_RCTL_BSEX;
13248 + rctl |= E1000_RCTL_SZ_4096;
13251 + rctl |= E1000_RCTL_SZ_8192;
13254 + rctl |= E1000_RCTL_SZ_16384;
13258 +#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
13260 + * 82571 and greater support packet-split where the protocol
13261 + * header is placed in skb->data and the packet data is
13262 + * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
13263 + * In the case of a non-split, skb->data is linearly filled,
13264 + * followed by the page buffers. Therefore, skb->data is
13265 + * sized to hold the largest protocol header.
13267 + * allocations using alloc_page take too long for regular MTU
13268 + * so only enable packet split for jumbo frames
13270 + * Using pages when the page size is greater than 16k wastes
13271 + * a lot of memory, since we allocate 3 pages at all times
13274 + adapter->rx_ps_pages = 0;
13275 + pages = PAGE_USE_COUNT(adapter->netdev->mtu);
13276 + if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
13277 + adapter->rx_ps_pages = pages;
13279 + if (adapter->rx_ps_pages) {
13280 + /* Configure extra packet-split registers */
13281 + rfctl = er32(RFCTL);
13282 + rfctl |= E1000_RFCTL_EXTEN;
13283 + /* disable packet split support for IPv6 extension headers,
13284 + * because some malformed IPv6 headers can hang the RX */
13285 + rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
13286 + E1000_RFCTL_NEW_IPV6_EXT_DIS);
13288 + ew32(RFCTL, rfctl);
13290 + /* disable the stripping of CRC because it breaks
13291 + * BMC firmware connected over SMBUS */
13292 + rctl |= E1000_RCTL_DTYP_PS /* | E1000_RCTL_SECRC */;
13294 + psrctl |= adapter->rx_ps_bsize0 >>
13295 + E1000_PSRCTL_BSIZE0_SHIFT;
13297 + switch (adapter->rx_ps_pages) {
13299 + psrctl |= PAGE_SIZE <<
13300 + E1000_PSRCTL_BSIZE3_SHIFT;
13302 + psrctl |= PAGE_SIZE <<
13303 + E1000_PSRCTL_BSIZE2_SHIFT;
13305 + psrctl |= PAGE_SIZE >>
13306 + E1000_PSRCTL_BSIZE1_SHIFT;
13310 + ew32(PSRCTL, psrctl);
13313 + ew32(RCTL, rctl);
13317 + * e1000_configure_rx - Configure Receive Unit after Reset
13318 + * @adapter: board private structure
13320 + * Configure the Rx unit of the MAC after a reset.
13322 +static void e1000_configure_rx(struct e1000_adapter *adapter)
13324 + struct e1000_hw *hw = &adapter->hw;
13325 + struct e1000_ring *rx_ring = adapter->rx_ring;
13327 + u32 rdlen, rctl, rxcsum, ctrl_ext;
13329 + if (adapter->rx_ps_pages) {
13330 + /* this is a 32 byte descriptor */
13331 + rdlen = rx_ring->count *
13332 + sizeof(union e1000_rx_desc_packet_split);
13333 + adapter->clean_rx = e1000_clean_rx_irq_ps;
13334 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
13335 + } else if (adapter->netdev->mtu > ETH_FRAME_LEN + VLAN_HLEN + 4) {
13336 + rdlen = rx_ring->count *
13337 + sizeof(struct e1000_rx_desc);
13338 + adapter->clean_rx = e1000_clean_rx_irq_jumbo;
13339 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers_jumbo;
13341 + rdlen = rx_ring->count *
13342 + sizeof(struct e1000_rx_desc);
13343 + adapter->clean_rx = e1000_clean_rx_irq;
13344 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
13347 + /* disable receives while setting up the descriptors */
13348 + rctl = er32(RCTL);
13349 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
13353 + /* set the Receive Delay Timer Register */
13354 + ew32(RDTR, adapter->rx_int_delay);
13356 + /* irq moderation */
13357 + ew32(RADV, adapter->rx_abs_int_delay);
13358 + if (adapter->itr_setting != 0)
13360 + 1000000000 / (adapter->itr * 256));
13362 + ctrl_ext = er32(CTRL_EXT);
13363 + /* Reset delay timers after every interrupt */
13364 + ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
13365 + /* Auto-Mask interrupts upon ICR access */
13366 + ctrl_ext |= E1000_CTRL_EXT_IAME;
13367 + ew32(IAM, 0xffffffff);
13368 + ew32(CTRL_EXT, ctrl_ext);
13371 + /* Setup the HW Rx Head and Tail Descriptor Pointers and
13372 + * the Base and Length of the Rx Descriptor Ring */
13373 + rdba = rx_ring->dma;
13374 + ew32(RDBAL, (rdba & DMA_32BIT_MASK));
13375 + ew32(RDBAH, (rdba >> 32));
13376 + ew32(RDLEN, rdlen);
13379 + rx_ring->head = E1000_RDH;
13380 + rx_ring->tail = E1000_RDT;
13382 + /* Enable Receive Checksum Offload for TCP and UDP */
13383 + rxcsum = er32(RXCSUM);
13384 + if (adapter->flags & FLAG_RX_CSUM_ENABLED) {
13385 + rxcsum |= E1000_RXCSUM_TUOFL;
13387 + /* IPv4 payload checksum for UDP fragments must be
13388 + * used in conjunction with packet-split. */
13389 + if (adapter->rx_ps_pages)
13390 + rxcsum |= E1000_RXCSUM_IPPCSE;
13392 + rxcsum &= ~E1000_RXCSUM_TUOFL;
13393 + /* no need to clear IPPCSE as it defaults to 0 */
13395 + ew32(RXCSUM, rxcsum);
13397 + /* Enable early receives on supported devices, only takes effect when
13398 + * packet size is equal or larger than the specified value (in 8 byte
13399 + * units), e.g. using jumbo frames when setting to E1000_ERT_2048 */
13400 + if ((adapter->flags & FLAG_HAS_ERT) &&
13401 + (adapter->netdev->mtu > ETH_DATA_LEN))
13402 + ew32(ERT, E1000_ERT_2048);
13404 + /* Enable Receives */
13405 + ew32(RCTL, rctl);
13409 + * e1000_mc_addr_list_update - Update Multicast addresses
13410 + * @hw: pointer to the HW structure
13411 + * @mc_addr_list: array of multicast addresses to program
13412 + * @mc_addr_count: number of multicast addresses to program
13413 + * @rar_used_count: the first RAR register free to program
13414 + * @rar_count: total number of supported Receive Address Registers
13416 + * Updates the Receive Address Registers and Multicast Table Array.
13417 + * The caller must have a packed mc_addr_list of multicast addresses.
13418 + * The parameter rar_count will usually be hw->mac.rar_entry_count
13419 + * unless there are workarounds that change this. Currently no func pointer
13420 + * exists and all implementations are handled in the generic version of this
13423 +static void e1000_mc_addr_list_update(struct e1000_hw *hw, u8 *mc_addr_list,
13424 + u32 mc_addr_count, u32 rar_used_count,
13427 + hw->mac.ops.mc_addr_list_update(hw, mc_addr_list, mc_addr_count,
13428 + rar_used_count, rar_count);
13432 + * e1000_set_multi - Multicast and Promiscuous mode set
13433 + * @netdev: network interface device structure
13435 + * The set_multi entry point is called whenever the multicast address
13436 + * list or the network interface flags are updated. This routine is
13437 + * responsible for configuring the hardware for proper multicast,
13438 + * promiscuous mode, and all-multi behavior.
13440 +static void e1000_set_multi(struct net_device *netdev)
13442 + struct e1000_adapter *adapter = netdev_priv(netdev);
13443 + struct e1000_hw *hw = &adapter->hw;
13444 + struct e1000_mac_info *mac = &hw->mac;
13445 + struct dev_mc_list *mc_ptr;
13450 + /* Check for Promiscuous and All Multicast modes */
13452 + rctl = er32(RCTL);
13454 + if (netdev->flags & IFF_PROMISC) {
13455 + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
13456 + } else if (netdev->flags & IFF_ALLMULTI) {
13457 + rctl |= E1000_RCTL_MPE;
13458 + rctl &= ~E1000_RCTL_UPE;
13460 + rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
13463 + ew32(RCTL, rctl);
13465 + if (netdev->mc_count) {
13466 + mta_list = kmalloc(netdev->mc_count * 6, GFP_ATOMIC);
13470 + /* prepare a packed array of only addresses. */
13471 + mc_ptr = netdev->mc_list;
13473 + for (i = 0; i < netdev->mc_count; i++) {
13476 + memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr,
13478 + mc_ptr = mc_ptr->next;
13481 + e1000_mc_addr_list_update(hw, mta_list, i, 1,
13482 + mac->rar_entry_count);
13486 + * if we're called from probe, we might not have
13487 + * anything to do here, so clear out the list
13489 + e1000_mc_addr_list_update(hw, NULL, 0, 1,
13490 + mac->rar_entry_count);
13495 + * e1000_configure - configure the hardware for RX and TX
13496 + * @adapter: private board structure
13498 +static void e1000_configure(struct e1000_adapter *adapter)
13500 + e1000_set_multi(adapter->netdev);
13502 + e1000_restore_vlan(adapter);
13503 + e1000_init_manageability(adapter);
13505 + e1000_configure_tx(adapter);
13506 + e1000_setup_rctl(adapter);
13507 + e1000_configure_rx(adapter);
13508 + adapter->alloc_rx_buf(adapter,
13509 + e1000_desc_unused(adapter->rx_ring));
13513 + * e1000e_power_up_phy - restore link in case the phy was powered down
13514 + * @adapter: address of board private structure
13516 + * The phy may be powered down to save power and turn off link when the
13517 + * driver is unloaded and wake on lan is not enabled (among others)
13518 + * *** this routine MUST be followed by a call to e1000e_reset ***
13520 +void e1000e_power_up_phy(struct e1000_adapter *adapter)
13524 + /* Just clear the power down bit to wake the phy back up */
13525 + if (adapter->hw.media_type == e1000_media_type_copper) {
13526 + /* according to the manual, the phy will retain its
13527 + * settings across a power-down/up cycle */
13528 + e1e_rphy(&adapter->hw, PHY_CONTROL, &mii_reg);
13529 + mii_reg &= ~MII_CR_POWER_DOWN;
13530 + e1e_wphy(&adapter->hw, PHY_CONTROL, mii_reg);
13533 + adapter->hw.mac.ops.setup_link(&adapter->hw);
13537 + * e1000_power_down_phy - Power down the PHY
13539 + * Power down the PHY so no link is implied when interface is down
13540 + * The PHY cannot be powered down is management or WoL is active
13542 +static void e1000_power_down_phy(struct e1000_adapter *adapter)
13544 + struct e1000_hw *hw = &adapter->hw;
13547 + /* WoL is enabled */
13548 + if (!adapter->wol)
13551 + /* non-copper PHY? */
13552 + if (adapter->hw.media_type != e1000_media_type_copper)
13555 + /* reset is blocked because of a SoL/IDER session */
13556 + if (e1000e_check_mng_mode(hw) ||
13557 + e1000_check_reset_block(hw))
13560 + /* managebility (AMT) is enabled */
13561 + if (er32(MANC) & E1000_MANC_SMBUS_EN)
13564 + /* power down the PHY */
13565 + e1e_rphy(hw, PHY_CONTROL, &mii_reg);
13566 + mii_reg |= MII_CR_POWER_DOWN;
13567 + e1e_wphy(hw, PHY_CONTROL, mii_reg);
13572 + * e1000e_reset - bring the hardware into a known good state
13574 + * This function boots the hardware and enables some settings that
13575 + * require a configuration cycle of the hardware - those cannot be
13576 + * set/changed during runtime. After reset the device needs to be
13577 + * properly configured for rx, tx etc.
13579 +void e1000e_reset(struct e1000_adapter *adapter)
13581 + struct e1000_mac_info *mac = &adapter->hw.mac;
13582 + struct e1000_hw *hw = &adapter->hw;
13583 + u32 tx_space, min_tx_space, min_rx_space;
13586 + if (mac->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN ) {
13587 + /* To maintain wire speed transmits, the Tx FIFO should be
13588 + * large enough to accommodate two full transmit packets,
13589 + * rounded up to the next 1KB and expressed in KB. Likewise,
13590 + * the Rx FIFO should be large enough to accommodate at least
13591 + * one full receive packet and is similarly rounded up and
13592 + * expressed in KB. */
13593 + adapter->pba = er32(PBA);
13594 + /* upper 16 bits has Tx packet buffer allocation size in KB */
13595 + tx_space = adapter->pba >> 16;
13596 + /* lower 16 bits has Rx packet buffer allocation size in KB */
13597 + adapter->pba &= 0xffff;
13598 + /* the tx fifo also stores 16 bytes of information about the tx
13599 + * but don't include ethernet FCS because hardware appends it */
13600 + min_tx_space = (mac->max_frame_size +
13601 + sizeof(struct e1000_tx_desc) -
13602 + ETH_FCS_LEN) * 2;
13603 + min_tx_space = ALIGN(min_tx_space, 1024);
13604 + min_tx_space >>= 10;
13605 + /* software strips receive CRC, so leave room for it */
13606 + min_rx_space = mac->max_frame_size;
13607 + min_rx_space = ALIGN(min_rx_space, 1024);
13608 + min_rx_space >>= 10;
13610 + /* If current Tx allocation is less than the min Tx FIFO size,
13611 + * and the min Tx FIFO size is less than the current Rx FIFO
13612 + * allocation, take space away from current Rx allocation */
13613 + if (tx_space < min_tx_space &&
13614 + ((min_tx_space - tx_space) < adapter->pba)) {
13615 + adapter->pba -= - (min_tx_space - tx_space);
13617 + /* if short on rx space, rx wins and must trump tx
13618 + * adjustment or use Early Receive if available */
13619 + if ((adapter->pba < min_rx_space) &&
13620 + (!(adapter->flags & FLAG_HAS_ERT)))
13621 + /* ERT enabled in e1000_configure_rx */
13622 + adapter->pba = min_rx_space;
13626 + ew32(PBA, adapter->pba);
13628 + /* flow control settings */
13629 + /* The high water mark must be low enough to fit one full frame
13630 + * (or the size used for early receive) above it in the Rx FIFO.
13631 + * Set it to the lower of:
13632 + * - 90% of the Rx FIFO size, and
13633 + * - the full Rx FIFO size minus the early receive size (for parts
13634 + * with ERT support assuming ERT set to E1000_ERT_2048), or
13635 + * - the full Rx FIFO size minus one full frame */
13636 + if (adapter->flags & FLAG_HAS_ERT)
13637 + hwm = min(((adapter->pba << 10) * 9 / 10),
13638 + ((adapter->pba << 10) - (E1000_ERT_2048 << 3)));
13640 + hwm = min(((adapter->pba << 10) * 9 / 10),
13641 + ((adapter->pba << 10) - mac->max_frame_size));
13643 + mac->fc_high_water = hwm & 0xFFF8; /* 8-byte granularity */
13644 + mac->fc_low_water = mac->fc_high_water - 8;
13646 + if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
13647 + mac->fc_pause_time = 0xFFFF;
13649 + mac->fc_pause_time = E1000_FC_PAUSE_TIME;
13650 + mac->fc = mac->original_fc;
13652 + /* Allow time for pending master requests to run */
13653 + mac->ops.reset_hw(hw);
13656 + if (mac->ops.init_hw(hw))
13657 + ndev_err(adapter->netdev, "Hardware Error\n");
13659 + e1000_update_mng_vlan(adapter);
13661 + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
13662 + ew32(VET, ETH_P_8021Q);
13664 + e1000e_reset_adaptive(hw);
13665 + e1000_get_phy_info(hw);
13667 + if (!(adapter->flags & FLAG_SMART_POWER_DOWN)) {
13668 + u16 phy_data = 0;
13669 + /* speed up time to link by disabling smart power down, ignore
13670 + * the return value of this function because there is nothing
13671 + * different we would do if it failed */
13672 + e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
13673 + phy_data &= ~IGP02E1000_PM_SPD;
13674 + e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
13677 + e1000_release_manageability(adapter);
13680 +int e1000e_up(struct e1000_adapter *adapter)
13682 + struct e1000_hw *hw = &adapter->hw;
13684 + /* hardware has been reset, we need to reload some things */
13685 + e1000_configure(adapter);
13687 + clear_bit(__E1000_DOWN, &adapter->state);
13689 + netif_poll_enable(adapter->netdev);
13690 + e1000_irq_enable(adapter);
13692 + /* fire a link change interrupt to start the watchdog */
13693 + ew32(ICS, E1000_ICS_LSC);
13697 +void e1000e_down(struct e1000_adapter *adapter)
13699 + struct net_device *netdev = adapter->netdev;
13700 + struct e1000_hw *hw = &adapter->hw;
13703 + /* signal that we're down so the interrupt handler does not
13704 + * reschedule our watchdog timer */
13705 + set_bit(__E1000_DOWN, &adapter->state);
13707 + /* disable receives in the hardware */
13708 + rctl = er32(RCTL);
13709 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
13710 + /* flush and sleep below */
13712 + netif_stop_queue(netdev);
13714 + /* disable transmits in the hardware */
13715 + tctl = er32(TCTL);
13716 + tctl &= ~E1000_TCTL_EN;
13717 + ew32(TCTL, tctl);
13718 + /* flush both disables and wait for them to finish */
13722 + netif_poll_disable(netdev);
13723 + e1000_irq_disable(adapter);
13725 + del_timer_sync(&adapter->watchdog_timer);
13726 + del_timer_sync(&adapter->phy_info_timer);
13728 + netdev->tx_queue_len = adapter->tx_queue_len;
13729 + netif_carrier_off(netdev);
13730 + adapter->link_speed = 0;
13731 + adapter->link_duplex = 0;
13733 + e1000e_reset(adapter);
13734 + e1000_clean_tx_ring(adapter);
13735 + e1000_clean_rx_ring(adapter);
13738 + * TODO: for power management, we could drop the link and
13739 + * pci_disable_device here.
13743 +void e1000e_reinit_locked(struct e1000_adapter *adapter)
13746 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
13748 + e1000e_down(adapter);
13749 + e1000e_up(adapter);
13750 + clear_bit(__E1000_RESETTING, &adapter->state);
13754 + * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
13755 + * @adapter: board private structure to initialize
13757 + * e1000_sw_init initializes the Adapter private data structure.
13758 + * Fields are initialized based on PCI device information and
13759 + * OS network device settings (MTU size).
13761 +static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
13763 + struct e1000_hw *hw = &adapter->hw;
13764 + struct net_device *netdev = adapter->netdev;
13766 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
13767 + adapter->rx_ps_bsize0 = 128;
13768 + hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
13769 + hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
13771 + adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
13772 + if (!adapter->tx_ring)
13775 + adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
13776 + if (!adapter->rx_ring)
13779 + spin_lock_init(&adapter->tx_queue_lock);
13781 + /* Explicitly disable IRQ since the NIC can be in any state. */
13782 + atomic_set(&adapter->irq_sem, 0);
13783 + e1000_irq_disable(adapter);
13785 + spin_lock_init(&adapter->stats_lock);
13787 + set_bit(__E1000_DOWN, &adapter->state);
13791 + ndev_err(netdev, "Unable to allocate memory for queues\n");
13792 + kfree(adapter->rx_ring);
13793 + kfree(adapter->tx_ring);
13798 + * e1000_open - Called when a network interface is made active
13799 + * @netdev: network interface device structure
13801 + * Returns 0 on success, negative value on failure
13803 + * The open entry point is called when a network interface is made
13804 + * active by the system (IFF_UP). At this point all resources needed
13805 + * for transmit and receive operations are allocated, the interrupt
13806 + * handler is registered with the OS, the watchdog timer is started,
13807 + * and the stack is notified that the interface is ready.
13809 +static int e1000_open(struct net_device *netdev)
13811 + struct e1000_adapter *adapter = netdev_priv(netdev);
13812 + struct e1000_hw *hw = &adapter->hw;
13815 + /* disallow open during test */
13816 + if (test_bit(__E1000_TESTING, &adapter->state))
13819 + /* allocate transmit descriptors */
13820 + err = e1000e_setup_tx_resources(adapter);
13822 + goto err_setup_tx;
13824 + /* allocate receive descriptors */
13825 + err = e1000e_setup_rx_resources(adapter);
13827 + goto err_setup_rx;
13829 + e1000e_power_up_phy(adapter);
13831 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
13832 + if ((adapter->hw.mng_cookie.status &
13833 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
13834 + e1000_update_mng_vlan(adapter);
13836 + /* If AMT is enabled, let the firmware know that the network
13837 + * interface is now open */
13838 + if ((adapter->flags & FLAG_HAS_AMT) &&
13839 + e1000e_check_mng_mode(&adapter->hw))
13840 + e1000_get_hw_control(adapter);
13842 + /* before we allocate an interrupt, we must be ready to handle it.
13843 + * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
13844 + * as soon as we call pci_request_irq, so we have to setup our
13845 + * clean_rx handler before we do so. */
13846 + e1000_configure(adapter);
13848 + err = e1000_request_irq(adapter);
13850 + goto err_req_irq;
13852 + /* From here on the code is the same as e1000e_up() */
13853 + clear_bit(__E1000_DOWN, &adapter->state);
13855 + netif_poll_enable(netdev);
13857 + e1000_irq_enable(adapter);
13859 + /* fire a link status change interrupt to start the watchdog */
13860 + ew32(ICS, E1000_ICS_LSC);
13865 + e1000_release_hw_control(adapter);
13866 + e1000_power_down_phy(adapter);
13867 + e1000e_free_rx_resources(adapter);
13869 + e1000e_free_tx_resources(adapter);
13871 + e1000e_reset(adapter);
13877 + * e1000_close - Disables a network interface
13878 + * @netdev: network interface device structure
13880 + * Returns 0, this is not allowed to fail
13882 + * The close entry point is called when an interface is de-activated
13883 + * by the OS. The hardware is still under the drivers control, but
13884 + * needs to be disabled. A global MAC reset is issued to stop the
13885 + * hardware, and all transmit and receive resources are freed.
13887 +static int e1000_close(struct net_device *netdev)
13889 + struct e1000_adapter *adapter = netdev_priv(netdev);
13891 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
13892 + e1000e_down(adapter);
13893 + e1000_power_down_phy(adapter);
13894 + e1000_free_irq(adapter);
13896 + e1000e_free_tx_resources(adapter);
13897 + e1000e_free_rx_resources(adapter);
13899 + /* kill manageability vlan ID if supported, but not if a vlan with
13900 + * the same ID is registered on the host OS (let 8021q kill it) */
13901 + if ((adapter->hw.mng_cookie.status &
13902 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
13903 + !(adapter->vlgrp &&
13904 + vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
13905 + e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
13907 + /* If AMT is enabled, let the firmware know that the network
13908 + * interface is now closed */
13909 + if ((adapter->flags & FLAG_HAS_AMT) &&
13910 + e1000e_check_mng_mode(&adapter->hw))
13911 + e1000_release_hw_control(adapter);
13916 + * e1000_set_mac - Change the Ethernet Address of the NIC
13917 + * @netdev: network interface device structure
13918 + * @p: pointer to an address structure
13920 + * Returns 0 on success, negative on failure
13922 +static int e1000_set_mac(struct net_device *netdev, void *p)
13924 + struct e1000_adapter *adapter = netdev_priv(netdev);
13925 + struct sockaddr *addr = p;
13927 + if (!is_valid_ether_addr(addr->sa_data))
13928 + return -EADDRNOTAVAIL;
13930 + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
13931 + memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
13933 + e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
13935 + if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
13936 + /* activate the work around */
13937 + e1000e_set_laa_state_82571(&adapter->hw, 1);
13939 + /* Hold a copy of the LAA in RAR[14] This is done so that
13940 + * between the time RAR[0] gets clobbered and the time it
13941 + * gets fixed (in e1000_watchdog), the actual LAA is in one
13942 + * of the RARs and no incoming packets directed to this port
13943 + * are dropped. Eventually the LAA will be in RAR[0] and
13945 + e1000e_rar_set(&adapter->hw,
13946 + adapter->hw.mac.addr,
13947 + adapter->hw.mac.rar_entry_count - 1);
13953 +/* Need to wait a few seconds after link up to get diagnostic information from
13955 +static void e1000_update_phy_info(unsigned long data)
13957 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
13958 + e1000_get_phy_info(&adapter->hw);
13962 + * e1000e_update_stats - Update the board statistics counters
13963 + * @adapter: board private structure
13965 +void e1000e_update_stats(struct e1000_adapter *adapter)
13967 + struct e1000_hw *hw = &adapter->hw;
13968 + struct pci_dev *pdev = adapter->pdev;
13969 + unsigned long irq_flags;
13972 +#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
13975 + * Prevent stats update while adapter is being reset, or if the pci
13976 + * connection is down.
13978 + if (adapter->link_speed == 0)
13980 + if (pci_channel_offline(pdev))
13983 + spin_lock_irqsave(&adapter->stats_lock, irq_flags);
13985 + /* these counters are modified from e1000_adjust_tbi_stats,
13986 + * called from the interrupt context, so they must only
13987 + * be written while holding adapter->stats_lock
13990 + adapter->stats.crcerrs += er32(CRCERRS);
13991 + adapter->stats.gprc += er32(GPRC);
13992 + adapter->stats.gorcl += er32(GORCL);
13993 + adapter->stats.gorch += er32(GORCH);
13994 + adapter->stats.bprc += er32(BPRC);
13995 + adapter->stats.mprc += er32(MPRC);
13996 + adapter->stats.roc += er32(ROC);
13998 + if (adapter->flags & FLAG_HAS_STATS_PTC_PRC) {
13999 + adapter->stats.prc64 += er32(PRC64);
14000 + adapter->stats.prc127 += er32(PRC127);
14001 + adapter->stats.prc255 += er32(PRC255);
14002 + adapter->stats.prc511 += er32(PRC511);
14003 + adapter->stats.prc1023 += er32(PRC1023);
14004 + adapter->stats.prc1522 += er32(PRC1522);
14005 + adapter->stats.symerrs += er32(SYMERRS);
14006 + adapter->stats.sec += er32(SEC);
14009 + adapter->stats.mpc += er32(MPC);
14010 + adapter->stats.scc += er32(SCC);
14011 + adapter->stats.ecol += er32(ECOL);
14012 + adapter->stats.mcc += er32(MCC);
14013 + adapter->stats.latecol += er32(LATECOL);
14014 + adapter->stats.dc += er32(DC);
14015 + adapter->stats.rlec += er32(RLEC);
14016 + adapter->stats.xonrxc += er32(XONRXC);
14017 + adapter->stats.xontxc += er32(XONTXC);
14018 + adapter->stats.xoffrxc += er32(XOFFRXC);
14019 + adapter->stats.xofftxc += er32(XOFFTXC);
14020 + adapter->stats.fcruc += er32(FCRUC);
14021 + adapter->stats.gptc += er32(GPTC);
14022 + adapter->stats.gotcl += er32(GOTCL);
14023 + adapter->stats.gotch += er32(GOTCH);
14024 + adapter->stats.rnbc += er32(RNBC);
14025 + adapter->stats.ruc += er32(RUC);
14026 + adapter->stats.rfc += er32(RFC);
14027 + adapter->stats.rjc += er32(RJC);
14028 + adapter->stats.torl += er32(TORL);
14029 + adapter->stats.torh += er32(TORH);
14030 + adapter->stats.totl += er32(TOTL);
14031 + adapter->stats.toth += er32(TOTH);
14032 + adapter->stats.tpr += er32(TPR);
14034 + if (adapter->flags & FLAG_HAS_STATS_PTC_PRC) {
14035 + adapter->stats.ptc64 += er32(PTC64);
14036 + adapter->stats.ptc127 += er32(PTC127);
14037 + adapter->stats.ptc255 += er32(PTC255);
14038 + adapter->stats.ptc511 += er32(PTC511);
14039 + adapter->stats.ptc1023 += er32(PTC1023);
14040 + adapter->stats.ptc1522 += er32(PTC1522);
14043 + adapter->stats.mptc += er32(MPTC);
14044 + adapter->stats.bptc += er32(BPTC);
14046 + /* used for adaptive IFS */
14048 + hw->mac.tx_packet_delta = er32(TPT);
14049 + adapter->stats.tpt += hw->mac.tx_packet_delta;
14050 + hw->mac.collision_delta = er32(COLC);
14051 + adapter->stats.colc += hw->mac.collision_delta;
14053 + adapter->stats.algnerrc += er32(ALGNERRC);
14054 + adapter->stats.rxerrc += er32(RXERRC);
14055 + adapter->stats.tncrs += er32(TNCRS);
14056 + adapter->stats.cexterr += er32(CEXTERR);
14057 + adapter->stats.tsctc += er32(TSCTC);
14058 + adapter->stats.tsctfc += er32(TSCTFC);
14060 + adapter->stats.iac += er32(IAC);
14062 + if (adapter->flags & FLAG_HAS_STATS_ICR_ICT) {
14063 + adapter->stats.icrxoc += er32(ICRXOC);
14064 + adapter->stats.icrxptc += er32(ICRXPTC);
14065 + adapter->stats.icrxatc += er32(ICRXATC);
14066 + adapter->stats.ictxptc += er32(ICTXPTC);
14067 + adapter->stats.ictxatc += er32(ICTXATC);
14068 + adapter->stats.ictxqec += er32(ICTXQEC);
14069 + adapter->stats.ictxqmtc += er32(ICTXQMTC);
14070 + adapter->stats.icrxdmtc += er32(ICRXDMTC);
14073 + /* Fill out the OS statistics structure */
14074 + adapter->net_stats.rx_packets = adapter->stats.gprc;
14075 + adapter->net_stats.tx_packets = adapter->stats.gptc;
14076 + adapter->net_stats.rx_bytes = adapter->stats.gorcl;
14077 + adapter->net_stats.tx_bytes = adapter->stats.gotcl;
14078 + adapter->net_stats.multicast = adapter->stats.mprc;
14079 + adapter->net_stats.collisions = adapter->stats.colc;
14083 + /* RLEC on some newer hardware can be incorrect so build
14084 + * our own version based on RUC and ROC */
14085 + adapter->net_stats.rx_errors = adapter->stats.rxerrc +
14086 + adapter->stats.crcerrs + adapter->stats.algnerrc +
14087 + adapter->stats.ruc + adapter->stats.roc +
14088 + adapter->stats.cexterr;
14089 + adapter->net_stats.rx_length_errors = adapter->stats.ruc +
14090 + adapter->stats.roc;
14091 + adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
14092 + adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
14093 + adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
14096 + adapter->net_stats.tx_errors = adapter->stats.ecol +
14097 + adapter->stats.latecol;
14098 + adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
14099 + adapter->net_stats.tx_window_errors = adapter->stats.latecol;
14100 + adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
14102 + /* Tx Dropped needs to be maintained elsewhere */
14105 + if (hw->media_type == e1000_media_type_copper) {
14106 + if ((adapter->link_speed == SPEED_1000) &&
14107 + (!e1e_rphy(hw, PHY_1000T_STATUS, &phy_tmp))) {
14108 + phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
14109 + adapter->phy_stats.idle_errors += phy_tmp;
14113 + /* Management Stats */
14114 + adapter->stats.mgptc += er32(MGTPTC);
14115 + adapter->stats.mgprc += er32(MGTPRC);
14116 + adapter->stats.mgpdc += er32(MGTPDC);
14118 + spin_unlock_irqrestore(&adapter->stats_lock, irq_flags);
14121 +static void e1000_print_link_info(struct e1000_adapter *adapter)
14123 + struct net_device *netdev = adapter->netdev;
14124 + struct e1000_hw *hw = &adapter->hw;
14125 + u32 ctrl = er32(CTRL);
14127 + ndev_info(netdev,
14128 + "Link is Up %d Mbps %s, Flow Control: %s\n",
14129 + adapter->link_speed,
14130 + (adapter->link_duplex == FULL_DUPLEX) ?
14131 + "Full Duplex" : "Half Duplex",
14132 + ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ?
14134 + ((ctrl & E1000_CTRL_RFCE) ? "RX" :
14135 + ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" )));
14139 + * e1000_watchdog - Timer Call-back
14140 + * @data: pointer to adapter cast into an unsigned long
14142 +static void e1000_watchdog(unsigned long data)
14144 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
14146 + /* Do the rest outside of interrupt context */
14147 + schedule_work(&adapter->watchdog_task);
14149 + /* TODO: make this use queue_delayed_work() */
14152 +static void e1000_watchdog_task(struct work_struct *work)
14154 + struct e1000_adapter *adapter = container_of(work,
14155 + struct e1000_adapter, watchdog_task);
14157 + struct net_device *netdev = adapter->netdev;
14158 + struct e1000_mac_info *mac = &adapter->hw.mac;
14159 + struct e1000_ring *tx_ring = adapter->tx_ring;
14160 + struct e1000_hw *hw = &adapter->hw;
14163 + int tx_pending = 0;
14165 + if ((netif_carrier_ok(netdev)) &&
14166 + (er32(STATUS) & E1000_STATUS_LU))
14169 + ret_val = mac->ops.check_for_link(hw);
14170 + if ((ret_val == E1000_ERR_PHY) &&
14171 + (adapter->hw.phy.type == e1000_phy_igp_3) &&
14173 + E1000_PHY_CTRL_GBE_DISABLE)) {
14174 + /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
14175 + ndev_info(netdev,
14176 + "Gigabit has been disabled, downgrading speed\n");
14179 + if ((e1000e_enable_tx_pkt_filtering(hw)) &&
14180 + (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
14181 + e1000_update_mng_vlan(adapter);
14183 + if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
14184 + !(er32(TXCW) & E1000_TXCW_ANE))
14185 + link = adapter->hw.mac.serdes_has_link;
14187 + link = er32(STATUS) & E1000_STATUS_LU;
14190 + if (!netif_carrier_ok(netdev)) {
14192 + mac->ops.get_link_up_info(&adapter->hw,
14193 + &adapter->link_speed,
14194 + &adapter->link_duplex);
14195 + e1000_print_link_info(adapter);
14196 + /* tweak tx_queue_len according to speed/duplex
14197 + * and adjust the timeout factor */
14198 + netdev->tx_queue_len = adapter->tx_queue_len;
14199 + adapter->tx_timeout_factor = 1;
14200 + switch (adapter->link_speed) {
14203 + netdev->tx_queue_len = 10;
14204 + adapter->tx_timeout_factor = 14;
14208 + netdev->tx_queue_len = 100;
14209 + /* maybe add some timeout factor ? */
14213 + /* workaround: re-program speed mode bit after
14214 + * link-up event */
14215 + if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
14218 + tarc0 = er32(TARC0);
14219 + tarc0 &= ~SPEED_MODE_BIT;
14220 + ew32(TARC0, tarc0);
14223 + /* disable TSO for pcie and 10/100 speeds, to avoid
14224 + * some hardware issues */
14225 + if (!(adapter->flags & FLAG_TSO_FORCE)) {
14226 + switch (adapter->link_speed) {
14229 + ndev_info(netdev,
14230 + "10/100 speed: disabling TSO\n");
14231 + netdev->features &= ~NETIF_F_TSO;
14232 + netdev->features &= ~NETIF_F_TSO6;
14235 + netdev->features |= NETIF_F_TSO;
14236 + netdev->features |= NETIF_F_TSO6;
14244 + /* enable transmits in the hardware, need to do this
14245 + * after setting TARC0 */
14246 + tctl = er32(TCTL);
14247 + tctl |= E1000_TCTL_EN;
14248 + ew32(TCTL, tctl);
14250 + netif_carrier_on(netdev);
14251 + netif_wake_queue(netdev);
14253 + if (!test_bit(__E1000_DOWN, &adapter->state))
14254 + mod_timer(&adapter->phy_info_timer,
14255 + round_jiffies(jiffies + 2 * HZ));
14257 + /* make sure the receive unit is started */
14258 + if (adapter->flags & FLAG_RX_NEEDS_RESTART) {
14259 + u32 rctl = er32(RCTL);
14260 + ew32(RCTL, rctl |
14265 + if (netif_carrier_ok(netdev)) {
14266 + adapter->link_speed = 0;
14267 + adapter->link_duplex = 0;
14268 + ndev_info(netdev, "Link is Down\n");
14269 + netif_carrier_off(netdev);
14270 + netif_stop_queue(netdev);
14271 + if (!test_bit(__E1000_DOWN, &adapter->state))
14272 + mod_timer(&adapter->phy_info_timer,
14273 + round_jiffies(jiffies + 2 * HZ));
14275 + if (adapter->flags & FLAG_RX_NEEDS_RESTART)
14276 + schedule_work(&adapter->reset_task);
14281 + e1000e_update_stats(adapter);
14283 + mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
14284 + adapter->tpt_old = adapter->stats.tpt;
14285 + mac->collision_delta = adapter->stats.colc - adapter->colc_old;
14286 + adapter->colc_old = adapter->stats.colc;
14288 + adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
14289 + adapter->gorcl_old = adapter->stats.gorcl;
14290 + adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
14291 + adapter->gotcl_old = adapter->stats.gotcl;
14293 + e1000e_update_adaptive(&adapter->hw);
14295 + if (!netif_carrier_ok(netdev)) {
14296 + tx_pending = (e1000_desc_unused(tx_ring) + 1 <
14298 + if (tx_pending) {
14299 + /* We've lost link, so the controller stops DMA,
14300 + * but we've got queued Tx work that's never going
14301 + * to get done, so reset controller to flush Tx.
14302 + * (Do the reset outside of interrupt context). */
14303 + adapter->tx_timeout_count++;
14304 + schedule_work(&adapter->reset_task);
14308 + /* Cause software interrupt to ensure rx ring is cleaned */
14309 + ew32(ICS, E1000_ICS_RXDMT0);
14311 + /* Force detection of hung controller every watchdog period */
14312 + adapter->detect_tx_hung = 1;
14314 + /* With 82571 controllers, LAA may be overwritten due to controller
14315 + * reset from the other port. Set the appropriate LAA in RAR[0] */
14316 + if (e1000e_get_laa_state_82571(hw))
14317 + e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
14319 + /* Reset the timer */
14320 + if (!test_bit(__E1000_DOWN, &adapter->state))
14321 + mod_timer(&adapter->watchdog_timer,
14322 + round_jiffies(jiffies + 2 * HZ));
14325 +#define E1000_TX_FLAGS_CSUM 0x00000001
14326 +#define E1000_TX_FLAGS_VLAN 0x00000002
14327 +#define E1000_TX_FLAGS_TSO 0x00000004
14328 +#define E1000_TX_FLAGS_IPV4 0x00000008
14329 +#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
14330 +#define E1000_TX_FLAGS_VLAN_SHIFT 16
14332 +static int e1000_tso(struct e1000_adapter *adapter,
14333 + struct sk_buff *skb)
14335 + struct e1000_ring *tx_ring = adapter->tx_ring;
14336 + struct e1000_context_desc *context_desc;
14337 + struct e1000_buffer *buffer_info;
14339 + u32 cmd_length = 0;
14340 + u16 ipcse = 0, tucse, mss;
14341 + u8 ipcss, ipcso, tucss, tucso, hdr_len;
14344 + if (skb_is_gso(skb)) {
14345 + if (skb_header_cloned(skb)) {
14346 + err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
14351 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
14352 + mss = skb_shinfo(skb)->gso_size;
14353 + if (skb->protocol == htons(ETH_P_IP)) {
14354 + struct iphdr *iph = ip_hdr(skb);
14355 + iph->tot_len = 0;
14357 + tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
14361 + cmd_length = E1000_TXD_CMD_IP;
14362 + ipcse = skb_transport_offset(skb) - 1;
14363 + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
14364 + ipv6_hdr(skb)->payload_len = 0;
14365 + tcp_hdr(skb)->check =
14366 + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
14367 + &ipv6_hdr(skb)->daddr,
14368 + 0, IPPROTO_TCP, 0);
14371 + ipcss = skb_network_offset(skb);
14372 + ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
14373 + tucss = skb_transport_offset(skb);
14374 + tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
14377 + cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
14378 + E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
14380 + i = tx_ring->next_to_use;
14381 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
14382 + buffer_info = &tx_ring->buffer_info[i];
14384 + context_desc->lower_setup.ip_fields.ipcss = ipcss;
14385 + context_desc->lower_setup.ip_fields.ipcso = ipcso;
14386 + context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
14387 + context_desc->upper_setup.tcp_fields.tucss = tucss;
14388 + context_desc->upper_setup.tcp_fields.tucso = tucso;
14389 + context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
14390 + context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
14391 + context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
14392 + context_desc->cmd_and_length = cpu_to_le32(cmd_length);
14394 + buffer_info->time_stamp = jiffies;
14395 + buffer_info->next_to_watch = i;
14398 + if (i == tx_ring->count)
14400 + tx_ring->next_to_use = i;
14408 +static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
14410 + struct e1000_ring *tx_ring = adapter->tx_ring;
14411 + struct e1000_context_desc *context_desc;
14412 + struct e1000_buffer *buffer_info;
14416 + if (skb->ip_summed == CHECKSUM_PARTIAL) {
14417 + css = skb_transport_offset(skb);
14419 + i = tx_ring->next_to_use;
14420 + buffer_info = &tx_ring->buffer_info[i];
14421 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
14423 + context_desc->lower_setup.ip_config = 0;
14424 + context_desc->upper_setup.tcp_fields.tucss = css;
14425 + context_desc->upper_setup.tcp_fields.tucso =
14426 + css + skb->csum_offset;
14427 + context_desc->upper_setup.tcp_fields.tucse = 0;
14428 + context_desc->tcp_seg_setup.data = 0;
14429 + context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
14431 + buffer_info->time_stamp = jiffies;
14432 + buffer_info->next_to_watch = i;
14435 + if (i == tx_ring->count)
14437 + tx_ring->next_to_use = i;
14445 +#define E1000_MAX_PER_TXD 8192
14446 +#define E1000_MAX_TXD_PWR 12
14448 +static int e1000_tx_map(struct e1000_adapter *adapter,
14449 + struct sk_buff *skb, unsigned int first,
14450 + unsigned int max_per_txd, unsigned int nr_frags,
14451 + unsigned int mss)
14453 + struct e1000_ring *tx_ring = adapter->tx_ring;
14454 + struct e1000_buffer *buffer_info;
14455 + unsigned int len = skb->len - skb->data_len;
14456 + unsigned int offset = 0, size, count = 0, i;
14459 + i = tx_ring->next_to_use;
14462 + buffer_info = &tx_ring->buffer_info[i];
14463 + size = min(len, max_per_txd);
14464 + /* Workaround for Controller erratum --
14465 + * descriptor for non-tso packet in a linear SKB that follows a
14466 + * tso gets written back prematurely before the data is fully
14467 + * DMA'd to the controller */
14468 + if (tx_ring->last_tx_tso && !skb_is_gso(skb)) {
14469 + tx_ring->last_tx_tso = 0;
14470 + if (!skb->data_len)
14474 + /* Workaround for premature desc write-backs
14475 + * in TSO mode. Append 4-byte sentinel desc */
14476 + if (mss && !nr_frags && size == len && size > 8)
14479 + buffer_info->length = size;
14480 + /* set time_stamp *before* dma to help avoid a possible race */
14481 + buffer_info->time_stamp = jiffies;
14482 + buffer_info->dma =
14483 + pci_map_single(adapter->pdev,
14484 + skb->data + offset,
14486 + PCI_DMA_TODEVICE);
14487 + if (pci_dma_mapping_error(buffer_info->dma)) {
14488 + dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
14489 + adapter->tx_dma_failed++;
14492 + buffer_info->next_to_watch = i;
14498 + if (i == tx_ring->count)
14502 + for (f = 0; f < nr_frags; f++) {
14503 + struct skb_frag_struct *frag;
14505 + frag = &skb_shinfo(skb)->frags[f];
14506 + len = frag->size;
14507 + offset = frag->page_offset;
14510 + buffer_info = &tx_ring->buffer_info[i];
14511 + size = min(len, max_per_txd);
14512 + /* Workaround for premature desc write-backs
14513 + * in TSO mode. Append 4-byte sentinel desc */
14514 + if (mss && f == (nr_frags-1) && size == len && size > 8)
14517 + buffer_info->length = size;
14518 + buffer_info->time_stamp = jiffies;
14519 + buffer_info->dma =
14520 + pci_map_page(adapter->pdev,
14524 + PCI_DMA_TODEVICE);
14525 + if (pci_dma_mapping_error(buffer_info->dma)) {
14526 + dev_err(&adapter->pdev->dev,
14527 + "TX DMA page map failed\n");
14528 + adapter->tx_dma_failed++;
14532 + buffer_info->next_to_watch = i;
14539 + if (i == tx_ring->count)
14545 + i = tx_ring->count - 1;
14549 + tx_ring->buffer_info[i].skb = skb;
14550 + tx_ring->buffer_info[first].next_to_watch = i;
14555 +static void e1000_tx_queue(struct e1000_adapter *adapter,
14556 + int tx_flags, int count)
14558 + struct e1000_ring *tx_ring = adapter->tx_ring;
14559 + struct e1000_tx_desc *tx_desc = NULL;
14560 + struct e1000_buffer *buffer_info;
14561 + u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
14564 + if (tx_flags & E1000_TX_FLAGS_TSO) {
14565 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
14566 + E1000_TXD_CMD_TSE;
14567 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
14569 + if (tx_flags & E1000_TX_FLAGS_IPV4)
14570 + txd_upper |= E1000_TXD_POPTS_IXSM << 8;
14573 + if (tx_flags & E1000_TX_FLAGS_CSUM) {
14574 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
14575 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
14578 + if (tx_flags & E1000_TX_FLAGS_VLAN) {
14579 + txd_lower |= E1000_TXD_CMD_VLE;
14580 + txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
14583 + i = tx_ring->next_to_use;
14585 + while (count--) {
14586 + buffer_info = &tx_ring->buffer_info[i];
14587 + tx_desc = E1000_TX_DESC(*tx_ring, i);
14588 + tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
14589 + tx_desc->lower.data =
14590 + cpu_to_le32(txd_lower | buffer_info->length);
14591 + tx_desc->upper.data = cpu_to_le32(txd_upper);
14594 + if (i == tx_ring->count)
14598 + tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
14600 + /* Force memory writes to complete before letting h/w
14601 + * know there are new descriptors to fetch. (Only
14602 + * applicable for weak-ordered memory model archs,
14603 + * such as IA-64). */
14606 + tx_ring->next_to_use = i;
14607 + writel(i, adapter->hw.hw_addr + tx_ring->tail);
14608 + /* we need this if more than one processor can write to our tail
14609 + * at a time, it synchronizes IO on IA64/Altix systems */
14613 +#define MINIMUM_DHCP_PACKET_SIZE 282
14614 +static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
14615 + struct sk_buff *skb)
14617 + struct e1000_hw *hw = &adapter->hw;
14618 + u16 length, offset;
14620 + if (vlan_tx_tag_present(skb)) {
14621 + if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id)
14622 + && (adapter->hw.mng_cookie.status &
14623 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
14627 + if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
14630 + if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
14634 + const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
14635 + struct udphdr *udp;
14637 + if (ip->protocol != IPPROTO_UDP)
14640 + udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
14641 + if (ntohs(udp->dest) != 67)
14644 + offset = (u8 *)udp + 8 - skb->data;
14645 + length = skb->len - offset;
14646 + return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
14652 +static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
14654 + struct e1000_adapter *adapter = netdev_priv(netdev);
14656 + netif_stop_queue(netdev);
14657 + /* Herbert's original patch had:
14658 + * smp_mb__after_netif_stop_queue();
14659 + * but since that doesn't exist yet, just open code it. */
14662 + /* We need to check again in a case another CPU has just
14663 + * made room available. */
14664 + if (e1000_desc_unused(adapter->tx_ring) < size)
14667 + /* A reprieve! */
14668 + netif_start_queue(netdev);
14669 + ++adapter->restart_queue;
14673 +static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
14675 + struct e1000_adapter *adapter = netdev_priv(netdev);
14677 + if (e1000_desc_unused(adapter->tx_ring) >= size)
14679 + return __e1000_maybe_stop_tx(netdev, size);
14682 +#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
14683 +static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
14685 + struct e1000_adapter *adapter = netdev_priv(netdev);
14686 + struct e1000_ring *tx_ring = adapter->tx_ring;
14687 + unsigned int first;
14688 + unsigned int max_per_txd = E1000_MAX_PER_TXD;
14689 + unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
14690 + unsigned int tx_flags = 0;
14691 + unsigned int len = skb->len;
14692 + unsigned long irq_flags;
14693 + unsigned int nr_frags = 0;
14694 + unsigned int mss = 0;
14698 + len -= skb->data_len;
14700 + if (test_bit(__E1000_DOWN, &adapter->state)) {
14701 + dev_kfree_skb_any(skb);
14702 + return NETDEV_TX_OK;
14705 + if (skb->len <= 0) {
14706 + dev_kfree_skb_any(skb);
14707 + return NETDEV_TX_OK;
14710 + mss = skb_shinfo(skb)->gso_size;
14711 + /* The controller does a simple calculation to
14712 + * make sure there is enough room in the FIFO before
14713 + * initiating the DMA for each buffer. The calc is:
14714 + * 4 = ceil(buffer len/mss). To make sure we don't
14715 + * overrun the FIFO, adjust the max buffer len if mss
14719 + max_per_txd = min(mss << 2, max_per_txd);
14720 + max_txd_pwr = fls(max_per_txd) - 1;
14722 + /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
14723 + * points to just header, pull a few bytes of payload from
14724 + * frags into skb->data */
14725 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
14726 + if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
14727 + unsigned int pull_size;
14729 + pull_size = min((unsigned int)4, skb->data_len);
14730 + if (!__pskb_pull_tail(skb, pull_size)) {
14732 + "__pskb_pull_tail failed.\n");
14733 + dev_kfree_skb_any(skb);
14734 + return NETDEV_TX_OK;
14736 + len = skb->len - skb->data_len;
14740 + /* reserve a descriptor for the offload context */
14741 + if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
14745 + /* Controller Erratum workaround */
14746 + if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
14749 + count += TXD_USE_COUNT(len, max_txd_pwr);
14751 + nr_frags = skb_shinfo(skb)->nr_frags;
14752 + for (f = 0; f < nr_frags; f++)
14753 + count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
14756 + if (adapter->hw.mac.tx_pkt_filtering)
14757 + e1000_transfer_dhcp_info(adapter, skb);
14759 + if (!spin_trylock_irqsave(&adapter->tx_queue_lock, irq_flags))
14760 + /* Collision - tell upper layer to requeue */
14761 + return NETDEV_TX_LOCKED;
14763 + /* need: count + 2 desc gap to keep tail from touching
14764 + * head, otherwise try next time */
14765 + if (e1000_maybe_stop_tx(netdev, count + 2)) {
14766 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
14767 + return NETDEV_TX_BUSY;
14770 + if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
14771 + tx_flags |= E1000_TX_FLAGS_VLAN;
14772 + tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
14775 + first = tx_ring->next_to_use;
14777 + tso = e1000_tso(adapter, skb);
14779 + dev_kfree_skb_any(skb);
14780 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
14781 + return NETDEV_TX_OK;
14785 + tx_ring->last_tx_tso = 1;
14786 + tx_flags |= E1000_TX_FLAGS_TSO;
14787 + } else if (e1000_tx_csum(adapter, skb)) {
14788 + tx_flags |= E1000_TX_FLAGS_CSUM;
14791 + /* Old method was to assume IPv4 packet by default if TSO was enabled.
14792 + * 82571 hardware supports TSO capabilities for IPv6 as well...
14793 + * no longer assume, we must. */
14794 + if (skb->protocol == htons(ETH_P_IP))
14795 + tx_flags |= E1000_TX_FLAGS_IPV4;
14797 + count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
14799 + /* handle pci_map_single() error in e1000_tx_map */
14800 + dev_kfree_skb_any(skb);
14801 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
14802 + return NETDEV_TX_BUSY;
14805 + e1000_tx_queue(adapter, tx_flags, count);
14807 + netdev->trans_start = jiffies;
14809 + /* Make sure there is space in the ring for the next send. */
14810 + e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2);
14812 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
14813 + return NETDEV_TX_OK;
14817 + * e1000_tx_timeout - Respond to a Tx Hang
14818 + * @netdev: network interface device structure
14820 +static void e1000_tx_timeout(struct net_device *netdev)
14822 + struct e1000_adapter *adapter = netdev_priv(netdev);
14824 + /* Do the reset outside of interrupt context */
14825 + adapter->tx_timeout_count++;
14826 + schedule_work(&adapter->reset_task);
14829 +static void e1000_reset_task(struct work_struct *work)
14831 + struct e1000_adapter *adapter;
14832 + adapter = container_of(work, struct e1000_adapter, reset_task);
14834 + e1000e_reinit_locked(adapter);
14838 + * e1000_get_stats - Get System Network Statistics
14839 + * @netdev: network interface device structure
14841 + * Returns the address of the device statistics structure.
14842 + * The statistics are actually updated from the timer callback.
14844 +static struct net_device_stats *e1000_get_stats(struct net_device *netdev)
14846 + struct e1000_adapter *adapter = netdev_priv(netdev);
14848 + /* only return the current stats */
14849 + return &adapter->net_stats;
14853 + * e1000_change_mtu - Change the Maximum Transfer Unit
14854 + * @netdev: network interface device structure
14855 + * @new_mtu: new value for maximum frame size
14857 + * Returns 0 on success, negative on failure
14859 +static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
14861 + struct e1000_adapter *adapter = netdev_priv(netdev);
14862 + int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
14864 + if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
14865 + (max_frame > MAX_JUMBO_FRAME_SIZE)) {
14866 + ndev_err(netdev, "Invalid MTU setting\n");
14870 + /* Jumbo frame size limits */
14871 + if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
14872 + if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
14873 + ndev_err(netdev, "Jumbo Frames not supported.\n");
14876 + if (adapter->hw.phy.type == e1000_phy_ife) {
14877 + ndev_err(netdev, "Jumbo Frames not supported.\n");
14882 +#define MAX_STD_JUMBO_FRAME_SIZE 9234
14883 + if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
14884 + ndev_err(netdev, "MTU > 9216 not supported.\n");
14888 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
14890 + /* e1000e_down has a dependency on max_frame_size */
14891 + adapter->hw.mac.max_frame_size = max_frame;
14892 + if (netif_running(netdev))
14893 + e1000e_down(adapter);
14895 + /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
14896 + * means we reserve 2 more, this pushes us to allocate from the next
14897 + * larger slab size.
14898 + * i.e. RXBUFFER_2048 --> size-4096 slab
14899 + * however with the new *_jumbo* routines, jumbo receives will use
14900 + * fragmented skbs */
14902 + if (max_frame <= 256)
14903 + adapter->rx_buffer_len = 256;
14904 + else if (max_frame <= 512)
14905 + adapter->rx_buffer_len = 512;
14906 + else if (max_frame <= 1024)
14907 + adapter->rx_buffer_len = 1024;
14908 + else if (max_frame <= 2048)
14909 + adapter->rx_buffer_len = 2048;
14911 + adapter->rx_buffer_len = 4096;
14913 + /* adjust allocation if LPE protects us, and we aren't using SBP */
14914 + if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
14915 + (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
14916 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
14919 + ndev_info(netdev, "changing MTU from %d to %d\n",
14920 + netdev->mtu, new_mtu);
14921 + netdev->mtu = new_mtu;
14923 + if (netif_running(netdev))
14924 + e1000e_up(adapter);
14926 + e1000e_reset(adapter);
14928 + clear_bit(__E1000_RESETTING, &adapter->state);
14933 +static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
14936 + struct e1000_adapter *adapter = netdev_priv(netdev);
14937 + struct mii_ioctl_data *data = if_mii(ifr);
14938 + unsigned long irq_flags;
14940 + if (adapter->hw.media_type != e1000_media_type_copper)
14941 + return -EOPNOTSUPP;
14944 + case SIOCGMIIPHY:
14945 + data->phy_id = adapter->hw.phy.addr;
14947 + case SIOCGMIIREG:
14948 + if (!capable(CAP_NET_ADMIN))
14950 + spin_lock_irqsave(&adapter->stats_lock, irq_flags);
14951 + if (e1e_rphy(&adapter->hw, data->reg_num & 0x1F,
14952 + &data->val_out)) {
14953 + spin_unlock_irqrestore(&adapter->stats_lock, irq_flags);
14956 + spin_unlock_irqrestore(&adapter->stats_lock, irq_flags);
14958 + case SIOCSMIIREG:
14960 + return -EOPNOTSUPP;
14965 +static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
14968 + case SIOCGMIIPHY:
14969 + case SIOCGMIIREG:
14970 + case SIOCSMIIREG:
14971 + return e1000_mii_ioctl(netdev, ifr, cmd);
14973 + return -EOPNOTSUPP;
14977 +static int e1000_suspend(struct pci_dev *pdev, pm_message_t state)
14979 + struct net_device *netdev = pci_get_drvdata(pdev);
14980 + struct e1000_adapter *adapter = netdev_priv(netdev);
14981 + struct e1000_hw *hw = &adapter->hw;
14982 + u32 ctrl, ctrl_ext, rctl, status;
14983 + u32 wufc = adapter->wol;
14986 + netif_device_detach(netdev);
14988 + if (netif_running(netdev)) {
14989 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
14990 + e1000e_down(adapter);
14991 + e1000_free_irq(adapter);
14994 + retval = pci_save_state(pdev);
14998 + status = er32(STATUS);
14999 + if (status & E1000_STATUS_LU)
15000 + wufc &= ~E1000_WUFC_LNKC;
15003 + e1000_setup_rctl(adapter);
15004 + e1000_set_multi(netdev);
15006 + /* turn on all-multi mode if wake on multicast is enabled */
15007 + if (wufc & E1000_WUFC_MC) {
15008 + rctl = er32(RCTL);
15009 + rctl |= E1000_RCTL_MPE;
15010 + ew32(RCTL, rctl);
15013 + ctrl = er32(CTRL);
15014 + /* advertise wake from D3Cold */
15015 + #define E1000_CTRL_ADVD3WUC 0x00100000
15016 + /* phy power management enable */
15017 + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
15018 + ctrl |= E1000_CTRL_ADVD3WUC |
15019 + E1000_CTRL_EN_PHY_PWR_MGMT;
15020 + ew32(CTRL, ctrl);
15022 + if (adapter->hw.media_type == e1000_media_type_fiber ||
15023 + adapter->hw.media_type == e1000_media_type_internal_serdes) {
15024 + /* keep the laser running in D3 */
15025 + ctrl_ext = er32(CTRL_EXT);
15026 + ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
15027 + ew32(CTRL_EXT, ctrl_ext);
15030 + /* Allow time for pending master requests to run */
15031 + e1000e_disable_pcie_master(&adapter->hw);
15033 + ew32(WUC, E1000_WUC_PME_EN);
15034 + ew32(WUFC, wufc);
15035 + pci_enable_wake(pdev, PCI_D3hot, 1);
15036 + pci_enable_wake(pdev, PCI_D3cold, 1);
15040 + pci_enable_wake(pdev, PCI_D3hot, 0);
15041 + pci_enable_wake(pdev, PCI_D3cold, 0);
15044 + e1000_release_manageability(adapter);
15046 + /* make sure adapter isn't asleep if manageability is enabled */
15047 + if (adapter->flags & FLAG_MNG_PT_ENABLED) {
15048 + pci_enable_wake(pdev, PCI_D3hot, 1);
15049 + pci_enable_wake(pdev, PCI_D3cold, 1);
15052 + if (adapter->hw.phy.type == e1000_phy_igp_3)
15053 + e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
15055 + /* Release control of h/w to f/w. If f/w is AMT enabled, this
15056 + * would have already happened in close and is redundant. */
15057 + e1000_release_hw_control(adapter);
15059 + pci_disable_device(pdev);
15061 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
15067 +static int e1000_resume(struct pci_dev *pdev)
15069 + struct net_device *netdev = pci_get_drvdata(pdev);
15070 + struct e1000_adapter *adapter = netdev_priv(netdev);
15071 + struct e1000_hw *hw = &adapter->hw;
15074 + pci_set_power_state(pdev, PCI_D0);
15075 + pci_restore_state(pdev);
15076 + err = pci_enable_device(pdev);
15078 + dev_err(&pdev->dev,
15079 + "Cannot enable PCI device from suspend\n");
15083 + pci_set_master(pdev);
15085 + pci_enable_wake(pdev, PCI_D3hot, 0);
15086 + pci_enable_wake(pdev, PCI_D3cold, 0);
15088 + if (netif_running(netdev)) {
15089 + err = e1000_request_irq(adapter);
15094 + e1000e_power_up_phy(adapter);
15095 + e1000e_reset(adapter);
15098 + e1000_init_manageability(adapter);
15100 + if (netif_running(netdev))
15101 + e1000e_up(adapter);
15103 + netif_device_attach(netdev);
15105 + /* If the controller has AMT, do not set DRV_LOAD until the interface
15106 + * is up. For all other cases, let the f/w know that the h/w is now
15107 + * under the control of the driver. */
15108 + if (!(adapter->flags & FLAG_HAS_AMT) || !e1000e_check_mng_mode(&adapter->hw))
15109 + e1000_get_hw_control(adapter);
15115 +static void e1000_shutdown(struct pci_dev *pdev)
15117 + e1000_suspend(pdev, PMSG_SUSPEND);
15120 +#ifdef CONFIG_NET_POLL_CONTROLLER
15122 + * Polling 'interrupt' - used by things like netconsole to send skbs
15123 + * without having to re-enable interrupts. It's not called while
15124 + * the interrupt routine is executing.
15126 +static void e1000_netpoll(struct net_device *netdev)
15128 + struct e1000_adapter *adapter = netdev_priv(netdev);
15130 + disable_irq(adapter->pdev->irq);
15131 + e1000_intr(adapter->pdev->irq, netdev);
15133 + e1000_clean_tx_irq(adapter);
15135 + enable_irq(adapter->pdev->irq);
15140 + * e1000_io_error_detected - called when PCI error is detected
15141 + * @pdev: Pointer to PCI device
15142 + * @state: The current pci connection state
15144 + * This function is called after a PCI bus error affecting
15145 + * this device has been detected.
15147 +static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
15148 + pci_channel_state_t state)
15150 + struct net_device *netdev = pci_get_drvdata(pdev);
15151 + struct e1000_adapter *adapter = netdev_priv(netdev);
15153 + netif_device_detach(netdev);
15155 + if (netif_running(netdev))
15156 + e1000e_down(adapter);
15157 + pci_disable_device(pdev);
15159 + /* Request a slot slot reset. */
15160 + return PCI_ERS_RESULT_NEED_RESET;
15164 + * e1000_io_slot_reset - called after the pci bus has been reset.
15165 + * @pdev: Pointer to PCI device
15167 + * Restart the card from scratch, as if from a cold-boot. Implementation
15168 + * resembles the first-half of the e1000_resume routine.
15170 +static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
15172 + struct net_device *netdev = pci_get_drvdata(pdev);
15173 + struct e1000_adapter *adapter = netdev_priv(netdev);
15174 + struct e1000_hw *hw = &adapter->hw;
15176 + if (pci_enable_device(pdev)) {
15177 + dev_err(&pdev->dev,
15178 + "Cannot re-enable PCI device after reset.\n");
15179 + return PCI_ERS_RESULT_DISCONNECT;
15181 + pci_set_master(pdev);
15183 + pci_enable_wake(pdev, PCI_D3hot, 0);
15184 + pci_enable_wake(pdev, PCI_D3cold, 0);
15186 + e1000e_reset(adapter);
15189 + return PCI_ERS_RESULT_RECOVERED;
15193 + * e1000_io_resume - called when traffic can start flowing again.
15194 + * @pdev: Pointer to PCI device
15196 + * This callback is called when the error recovery driver tells us that
15197 + * its OK to resume normal operation. Implementation resembles the
15198 + * second-half of the e1000_resume routine.
15200 +static void e1000_io_resume(struct pci_dev *pdev)
15202 + struct net_device *netdev = pci_get_drvdata(pdev);
15203 + struct e1000_adapter *adapter = netdev_priv(netdev);
15205 + e1000_init_manageability(adapter);
15207 + if (netif_running(netdev)) {
15208 + if (e1000e_up(adapter)) {
15209 + dev_err(&pdev->dev,
15210 + "can't bring device back up after reset\n");
15215 + netif_device_attach(netdev);
15217 + /* If the controller has AMT, do not set DRV_LOAD until the interface
15218 + * is up. For all other cases, let the f/w know that the h/w is now
15219 + * under the control of the driver. */
15220 + if (!(adapter->flags & FLAG_HAS_AMT) ||
15221 + !e1000e_check_mng_mode(&adapter->hw))
15222 + e1000_get_hw_control(adapter);
15226 +static void e1000_print_device_info(struct e1000_adapter *adapter)
15228 + struct e1000_hw *hw = &adapter->hw;
15229 + struct net_device *netdev = adapter->netdev;
15231 + /* print bus type/speed/width info */
15232 + ndev_info(netdev, "(PCI Express:2.5GB/s:%s) "
15233 + "%02x:%02x:%02x:%02x:%02x:%02x\n",
15235 + ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
15237 + /* MAC address */
15238 + netdev->dev_addr[0], netdev->dev_addr[1],
15239 + netdev->dev_addr[2], netdev->dev_addr[3],
15240 + netdev->dev_addr[4], netdev->dev_addr[5]);
15241 + ndev_info(netdev, "Intel(R) PRO/%s Network Connection\n",
15242 + (hw->phy.type == e1000_phy_ife)
15243 + ? "10/100" : "1000");
15247 + * e1000_probe - Device Initialization Routine
15248 + * @pdev: PCI device information struct
15249 + * @ent: entry in e1000_pci_tbl
15251 + * Returns 0 on success, negative on failure
15253 + * e1000_probe initializes an adapter identified by a pci_dev structure.
15254 + * The OS initialization, configuring of the adapter private structure,
15255 + * and a hardware reset occur.
15257 +static int __devinit e1000_probe(struct pci_dev *pdev,
15258 + const struct pci_device_id *ent)
15260 + struct net_device *netdev;
15261 + struct e1000_adapter *adapter;
15262 + struct e1000_hw *hw;
15263 + const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
15264 + unsigned long mmio_start, mmio_len;
15265 + unsigned long flash_start, flash_len;
15267 + static int cards_found;
15268 + int i, err, pci_using_dac;
15269 + u16 eeprom_data = 0;
15270 + u16 eeprom_apme_mask = E1000_EEPROM_APME;
15272 + err = pci_enable_device(pdev);
15276 + pci_using_dac = 0;
15277 + err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
15279 + err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
15281 + pci_using_dac = 1;
15283 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
15285 + err = pci_set_consistent_dma_mask(pdev,
15288 + dev_err(&pdev->dev, "No usable DMA "
15289 + "configuration, aborting\n");
15295 + err = pci_request_regions(pdev, e1000e_driver_name);
15297 + goto err_pci_reg;
15299 + pci_set_master(pdev);
15302 + netdev = alloc_etherdev(sizeof(struct e1000_adapter));
15304 + goto err_alloc_etherdev;
15306 + SET_MODULE_OWNER(netdev);
15307 + SET_NETDEV_DEV(netdev, &pdev->dev);
15309 + pci_set_drvdata(pdev, netdev);
15310 + adapter = netdev_priv(netdev);
15311 + hw = &adapter->hw;
15312 + adapter->netdev = netdev;
15313 + adapter->pdev = pdev;
15314 + adapter->ei = ei;
15315 + adapter->pba = ei->pba;
15316 + adapter->flags = ei->flags;
15317 + adapter->hw.adapter = adapter;
15318 + adapter->hw.mac.type = ei->mac;
15319 + adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
15321 + mmio_start = pci_resource_start(pdev, 0);
15322 + mmio_len = pci_resource_len(pdev, 0);
15325 + adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
15326 + if (!adapter->hw.hw_addr)
15327 + goto err_ioremap;
15329 + if ((adapter->flags & FLAG_HAS_FLASH) &&
15330 + (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
15331 + flash_start = pci_resource_start(pdev, 1);
15332 + flash_len = pci_resource_len(pdev, 1);
15333 + adapter->hw.flash_address = ioremap(flash_start, flash_len);
15334 + if (!adapter->hw.flash_address)
15335 + goto err_flashmap;
15338 + /* construct the net_device struct */
15339 + netdev->open = &e1000_open;
15340 + netdev->stop = &e1000_close;
15341 + netdev->hard_start_xmit = &e1000_xmit_frame;
15342 + netdev->get_stats = &e1000_get_stats;
15343 + netdev->set_multicast_list = &e1000_set_multi;
15344 + netdev->set_mac_address = &e1000_set_mac;
15345 + netdev->change_mtu = &e1000_change_mtu;
15346 + netdev->do_ioctl = &e1000_ioctl;
15347 + e1000e_set_ethtool_ops(netdev);
15348 + netdev->tx_timeout = &e1000_tx_timeout;
15349 + netdev->watchdog_timeo = 5 * HZ;
15350 + netdev->poll = &e1000_clean;
15351 + netdev->weight = 64;
15352 + netdev->vlan_rx_register = e1000_vlan_rx_register;
15353 + netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
15354 + netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
15355 +#ifdef CONFIG_NET_POLL_CONTROLLER
15356 + netdev->poll_controller = e1000_netpoll;
15358 + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
15360 + netdev->mem_start = mmio_start;
15361 + netdev->mem_end = mmio_start + mmio_len;
15363 + adapter->bd_number = cards_found++;
15365 + /* setup adapter struct */
15366 + err = e1000_sw_init(adapter);
15368 + goto err_sw_init;
15372 + memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
15373 + memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
15374 + memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
15376 + err = ei->get_invariants(adapter);
15378 + goto err_hw_init;
15380 + hw->mac.ops.get_bus_info(&adapter->hw);
15382 + adapter->hw.phy.wait_for_link = 0;
15384 + /* Copper options */
15385 + if (adapter->hw.media_type == e1000_media_type_copper) {
15386 + adapter->hw.phy.mdix = AUTO_ALL_MODES;
15387 + adapter->hw.phy.disable_polarity_correction = 0;
15388 + adapter->hw.phy.ms_type = e1000_ms_hw_default;
15391 + if (e1000_check_reset_block(&adapter->hw))
15392 + ndev_info(netdev,
15393 + "PHY reset is blocked due to SOL/IDER session.\n");
15395 + netdev->features = NETIF_F_SG |
15396 + NETIF_F_HW_CSUM |
15397 + NETIF_F_HW_VLAN_TX |
15398 + NETIF_F_HW_VLAN_RX;
15400 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
15401 + netdev->features |= NETIF_F_HW_VLAN_FILTER;
15403 + netdev->features |= NETIF_F_TSO;
15404 + netdev->features |= NETIF_F_TSO6;
15406 + if (pci_using_dac)
15407 + netdev->features |= NETIF_F_HIGHDMA;
15409 + /* We should not be using LLTX anymore, but we are still TX faster with
15411 + netdev->features |= NETIF_F_LLTX;
15413 + if (e1000e_enable_mng_pass_thru(&adapter->hw))
15414 + adapter->flags |= FLAG_MNG_PT_ENABLED;
15416 + /* before reading the NVM, reset the controller to
15417 + * put the device in a known good starting state */
15418 + adapter->hw.mac.ops.reset_hw(&adapter->hw);
15421 + * systems with ASPM and others may see the checksum fail on the first
15422 + * attempt. Let's give it a few tries
15424 + for (i = 0;; i++) {
15425 + if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
15428 + ndev_err(netdev, "The NVM Checksum Is Not Valid\n");
15434 + /* copy the MAC address out of the NVM */
15435 + if (e1000e_read_mac_addr(&adapter->hw))
15436 + ndev_err(netdev, "NVM Read Error while reading MAC address\n");
15438 + memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
15439 + memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
15441 + if (!is_valid_ether_addr(netdev->perm_addr)) {
15442 + ndev_err(netdev, "Invalid MAC Address: "
15443 + "%02x:%02x:%02x:%02x:%02x:%02x\n",
15444 + netdev->perm_addr[0], netdev->perm_addr[1],
15445 + netdev->perm_addr[2], netdev->perm_addr[3],
15446 + netdev->perm_addr[4], netdev->perm_addr[5]);
15451 + init_timer(&adapter->watchdog_timer);
15452 + adapter->watchdog_timer.function = &e1000_watchdog;
15453 + adapter->watchdog_timer.data = (unsigned long) adapter;
15455 + init_timer(&adapter->phy_info_timer);
15456 + adapter->phy_info_timer.function = &e1000_update_phy_info;
15457 + adapter->phy_info_timer.data = (unsigned long) adapter;
15459 + INIT_WORK(&adapter->reset_task, e1000_reset_task);
15460 + INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
15462 + e1000e_check_options(adapter);
15464 + /* Initialize link parameters. User can change them with ethtool */
15465 + adapter->hw.mac.autoneg = 1;
15466 + adapter->hw.mac.original_fc = e1000_fc_default;
15467 + adapter->hw.mac.fc = e1000_fc_default;
15468 + adapter->hw.phy.autoneg_advertised = 0x2f;
15470 + /* ring size defaults */
15471 + adapter->rx_ring->count = 256;
15472 + adapter->tx_ring->count = 256;
15475 + * Initial Wake on LAN setting - If APM wake is enabled in
15476 + * the EEPROM, enable the ACPI Magic Packet filter
15478 + if (adapter->flags & FLAG_APME_IN_WUC) {
15479 + /* APME bit in EEPROM is mapped to WUC.APME */
15480 + eeprom_data = er32(WUC);
15481 + eeprom_apme_mask = E1000_WUC_APME;
15482 + } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
15483 + if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
15484 + (adapter->hw.bus.func == 1))
15485 + e1000_read_nvm(&adapter->hw,
15486 + NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
15488 + e1000_read_nvm(&adapter->hw,
15489 + NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
15492 + /* fetch WoL from EEPROM */
15493 + if (eeprom_data & eeprom_apme_mask)
15494 + adapter->eeprom_wol |= E1000_WUFC_MAG;
15497 + * now that we have the eeprom settings, apply the special cases
15498 + * where the eeprom may be wrong or the board simply won't support
15499 + * wake on lan on a particular port
15501 + if (!(adapter->flags & FLAG_HAS_WOL))
15502 + adapter->eeprom_wol = 0;
15504 + /* initialize the wol settings based on the eeprom settings */
15505 + adapter->wol = adapter->eeprom_wol;
15507 + /* reset the hardware with the new settings */
15508 + e1000e_reset(adapter);
15510 + /* If the controller has AMT, do not set DRV_LOAD until the interface
15511 + * is up. For all other cases, let the f/w know that the h/w is now
15512 + * under the control of the driver. */
15513 + if (!(adapter->flags & FLAG_HAS_AMT) ||
15514 + !e1000e_check_mng_mode(&adapter->hw))
15515 + e1000_get_hw_control(adapter);
15517 + /* tell the stack to leave us alone until e1000_open() is called */
15518 + netif_carrier_off(netdev);
15519 + netif_stop_queue(netdev);
15520 + netif_poll_disable(netdev);
15522 + strcpy(netdev->name, "eth%d");
15523 + err = register_netdev(netdev);
15525 + goto err_register;
15527 + e1000_print_device_info(adapter);
15533 + e1000_release_hw_control(adapter);
15535 + if (!e1000_check_reset_block(&adapter->hw))
15536 + e1000_phy_hw_reset(&adapter->hw);
15538 + if (adapter->hw.flash_address)
15539 + iounmap(adapter->hw.flash_address);
15542 + kfree(adapter->tx_ring);
15543 + kfree(adapter->rx_ring);
15545 + iounmap(adapter->hw.hw_addr);
15547 + free_netdev(netdev);
15548 +err_alloc_etherdev:
15549 + pci_release_regions(pdev);
15552 + pci_disable_device(pdev);
15557 + * e1000_remove - Device Removal Routine
15558 + * @pdev: PCI device information struct
15560 + * e1000_remove is called by the PCI subsystem to alert the driver
15561 + * that it should release a PCI device. The could be caused by a
15562 + * Hot-Plug event, or because the driver is going to be removed from
15565 +static void __devexit e1000_remove(struct pci_dev *pdev)
15567 + struct net_device *netdev = pci_get_drvdata(pdev);
15568 + struct e1000_adapter *adapter = netdev_priv(netdev);
15570 + /* flush_scheduled work may reschedule our watchdog task, so
15571 + * explicitly disable watchdog tasks from being rescheduled */
15572 + set_bit(__E1000_DOWN, &adapter->state);
15573 + del_timer_sync(&adapter->watchdog_timer);
15574 + del_timer_sync(&adapter->phy_info_timer);
15576 + flush_scheduled_work();
15578 + e1000_release_manageability(adapter);
15580 + /* Release control of h/w to f/w. If f/w is AMT enabled, this
15581 + * would have already happened in close and is redundant. */
15582 + e1000_release_hw_control(adapter);
15584 + unregister_netdev(netdev);
15586 + if (!e1000_check_reset_block(&adapter->hw))
15587 + e1000_phy_hw_reset(&adapter->hw);
15589 + kfree(adapter->tx_ring);
15590 + kfree(adapter->rx_ring);
15592 + iounmap(adapter->hw.hw_addr);
15593 + if (adapter->hw.flash_address)
15594 + iounmap(adapter->hw.flash_address);
15595 + pci_release_regions(pdev);
15597 + free_netdev(netdev);
15599 + pci_disable_device(pdev);
15602 +/* PCI Error Recovery (ERS) */
15603 +static struct pci_error_handlers e1000_err_handler = {
15604 + .error_detected = e1000_io_error_detected,
15605 + .slot_reset = e1000_io_slot_reset,
15606 + .resume = e1000_io_resume,
15609 +static struct pci_device_id e1000_pci_tbl[] = {
15611 + * Support for 82571/2/3, es2lan and ich8 will be phased in
15614 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
15615 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
15616 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
15617 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
15618 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
15619 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
15620 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
15621 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
15622 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
15623 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
15624 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
15625 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
15626 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
15627 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
15628 + board_80003es2lan },
15629 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
15630 + board_80003es2lan },
15631 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
15632 + board_80003es2lan },
15633 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
15634 + board_80003es2lan },
15635 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
15636 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
15637 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
15638 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
15639 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
15640 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
15641 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
15644 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
15645 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
15646 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
15647 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
15648 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
15650 + { } /* terminate list */
15652 +MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
15654 +/* PCI Device API Driver */
15655 +static struct pci_driver e1000_driver = {
15656 + .name = e1000e_driver_name,
15657 + .id_table = e1000_pci_tbl,
15658 + .probe = e1000_probe,
15659 + .remove = __devexit_p(e1000_remove),
15661 + /* Power Managment Hooks */
15662 + .suspend = e1000_suspend,
15663 + .resume = e1000_resume,
15665 + .shutdown = e1000_shutdown,
15666 + .err_handler = &e1000_err_handler
15670 + * e1000_init_module - Driver Registration Routine
15672 + * e1000_init_module is the first routine called when the driver is
15673 + * loaded. All it does is register with the PCI subsystem.
15675 +static int __init e1000_init_module(void)
15678 + printk(KERN_INFO "Intel(R) PRO/1000 Network Driver - %s\n",
15679 + e1000e_driver_version);
15680 + printk(KERN_INFO "Copyright (c) 1999-2007 Intel Corporation.\n");
15681 + ret = pci_register_driver(&e1000_driver);
15685 +module_init(e1000_init_module);
15688 + * e1000_exit_module - Driver Exit Cleanup Routine
15690 + * e1000_exit_module is called just before the driver is removed
15693 +static void __exit e1000_exit_module(void)
15695 + pci_unregister_driver(&e1000_driver);
15697 +module_exit(e1000_exit_module);
15700 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
15701 +MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
15702 +MODULE_LICENSE("GPL");
15703 +MODULE_VERSION(DRV_VERSION);
15705 +/* e1000_main.c */
15706 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/param.c linux-2.6.22-10/drivers/net/e1000e/param.c
15707 --- linux-2.6.22-0/drivers/net/e1000e/param.c 1969-12-31 19:00:00.000000000 -0500
15708 +++ linux-2.6.22-10/drivers/net/e1000e/param.c 2007-11-21 13:55:28.000000000 -0500
15710 +/*******************************************************************************
15712 + Intel PRO/1000 Linux driver
15713 + Copyright(c) 1999 - 2007 Intel Corporation.
15715 + This program is free software; you can redistribute it and/or modify it
15716 + under the terms and conditions of the GNU General Public License,
15717 + version 2, as published by the Free Software Foundation.
15719 + This program is distributed in the hope it will be useful, but WITHOUT
15720 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15721 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15724 + You should have received a copy of the GNU General Public License along with
15725 + this program; if not, write to the Free Software Foundation, Inc.,
15726 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
15728 + The full GNU General Public License is included in this distribution in
15729 + the file called "COPYING".
15731 + Contact Information:
15732 + Linux NICS <linux.nics@intel.com>
15733 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
15734 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15736 +*******************************************************************************/
15738 +#include <linux/netdevice.h>
15740 +#include "e1000.h"
15742 +/* This is the only thing that needs to be changed to adjust the
15743 + * maximum number of ports that the driver can manage.
15746 +#define E1000_MAX_NIC 32
15748 +#define OPTION_UNSET -1
15749 +#define OPTION_DISABLED 0
15750 +#define OPTION_ENABLED 1
15752 +#define COPYBREAK_DEFAULT 256
15753 +unsigned int copybreak = COPYBREAK_DEFAULT;
15754 +module_param(copybreak, uint, 0644);
15755 +MODULE_PARM_DESC(copybreak,
15756 + "Maximum size of packet that is copied to a new buffer on receive");
15758 +/* All parameters are treated the same, as an integer array of values.
15759 + * This macro just reduces the need to repeat the same declaration code
15760 + * over and over (plus this helps to avoid typo bugs).
15763 +#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
15764 +#define E1000_PARAM(X, desc) \
15765 + static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
15766 + static int num_##X; \
15767 + module_param_array_named(X, X, int, &num_##X, 0); \
15768 + MODULE_PARM_DESC(X, desc);
15771 +/* Transmit Interrupt Delay in units of 1.024 microseconds
15772 + * Tx interrupt delay needs to typically be set to something non zero
15774 + * Valid Range: 0-65535
15776 +E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
15777 +#define DEFAULT_TIDV 8
15778 +#define MAX_TXDELAY 0xFFFF
15779 +#define MIN_TXDELAY 0
15781 +/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
15783 + * Valid Range: 0-65535
15785 +E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
15786 +#define DEFAULT_TADV 32
15787 +#define MAX_TXABSDELAY 0xFFFF
15788 +#define MIN_TXABSDELAY 0
15790 +/* Receive Interrupt Delay in units of 1.024 microseconds
15791 + * hardware will likely hang if you set this to anything but zero.
15793 + * Valid Range: 0-65535
15795 +E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
15796 +#define DEFAULT_RDTR 0
15797 +#define MAX_RXDELAY 0xFFFF
15798 +#define MIN_RXDELAY 0
15800 +/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
15802 + * Valid Range: 0-65535
15804 +E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
15805 +#define DEFAULT_RADV 8
15806 +#define MAX_RXABSDELAY 0xFFFF
15807 +#define MIN_RXABSDELAY 0
15809 +/* Interrupt Throttle Rate (interrupts/sec)
15811 + * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
15813 +E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
15814 +#define DEFAULT_ITR 3
15815 +#define MAX_ITR 100000
15816 +#define MIN_ITR 100
15818 +/* Enable Smart Power Down of the PHY
15820 + * Valid Range: 0, 1
15822 + * Default Value: 0 (disabled)
15824 +E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
15826 +/* Enable Kumeran Lock Loss workaround
15828 + * Valid Range: 0, 1
15830 + * Default Value: 1 (enabled)
15832 +E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
15834 +struct e1000_option {
15835 + enum { enable_option, range_option, list_option } type;
15840 + struct { /* range_option info */
15844 + struct { /* list_option info */
15846 + struct e1000_opt_list { int i; char *str; } *p;
15851 +static int __devinit e1000_validate_option(int *value,
15852 + struct e1000_option *opt,
15853 + struct e1000_adapter *adapter)
15855 + if (*value == OPTION_UNSET) {
15856 + *value = opt->def;
15860 + switch (opt->type) {
15861 + case enable_option:
15862 + switch (*value) {
15863 + case OPTION_ENABLED:
15864 + ndev_info(adapter->netdev, "%s Enabled\n", opt->name);
15866 + case OPTION_DISABLED:
15867 + ndev_info(adapter->netdev, "%s Disabled\n", opt->name);
15871 + case range_option:
15872 + if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
15873 + ndev_info(adapter->netdev,
15874 + "%s set to %i\n", opt->name, *value);
15878 + case list_option: {
15880 + struct e1000_opt_list *ent;
15882 + for (i = 0; i < opt->arg.l.nr; i++) {
15883 + ent = &opt->arg.l.p[i];
15884 + if (*value == ent->i) {
15885 + if (ent->str[0] != '\0')
15886 + ndev_info(adapter->netdev, "%s\n",
15897 + ndev_info(adapter->netdev, "Invalid %s value specified (%i) %s\n",
15898 + opt->name, *value, opt->err);
15899 + *value = opt->def;
15904 + * e1000e_check_options - Range Checking for Command Line Parameters
15905 + * @adapter: board private structure
15907 + * This routine checks all command line parameters for valid user
15908 + * input. If an invalid value is given, or if no user specified
15909 + * value exists, a default value is used. The final value is stored
15910 + * in a variable in the adapter structure.
15912 +void __devinit e1000e_check_options(struct e1000_adapter *adapter)
15914 + struct e1000_hw *hw = &adapter->hw;
15915 + struct net_device *netdev = adapter->netdev;
15916 + int bd = adapter->bd_number;
15918 + if (bd >= E1000_MAX_NIC) {
15919 + ndev_notice(netdev,
15920 + "Warning: no configuration for board #%i\n", bd);
15921 + ndev_notice(netdev, "Using defaults for all values\n");
15924 + { /* Transmit Interrupt Delay */
15925 + struct e1000_option opt = {
15926 + .type = range_option,
15927 + .name = "Transmit Interrupt Delay",
15928 + .err = "using default of "
15929 + __MODULE_STRING(DEFAULT_TIDV),
15930 + .def = DEFAULT_TIDV,
15931 + .arg = { .r = { .min = MIN_TXDELAY,
15932 + .max = MAX_TXDELAY } }
15935 + if (num_TxIntDelay > bd) {
15936 + adapter->tx_int_delay = TxIntDelay[bd];
15937 + e1000_validate_option(&adapter->tx_int_delay, &opt,
15940 + adapter->tx_int_delay = opt.def;
15943 + { /* Transmit Absolute Interrupt Delay */
15944 + struct e1000_option opt = {
15945 + .type = range_option,
15946 + .name = "Transmit Absolute Interrupt Delay",
15947 + .err = "using default of "
15948 + __MODULE_STRING(DEFAULT_TADV),
15949 + .def = DEFAULT_TADV,
15950 + .arg = { .r = { .min = MIN_TXABSDELAY,
15951 + .max = MAX_TXABSDELAY } }
15954 + if (num_TxAbsIntDelay > bd) {
15955 + adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
15956 + e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
15959 + adapter->tx_abs_int_delay = opt.def;
15962 + { /* Receive Interrupt Delay */
15963 + struct e1000_option opt = {
15964 + .type = range_option,
15965 + .name = "Receive Interrupt Delay",
15966 + .err = "using default of "
15967 + __MODULE_STRING(DEFAULT_RDTR),
15968 + .def = DEFAULT_RDTR,
15969 + .arg = { .r = { .min = MIN_RXDELAY,
15970 + .max = MAX_RXDELAY } }
15973 + /* modify min and default if 82573 for slow ping w/a,
15974 + * a value greater than 8 needs to be set for RDTR */
15975 + if (adapter->flags & FLAG_HAS_ASPM) {
15977 + opt.arg.r.min = 8;
15980 + if (num_RxIntDelay > bd) {
15981 + adapter->rx_int_delay = RxIntDelay[bd];
15982 + e1000_validate_option(&adapter->rx_int_delay, &opt,
15985 + adapter->rx_int_delay = opt.def;
15988 + { /* Receive Absolute Interrupt Delay */
15989 + struct e1000_option opt = {
15990 + .type = range_option,
15991 + .name = "Receive Absolute Interrupt Delay",
15992 + .err = "using default of "
15993 + __MODULE_STRING(DEFAULT_RADV),
15994 + .def = DEFAULT_RADV,
15995 + .arg = { .r = { .min = MIN_RXABSDELAY,
15996 + .max = MAX_RXABSDELAY } }
15999 + if (num_RxAbsIntDelay > bd) {
16000 + adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
16001 + e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
16004 + adapter->rx_abs_int_delay = opt.def;
16007 + { /* Interrupt Throttling Rate */
16008 + struct e1000_option opt = {
16009 + .type = range_option,
16010 + .name = "Interrupt Throttling Rate (ints/sec)",
16011 + .err = "using default of "
16012 + __MODULE_STRING(DEFAULT_ITR),
16013 + .def = DEFAULT_ITR,
16014 + .arg = { .r = { .min = MIN_ITR,
16015 + .max = MAX_ITR } }
16018 + if (num_InterruptThrottleRate > bd) {
16019 + adapter->itr = InterruptThrottleRate[bd];
16020 + switch (adapter->itr) {
16022 + ndev_info(netdev, "%s turned off\n",
16026 + ndev_info(netdev,
16027 + "%s set to dynamic mode\n",
16029 + adapter->itr_setting = adapter->itr;
16030 + adapter->itr = 20000;
16033 + ndev_info(netdev,
16034 + "%s set to dynamic conservative mode\n",
16036 + adapter->itr_setting = adapter->itr;
16037 + adapter->itr = 20000;
16040 + e1000_validate_option(&adapter->itr, &opt,
16043 + * save the setting, because the dynamic bits
16044 + * change itr. clear the lower two bits
16045 + * because they are used as control
16047 + adapter->itr_setting = adapter->itr & ~3;
16051 + adapter->itr_setting = opt.def;
16052 + adapter->itr = 20000;
16055 + { /* Smart Power Down */
16056 + struct e1000_option opt = {
16057 + .type = enable_option,
16058 + .name = "PHY Smart Power Down",
16059 + .err = "defaulting to Disabled",
16060 + .def = OPTION_DISABLED
16063 + if (num_SmartPowerDownEnable > bd) {
16064 + int spd = SmartPowerDownEnable[bd];
16065 + e1000_validate_option(&spd, &opt, adapter);
16066 + if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN)
16068 + adapter->flags |= FLAG_SMART_POWER_DOWN;
16071 + { /* Kumeran Lock Loss Workaround */
16072 + struct e1000_option opt = {
16073 + .type = enable_option,
16074 + .name = "Kumeran Lock Loss Workaround",
16075 + .err = "defaulting to Enabled",
16076 + .def = OPTION_ENABLED
16079 + if (num_KumeranLockLoss > bd) {
16080 + int kmrn_lock_loss = KumeranLockLoss[bd];
16081 + e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
16082 + if (hw->mac.type == e1000_ich8lan)
16083 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
16086 + if (hw->mac.type == e1000_ich8lan)
16087 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
16092 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/phy.c linux-2.6.22-10/drivers/net/e1000e/phy.c
16093 --- linux-2.6.22-0/drivers/net/e1000e/phy.c 1969-12-31 19:00:00.000000000 -0500
16094 +++ linux-2.6.22-10/drivers/net/e1000e/phy.c 2007-11-21 13:55:36.000000000 -0500
16096 +/*******************************************************************************
16098 + Intel PRO/1000 Linux driver
16099 + Copyright(c) 1999 - 2007 Intel Corporation.
16101 + This program is free software; you can redistribute it and/or modify it
16102 + under the terms and conditions of the GNU General Public License,
16103 + version 2, as published by the Free Software Foundation.
16105 + This program is distributed in the hope it will be useful, but WITHOUT
16106 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16107 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16110 + You should have received a copy of the GNU General Public License along with
16111 + this program; if not, write to the Free Software Foundation, Inc.,
16112 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16114 + The full GNU General Public License is included in this distribution in
16115 + the file called "COPYING".
16117 + Contact Information:
16118 + Linux NICS <linux.nics@intel.com>
16119 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
16120 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
16122 +*******************************************************************************/
16124 +#include <linux/delay.h>
16126 +#include "e1000.h"
16128 +static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
16129 +static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
16130 +static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
16131 +static s32 e1000_wait_autoneg(struct e1000_hw *hw);
16133 +/* Cable length tables */
16134 +static const u16 e1000_m88_cable_length_table[] =
16135 + { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
16137 +static const u16 e1000_igp_2_cable_length_table[] =
16138 + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
16139 + 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
16140 + 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
16141 + 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
16142 + 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
16143 + 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
16144 + 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
16146 +#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
16147 + (sizeof(e1000_igp_2_cable_length_table) / \
16148 + sizeof(e1000_igp_2_cable_length_table[0]))
16151 + * e1000e_check_reset_block_generic - Check if PHY reset is blocked
16152 + * @hw: pointer to the HW structure
16154 + * Read the PHY management control register and check whether a PHY reset
16155 + * is blocked. If a reset is not blocked return 0, otherwise
16156 + * return E1000_BLK_PHY_RESET (12).
16158 +s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
16162 + manc = er32(MANC);
16164 + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
16165 + E1000_BLK_PHY_RESET : 0;
16169 + * e1000e_get_phy_id - Retrieve the PHY ID and revision
16170 + * @hw: pointer to the HW structure
16172 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
16173 + * revision in the hardware structure.
16175 +s32 e1000e_get_phy_id(struct e1000_hw *hw)
16177 + struct e1000_phy_info *phy = &hw->phy;
16181 + ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
16185 + phy->id = (u32)(phy_id << 16);
16187 + ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
16191 + phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
16192 + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
16198 + * e1000e_phy_reset_dsp - Reset PHY DSP
16199 + * @hw: pointer to the HW structure
16201 + * Reset the digital signal processor.
16203 +s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
16207 + ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
16211 + return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
16215 + * e1000_read_phy_reg_mdic - Read MDI control register
16216 + * @hw: pointer to the HW structure
16217 + * @offset: register offset to be read
16218 + * @data: pointer to the read data
16220 + * Reads the MDI control regsiter in the PHY at offset and stores the
16221 + * information read to data.
16223 +static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
16225 + struct e1000_phy_info *phy = &hw->phy;
16228 + if (offset > MAX_PHY_REG_ADDRESS) {
16229 + hw_dbg(hw, "PHY Address %d is out of range\n", offset);
16230 + return -E1000_ERR_PARAM;
16233 + /* Set up Op-code, Phy Address, and register offset in the MDI
16234 + * Control register. The MAC will take care of interfacing with the
16235 + * PHY to retrieve the desired data.
16237 + mdic = ((offset << E1000_MDIC_REG_SHIFT) |
16238 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
16239 + (E1000_MDIC_OP_READ));
16241 + ew32(MDIC, mdic);
16243 + /* Poll the ready bit to see if the MDI read completed */
16244 + for (i = 0; i < 64; i++) {
16246 + mdic = er32(MDIC);
16247 + if (mdic & E1000_MDIC_READY)
16250 + if (!(mdic & E1000_MDIC_READY)) {
16251 + hw_dbg(hw, "MDI Read did not complete\n");
16252 + return -E1000_ERR_PHY;
16254 + if (mdic & E1000_MDIC_ERROR) {
16255 + hw_dbg(hw, "MDI Error\n");
16256 + return -E1000_ERR_PHY;
16258 + *data = (u16) mdic;
16264 + * e1000_write_phy_reg_mdic - Write MDI control register
16265 + * @hw: pointer to the HW structure
16266 + * @offset: register offset to write to
16267 + * @data: data to write to register at offset
16269 + * Writes data to MDI control register in the PHY at offset.
16271 +static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
16273 + struct e1000_phy_info *phy = &hw->phy;
16276 + if (offset > MAX_PHY_REG_ADDRESS) {
16277 + hw_dbg(hw, "PHY Address %d is out of range\n", offset);
16278 + return -E1000_ERR_PARAM;
16281 + /* Set up Op-code, Phy Address, and register offset in the MDI
16282 + * Control register. The MAC will take care of interfacing with the
16283 + * PHY to retrieve the desired data.
16285 + mdic = (((u32)data) |
16286 + (offset << E1000_MDIC_REG_SHIFT) |
16287 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
16288 + (E1000_MDIC_OP_WRITE));
16290 + ew32(MDIC, mdic);
16292 + /* Poll the ready bit to see if the MDI read completed */
16293 + for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
16295 + mdic = er32(MDIC);
16296 + if (mdic & E1000_MDIC_READY)
16299 + if (!(mdic & E1000_MDIC_READY)) {
16300 + hw_dbg(hw, "MDI Write did not complete\n");
16301 + return -E1000_ERR_PHY;
16308 + * e1000e_read_phy_reg_m88 - Read m88 PHY register
16309 + * @hw: pointer to the HW structure
16310 + * @offset: register offset to be read
16311 + * @data: pointer to the read data
16313 + * Acquires semaphore, if necessary, then reads the PHY register at offset
16314 + * and storing the retrieved information in data. Release any acquired
16315 + * semaphores before exiting.
16317 +s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
16321 + ret_val = hw->phy.ops.acquire_phy(hw);
16325 + ret_val = e1000_read_phy_reg_mdic(hw,
16326 + MAX_PHY_REG_ADDRESS & offset,
16329 + hw->phy.ops.release_phy(hw);
16335 + * e1000e_write_phy_reg_m88 - Write m88 PHY register
16336 + * @hw: pointer to the HW structure
16337 + * @offset: register offset to write to
16338 + * @data: data to write at register offset
16340 + * Acquires semaphore, if necessary, then writes the data to PHY register
16341 + * at the offset. Release any acquired semaphores before exiting.
16343 +s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
16347 + ret_val = hw->phy.ops.acquire_phy(hw);
16351 + ret_val = e1000_write_phy_reg_mdic(hw,
16352 + MAX_PHY_REG_ADDRESS & offset,
16355 + hw->phy.ops.release_phy(hw);
16361 + * e1000e_read_phy_reg_igp - Read igp PHY register
16362 + * @hw: pointer to the HW structure
16363 + * @offset: register offset to be read
16364 + * @data: pointer to the read data
16366 + * Acquires semaphore, if necessary, then reads the PHY register at offset
16367 + * and storing the retrieved information in data. Release any acquired
16368 + * semaphores before exiting.
16370 +s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
16374 + ret_val = hw->phy.ops.acquire_phy(hw);
16378 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
16379 + ret_val = e1000_write_phy_reg_mdic(hw,
16380 + IGP01E1000_PHY_PAGE_SELECT,
16383 + hw->phy.ops.release_phy(hw);
16388 + ret_val = e1000_read_phy_reg_mdic(hw,
16389 + MAX_PHY_REG_ADDRESS & offset,
16392 + hw->phy.ops.release_phy(hw);
16398 + * e1000e_write_phy_reg_igp - Write igp PHY register
16399 + * @hw: pointer to the HW structure
16400 + * @offset: register offset to write to
16401 + * @data: data to write at register offset
16403 + * Acquires semaphore, if necessary, then writes the data to PHY register
16404 + * at the offset. Release any acquired semaphores before exiting.
16406 +s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
16410 + ret_val = hw->phy.ops.acquire_phy(hw);
16414 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
16415 + ret_val = e1000_write_phy_reg_mdic(hw,
16416 + IGP01E1000_PHY_PAGE_SELECT,
16419 + hw->phy.ops.release_phy(hw);
16424 + ret_val = e1000_write_phy_reg_mdic(hw,
16425 + MAX_PHY_REG_ADDRESS & offset,
16428 + hw->phy.ops.release_phy(hw);
16434 + * e1000e_read_kmrn_reg - Read kumeran register
16435 + * @hw: pointer to the HW structure
16436 + * @offset: register offset to be read
16437 + * @data: pointer to the read data
16439 + * Acquires semaphore, if necessary. Then reads the PHY register at offset
16440 + * using the kumeran interface. The information retrieved is stored in data.
16441 + * Release any acquired semaphores before exiting.
16443 +s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
16448 + ret_val = hw->phy.ops.acquire_phy(hw);
16452 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
16453 + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
16454 + ew32(KMRNCTRLSTA, kmrnctrlsta);
16458 + kmrnctrlsta = er32(KMRNCTRLSTA);
16459 + *data = (u16)kmrnctrlsta;
16461 + hw->phy.ops.release_phy(hw);
16467 + * e1000e_write_kmrn_reg - Write kumeran register
16468 + * @hw: pointer to the HW structure
16469 + * @offset: register offset to write to
16470 + * @data: data to write at register offset
16472 + * Acquires semaphore, if necessary. Then write the data to PHY register
16473 + * at the offset using the kumeran interface. Release any acquired semaphores
16474 + * before exiting.
16476 +s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
16481 + ret_val = hw->phy.ops.acquire_phy(hw);
16485 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
16486 + E1000_KMRNCTRLSTA_OFFSET) | data;
16487 + ew32(KMRNCTRLSTA, kmrnctrlsta);
16490 + hw->phy.ops.release_phy(hw);
16496 + * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
16497 + * @hw: pointer to the HW structure
16499 + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
16500 + * and downshift values are set also.
16502 +s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
16504 + struct e1000_phy_info *phy = &hw->phy;
16508 + /* Enable CRS on TX. This must be set for half-duplex operation. */
16509 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
16513 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
16516 + * MDI/MDI-X = 0 (default)
16517 + * 0 - Auto for all speeds
16520 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
16522 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
16524 + switch (phy->mdix) {
16526 + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
16529 + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
16532 + phy_data |= M88E1000_PSCR_AUTO_X_1000T;
16536 + phy_data |= M88E1000_PSCR_AUTO_X_MODE;
16541 + * disable_polarity_correction = 0 (default)
16542 + * Automatic Correction for Reversed Cable Polarity
16546 + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
16547 + if (phy->disable_polarity_correction == 1)
16548 + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
16550 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
16554 + if (phy->revision < 4) {
16555 + /* Force TX_CLK in the Extended PHY Specific Control Register
16556 + * to 25MHz clock.
16558 + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
16562 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
16564 + if ((phy->revision == 2) &&
16565 + (phy->id == M88E1111_I_PHY_ID)) {
16566 + /* 82573L PHY - set the downshift counter to 5x. */
16567 + phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
16568 + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
16570 + /* Configure Master and Slave downshift values */
16571 + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
16572 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
16573 + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
16574 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
16576 + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
16581 + /* Commit the changes. */
16582 + ret_val = e1000e_commit_phy(hw);
16584 + hw_dbg(hw, "Error committing the PHY changes\n");
16590 + * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
16591 + * @hw: pointer to the HW structure
16593 + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
16596 +s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
16598 + struct e1000_phy_info *phy = &hw->phy;
16602 + ret_val = e1000_phy_hw_reset(hw);
16604 + hw_dbg(hw, "Error resetting the PHY.\n");
16608 + /* Wait 15ms for MAC to configure PHY from NVM settings. */
16611 + /* disable lplu d0 during driver init */
16612 + ret_val = e1000_set_d0_lplu_state(hw, 0);
16614 + hw_dbg(hw, "Error Disabling LPLU D0\n");
16617 + /* Configure mdi-mdix settings */
16618 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
16622 + data &= ~IGP01E1000_PSCR_AUTO_MDIX;
16624 + switch (phy->mdix) {
16626 + data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
16629 + data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
16633 + data |= IGP01E1000_PSCR_AUTO_MDIX;
16636 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
16640 + /* set auto-master slave resolution settings */
16641 + if (hw->mac.autoneg) {
16642 + /* when autonegotiation advertisement is only 1000Mbps then we
16643 + * should disable SmartSpeed and enable Auto MasterSlave
16644 + * resolution as hardware default. */
16645 + if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
16646 + /* Disable SmartSpeed */
16647 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
16652 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
16653 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
16658 + /* Set auto Master/Slave resolution process */
16659 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
16663 + data &= ~CR_1000T_MS_ENABLE;
16664 + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
16669 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
16673 + /* load defaults for future use */
16674 + phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
16675 + ((data & CR_1000T_MS_VALUE) ?
16676 + e1000_ms_force_master :
16677 + e1000_ms_force_slave) :
16680 + switch (phy->ms_type) {
16681 + case e1000_ms_force_master:
16682 + data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
16684 + case e1000_ms_force_slave:
16685 + data |= CR_1000T_MS_ENABLE;
16686 + data &= ~(CR_1000T_MS_VALUE);
16688 + case e1000_ms_auto:
16689 + data &= ~CR_1000T_MS_ENABLE;
16693 + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
16700 + * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
16701 + * @hw: pointer to the HW structure
16703 + * Reads the MII auto-neg advertisement register and/or the 1000T control
16704 + * register and if the PHY is already setup for auto-negotiation, then
16705 + * return successful. Otherwise, setup advertisement and flow control to
16706 + * the appropriate values for the wanted auto-negotiation.
16708 +static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
16710 + struct e1000_phy_info *phy = &hw->phy;
16712 + u16 mii_autoneg_adv_reg;
16713 + u16 mii_1000t_ctrl_reg = 0;
16715 + phy->autoneg_advertised &= phy->autoneg_mask;
16717 + /* Read the MII Auto-Neg Advertisement Register (Address 4). */
16718 + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
16722 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
16723 + /* Read the MII 1000Base-T Control Register (Address 9). */
16724 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
16729 + /* Need to parse both autoneg_advertised and fc and set up
16730 + * the appropriate PHY registers. First we will parse for
16731 + * autoneg_advertised software override. Since we can advertise
16732 + * a plethora of combinations, we need to check each bit
16736 + /* First we clear all the 10/100 mb speed bits in the Auto-Neg
16737 + * Advertisement Register (Address 4) and the 1000 mb speed bits in
16738 + * the 1000Base-T Control Register (Address 9).
16740 + mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
16741 + NWAY_AR_100TX_HD_CAPS |
16742 + NWAY_AR_10T_FD_CAPS |
16743 + NWAY_AR_10T_HD_CAPS);
16744 + mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
16746 + hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
16748 + /* Do we want to advertise 10 Mb Half Duplex? */
16749 + if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
16750 + hw_dbg(hw, "Advertise 10mb Half duplex\n");
16751 + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
16754 + /* Do we want to advertise 10 Mb Full Duplex? */
16755 + if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
16756 + hw_dbg(hw, "Advertise 10mb Full duplex\n");
16757 + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
16760 + /* Do we want to advertise 100 Mb Half Duplex? */
16761 + if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
16762 + hw_dbg(hw, "Advertise 100mb Half duplex\n");
16763 + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
16766 + /* Do we want to advertise 100 Mb Full Duplex? */
16767 + if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
16768 + hw_dbg(hw, "Advertise 100mb Full duplex\n");
16769 + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
16772 + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
16773 + if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
16774 + hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
16776 + /* Do we want to advertise 1000 Mb Full Duplex? */
16777 + if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
16778 + hw_dbg(hw, "Advertise 1000mb Full duplex\n");
16779 + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
16782 + /* Check for a software override of the flow control settings, and
16783 + * setup the PHY advertisement registers accordingly. If
16784 + * auto-negotiation is enabled, then software will have to set the
16785 + * "PAUSE" bits to the correct value in the Auto-Negotiation
16786 + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
16789 + * The possible values of the "fc" parameter are:
16790 + * 0: Flow control is completely disabled
16791 + * 1: Rx flow control is enabled (we can receive pause frames
16792 + * but not send pause frames).
16793 + * 2: Tx flow control is enabled (we can send pause frames
16794 + * but we do not support receiving pause frames).
16795 + * 3: Both Rx and TX flow control (symmetric) are enabled.
16796 + * other: No software override. The flow control configuration
16797 + * in the EEPROM is used.
16799 + switch (hw->mac.fc) {
16800 + case e1000_fc_none:
16801 + /* Flow control (RX & TX) is completely disabled by a
16802 + * software over-ride.
16804 + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
16806 + case e1000_fc_rx_pause:
16807 + /* RX Flow control is enabled, and TX Flow control is
16808 + * disabled, by a software over-ride.
16810 + /* Since there really isn't a way to advertise that we are
16811 + * capable of RX Pause ONLY, we will advertise that we
16812 + * support both symmetric and asymmetric RX PAUSE. Later
16813 + * (in e1000e_config_fc_after_link_up) we will disable the
16814 + * hw's ability to send PAUSE frames.
16816 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
16818 + case e1000_fc_tx_pause:
16819 + /* TX Flow control is enabled, and RX Flow control is
16820 + * disabled, by a software over-ride.
16822 + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
16823 + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
16825 + case e1000_fc_full:
16826 + /* Flow control (both RX and TX) is enabled by a software
16829 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
16832 + hw_dbg(hw, "Flow control param set incorrectly\n");
16833 + ret_val = -E1000_ERR_CONFIG;
16837 + ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
16841 + hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
16843 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
16844 + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
16851 + * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
16852 + * @hw: pointer to the HW structure
16854 + * Performs initial bounds checking on autoneg advertisement parameter, then
16855 + * configure to advertise the full capability. Setup the PHY to autoneg
16856 + * and restart the negotiation process between the link partner. If
16857 + * wait_for_link, then wait for autoneg to complete before exiting.
16859 +static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
16861 + struct e1000_phy_info *phy = &hw->phy;
16865 + /* Perform some bounds checking on the autoneg advertisement
16868 + phy->autoneg_advertised &= phy->autoneg_mask;
16870 + /* If autoneg_advertised is zero, we assume it was not defaulted
16871 + * by the calling code so we set to advertise full capability.
16873 + if (phy->autoneg_advertised == 0)
16874 + phy->autoneg_advertised = phy->autoneg_mask;
16876 + hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
16877 + ret_val = e1000_phy_setup_autoneg(hw);
16879 + hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
16882 + hw_dbg(hw, "Restarting Auto-Neg\n");
16884 + /* Restart auto-negotiation by setting the Auto Neg Enable bit and
16885 + * the Auto Neg Restart bit in the PHY control register.
16887 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
16891 + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
16892 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
16896 + /* Does the user want to wait for Auto-Neg to complete here, or
16897 + * check at a later time (for example, callback routine).
16899 + if (phy->wait_for_link) {
16900 + ret_val = e1000_wait_autoneg(hw);
16902 + hw_dbg(hw, "Error while waiting for "
16903 + "autoneg to complete\n");
16908 + hw->mac.get_link_status = 1;
16914 + * e1000e_setup_copper_link - Configure copper link settings
16915 + * @hw: pointer to the HW structure
16917 + * Calls the appropriate function to configure the link for auto-neg or forced
16918 + * speed and duplex. Then we check for link, once link is established calls
16919 + * to configure collision distance and flow control are called. If link is
16920 + * not established, we return -E1000_ERR_PHY (-2).
16922 +s32 e1000e_setup_copper_link(struct e1000_hw *hw)
16927 + if (hw->mac.autoneg) {
16928 + /* Setup autoneg and flow control advertisement and perform
16929 + * autonegotiation. */
16930 + ret_val = e1000_copper_link_autoneg(hw);
16934 + /* PHY will be set to 10H, 10F, 100H or 100F
16935 + * depending on user settings. */
16936 + hw_dbg(hw, "Forcing Speed and Duplex\n");
16937 + ret_val = e1000_phy_force_speed_duplex(hw);
16939 + hw_dbg(hw, "Error Forcing Speed and Duplex\n");
16944 + /* Check link status. Wait up to 100 microseconds for link to become
16947 + ret_val = e1000e_phy_has_link_generic(hw,
16948 + COPPER_LINK_UP_LIMIT,
16955 + hw_dbg(hw, "Valid link established!!!\n");
16956 + e1000e_config_collision_dist(hw);
16957 + ret_val = e1000e_config_fc_after_link_up(hw);
16959 + hw_dbg(hw, "Unable to establish link!!!\n");
16966 + * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
16967 + * @hw: pointer to the HW structure
16969 + * Calls the PHY setup function to force speed and duplex. Clears the
16970 + * auto-crossover to force MDI manually. Waits for link and returns
16971 + * successful if link up is successful, else -E1000_ERR_PHY (-2).
16973 +s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
16975 + struct e1000_phy_info *phy = &hw->phy;
16980 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
16984 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
16986 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
16990 + /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
16991 + * forced whenever speed and duplex are forced.
16993 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
16997 + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
16998 + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
17000 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
17004 + hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
17008 + if (phy->wait_for_link) {
17009 + hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
17011 + ret_val = e1000e_phy_has_link_generic(hw,
17019 + hw_dbg(hw, "Link taking longer than expected.\n");
17021 + /* Try once more */
17022 + ret_val = e1000e_phy_has_link_generic(hw,
17034 + * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
17035 + * @hw: pointer to the HW structure
17037 + * Calls the PHY setup function to force speed and duplex. Clears the
17038 + * auto-crossover to force MDI manually. Resets the PHY to commit the
17039 + * changes. If time expires while waiting for link up, we reset the DSP.
17040 + * After reset, TX_CLK and CRS on TX must be set. Return successful upon
17041 + * successful completion, else return corresponding error code.
17043 +s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
17045 + struct e1000_phy_info *phy = &hw->phy;
17050 + /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
17051 + * forced whenever speed and duplex are forced.
17053 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
17057 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
17058 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
17062 + hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
17064 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
17068 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
17070 + /* Reset the phy to commit changes. */
17071 + phy_data |= MII_CR_RESET;
17073 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
17079 + if (phy->wait_for_link) {
17080 + hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
17082 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
17088 + /* We didn't get link.
17089 + * Reset the DSP and cross our fingers.
17091 + ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d);
17094 + ret_val = e1000e_phy_reset_dsp(hw);
17099 + /* Try once more */
17100 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
17106 + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
17110 + /* Resetting the phy means we need to re-force TX_CLK in the
17111 + * Extended PHY Specific Control Register to 25MHz clock from
17112 + * the reset value of 2.5MHz.
17114 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
17115 + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
17119 + /* In addition, we must re-enable CRS on Tx for both half and full
17122 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
17126 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
17127 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
17133 + * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
17134 + * @hw: pointer to the HW structure
17135 + * @phy_ctrl: pointer to current value of PHY_CONTROL
17137 + * Forces speed and duplex on the PHY by doing the following: disable flow
17138 + * control, force speed/duplex on the MAC, disable auto speed detection,
17139 + * disable auto-negotiation, configure duplex, configure speed, configure
17140 + * the collision distance, write configuration to CTRL register. The
17141 + * caller must write to the PHY_CONTROL register for these settings to
17144 +void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
17146 + struct e1000_mac_info *mac = &hw->mac;
17149 + /* Turn off flow control when forcing speed/duplex */
17150 + mac->fc = e1000_fc_none;
17152 + /* Force speed/duplex on the mac */
17153 + ctrl = er32(CTRL);
17154 + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
17155 + ctrl &= ~E1000_CTRL_SPD_SEL;
17157 + /* Disable Auto Speed Detection */
17158 + ctrl &= ~E1000_CTRL_ASDE;
17160 + /* Disable autoneg on the phy */
17161 + *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
17163 + /* Forcing Full or Half Duplex? */
17164 + if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
17165 + ctrl &= ~E1000_CTRL_FD;
17166 + *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
17167 + hw_dbg(hw, "Half Duplex\n");
17169 + ctrl |= E1000_CTRL_FD;
17170 + *phy_ctrl |= MII_CR_FULL_DUPLEX;
17171 + hw_dbg(hw, "Full Duplex\n");
17174 + /* Forcing 10mb or 100mb? */
17175 + if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
17176 + ctrl |= E1000_CTRL_SPD_100;
17177 + *phy_ctrl |= MII_CR_SPEED_100;
17178 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
17179 + hw_dbg(hw, "Forcing 100mb\n");
17181 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
17182 + *phy_ctrl |= MII_CR_SPEED_10;
17183 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
17184 + hw_dbg(hw, "Forcing 10mb\n");
17187 + e1000e_config_collision_dist(hw);
17189 + ew32(CTRL, ctrl);
17193 + * e1000e_set_d3_lplu_state - Sets low power link up state for D3
17194 + * @hw: pointer to the HW structure
17195 + * @active: boolean used to enable/disable lplu
17197 + * Success returns 0, Failure returns 1
17199 + * The low power link up (lplu) state is set to the power management level D3
17200 + * and SmartSpeed is disabled when active is true, else clear lplu for D3
17201 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
17202 + * is used during Dx states where the power conservation is most important.
17203 + * During driver activity, SmartSpeed should be enabled so performance is
17206 +s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
17208 + struct e1000_phy_info *phy = &hw->phy;
17212 + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
17217 + data &= ~IGP02E1000_PM_D3_LPLU;
17218 + ret_val = e1e_wphy(hw,
17219 + IGP02E1000_PHY_POWER_MGMT,
17223 + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
17224 + * during Dx states where the power conservation is most
17225 + * important. During driver activity we should enable
17226 + * SmartSpeed, so performance is maintained. */
17227 + if (phy->smart_speed == e1000_smart_speed_on) {
17228 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
17233 + data |= IGP01E1000_PSCFR_SMART_SPEED;
17234 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
17238 + } else if (phy->smart_speed == e1000_smart_speed_off) {
17239 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
17244 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
17245 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
17250 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
17251 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
17252 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
17253 + data |= IGP02E1000_PM_D3_LPLU;
17254 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
17258 + /* When LPLU is enabled, we should disable SmartSpeed */
17259 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
17263 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
17264 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
17271 + * e1000e_check_downshift - Checks whether a downshift in speed occured
17272 + * @hw: pointer to the HW structure
17274 + * Success returns 0, Failure returns 1
17276 + * A downshift is detected by querying the PHY link health.
17278 +s32 e1000e_check_downshift(struct e1000_hw *hw)
17280 + struct e1000_phy_info *phy = &hw->phy;
17282 + u16 phy_data, offset, mask;
17284 + switch (phy->type) {
17285 + case e1000_phy_m88:
17286 + case e1000_phy_gg82563:
17287 + offset = M88E1000_PHY_SPEC_STATUS;
17288 + mask = M88E1000_PSSR_DOWNSHIFT;
17290 + case e1000_phy_igp_2:
17291 + case e1000_phy_igp_3:
17292 + offset = IGP01E1000_PHY_LINK_HEALTH;
17293 + mask = IGP01E1000_PLHR_SS_DOWNGRADE;
17296 + /* speed downshift not supported */
17297 + phy->speed_downgraded = 0;
17301 + ret_val = e1e_rphy(hw, offset, &phy_data);
17304 + phy->speed_downgraded = (phy_data & mask);
17310 + * e1000_check_polarity_m88 - Checks the polarity.
17311 + * @hw: pointer to the HW structure
17313 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
17315 + * Polarity is determined based on the PHY specific status register.
17317 +static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
17319 + struct e1000_phy_info *phy = &hw->phy;
17323 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
17326 + phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
17327 + ? e1000_rev_polarity_reversed
17328 + : e1000_rev_polarity_normal;
17334 + * e1000_check_polarity_igp - Checks the polarity.
17335 + * @hw: pointer to the HW structure
17337 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
17339 + * Polarity is determined based on the PHY port status register, and the
17340 + * current speed (since there is no polarity at 100Mbps).
17342 +static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
17344 + struct e1000_phy_info *phy = &hw->phy;
17346 + u16 data, offset, mask;
17348 + /* Polarity is determined based on the speed of
17349 + * our connection. */
17350 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
17354 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
17355 + IGP01E1000_PSSR_SPEED_1000MBPS) {
17356 + offset = IGP01E1000_PHY_PCS_INIT_REG;
17357 + mask = IGP01E1000_PHY_POLARITY_MASK;
17359 + /* This really only applies to 10Mbps since
17360 + * there is no polarity for 100Mbps (always 0).
17362 + offset = IGP01E1000_PHY_PORT_STATUS;
17363 + mask = IGP01E1000_PSSR_POLARITY_REVERSED;
17366 + ret_val = e1e_rphy(hw, offset, &data);
17369 + phy->cable_polarity = (data & mask)
17370 + ? e1000_rev_polarity_reversed
17371 + : e1000_rev_polarity_normal;
17377 + * e1000_wait_autoneg - Wait for auto-neg compeletion
17378 + * @hw: pointer to the HW structure
17380 + * Waits for auto-negotiation to complete or for the auto-negotiation time
17381 + * limit to expire, which ever happens first.
17383 +static s32 e1000_wait_autoneg(struct e1000_hw *hw)
17386 + u16 i, phy_status;
17388 + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
17389 + for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
17390 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
17393 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
17396 + if (phy_status & MII_SR_AUTONEG_COMPLETE)
17401 + /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
17408 + * e1000e_phy_has_link_generic - Polls PHY for link
17409 + * @hw: pointer to the HW structure
17410 + * @iterations: number of times to poll for link
17411 + * @usec_interval: delay between polling attempts
17412 + * @success: pointer to whether polling was successful or not
17414 + * Polls the PHY status register for link, 'iterations' number of times.
17416 +s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
17417 + u32 usec_interval, bool *success)
17420 + u16 i, phy_status;
17422 + for (i = 0; i < iterations; i++) {
17423 + /* Some PHYs require the PHY_STATUS register to be read
17424 + * twice due to the link bit being sticky. No harm doing
17425 + * it across the board.
17427 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
17430 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
17433 + if (phy_status & MII_SR_LINK_STATUS)
17435 + if (usec_interval >= 1000)
17436 + mdelay(usec_interval/1000);
17438 + udelay(usec_interval);
17441 + *success = (i < iterations);
17447 + * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
17448 + * @hw: pointer to the HW structure
17450 + * Reads the PHY specific status register to retrieve the cable length
17451 + * information. The cable length is determined by averaging the minimum and
17452 + * maximum values to get the "average" cable length. The m88 PHY has four
17453 + * possible cable length values, which are:
17454 + * Register Value Cable Length
17456 + * 1 50 - 80 meters
17457 + * 2 80 - 110 meters
17458 + * 3 110 - 140 meters
17461 +s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
17463 + struct e1000_phy_info *phy = &hw->phy;
17465 + u16 phy_data, index;
17467 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
17471 + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
17472 + M88E1000_PSSR_CABLE_LENGTH_SHIFT;
17473 + phy->min_cable_length = e1000_m88_cable_length_table[index];
17474 + phy->max_cable_length = e1000_m88_cable_length_table[index+1];
17476 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
17482 + * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
17483 + * @hw: pointer to the HW structure
17485 + * The automatic gain control (agc) normalizes the amplitude of the
17486 + * received signal, adjusting for the attenuation produced by the
17487 + * cable. By reading the AGC registers, which reperesent the
17488 + * cobination of course and fine gain value, the value can be put
17489 + * into a lookup table to obtain the approximate cable length
17490 + * for each channel.
17492 +s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
17494 + struct e1000_phy_info *phy = &hw->phy;
17496 + u16 phy_data, i, agc_value = 0;
17497 + u16 cur_agc_index, max_agc_index = 0;
17498 + u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
17499 + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
17500 + {IGP02E1000_PHY_AGC_A,
17501 + IGP02E1000_PHY_AGC_B,
17502 + IGP02E1000_PHY_AGC_C,
17503 + IGP02E1000_PHY_AGC_D};
17505 + /* Read the AGC registers for all channels */
17506 + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
17507 + ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
17511 + /* Getting bits 15:9, which represent the combination of
17512 + * course and fine gain values. The result is a number
17513 + * that can be put into the lookup table to obtain the
17514 + * approximate cable length. */
17515 + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
17516 + IGP02E1000_AGC_LENGTH_MASK;
17518 + /* Array index bound check. */
17519 + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
17520 + (cur_agc_index == 0))
17521 + return -E1000_ERR_PHY;
17523 + /* Remove min & max AGC values from calculation. */
17524 + if (e1000_igp_2_cable_length_table[min_agc_index] >
17525 + e1000_igp_2_cable_length_table[cur_agc_index])
17526 + min_agc_index = cur_agc_index;
17527 + if (e1000_igp_2_cable_length_table[max_agc_index] <
17528 + e1000_igp_2_cable_length_table[cur_agc_index])
17529 + max_agc_index = cur_agc_index;
17531 + agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
17534 + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
17535 + e1000_igp_2_cable_length_table[max_agc_index]);
17536 + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
17538 + /* Calculate cable length with the error range of +/- 10 meters. */
17539 + phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
17540 + (agc_value - IGP02E1000_AGC_RANGE) : 0;
17541 + phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
17543 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
17549 + * e1000e_get_phy_info_m88 - Retrieve PHY information
17550 + * @hw: pointer to the HW structure
17552 + * Valid for only copper links. Read the PHY status register (sticky read)
17553 + * to verify that link is up. Read the PHY special control register to
17554 + * determine the polarity and 10base-T extended distance. Read the PHY
17555 + * special status register to determine MDI/MDIx and current speed. If
17556 + * speed is 1000, then determine cable length, local and remote receiver.
17558 +s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
17560 + struct e1000_phy_info *phy = &hw->phy;
17565 + if (hw->media_type != e1000_media_type_copper) {
17566 + hw_dbg(hw, "Phy info is only valid for copper media\n");
17567 + return -E1000_ERR_CONFIG;
17570 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
17575 + hw_dbg(hw, "Phy info is only valid if link is up\n");
17576 + return -E1000_ERR_CONFIG;
17579 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
17583 + phy->polarity_correction = (phy_data &
17584 + M88E1000_PSCR_POLARITY_REVERSAL);
17586 + ret_val = e1000_check_polarity_m88(hw);
17590 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
17594 + phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
17596 + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
17597 + ret_val = e1000_get_cable_length(hw);
17601 + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
17605 + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
17606 + ? e1000_1000t_rx_status_ok
17607 + : e1000_1000t_rx_status_not_ok;
17609 + phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
17610 + ? e1000_1000t_rx_status_ok
17611 + : e1000_1000t_rx_status_not_ok;
17613 + /* Set values to "undefined" */
17614 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
17615 + phy->local_rx = e1000_1000t_rx_status_undefined;
17616 + phy->remote_rx = e1000_1000t_rx_status_undefined;
17623 + * e1000e_get_phy_info_igp - Retrieve igp PHY information
17624 + * @hw: pointer to the HW structure
17626 + * Read PHY status to determine if link is up. If link is up, then
17627 + * set/determine 10base-T extended distance and polarity correction. Read
17628 + * PHY port status to determine MDI/MDIx and speed. Based on the speed,
17629 + * determine on the cable length, local and remote receiver.
17631 +s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
17633 + struct e1000_phy_info *phy = &hw->phy;
17638 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
17643 + hw_dbg(hw, "Phy info is only valid if link is up\n");
17644 + return -E1000_ERR_CONFIG;
17647 + phy->polarity_correction = 1;
17649 + ret_val = e1000_check_polarity_igp(hw);
17653 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
17657 + phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
17659 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
17660 + IGP01E1000_PSSR_SPEED_1000MBPS) {
17661 + ret_val = e1000_get_cable_length(hw);
17665 + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
17669 + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
17670 + ? e1000_1000t_rx_status_ok
17671 + : e1000_1000t_rx_status_not_ok;
17673 + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
17674 + ? e1000_1000t_rx_status_ok
17675 + : e1000_1000t_rx_status_not_ok;
17677 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
17678 + phy->local_rx = e1000_1000t_rx_status_undefined;
17679 + phy->remote_rx = e1000_1000t_rx_status_undefined;
17686 + * e1000e_phy_sw_reset - PHY software reset
17687 + * @hw: pointer to the HW structure
17689 + * Does a software reset of the PHY by reading the PHY control register and
17690 + * setting/write the control register reset bit to the PHY.
17692 +s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
17697 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
17701 + phy_ctrl |= MII_CR_RESET;
17702 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
17712 + * e1000e_phy_hw_reset_generic - PHY hardware reset
17713 + * @hw: pointer to the HW structure
17715 + * Verify the reset block is not blocking us from resetting. Acquire
17716 + * semaphore (if necessary) and read/set/write the device control reset
17717 + * bit in the PHY. Wait the appropriate delay time for the device to
17718 + * reset and relase the semaphore (if necessary).
17720 +s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
17722 + struct e1000_phy_info *phy = &hw->phy;
17726 + ret_val = e1000_check_reset_block(hw);
17730 + ret_val = phy->ops.acquire_phy(hw);
17734 + ctrl = er32(CTRL);
17735 + ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
17738 + udelay(phy->reset_delay_us);
17740 + ew32(CTRL, ctrl);
17745 + phy->ops.release_phy(hw);
17747 + return e1000_get_phy_cfg_done(hw);
17751 + * e1000e_get_cfg_done - Generic configuration done
17752 + * @hw: pointer to the HW structure
17754 + * Generic function to wait 10 milli-seconds for configuration to complete
17755 + * and return success.
17757 +s32 e1000e_get_cfg_done(struct e1000_hw *hw)
17763 +/* Internal function pointers */
17766 + * e1000_get_phy_cfg_done - Generic PHY configuration done
17767 + * @hw: pointer to the HW structure
17769 + * Return success if silicon family did not implement a family specific
17770 + * get_cfg_done function.
17772 +static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
17774 + if (hw->phy.ops.get_cfg_done)
17775 + return hw->phy.ops.get_cfg_done(hw);
17781 + * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
17782 + * @hw: pointer to the HW structure
17784 + * When the silicon family has not implemented a forced speed/duplex
17785 + * function for the PHY, simply return 0.
17787 +static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
17789 + if (hw->phy.ops.force_speed_duplex)
17790 + return hw->phy.ops.force_speed_duplex(hw);
17796 + * e1000e_get_phy_type_from_id - Get PHY type from id
17797 + * @phy_id: phy_id read from the phy
17799 + * Returns the phy type from the id.
17801 +enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
17803 + enum e1000_phy_type phy_type = e1000_phy_unknown;
17805 + switch (phy_id) {
17806 + case M88E1000_I_PHY_ID:
17807 + case M88E1000_E_PHY_ID:
17808 + case M88E1111_I_PHY_ID:
17809 + case M88E1011_I_PHY_ID:
17810 + phy_type = e1000_phy_m88;
17812 + case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
17813 + phy_type = e1000_phy_igp_2;
17815 + case GG82563_E_PHY_ID:
17816 + phy_type = e1000_phy_gg82563;
17818 + case IGP03E1000_E_PHY_ID:
17819 + phy_type = e1000_phy_igp_3;
17821 + case IFE_E_PHY_ID:
17822 + case IFE_PLUS_E_PHY_ID:
17823 + case IFE_C_E_PHY_ID:
17824 + phy_type = e1000_phy_ife;
17827 + phy_type = e1000_phy_unknown;
17834 + * e1000e_commit_phy - Soft PHY reset
17835 + * @hw: pointer to the HW structure
17837 + * Performs a soft PHY reset on those that apply. This is a function pointer
17838 + * entry point called by drivers.
17840 +s32 e1000e_commit_phy(struct e1000_hw *hw)
17842 + if (hw->phy.ops.commit_phy)
17843 + return hw->phy.ops.commit_phy(hw);
17849 + * e1000_set_d0_lplu_state - Sets low power link up state for D0
17850 + * @hw: pointer to the HW structure
17851 + * @active: boolean used to enable/disable lplu
17853 + * Success returns 0, Failure returns 1
17855 + * The low power link up (lplu) state is set to the power management level D0
17856 + * and SmartSpeed is disabled when active is true, else clear lplu for D0
17857 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
17858 + * is used during Dx states where the power conservation is most important.
17859 + * During driver activity, SmartSpeed should be enabled so performance is
17860 + * maintained. This is a function pointer entry point called by drivers.
17862 +static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
17864 + if (hw->phy.ops.set_d0_lplu_state)
17865 + return hw->phy.ops.set_d0_lplu_state(hw, active);
17869 diff -Nurp linux-2.6.22-0/drivers/net/Kconfig linux-2.6.22-10/drivers/net/Kconfig
17870 --- linux-2.6.22-0/drivers/net/Kconfig 2007-07-21 18:00:07.000000000 -0400
17871 +++ linux-2.6.22-10/drivers/net/Kconfig 2007-11-21 13:55:13.000000000 -0500
17872 @@ -1993,6 +1993,29 @@ config E1000_DISABLE_PACKET_SPLIT
17874 If in doubt, say N.
17877 + tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
17880 + This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
17881 + ethernet family of adapters. For PCI or PCI-X e1000 adapters,
17882 + use the regular e1000 driver For more information on how to
17883 + identify your adapter, go to the Adapter & Driver ID Guide at:
17885 + <http://support.intel.com/support/network/adapter/pro100/21397.htm>
17887 + For general information and support, go to the Intel support
17890 + <http://support.intel.com>
17892 + More specific information on configuring the driver is in
17893 + <file:Documentation/networking/e1000e.txt>.
17895 + To compile this driver as a module, choose M here and read
17896 + <file:Documentation/networking/net-modules.txt>. The module
17897 + will be called e1000e.
17899 source "drivers/net/ixp2000/Kconfig"
17902 diff -Nurp linux-2.6.22-0/drivers/net/Makefile linux-2.6.22-10/drivers/net/Makefile
17903 --- linux-2.6.22-0/drivers/net/Makefile 2007-07-21 18:00:07.000000000 -0400
17904 +++ linux-2.6.22-10/drivers/net/Makefile 2007-11-21 13:55:13.000000000 -0500
17908 obj-$(CONFIG_E1000) += e1000/
17909 +obj-$(CONFIG_E1000E) += e1000e/
17910 obj-$(CONFIG_IBM_EMAC) += ibm_emac/
17911 obj-$(CONFIG_IXGB) += ixgb/
17912 obj-$(CONFIG_CHELSIO_T1) += chelsio/