1 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.c linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.c
2 --- linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.c 2008-10-14 01:51:32.000000000 +0200
5 +/*******************************************************************************
7 + Intel PRO/1000 Linux driver
8 + Copyright(c) 1999 - 2008 Intel Corporation.
10 + This program is free software; you can redistribute it and/or modify it
11 + under the terms and conditions of the GNU General Public License,
12 + version 2, as published by the Free Software Foundation.
14 + This program is distributed in the hope it will be useful, but WITHOUT
15 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 + You should have received a copy of the GNU General Public License along with
20 + this program; if not, write to the Free Software Foundation, Inc.,
21 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 + The full GNU General Public License is included in this distribution in
24 + the file called "COPYING".
26 + Contact Information:
27 + Linux NICS <linux.nics@intel.com>
28 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
29 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 +*******************************************************************************/
36 +#include "e1000_hw.h"
38 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
39 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
40 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
41 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 +static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw);
43 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
44 +static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw);
45 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
46 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
47 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
54 + u16 words, u16 *data);
55 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
56 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
57 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
58 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
60 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
61 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
62 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
63 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
64 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
65 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
66 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
67 +static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
68 +static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data);
69 +static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data);
70 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
71 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
72 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
73 +static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
74 +static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
77 + * A table for the GG82563 cable length where the range is defined
78 + * with a lower bound at "index" and the upper bound at
81 +static const u16 e1000_gg82563_cable_length_table[] =
82 + { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
83 +#define GG82563_CABLE_LENGTH_TABLE_SIZE \
84 + (sizeof(e1000_gg82563_cable_length_table) / \
85 + sizeof(e1000_gg82563_cable_length_table[0]))
88 + * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
89 + * @hw: pointer to the HW structure
91 + * This is a function pointer entry point called by the api module.
93 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
95 + struct e1000_phy_info *phy = &hw->phy;
96 + s32 ret_val = E1000_SUCCESS;
98 + DEBUGFUNC("e1000_init_phy_params_80003es2lan");
100 + if (hw->phy.media_type != e1000_media_type_copper) {
101 + phy->type = e1000_phy_none;
104 + phy->ops.power_up = e1000_power_up_phy_copper;
105 + phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
109 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
110 + phy->reset_delay_us = 100;
111 + phy->type = e1000_phy_gg82563;
113 + phy->ops.acquire = e1000_acquire_phy_80003es2lan;
114 + phy->ops.check_polarity = e1000_check_polarity_m88;
115 + phy->ops.check_reset_block = e1000_check_reset_block_generic;
116 + phy->ops.commit = e1000_phy_sw_reset_generic;
117 + phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
118 + phy->ops.get_info = e1000_get_phy_info_m88;
119 + phy->ops.release = e1000_release_phy_80003es2lan;
120 + phy->ops.reset = e1000_phy_hw_reset_generic;
121 + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
123 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
124 + phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
125 + phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
126 + phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
128 + phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
130 + /* This can only be done after all function pointers are setup. */
131 + ret_val = e1000_get_phy_id(hw);
133 + /* Verify phy id */
134 + if (phy->id != GG82563_E_PHY_ID) {
135 + ret_val = -E1000_ERR_PHY;
144 + * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
145 + * @hw: pointer to the HW structure
147 + * This is a function pointer entry point called by the api module.
149 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
151 + struct e1000_nvm_info *nvm = &hw->nvm;
152 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
155 + DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
157 + nvm->opcode_bits = 8;
158 + nvm->delay_usec = 1;
159 + switch (nvm->override) {
160 + case e1000_nvm_override_spi_large:
161 + nvm->page_size = 32;
162 + nvm->address_bits = 16;
164 + case e1000_nvm_override_spi_small:
165 + nvm->page_size = 8;
166 + nvm->address_bits = 8;
169 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
170 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
174 + nvm->type = e1000_nvm_eeprom_spi;
176 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
177 + E1000_EECD_SIZE_EX_SHIFT);
180 + * Added to a constant, "size" becomes the left-shift value
181 + * for setting word_size.
183 + size += NVM_WORD_SIZE_BASE_SHIFT;
185 + /* EEPROM access above 16k is unsupported */
188 + nvm->word_size = 1 << size;
190 + /* Function Pointers */
191 + nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
192 + nvm->ops.read = e1000_read_nvm_eerd;
193 + nvm->ops.release = e1000_release_nvm_80003es2lan;
194 + nvm->ops.update = e1000_update_nvm_checksum_generic;
195 + nvm->ops.valid_led_default = e1000_valid_led_default_generic;
196 + nvm->ops.validate = e1000_validate_nvm_checksum_generic;
197 + nvm->ops.write = e1000_write_nvm_80003es2lan;
199 + return E1000_SUCCESS;
203 + * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 + * @hw: pointer to the HW structure
206 + * This is a function pointer entry point called by the api module.
208 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
210 + struct e1000_mac_info *mac = &hw->mac;
211 + s32 ret_val = E1000_SUCCESS;
213 + DEBUGFUNC("e1000_init_mac_params_80003es2lan");
215 + /* Set media type */
216 + switch (hw->device_id) {
217 + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
218 + hw->phy.media_type = e1000_media_type_internal_serdes;
221 + hw->phy.media_type = e1000_media_type_copper;
225 + /* Set mta register count */
226 + mac->mta_reg_count = 128;
227 + /* Set rar entry count */
228 + mac->rar_entry_count = E1000_RAR_ENTRIES;
229 + /* Set if part includes ASF firmware */
230 + mac->asf_firmware_present = true;
231 + /* Set if manageability features are enabled. */
232 + mac->arc_subsystem_valid =
233 + (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
236 + /* Function pointers */
238 + /* bus type/speed/width */
239 + mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
241 + mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
242 + /* hw initialization */
243 + mac->ops.init_hw = e1000_init_hw_80003es2lan;
245 + mac->ops.setup_link = e1000_setup_link_generic;
246 + /* physical interface link setup */
247 + mac->ops.setup_physical_interface =
248 + (hw->phy.media_type == e1000_media_type_copper)
249 + ? e1000_setup_copper_link_80003es2lan
250 + : e1000_setup_fiber_serdes_link_generic;
251 + /* check for link */
252 + switch (hw->phy.media_type) {
253 + case e1000_media_type_copper:
254 + mac->ops.check_for_link = e1000_check_for_copper_link_generic;
256 + case e1000_media_type_fiber:
257 + mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
259 + case e1000_media_type_internal_serdes:
260 + mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
263 + ret_val = -E1000_ERR_CONFIG;
267 + /* check management mode */
268 + mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
269 + /* multicast address update */
270 + mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
272 + mac->ops.write_vfta = e1000_write_vfta_generic;
273 + /* clearing VFTA */
274 + mac->ops.clear_vfta = e1000_clear_vfta_generic;
276 + mac->ops.mta_set = e1000_mta_set_generic;
277 + /* read mac address */
278 + mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
280 + mac->ops.blink_led = e1000_blink_led_generic;
282 + mac->ops.setup_led = e1000_setup_led_generic;
284 + mac->ops.cleanup_led = e1000_cleanup_led_generic;
285 + /* turn on/off LED */
286 + mac->ops.led_on = e1000_led_on_generic;
287 + mac->ops.led_off = e1000_led_off_generic;
288 + /* remove device */
289 + mac->ops.remove_device = e1000_remove_device_generic;
290 + /* clear hardware counters */
291 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
293 + mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
300 + * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
301 + * @hw: pointer to the HW structure
303 + * The only function explicitly called by the api module to initialize
304 + * all function pointers and parameters.
306 +void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
308 + DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
310 + e1000_init_mac_ops_generic(hw);
311 + e1000_init_nvm_ops_generic(hw);
312 + hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
313 + hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
314 + hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
315 + e1000_get_bus_info_pcie_generic(hw);
319 + * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
320 + * @hw: pointer to the HW structure
322 + * A wrapper to acquire access rights to the correct PHY. This is a
323 + * function pointer entry point called by the api module.
325 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
329 + DEBUGFUNC("e1000_acquire_phy_80003es2lan");
331 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
332 + return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
336 + * e1000_release_phy_80003es2lan - Release rights to access PHY
337 + * @hw: pointer to the HW structure
339 + * A wrapper to release access rights to the correct PHY. This is a
340 + * function pointer entry point called by the api module.
342 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
346 + DEBUGFUNC("e1000_release_phy_80003es2lan");
348 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
349 + e1000_release_swfw_sync_80003es2lan(hw, mask);
354 + * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
355 + * @hw: pointer to the HW structure
357 + * Acquire the semaphore to access the Kumeran interface.
360 +static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
364 + DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
366 + mask = E1000_SWFW_CSR_SM;
368 + return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
372 + * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
373 + * @hw: pointer to the HW structure
375 + * Release the semaphore used to access the Kumeran interface
377 +static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
381 + DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
383 + mask = E1000_SWFW_CSR_SM;
385 + e1000_release_swfw_sync_80003es2lan(hw, mask);
389 + * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
390 + * @hw: pointer to the HW structure
392 + * Acquire the semaphore to access the EEPROM. This is a function
393 + * pointer entry point called by the api module.
395 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
399 + DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
401 + ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
405 + ret_val = e1000_acquire_nvm_generic(hw);
408 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
415 + * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
416 + * @hw: pointer to the HW structure
418 + * Release the semaphore used to access the EEPROM. This is a
419 + * function pointer entry point called by the api module.
421 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
423 + DEBUGFUNC("e1000_release_nvm_80003es2lan");
425 + e1000_release_nvm_generic(hw);
426 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
430 + * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
431 + * @hw: pointer to the HW structure
432 + * @mask: specifies which semaphore to acquire
434 + * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
435 + * will also specify which port we're acquiring the lock for.
437 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
441 + u32 fwmask = mask << 16;
442 + s32 ret_val = E1000_SUCCESS;
443 + s32 i = 0, timeout = 50;
445 + DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
447 + while (i < timeout) {
448 + if (e1000_get_hw_semaphore_generic(hw)) {
449 + ret_val = -E1000_ERR_SWFW_SYNC;
453 + swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
454 + if (!(swfw_sync & (fwmask | swmask)))
458 + * Firmware currently using resource (fwmask)
459 + * or other software thread using resource (swmask)
461 + e1000_put_hw_semaphore_generic(hw);
466 + if (i == timeout) {
467 + DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
468 + ret_val = -E1000_ERR_SWFW_SYNC;
472 + swfw_sync |= swmask;
473 + E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
475 + e1000_put_hw_semaphore_generic(hw);
482 + * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
483 + * @hw: pointer to the HW structure
484 + * @mask: specifies which semaphore to acquire
486 + * Release the SW/FW semaphore used to access the PHY or NVM. The mask
487 + * will also specify which port we're releasing the lock for.
489 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
493 + DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
495 + while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
498 + swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
499 + swfw_sync &= ~mask;
500 + E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
502 + e1000_put_hw_semaphore_generic(hw);
506 + * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
507 + * @hw: pointer to the HW structure
508 + * @offset: offset of the register to read
509 + * @data: pointer to the data returned from the operation
511 + * Read the GG82563 PHY register. This is a function pointer entry
512 + * point called by the api module.
514 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
515 + u32 offset, u16 *data)
521 + DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
523 + ret_val = e1000_acquire_phy_80003es2lan(hw);
527 + /* Select Configuration Page */
528 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
529 + page_select = GG82563_PHY_PAGE_SELECT;
532 + * Use Alternative Page Select register to access
533 + * registers 30 and 31
535 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
538 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
539 + ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
541 + e1000_release_phy_80003es2lan(hw);
546 + * The "ready" bit in the MDIC register may be incorrectly set
547 + * before the device has completed the "Page Select" MDI
548 + * transaction. So we wait 200us after each MDI command...
552 + /* ...and verify the command was successful. */
553 + ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
555 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
556 + ret_val = -E1000_ERR_PHY;
557 + e1000_release_phy_80003es2lan(hw);
563 + ret_val = e1000_read_phy_reg_mdic(hw,
564 + MAX_PHY_REG_ADDRESS & offset,
568 + e1000_release_phy_80003es2lan(hw);
575 + * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
576 + * @hw: pointer to the HW structure
577 + * @offset: offset of the register to read
578 + * @data: value to write to the register
580 + * Write to the GG82563 PHY register. This is a function pointer entry
581 + * point called by the api module.
583 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
584 + u32 offset, u16 data)
590 + DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
592 + ret_val = e1000_acquire_phy_80003es2lan(hw);
596 + /* Select Configuration Page */
597 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
598 + page_select = GG82563_PHY_PAGE_SELECT;
601 + * Use Alternative Page Select register to access
602 + * registers 30 and 31
604 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
607 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
608 + ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
610 + e1000_release_phy_80003es2lan(hw);
616 + * The "ready" bit in the MDIC register may be incorrectly set
617 + * before the device has completed the "Page Select" MDI
618 + * transaction. So we wait 200us after each MDI command...
622 + /* ...and verify the command was successful. */
623 + ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
625 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
626 + ret_val = -E1000_ERR_PHY;
627 + e1000_release_phy_80003es2lan(hw);
633 + ret_val = e1000_write_phy_reg_mdic(hw,
634 + MAX_PHY_REG_ADDRESS & offset,
638 + e1000_release_phy_80003es2lan(hw);
645 + * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
646 + * @hw: pointer to the HW structure
647 + * @offset: offset of the register to read
648 + * @words: number of words to write
649 + * @data: buffer of data to write to the NVM
651 + * Write "words" of data to the ESB2 NVM. This is a function
652 + * pointer entry point called by the api module.
654 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
655 + u16 words, u16 *data)
657 + DEBUGFUNC("e1000_write_nvm_80003es2lan");
659 + return e1000_write_nvm_spi(hw, offset, words, data);
663 + * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
664 + * @hw: pointer to the HW structure
666 + * Wait a specific amount of time for manageability processes to complete.
667 + * This is a function pointer entry point called by the phy module.
669 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
671 + s32 timeout = PHY_CFG_TIMEOUT;
672 + s32 ret_val = E1000_SUCCESS;
673 + u32 mask = E1000_NVM_CFG_DONE_PORT_0;
675 + DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
677 + if (hw->bus.func == 1)
678 + mask = E1000_NVM_CFG_DONE_PORT_1;
681 + if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
687 + DEBUGOUT("MNG configuration cycle has not completed.\n");
688 + ret_val = -E1000_ERR_RESET;
697 + * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
698 + * @hw: pointer to the HW structure
700 + * Force the speed and duplex settings onto the PHY. This is a
701 + * function pointer entry point called by the phy module.
703 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
705 + s32 ret_val = E1000_SUCCESS;
709 + DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
711 + if (!(hw->phy.ops.read_reg))
715 + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
716 + * forced whenever speed and duplex are forced.
718 + ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
722 + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
723 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
727 + DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
729 + ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
733 + e1000_phy_force_speed_duplex_setup(hw, &phy_data);
735 + /* Reset the phy to commit changes. */
736 + phy_data |= MII_CR_RESET;
738 + ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
744 + if (hw->phy.autoneg_wait_to_complete) {
745 + DEBUGOUT("Waiting for forced speed/duplex link "
746 + "on GG82563 phy.\n");
748 + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
755 + * We didn't get link.
756 + * Reset the DSP and cross our fingers.
758 + ret_val = e1000_phy_reset_dsp_generic(hw);
763 + /* Try once more */
764 + ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
770 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
775 + * Resetting the phy means we need to verify the TX_CLK corresponds
776 + * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
778 + phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
779 + if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
780 + phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
782 + phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
785 + * In addition, we must re-enable CRS on Tx for both half and full
788 + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
789 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
796 + * e1000_get_cable_length_80003es2lan - Set approximate cable length
797 + * @hw: pointer to the HW structure
799 + * Find the approximate cable length as measured by the GG82563 PHY.
800 + * This is a function pointer entry point called by the phy module.
802 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
804 + struct e1000_phy_info *phy = &hw->phy;
805 + s32 ret_val = E1000_SUCCESS;
806 + u16 phy_data, index;
808 + DEBUGFUNC("e1000_get_cable_length_80003es2lan");
810 + if (!(hw->phy.ops.read_reg))
813 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
817 + index = phy_data & GG82563_DSPD_CABLE_LENGTH;
818 + phy->min_cable_length = e1000_gg82563_cable_length_table[index];
819 + phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
821 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
828 + * e1000_get_link_up_info_80003es2lan - Report speed and duplex
829 + * @hw: pointer to the HW structure
830 + * @speed: pointer to speed buffer
831 + * @duplex: pointer to duplex buffer
833 + * Retrieve the current speed and duplex configuration.
834 + * This is a function pointer entry point called by the api module.
836 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
841 + DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
843 + if (hw->phy.media_type == e1000_media_type_copper) {
844 + ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
848 + ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
857 + * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
858 + * @hw: pointer to the HW structure
860 + * Perform a global reset to the ESB2 controller.
861 + * This is a function pointer entry point called by the api module.
863 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
868 + DEBUGFUNC("e1000_reset_hw_80003es2lan");
871 + * Prevent the PCI-E bus from sticking if there is no TLP connection
872 + * on the last TLP read/write transaction when MAC is reset.
874 + ret_val = e1000_disable_pcie_master_generic(hw);
876 + DEBUGOUT("PCI-E Master disable polling has failed.\n");
879 + DEBUGOUT("Masking off all interrupts\n");
880 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
882 + E1000_WRITE_REG(hw, E1000_RCTL, 0);
883 + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
884 + E1000_WRITE_FLUSH(hw);
888 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
890 + ret_val = e1000_acquire_phy_80003es2lan(hw);
891 + DEBUGOUT("Issuing a global reset to MAC\n");
892 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
893 + e1000_release_phy_80003es2lan(hw);
895 + ret_val = e1000_get_auto_rd_done_generic(hw);
897 + /* We don't want to continue accessing MAC registers. */
900 + /* Clear any pending interrupt events. */
901 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
902 + icr = E1000_READ_REG(hw, E1000_ICR);
904 + e1000_check_alt_mac_addr_generic(hw);
911 + * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
912 + * @hw: pointer to the HW structure
914 + * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
915 + * This is a function pointer entry point called by the api module.
917 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
919 + struct e1000_mac_info *mac = &hw->mac;
924 + DEBUGFUNC("e1000_init_hw_80003es2lan");
926 + e1000_initialize_hw_bits_80003es2lan(hw);
928 + /* Initialize identification LED */
929 + ret_val = e1000_id_led_init_generic(hw);
931 + DEBUGOUT("Error initializing identification LED\n");
932 + /* This is not fatal and we should not stop init due to this */
935 + /* Disabling VLAN filtering */
936 + DEBUGOUT("Initializing the IEEE VLAN\n");
937 + mac->ops.clear_vfta(hw);
939 + /* Setup the receive address. */
940 + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
942 + /* Zero out the Multicast HASH table */
943 + DEBUGOUT("Zeroing the MTA\n");
944 + for (i = 0; i < mac->mta_reg_count; i++)
945 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
947 + /* Setup link and flow control */
948 + ret_val = mac->ops.setup_link(hw);
950 + /* Set the transmit descriptor write-back policy */
951 + reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
952 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
953 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
954 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
956 + /* ...for both queues. */
957 + reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
958 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
959 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
960 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
962 + /* Enable retransmit on late collisions */
963 + reg_data = E1000_READ_REG(hw, E1000_TCTL);
964 + reg_data |= E1000_TCTL_RTLC;
965 + E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
967 + /* Configure Gigabit Carry Extend Padding */
968 + reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
969 + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
970 + reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
971 + E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
973 + /* Configure Transmit Inter-Packet Gap */
974 + reg_data = E1000_READ_REG(hw, E1000_TIPG);
975 + reg_data &= ~E1000_TIPG_IPGT_MASK;
976 + reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
977 + E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
979 + reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
980 + reg_data &= ~0x00100000;
981 + E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
984 + * Clear all of the statistics registers (clear on read). It is
985 + * important that we do this after we have tried to establish link
986 + * because the symbol error count will increment wildly if there
989 + e1000_clear_hw_cntrs_80003es2lan(hw);
995 + * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
996 + * @hw: pointer to the HW structure
998 + * Initializes required hardware-dependent bits needed for normal operation.
1000 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1004 + DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
1006 + if (hw->mac.disable_hw_init_bits)
1009 + /* Transmit Descriptor Control 0 */
1010 + reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1012 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1014 + /* Transmit Descriptor Control 1 */
1015 + reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1017 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1019 + /* Transmit Arbitration Control 0 */
1020 + reg = E1000_READ_REG(hw, E1000_TARC(0));
1021 + reg &= ~(0xF << 27); /* 30:27 */
1022 + if (hw->phy.media_type != e1000_media_type_copper)
1023 + reg &= ~(1 << 20);
1024 + E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1026 + /* Transmit Arbitration Control 1 */
1027 + reg = E1000_READ_REG(hw, E1000_TARC(1));
1028 + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1029 + reg &= ~(1 << 28);
1032 + E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1039 + * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1040 + * @hw: pointer to the HW structure
1042 + * Setup some GG82563 PHY registers for obtaining link
1044 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1046 + struct e1000_phy_info *phy = &hw->phy;
1051 + DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1053 + if (!phy->reset_disable) {
1054 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1059 + data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1060 + /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1061 + data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1063 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1070 + * MDI/MDI-X = 0 (default)
1071 + * 0 - Auto for all speeds
1074 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1076 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1080 + data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1082 + switch (phy->mdix) {
1084 + data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1087 + data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1091 + data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1097 + * disable_polarity_correction = 0 (default)
1098 + * Automatic Correction for Reversed Cable Polarity
1102 + data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1103 + if (phy->disable_polarity_correction)
1104 + data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1106 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1110 + /* SW Reset the PHY so all changes take effect */
1111 + ret_val = hw->phy.ops.commit(hw);
1113 + DEBUGOUT("Error Resetting the PHY\n");
1119 + /* Bypass Rx and Tx FIFO's */
1120 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1121 + E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1122 + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1123 + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1127 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1128 + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1132 + data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1133 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1134 + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1139 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1143 + data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1144 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1148 + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1149 + ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1150 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1152 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1157 + * Do not init these registers when the HW is in IAMT mode, since the
1158 + * firmware will have already initialized them. We only initialize
1159 + * them if the HW is not in IAMT mode.
1161 + if (!(hw->mac.ops.check_mng_mode(hw))) {
1162 + /* Enable Electrical Idle on the PHY */
1163 + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1164 + ret_val = hw->phy.ops.write_reg(hw,
1165 + GG82563_PHY_PWR_MGMT_CTRL,
1169 + ret_val = hw->phy.ops.read_reg(hw,
1170 + GG82563_PHY_KMRN_MODE_CTRL,
1175 + data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1176 + ret_val = hw->phy.ops.write_reg(hw,
1177 + GG82563_PHY_KMRN_MODE_CTRL,
1185 + * Workaround: Disable padding in Kumeran interface in the MAC
1186 + * and in the PHY to avoid CRC errors.
1188 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1192 + data |= GG82563_ICR_DIS_PADDING;
1193 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1202 + * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1203 + * @hw: pointer to the HW structure
1205 + * Essentially a wrapper for setting up all things "copper" related.
1206 + * This is a function pointer entry point called by the mac module.
1208 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1214 + DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1216 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
1217 + ctrl |= E1000_CTRL_SLU;
1218 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1219 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1222 + * Set the mac to wait the maximum time between each
1223 + * iteration and increase the max iterations when
1224 + * polling the phy; this fixes erroneous timeouts at 10Mbps.
1226 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1230 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1235 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1239 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1240 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1244 + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1245 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1246 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1251 + ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1255 + ret_val = e1000_setup_copper_link_generic(hw);
1262 + * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1263 + * @hw: pointer to the HW structure
1264 + * @duplex: current duplex setting
1266 + * Configure the KMRN interface by applying last minute quirks for
1267 + * 10/100 operation.
1269 +static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1271 + s32 ret_val = E1000_SUCCESS;
1275 + DEBUGFUNC("e1000_configure_on_link_up");
1277 + if (hw->phy.media_type == e1000_media_type_copper) {
1279 + ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1285 + if (speed == SPEED_1000)
1286 + ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1288 + ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1296 + * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1297 + * @hw: pointer to the HW structure
1298 + * @duplex: current duplex setting
1300 + * Configure the KMRN interface by applying last minute quirks for
1301 + * 10/100 operation.
1303 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1305 + s32 ret_val = E1000_SUCCESS;
1308 + u16 reg_data, reg_data2;
1310 + DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1312 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1313 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1314 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1319 + /* Configure Transmit Inter-Packet Gap */
1320 + tipg = E1000_READ_REG(hw, E1000_TIPG);
1321 + tipg &= ~E1000_TIPG_IPGT_MASK;
1322 + tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1323 + E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1327 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1332 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1337 + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1339 + if (duplex == HALF_DUPLEX)
1340 + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1342 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1344 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1351 + * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1352 + * @hw: pointer to the HW structure
1354 + * Configure the KMRN interface by applying last minute quirks for
1355 + * gigabit operation.
1357 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1359 + s32 ret_val = E1000_SUCCESS;
1360 + u16 reg_data, reg_data2;
1364 + DEBUGFUNC("e1000_configure_kmrn_for_1000");
1366 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1367 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1368 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1373 + /* Configure Transmit Inter-Packet Gap */
1374 + tipg = E1000_READ_REG(hw, E1000_TIPG);
1375 + tipg &= ~E1000_TIPG_IPGT_MASK;
1376 + tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1377 + E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1381 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1386 + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1391 + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1393 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1394 + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1401 + * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1402 + * @hw: pointer to the HW structure
1403 + * @offset: register offset to be read
1404 + * @data: pointer to the read data
1406 + * Acquire semaphore, then read the PHY register at offset
1407 + * using the kumeran interface. The information retrieved is stored in data.
1408 + * Release the semaphore before exiting.
1410 +s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data)
1413 + s32 ret_val = E1000_SUCCESS;
1415 + DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1417 + ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1421 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1422 + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1423 + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1427 + kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1428 + *data = (u16)kmrnctrlsta;
1430 + e1000_release_mac_csr_80003es2lan(hw);
1437 + * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1438 + * @hw: pointer to the HW structure
1439 + * @offset: register offset to write to
1440 + * @data: data to write at register offset
1442 + * Acquire semaphore, then write the data to PHY register
1443 + * at the offset using the kumeran interface. Release semaphore
1446 +s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data)
1449 + s32 ret_val = E1000_SUCCESS;
1451 + DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1453 + ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1457 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1458 + E1000_KMRNCTRLSTA_OFFSET) | data;
1459 + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1463 + e1000_release_mac_csr_80003es2lan(hw);
1470 + * e1000_read_mac_addr_80003es2lan - Read device MAC address
1471 + * @hw: pointer to the HW structure
1473 +static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1475 + s32 ret_val = E1000_SUCCESS;
1477 + DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1478 + if (e1000_check_alt_mac_addr_generic(hw))
1479 + ret_val = e1000_read_mac_addr_generic(hw);
1485 + * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1486 + * @hw: pointer to the HW structure
1488 + * In the case of a PHY power down to save power, or to turn off link during a
1489 + * driver unload, or wake on lan is not enabled, remove the link.
1491 +static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1493 + /* If the management interface is not enabled, then power down */
1494 + if (!(hw->mac.ops.check_mng_mode(hw) ||
1495 + hw->phy.ops.check_reset_block(hw)))
1496 + e1000_power_down_phy_copper(hw);
1502 + * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1503 + * @hw: pointer to the HW structure
1505 + * Clears the hardware counters by reading the counter registers.
1507 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1509 + volatile u32 temp;
1511 + DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1513 + e1000_clear_hw_cntrs_base_generic(hw);
1515 + temp = E1000_READ_REG(hw, E1000_PRC64);
1516 + temp = E1000_READ_REG(hw, E1000_PRC127);
1517 + temp = E1000_READ_REG(hw, E1000_PRC255);
1518 + temp = E1000_READ_REG(hw, E1000_PRC511);
1519 + temp = E1000_READ_REG(hw, E1000_PRC1023);
1520 + temp = E1000_READ_REG(hw, E1000_PRC1522);
1521 + temp = E1000_READ_REG(hw, E1000_PTC64);
1522 + temp = E1000_READ_REG(hw, E1000_PTC127);
1523 + temp = E1000_READ_REG(hw, E1000_PTC255);
1524 + temp = E1000_READ_REG(hw, E1000_PTC511);
1525 + temp = E1000_READ_REG(hw, E1000_PTC1023);
1526 + temp = E1000_READ_REG(hw, E1000_PTC1522);
1528 + temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1529 + temp = E1000_READ_REG(hw, E1000_RXERRC);
1530 + temp = E1000_READ_REG(hw, E1000_TNCRS);
1531 + temp = E1000_READ_REG(hw, E1000_CEXTERR);
1532 + temp = E1000_READ_REG(hw, E1000_TSCTC);
1533 + temp = E1000_READ_REG(hw, E1000_TSCTFC);
1535 + temp = E1000_READ_REG(hw, E1000_MGTPRC);
1536 + temp = E1000_READ_REG(hw, E1000_MGTPDC);
1537 + temp = E1000_READ_REG(hw, E1000_MGTPTC);
1539 + temp = E1000_READ_REG(hw, E1000_IAC);
1540 + temp = E1000_READ_REG(hw, E1000_ICRXOC);
1542 + temp = E1000_READ_REG(hw, E1000_ICRXPTC);
1543 + temp = E1000_READ_REG(hw, E1000_ICRXATC);
1544 + temp = E1000_READ_REG(hw, E1000_ICTXPTC);
1545 + temp = E1000_READ_REG(hw, E1000_ICTXATC);
1546 + temp = E1000_READ_REG(hw, E1000_ICTXQEC);
1547 + temp = E1000_READ_REG(hw, E1000_ICTXQMTC);
1548 + temp = E1000_READ_REG(hw, E1000_ICRXDMTC);
1550 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.h linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.h
1551 --- linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.h 1970-01-01 01:00:00.000000000 +0100
1552 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.h 2008-10-14 01:51:32.000000000 +0200
1554 +/*******************************************************************************
1556 + Intel PRO/1000 Linux driver
1557 + Copyright(c) 1999 - 2008 Intel Corporation.
1559 + This program is free software; you can redistribute it and/or modify it
1560 + under the terms and conditions of the GNU General Public License,
1561 + version 2, as published by the Free Software Foundation.
1563 + This program is distributed in the hope it will be useful, but WITHOUT
1564 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1565 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1568 + You should have received a copy of the GNU General Public License along with
1569 + this program; if not, write to the Free Software Foundation, Inc.,
1570 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1572 + The full GNU General Public License is included in this distribution in
1573 + the file called "COPYING".
1575 + Contact Information:
1576 + Linux NICS <linux.nics@intel.com>
1577 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1578 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
1580 +*******************************************************************************/
1582 +#ifndef _E1000_80003ES2LAN_H_
1583 +#define _E1000_80003ES2LAN_H_
1585 +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
1586 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
1587 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
1588 +#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
1590 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
1591 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
1592 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
1594 +#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
1595 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
1596 +#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
1598 +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1599 +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
1601 +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
1602 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
1604 +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
1605 +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
1606 +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
1607 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
1608 +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
1609 +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
1611 +/* PHY Specific Control Register 2 (Page 0, Register 26) */
1612 +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
1613 + /* 1=Reverse Auto-Negotiation */
1615 +/* MAC Specific Control Register (Page 2, Register 21) */
1616 +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
1617 +#define GG82563_MSCR_TX_CLK_MASK 0x0007
1618 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
1619 +#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
1620 +#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006
1621 +#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
1623 +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
1625 +/* DSP Distance Register (Page 5, Register 26) */
1633 +#define GG82563_DSPD_CABLE_LENGTH 0x0007
1635 +/* Kumeran Mode Control Register (Page 193, Register 16) */
1636 +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
1638 +/* Max number of times Kumeran read/write should be validated */
1639 +#define GG82563_MAX_KMRN_RETRY 0x5
1641 +/* Power Management Control Register (Page 193, Register 20) */
1642 +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
1643 + /* 1=Enable SERDES Electrical Idle */
1645 +/* In-Band Control Register (Page 194, Register 18) */
1646 +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
1649 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_82571.c linux-2.6.22-10/drivers/net/e1000e/e1000_82571.c
1650 --- linux-2.6.22-0/drivers/net/e1000e/e1000_82571.c 1970-01-01 01:00:00.000000000 +0100
1651 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_82571.c 2008-10-14 01:51:32.000000000 +0200
1653 +/*******************************************************************************
1655 + Intel PRO/1000 Linux driver
1656 + Copyright(c) 1999 - 2008 Intel Corporation.
1658 + This program is free software; you can redistribute it and/or modify it
1659 + under the terms and conditions of the GNU General Public License,
1660 + version 2, as published by the Free Software Foundation.
1662 + This program is distributed in the hope it will be useful, but WITHOUT
1663 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1664 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1667 + You should have received a copy of the GNU General Public License along with
1668 + this program; if not, write to the Free Software Foundation, Inc.,
1669 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1671 + The full GNU General Public License is included in this distribution in
1672 + the file called "COPYING".
1674 + Contact Information:
1675 + Linux NICS <linux.nics@intel.com>
1676 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1677 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
1679 +*******************************************************************************/
1687 +#include "e1000_hw.h"
1689 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
1690 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
1691 +static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
1692 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
1693 +static void e1000_release_nvm_82571(struct e1000_hw *hw);
1694 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
1695 + u16 words, u16 *data);
1696 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
1697 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
1698 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
1699 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
1701 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
1702 +static s32 e1000_init_hw_82571(struct e1000_hw *hw);
1703 +static void e1000_clear_vfta_82571(struct e1000_hw *hw);
1704 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
1705 +static s32 e1000_led_on_82574(struct e1000_hw *hw);
1706 +static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1707 + u8 *mc_addr_list, u32 mc_addr_count,
1708 + u32 rar_used_count, u32 rar_count);
1709 +static s32 e1000_setup_link_82571(struct e1000_hw *hw);
1710 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
1711 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
1712 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
1713 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
1714 +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
1715 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
1716 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
1717 +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
1718 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
1719 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
1720 + u16 words, u16 *data);
1721 +static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
1722 +static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
1724 +struct e1000_dev_spec_82571 {
1725 + bool laa_is_present;
1729 + * e1000_init_phy_params_82571 - Init PHY func ptrs.
1730 + * @hw: pointer to the HW structure
1732 + * This is a function pointer entry point called by the api module.
1734 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
1736 + struct e1000_phy_info *phy = &hw->phy;
1737 + s32 ret_val = E1000_SUCCESS;
1739 + DEBUGFUNC("e1000_init_phy_params_82571");
1741 + if (hw->phy.media_type != e1000_media_type_copper) {
1742 + phy->type = e1000_phy_none;
1747 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1748 + phy->reset_delay_us = 100;
1750 + phy->ops.acquire = e1000_get_hw_semaphore_82571;
1751 + phy->ops.check_polarity = e1000_check_polarity_igp;
1752 + phy->ops.check_reset_block = e1000_check_reset_block_generic;
1753 + phy->ops.release = e1000_put_hw_semaphore_82571;
1754 + phy->ops.reset = e1000_phy_hw_reset_generic;
1755 + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
1756 + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
1757 + phy->ops.power_up = e1000_power_up_phy_copper;
1758 + phy->ops.power_down = e1000_power_down_phy_copper_82571;
1760 + switch (hw->mac.type) {
1763 + phy->type = e1000_phy_igp_2;
1764 + phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
1765 + phy->ops.get_info = e1000_get_phy_info_igp;
1766 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
1767 + phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
1768 + phy->ops.read_reg = e1000_read_phy_reg_igp;
1769 + phy->ops.write_reg = e1000_write_phy_reg_igp;
1771 + /* This uses above function pointers */
1772 + ret_val = e1000_get_phy_id_82571(hw);
1774 + /* Verify PHY ID */
1775 + if (phy->id != IGP01E1000_I_PHY_ID) {
1776 + ret_val = -E1000_ERR_PHY;
1781 + phy->type = e1000_phy_m88;
1782 + phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
1783 + phy->ops.get_info = e1000_get_phy_info_m88;
1784 + phy->ops.commit = e1000_phy_sw_reset_generic;
1785 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
1786 + phy->ops.get_cable_length = e1000_get_cable_length_m88;
1787 + phy->ops.read_reg = e1000_read_phy_reg_m88;
1788 + phy->ops.write_reg = e1000_write_phy_reg_m88;
1790 + /* This uses above function pointers */
1791 + ret_val = e1000_get_phy_id_82571(hw);
1793 + /* Verify PHY ID */
1794 + if (phy->id != M88E1111_I_PHY_ID) {
1795 + ret_val = -E1000_ERR_PHY;
1796 + DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
1801 + phy->type = e1000_phy_bm;
1802 + phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
1803 + phy->ops.get_info = e1000_get_phy_info_m88;
1804 + phy->ops.commit = e1000_phy_sw_reset_generic;
1805 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
1806 + phy->ops.get_cable_length = e1000_get_cable_length_m88;
1807 + phy->ops.read_reg = e1000_read_phy_reg_bm2;
1808 + phy->ops.write_reg = e1000_write_phy_reg_bm2;
1810 + /* This uses above function pointers */
1811 + ret_val = e1000_get_phy_id_82571(hw);
1812 + /* Verify PHY ID */
1813 + if (phy->id != BME1000_E_PHY_ID_R2) {
1814 + ret_val = -E1000_ERR_PHY;
1815 + DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
1820 + ret_val = -E1000_ERR_PHY;
1830 + * e1000_init_nvm_params_82571 - Init NVM func ptrs.
1831 + * @hw: pointer to the HW structure
1833 + * This is a function pointer entry point called by the api module.
1835 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
1837 + struct e1000_nvm_info *nvm = &hw->nvm;
1838 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1841 + DEBUGFUNC("e1000_init_nvm_params_82571");
1843 + nvm->opcode_bits = 8;
1844 + nvm->delay_usec = 1;
1845 + switch (nvm->override) {
1846 + case e1000_nvm_override_spi_large:
1847 + nvm->page_size = 32;
1848 + nvm->address_bits = 16;
1850 + case e1000_nvm_override_spi_small:
1851 + nvm->page_size = 8;
1852 + nvm->address_bits = 8;
1855 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
1856 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
1860 + switch (hw->mac.type) {
1863 + if (((eecd >> 15) & 0x3) == 0x3) {
1864 + nvm->type = e1000_nvm_flash_hw;
1865 + nvm->word_size = 2048;
1867 + * Autonomous Flash update bit must be cleared due
1868 + * to Flash update issue.
1870 + eecd &= ~E1000_EECD_AUPDEN;
1871 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
1874 + /* Fall Through */
1876 + nvm->type = e1000_nvm_eeprom_spi;
1877 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
1878 + E1000_EECD_SIZE_EX_SHIFT);
1880 + * Added to a constant, "size" becomes the left-shift value
1881 + * for setting word_size.
1883 + size += NVM_WORD_SIZE_BASE_SHIFT;
1885 + /* EEPROM access above 16k is unsupported */
1888 + nvm->word_size = 1 << size;
1892 + /* Function Pointers */
1893 + nvm->ops.acquire = e1000_acquire_nvm_82571;
1894 + nvm->ops.read = e1000_read_nvm_eerd;
1895 + nvm->ops.release = e1000_release_nvm_82571;
1896 + nvm->ops.update = e1000_update_nvm_checksum_82571;
1897 + nvm->ops.validate = e1000_validate_nvm_checksum_82571;
1898 + nvm->ops.valid_led_default = e1000_valid_led_default_82571;
1899 + nvm->ops.write = e1000_write_nvm_82571;
1901 + return E1000_SUCCESS;
1905 + * e1000_init_mac_params_82571 - Init MAC func ptrs.
1906 + * @hw: pointer to the HW structure
1908 + * This is a function pointer entry point called by the api module.
1910 +static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
1912 + struct e1000_mac_info *mac = &hw->mac;
1913 + s32 ret_val = E1000_SUCCESS;
1915 + DEBUGFUNC("e1000_init_mac_params_82571");
1917 + /* Set media type */
1918 + switch (hw->device_id) {
1919 + case E1000_DEV_ID_82571EB_FIBER:
1920 + case E1000_DEV_ID_82572EI_FIBER:
1921 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
1922 + hw->phy.media_type = e1000_media_type_fiber;
1924 + case E1000_DEV_ID_82571EB_SERDES:
1925 + case E1000_DEV_ID_82571EB_SERDES_DUAL:
1926 + case E1000_DEV_ID_82571EB_SERDES_QUAD:
1927 + case E1000_DEV_ID_82572EI_SERDES:
1928 + hw->phy.media_type = e1000_media_type_internal_serdes;
1931 + hw->phy.media_type = e1000_media_type_copper;
1935 + /* Set mta register count */
1936 + mac->mta_reg_count = 128;
1937 + /* Set rar entry count */
1938 + mac->rar_entry_count = E1000_RAR_ENTRIES;
1939 + /* Set if part includes ASF firmware */
1940 + mac->asf_firmware_present = true;
1941 + /* Set if manageability features are enabled. */
1942 + mac->arc_subsystem_valid =
1943 + (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
1946 + /* Function pointers */
1948 + /* bus type/speed/width */
1949 + mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
1951 + mac->ops.reset_hw = e1000_reset_hw_82571;
1952 + /* hw initialization */
1953 + mac->ops.init_hw = e1000_init_hw_82571;
1955 + mac->ops.setup_link = e1000_setup_link_82571;
1956 + /* physical interface link setup */
1957 + mac->ops.setup_physical_interface =
1958 + (hw->phy.media_type == e1000_media_type_copper)
1959 + ? e1000_setup_copper_link_82571
1960 + : e1000_setup_fiber_serdes_link_82571;
1961 + /* check for link */
1962 + switch (hw->phy.media_type) {
1963 + case e1000_media_type_copper:
1964 + mac->ops.check_for_link = e1000_check_for_copper_link_generic;
1966 + case e1000_media_type_fiber:
1967 + mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
1969 + case e1000_media_type_internal_serdes:
1970 + mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
1973 + ret_val = -E1000_ERR_CONFIG;
1977 + /* check management mode */
1978 + switch (hw->mac.type) {
1980 + mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
1983 + mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
1986 + /* multicast address update */
1987 + mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571;
1988 + /* writing VFTA */
1989 + mac->ops.write_vfta = e1000_write_vfta_generic;
1990 + /* clearing VFTA */
1991 + mac->ops.clear_vfta = e1000_clear_vfta_82571;
1993 + mac->ops.mta_set = e1000_mta_set_generic;
1994 + /* read mac address */
1995 + mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
1997 + mac->ops.blink_led = e1000_blink_led_generic;
1999 + mac->ops.setup_led = e1000_setup_led_generic;
2001 + mac->ops.cleanup_led = e1000_cleanup_led_generic;
2002 + /* turn on/off LED */
2003 + switch (hw->mac.type) {
2005 + mac->ops.led_on = e1000_led_on_82574;
2008 + mac->ops.led_on = e1000_led_on_generic;
2011 + mac->ops.led_off = e1000_led_off_generic;
2012 + /* remove device */
2013 + mac->ops.remove_device = e1000_remove_device_generic;
2014 + /* clear hardware counters */
2015 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
2017 + mac->ops.get_link_up_info =
2018 + (hw->phy.media_type == e1000_media_type_copper)
2019 + ? e1000_get_speed_and_duplex_copper_generic
2020 + : e1000_get_speed_and_duplex_fiber_serdes_generic;
2022 + hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571);
2024 + /* Device-specific structure allocation */
2025 + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
2032 + * e1000_init_function_pointers_82571 - Init func ptrs.
2033 + * @hw: pointer to the HW structure
2035 + * The only function explicitly called by the api module to initialize
2036 + * all function pointers and parameters.
2038 +void e1000_init_function_pointers_82571(struct e1000_hw *hw)
2040 + DEBUGFUNC("e1000_init_function_pointers_82571");
2042 + e1000_init_mac_ops_generic(hw);
2043 + e1000_init_nvm_ops_generic(hw);
2044 + hw->mac.ops.init_params = e1000_init_mac_params_82571;
2045 + hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
2046 + hw->phy.ops.init_params = e1000_init_phy_params_82571;
2050 + * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
2051 + * @hw: pointer to the HW structure
2053 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
2054 + * revision in the hardware structure.
2056 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
2058 + struct e1000_phy_info *phy = &hw->phy;
2059 + s32 ret_val = E1000_SUCCESS;
2062 + DEBUGFUNC("e1000_get_phy_id_82571");
2064 + switch (hw->mac.type) {
2068 + * The 82571 firmware may still be configuring the PHY.
2069 + * In this case, we cannot access the PHY until the
2070 + * configuration is done. So we explicitly set the
2073 + phy->id = IGP01E1000_I_PHY_ID;
2076 + ret_val = e1000_get_phy_id(hw);
2079 + ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
2083 + phy->id = (u32)(phy_id << 16);
2085 + ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
2089 + phy->id |= (u32)(phy_id);
2090 + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
2093 + ret_val = -E1000_ERR_PHY;
2102 + * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
2103 + * @hw: pointer to the HW structure
2105 + * Acquire the HW semaphore to access the PHY or NVM
2107 +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
2110 + s32 ret_val = E1000_SUCCESS;
2111 + s32 timeout = hw->nvm.word_size + 1;
2114 + DEBUGFUNC("e1000_get_hw_semaphore_82571");
2116 + /* Get the FW semaphore. */
2117 + for (i = 0; i < timeout; i++) {
2118 + swsm = E1000_READ_REG(hw, E1000_SWSM);
2119 + E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
2121 + /* Semaphore acquired if bit latched */
2122 + if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
2128 + if (i == timeout) {
2129 + /* Release semaphores */
2130 + e1000_put_hw_semaphore_generic(hw);
2131 + DEBUGOUT("Driver can't access the NVM\n");
2132 + ret_val = -E1000_ERR_NVM;
2141 + * e1000_put_hw_semaphore_82571 - Release hardware semaphore
2142 + * @hw: pointer to the HW structure
2144 + * Release hardware semaphore used to access the PHY or NVM
2146 +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
2150 + DEBUGFUNC("e1000_put_hw_semaphore_82571");
2152 + swsm = E1000_READ_REG(hw, E1000_SWSM);
2154 + swsm &= ~E1000_SWSM_SWESMBI;
2156 + E1000_WRITE_REG(hw, E1000_SWSM, swsm);
2160 + * e1000_acquire_nvm_82571 - Request for access to the EEPROM
2161 + * @hw: pointer to the HW structure
2163 + * To gain access to the EEPROM, first we must obtain a hardware semaphore.
2164 + * Then for non-82573 hardware, set the EEPROM access request bit and wait
2165 + * for EEPROM access grant bit. If the access grant bit is not set, release
2166 + * hardware semaphore.
2168 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
2172 + DEBUGFUNC("e1000_acquire_nvm_82571");
2174 + ret_val = e1000_get_hw_semaphore_82571(hw);
2178 + if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
2179 + ret_val = e1000_acquire_nvm_generic(hw);
2182 + e1000_put_hw_semaphore_82571(hw);
2189 + * e1000_release_nvm_82571 - Release exclusive access to EEPROM
2190 + * @hw: pointer to the HW structure
2192 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
2194 +static void e1000_release_nvm_82571(struct e1000_hw *hw)
2196 + DEBUGFUNC("e1000_release_nvm_82571");
2198 + e1000_release_nvm_generic(hw);
2199 + e1000_put_hw_semaphore_82571(hw);
2203 + * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
2204 + * @hw: pointer to the HW structure
2205 + * @offset: offset within the EEPROM to be written to
2206 + * @words: number of words to write
2207 + * @data: 16 bit word(s) to be written to the EEPROM
2209 + * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
2211 + * If e1000_update_nvm_checksum is not called after this function, the
2212 + * EEPROM will most likely contain an invalid checksum.
2214 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
2217 + s32 ret_val = E1000_SUCCESS;
2219 + DEBUGFUNC("e1000_write_nvm_82571");
2221 + switch (hw->mac.type) {
2224 + ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
2228 + ret_val = e1000_write_nvm_spi(hw, offset, words, data);
2231 + ret_val = -E1000_ERR_NVM;
2239 + * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
2240 + * @hw: pointer to the HW structure
2242 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2243 + * up to the checksum. Then calculates the EEPROM checksum and writes the
2244 + * value to the EEPROM.
2246 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
2252 + DEBUGFUNC("e1000_update_nvm_checksum_82571");
2254 + ret_val = e1000_update_nvm_checksum_generic(hw);
2259 + * If our nvm is an EEPROM, then we're done
2260 + * otherwise, commit the checksum to the flash NVM.
2262 + if (hw->nvm.type != e1000_nvm_flash_hw)
2265 + /* Check for pending operations. */
2266 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
2268 + if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
2272 + if (i == E1000_FLASH_UPDATES) {
2273 + ret_val = -E1000_ERR_NVM;
2277 + /* Reset the firmware if using STM opcode. */
2278 + if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
2280 + * The enabling of and the actual reset must be done
2281 + * in two write cycles.
2283 + E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
2284 + E1000_WRITE_FLUSH(hw);
2285 + E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
2288 + /* Commit the write to flash */
2289 + eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
2290 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
2292 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
2294 + if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
2298 + if (i == E1000_FLASH_UPDATES) {
2299 + ret_val = -E1000_ERR_NVM;
2308 + * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
2309 + * @hw: pointer to the HW structure
2311 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2312 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2314 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
2316 + DEBUGFUNC("e1000_validate_nvm_checksum_82571");
2318 + if (hw->nvm.type == e1000_nvm_flash_hw)
2319 + e1000_fix_nvm_checksum_82571(hw);
2321 + return e1000_validate_nvm_checksum_generic(hw);
2325 + * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
2326 + * @hw: pointer to the HW structure
2327 + * @offset: offset within the EEPROM to be written to
2328 + * @words: number of words to write
2329 + * @data: 16 bit word(s) to be written to the EEPROM
2331 + * After checking for invalid values, poll the EEPROM to ensure the previous
2332 + * command has completed before trying to write the next word. After write
2333 + * poll for completion.
2335 + * If e1000_update_nvm_checksum is not called after this function, the
2336 + * EEPROM will most likely contain an invalid checksum.
2338 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
2339 + u16 words, u16 *data)
2341 + struct e1000_nvm_info *nvm = &hw->nvm;
2345 + DEBUGFUNC("e1000_write_nvm_eewr_82571");
2348 + * A check for invalid values: offset too large, too many words,
2349 + * and not enough words.
2351 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2353 + DEBUGOUT("nvm parameter(s) out of bounds\n");
2354 + ret_val = -E1000_ERR_NVM;
2358 + for (i = 0; i < words; i++) {
2359 + eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
2360 + ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
2361 + E1000_NVM_RW_REG_START;
2363 + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
2367 + E1000_WRITE_REG(hw, E1000_EEWR, eewr);
2369 + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
2379 + * e1000_get_cfg_done_82571 - Poll for configuration done
2380 + * @hw: pointer to the HW structure
2382 + * Reads the management control register for the config done bit to be set.
2384 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
2386 + s32 timeout = PHY_CFG_TIMEOUT;
2387 + s32 ret_val = E1000_SUCCESS;
2389 + DEBUGFUNC("e1000_get_cfg_done_82571");
2392 + if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
2398 + DEBUGOUT("MNG configuration cycle has not completed.\n");
2399 + ret_val = -E1000_ERR_RESET;
2408 + * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
2409 + * @hw: pointer to the HW structure
2410 + * @active: true to enable LPLU, false to disable
2412 + * Sets the LPLU D0 state according to the active flag. When activating LPLU
2413 + * this function also disables smart speed and vice versa. LPLU will not be
2414 + * activated unless the device autonegotiation advertisement meets standards
2415 + * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
2416 + * pointer entry point only called by PHY setup routines.
2418 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
2420 + struct e1000_phy_info *phy = &hw->phy;
2421 + s32 ret_val = E1000_SUCCESS;
2424 + DEBUGFUNC("e1000_set_d0_lplu_state_82571");
2426 + if (!(phy->ops.read_reg))
2429 + ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2434 + data |= IGP02E1000_PM_D0_LPLU;
2435 + ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2440 + /* When LPLU is enabled, we should disable SmartSpeed */
2441 + ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2443 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2444 + ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2449 + data &= ~IGP02E1000_PM_D0_LPLU;
2450 + ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2453 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2454 + * during Dx states where the power conservation is most
2455 + * important. During driver activity we should enable
2456 + * SmartSpeed, so performance is maintained.
2458 + if (phy->smart_speed == e1000_smart_speed_on) {
2459 + ret_val = phy->ops.read_reg(hw,
2460 + IGP01E1000_PHY_PORT_CONFIG,
2465 + data |= IGP01E1000_PSCFR_SMART_SPEED;
2466 + ret_val = phy->ops.write_reg(hw,
2467 + IGP01E1000_PHY_PORT_CONFIG,
2471 + } else if (phy->smart_speed == e1000_smart_speed_off) {
2472 + ret_val = phy->ops.read_reg(hw,
2473 + IGP01E1000_PHY_PORT_CONFIG,
2478 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2479 + ret_val = phy->ops.write_reg(hw,
2480 + IGP01E1000_PHY_PORT_CONFIG,
2492 + * e1000_reset_hw_82571 - Reset hardware
2493 + * @hw: pointer to the HW structure
2495 + * This resets the hardware into a known state. This is a
2496 + * function pointer entry point called by the api module.
2498 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
2500 + u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
2504 + DEBUGFUNC("e1000_reset_hw_82571");
2507 + * Prevent the PCI-E bus from sticking if there is no TLP connection
2508 + * on the last TLP read/write transaction when MAC is reset.
2510 + ret_val = e1000_disable_pcie_master_generic(hw);
2512 + DEBUGOUT("PCI-E Master disable polling has failed.\n");
2515 + DEBUGOUT("Masking off all interrupts\n");
2516 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2518 + E1000_WRITE_REG(hw, E1000_RCTL, 0);
2519 + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2520 + E1000_WRITE_FLUSH(hw);
2525 + * Must acquire the MDIO ownership before MAC reset.
2526 + * Ownership defaults to firmware after a reset.
2528 + if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
2529 + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2530 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
2533 + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2534 + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2536 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2539 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
2543 + } while (i < MDIO_OWNERSHIP_TIMEOUT);
2546 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
2548 + DEBUGOUT("Issuing a global reset to MAC\n");
2549 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
2551 + if (hw->nvm.type == e1000_nvm_flash_hw) {
2553 + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2554 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2555 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2556 + E1000_WRITE_FLUSH(hw);
2559 + ret_val = e1000_get_auto_rd_done_generic(hw);
2561 + /* We don't want to continue accessing MAC registers. */
2565 + * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
2566 + * Need to wait for Phy configuration completion before accessing
2569 + if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
2572 + /* Clear any pending interrupt events. */
2573 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2574 + icr = E1000_READ_REG(hw, E1000_ICR);
2576 + if (!(e1000_check_alt_mac_addr_generic(hw)))
2577 + e1000_set_laa_state_82571(hw, true);
2584 + * e1000_init_hw_82571 - Initialize hardware
2585 + * @hw: pointer to the HW structure
2587 + * This inits the hardware readying it for operation.
2589 +static s32 e1000_init_hw_82571(struct e1000_hw *hw)
2591 + struct e1000_mac_info *mac = &hw->mac;
2594 + u16 i, rar_count = mac->rar_entry_count;
2596 + DEBUGFUNC("e1000_init_hw_82571");
2598 + e1000_initialize_hw_bits_82571(hw);
2600 + /* Initialize identification LED */
2601 + ret_val = e1000_id_led_init_generic(hw);
2603 + DEBUGOUT("Error initializing identification LED\n");
2604 + /* This is not fatal and we should not stop init due to this */
2607 + /* Disabling VLAN filtering */
2608 + DEBUGOUT("Initializing the IEEE VLAN\n");
2609 + mac->ops.clear_vfta(hw);
2611 + /* Setup the receive address. */
2613 + * If, however, a locally administered address was assigned to the
2614 + * 82571, we must reserve a RAR for it to work around an issue where
2615 + * resetting one port will reload the MAC on the other port.
2617 + if (e1000_get_laa_state_82571(hw))
2619 + e1000_init_rx_addrs_generic(hw, rar_count);
2621 + /* Zero out the Multicast HASH table */
2622 + DEBUGOUT("Zeroing the MTA\n");
2623 + for (i = 0; i < mac->mta_reg_count; i++)
2624 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2626 + /* Setup link and flow control */
2627 + ret_val = mac->ops.setup_link(hw);
2629 + /* Set the transmit descriptor write-back policy */
2630 + reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
2631 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
2632 + E1000_TXDCTL_FULL_TX_DESC_WB |
2633 + E1000_TXDCTL_COUNT_DESC;
2634 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
2636 + /* ...for both queues. */
2637 + if (mac->type != e1000_82573 && mac->type != e1000_82574) {
2638 + reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
2639 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
2640 + E1000_TXDCTL_FULL_TX_DESC_WB |
2641 + E1000_TXDCTL_COUNT_DESC;
2642 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
2644 + e1000_enable_tx_pkt_filtering_generic(hw);
2645 + reg_data = E1000_READ_REG(hw, E1000_GCR);
2646 + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2647 + E1000_WRITE_REG(hw, E1000_GCR, reg_data);
2651 + * Clear all of the statistics registers (clear on read). It is
2652 + * important that we do this after we have tried to establish link
2653 + * because the symbol error count will increment wildly if there
2656 + e1000_clear_hw_cntrs_82571(hw);
2662 + * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
2663 + * @hw: pointer to the HW structure
2665 + * Initializes required hardware-dependent bits needed for normal operation.
2667 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
2671 + DEBUGFUNC("e1000_initialize_hw_bits_82571");
2673 + if (hw->mac.disable_hw_init_bits)
2676 + /* Transmit Descriptor Control 0 */
2677 + reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2679 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2681 + /* Transmit Descriptor Control 1 */
2682 + reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2684 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2686 + /* Transmit Arbitration Control 0 */
2687 + reg = E1000_READ_REG(hw, E1000_TARC(0));
2688 + reg &= ~(0xF << 27); /* 30:27 */
2689 + switch (hw->mac.type) {
2692 + reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
2697 + E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2699 + /* Transmit Arbitration Control 1 */
2700 + reg = E1000_READ_REG(hw, E1000_TARC(1));
2701 + switch (hw->mac.type) {
2704 + reg &= ~((1 << 29) | (1 << 30));
2705 + reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
2706 + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2707 + reg &= ~(1 << 28);
2710 + E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2716 + /* Device Control */
2717 + if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
2718 + reg = E1000_READ_REG(hw, E1000_CTRL);
2719 + reg &= ~(1 << 29);
2720 + E1000_WRITE_REG(hw, E1000_CTRL, reg);
2723 + /* Extended Device Control */
2724 + if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
2725 + reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2726 + reg &= ~(1 << 23);
2728 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2731 + /* PCI-Ex Control Register */
2732 + if (hw->mac.type == e1000_82574) {
2733 + reg = E1000_READ_REG(hw, E1000_GCR);
2735 + E1000_WRITE_REG(hw, E1000_GCR, reg);
2743 + * e1000_clear_vfta_82571 - Clear VLAN filter table
2744 + * @hw: pointer to the HW structure
2746 + * Clears the register array which contains the VLAN filter table by
2747 + * setting all the values to 0.
2749 +static void e1000_clear_vfta_82571(struct e1000_hw *hw)
2752 + u32 vfta_value = 0;
2753 + u32 vfta_offset = 0;
2754 + u32 vfta_bit_in_reg = 0;
2756 + DEBUGFUNC("e1000_clear_vfta_82571");
2758 + if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
2759 + if (hw->mng_cookie.vlan_id != 0) {
2761 + * The VFTA is a 4096b bit-field, each identifying
2762 + * a single VLAN ID. The following operations
2763 + * determine which 32b entry (i.e. offset) into the
2764 + * array we want to set the VLAN ID (i.e. bit) of
2765 + * the manageability unit.
2767 + vfta_offset = (hw->mng_cookie.vlan_id >>
2768 + E1000_VFTA_ENTRY_SHIFT) &
2769 + E1000_VFTA_ENTRY_MASK;
2770 + vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
2771 + E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
2774 + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2776 + * If the offset we want to clear is the same offset of the
2777 + * manageability VLAN ID, then clear all bits except that of
2778 + * the manageability unit.
2780 + vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
2781 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
2782 + E1000_WRITE_FLUSH(hw);
2787 + * e1000_check_mng_mode_82574 - Check manageability is enabled
2788 + * @hw: pointer to the HW structure
2790 + * Reads the NVM Initialization Control Word 2 and returns true
2791 + * (>0) if any manageability is enabled, else false (0).
2793 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
2797 + DEBUGFUNC("e1000_check_mng_mode_82574");
2799 + hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2800 + return ((data & E1000_NVM_INIT_CTRL2_MNGM) != 0);
2804 + * e1000_led_on_82574 - Turn LED on
2805 + * @hw: pointer to the HW structure
2809 +static s32 e1000_led_on_82574(struct e1000_hw *hw)
2814 + DEBUGFUNC("e1000_led_on_82574");
2816 + ctrl = hw->mac.ledctl_mode2;
2817 + if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
2819 + * If no link, then turn LED on by setting the invert bit
2820 + * for each LED that's "on" (0x0E) in ledctl_mode2.
2822 + for (i = 0; i < 4; i++)
2823 + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
2824 + E1000_LEDCTL_MODE_LED_ON)
2825 + ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
2827 + E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
2829 + return E1000_SUCCESS;
2833 + * e1000_update_mc_addr_list_82571 - Update Multicast addresses
2834 + * @hw: pointer to the HW structure
2835 + * @mc_addr_list: array of multicast addresses to program
2836 + * @mc_addr_count: number of multicast addresses to program
2837 + * @rar_used_count: the first RAR register free to program
2838 + * @rar_count: total number of supported Receive Address Registers
2840 + * Updates the Receive Address Registers and Multicast Table Array.
2841 + * The caller must have a packed mc_addr_list of multicast addresses.
2842 + * The parameter rar_count will usually be hw->mac.rar_entry_count
2843 + * unless there are workarounds that change this.
2845 +static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
2846 + u8 *mc_addr_list, u32 mc_addr_count,
2847 + u32 rar_used_count, u32 rar_count)
2849 + DEBUGFUNC("e1000_update_mc_addr_list_82571");
2851 + if (e1000_get_laa_state_82571(hw))
2854 + e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
2855 + rar_used_count, rar_count);
2859 + * e1000_setup_link_82571 - Setup flow control and link settings
2860 + * @hw: pointer to the HW structure
2862 + * Determines which flow control settings to use, then configures flow
2863 + * control. Calls the appropriate media-specific link configuration
2864 + * function. Assuming the adapter has a valid link partner, a valid link
2865 + * should be established. Assumes the hardware has previously been reset
2866 + * and the transmitter and receiver are not enabled.
2868 +static s32 e1000_setup_link_82571(struct e1000_hw *hw)
2870 + DEBUGFUNC("e1000_setup_link_82571");
2873 + * 82573 does not have a word in the NVM to determine
2874 + * the default flow control setting, so we explicitly
2877 + if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
2878 + hw->fc.type == e1000_fc_default)
2879 + hw->fc.type = e1000_fc_full;
2881 + return e1000_setup_link_generic(hw);
2885 + * e1000_setup_copper_link_82571 - Configure copper link settings
2886 + * @hw: pointer to the HW structure
2888 + * Configures the link for auto-neg or forced speed and duplex. Then we check
2889 + * for link, once link is established calls to configure collision distance
2890 + * and flow control are called.
2892 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
2894 + u32 ctrl, led_ctrl;
2897 + DEBUGFUNC("e1000_setup_copper_link_82571");
2899 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
2900 + ctrl |= E1000_CTRL_SLU;
2901 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2902 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2904 + switch (hw->phy.type) {
2905 + case e1000_phy_m88:
2906 + case e1000_phy_bm:
2907 + ret_val = e1000_copper_link_setup_m88(hw);
2909 + case e1000_phy_igp_2:
2910 + ret_val = e1000_copper_link_setup_igp(hw);
2911 + /* Setup activity LED */
2912 + led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
2913 + led_ctrl &= IGP_ACTIVITY_LED_MASK;
2914 + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2915 + E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
2918 + ret_val = -E1000_ERR_PHY;
2925 + ret_val = e1000_setup_copper_link_generic(hw);
2932 + * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
2933 + * @hw: pointer to the HW structure
2935 + * Configures collision distance and flow control for fiber and serdes links.
2936 + * Upon successful setup, poll for link.
2938 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
2940 + DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
2942 + switch (hw->mac.type) {
2946 + * If SerDes loopback mode is entered, there is no form
2947 + * of reset to take the adapter out of that mode. So we
2948 + * have to explicitly take the adapter out of loopback
2949 + * mode. This prevents drivers from twiddling their thumbs
2950 + * if another tool failed to take it out of loopback mode.
2952 + E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
2958 + return e1000_setup_fiber_serdes_link_generic(hw);
2962 + * e1000_valid_led_default_82571 - Verify a valid default LED config
2963 + * @hw: pointer to the HW structure
2964 + * @data: pointer to the NVM (EEPROM)
2966 + * Read the EEPROM for the current default LED configuration. If the
2967 + * LED configuration is not valid, set to a valid LED configuration.
2969 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
2973 + DEBUGFUNC("e1000_valid_led_default_82571");
2975 + ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2977 + DEBUGOUT("NVM Read Error\n");
2981 + if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
2982 + *data == ID_LED_RESERVED_F746)
2983 + *data = ID_LED_DEFAULT_82573;
2984 + else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
2985 + *data = ID_LED_DEFAULT;
2991 + * e1000_get_laa_state_82571 - Get locally administered address state
2992 + * @hw: pointer to the HW structure
2994 + * Retrieve and return the current locally administered address state.
2996 +bool e1000_get_laa_state_82571(struct e1000_hw *hw)
2998 + struct e1000_dev_spec_82571 *dev_spec;
2999 + bool state = false;
3001 + DEBUGFUNC("e1000_get_laa_state_82571");
3003 + if (hw->mac.type != e1000_82571)
3006 + dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec;
3008 + state = dev_spec->laa_is_present;
3015 + * e1000_set_laa_state_82571 - Set locally administered address state
3016 + * @hw: pointer to the HW structure
3017 + * @state: enable/disable locally administered address
3019 + * Enable/Disable the current locally administered address state.
3021 +void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
3023 + struct e1000_dev_spec_82571 *dev_spec;
3025 + DEBUGFUNC("e1000_set_laa_state_82571");
3027 + if (hw->mac.type != e1000_82571)
3030 + dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec;
3032 + dev_spec->laa_is_present = state;
3034 + /* If workaround is activated... */
3037 + * Hold a copy of the LAA in RAR[14] This is done so that
3038 + * between the time RAR[0] gets clobbered and the time it
3039 + * gets fixed, the actual LAA is in one of the RARs and no
3040 + * incoming packets directed to this port are dropped.
3041 + * Eventually the LAA will be in RAR[0] and RAR[14].
3043 + e1000_rar_set_generic(hw, hw->mac.addr,
3044 + hw->mac.rar_entry_count - 1);
3052 + * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
3053 + * @hw: pointer to the HW structure
3055 + * Verifies that the EEPROM has completed the update. After updating the
3056 + * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
3057 + * the checksum fix is not implemented, we need to set the bit and update
3058 + * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
3059 + * we need to return bad checksum.
3061 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
3063 + struct e1000_nvm_info *nvm = &hw->nvm;
3064 + s32 ret_val = E1000_SUCCESS;
3067 + DEBUGFUNC("e1000_fix_nvm_checksum_82571");
3069 + if (nvm->type != e1000_nvm_flash_hw)
3073 + * Check bit 4 of word 10h. If it is 0, firmware is done updating
3074 + * 10h-12h. Checksum may need to be fixed.
3076 + ret_val = nvm->ops.read(hw, 0x10, 1, &data);
3080 + if (!(data & 0x10)) {
3082 + * Read 0x23 and check bit 15. This bit is a 1
3083 + * when the checksum has already been fixed. If
3084 + * the checksum is still wrong and this bit is a
3085 + * 1, we need to return bad checksum. Otherwise,
3086 + * we need to set this bit to a 1 and update the
3089 + ret_val = nvm->ops.read(hw, 0x23, 1, &data);
3093 + if (!(data & 0x8000)) {
3095 + ret_val = nvm->ops.write(hw, 0x23, 1, &data);
3098 + ret_val = nvm->ops.update(hw);
3107 + * e1000_read_mac_addr_82571 - Read device MAC address
3108 + * @hw: pointer to the HW structure
3110 +static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
3112 + s32 ret_val = E1000_SUCCESS;
3114 + DEBUGFUNC("e1000_read_mac_addr_82571");
3115 + if (e1000_check_alt_mac_addr_generic(hw))
3116 + ret_val = e1000_read_mac_addr_generic(hw);
3122 + * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
3123 + * @hw: pointer to the HW structure
3125 + * In the case of a PHY power down to save power, or to turn off link during a
3126 + * driver unload, or wake on lan is not enabled, remove the link.
3128 +static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
3130 + struct e1000_phy_info *phy = &hw->phy;
3131 + struct e1000_mac_info *mac = &hw->mac;
3133 + if (!(phy->ops.check_reset_block))
3136 + /* If the management interface is not enabled, then power down */
3137 + if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
3138 + e1000_power_down_phy_copper(hw);
3144 + * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
3145 + * @hw: pointer to the HW structure
3147 + * Clears the hardware counters by reading the counter registers.
3149 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
3151 + volatile u32 temp;
3153 + DEBUGFUNC("e1000_clear_hw_cntrs_82571");
3155 + e1000_clear_hw_cntrs_base_generic(hw);
3156 + temp = E1000_READ_REG(hw, E1000_PRC64);
3157 + temp = E1000_READ_REG(hw, E1000_PRC127);
3158 + temp = E1000_READ_REG(hw, E1000_PRC255);
3159 + temp = E1000_READ_REG(hw, E1000_PRC511);
3160 + temp = E1000_READ_REG(hw, E1000_PRC1023);
3161 + temp = E1000_READ_REG(hw, E1000_PRC1522);
3162 + temp = E1000_READ_REG(hw, E1000_PTC64);
3163 + temp = E1000_READ_REG(hw, E1000_PTC127);
3164 + temp = E1000_READ_REG(hw, E1000_PTC255);
3165 + temp = E1000_READ_REG(hw, E1000_PTC511);
3166 + temp = E1000_READ_REG(hw, E1000_PTC1023);
3167 + temp = E1000_READ_REG(hw, E1000_PTC1522);
3169 + temp = E1000_READ_REG(hw, E1000_ALGNERRC);
3170 + temp = E1000_READ_REG(hw, E1000_RXERRC);
3171 + temp = E1000_READ_REG(hw, E1000_TNCRS);
3172 + temp = E1000_READ_REG(hw, E1000_CEXTERR);
3173 + temp = E1000_READ_REG(hw, E1000_TSCTC);
3174 + temp = E1000_READ_REG(hw, E1000_TSCTFC);
3176 + temp = E1000_READ_REG(hw, E1000_MGTPRC);
3177 + temp = E1000_READ_REG(hw, E1000_MGTPDC);
3178 + temp = E1000_READ_REG(hw, E1000_MGTPTC);
3180 + temp = E1000_READ_REG(hw, E1000_IAC);
3181 + temp = E1000_READ_REG(hw, E1000_ICRXOC);
3183 + temp = E1000_READ_REG(hw, E1000_ICRXPTC);
3184 + temp = E1000_READ_REG(hw, E1000_ICRXATC);
3185 + temp = E1000_READ_REG(hw, E1000_ICTXPTC);
3186 + temp = E1000_READ_REG(hw, E1000_ICTXATC);
3187 + temp = E1000_READ_REG(hw, E1000_ICTXQEC);
3188 + temp = E1000_READ_REG(hw, E1000_ICTXQMTC);
3189 + temp = E1000_READ_REG(hw, E1000_ICRXDMTC);
3191 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_82571.h linux-2.6.22-10/drivers/net/e1000e/e1000_82571.h
3192 --- linux-2.6.22-0/drivers/net/e1000e/e1000_82571.h 1970-01-01 01:00:00.000000000 +0100
3193 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_82571.h 2008-10-14 01:51:32.000000000 +0200
3195 +/*******************************************************************************
3197 + Intel PRO/1000 Linux driver
3198 + Copyright(c) 1999 - 2008 Intel Corporation.
3200 + This program is free software; you can redistribute it and/or modify it
3201 + under the terms and conditions of the GNU General Public License,
3202 + version 2, as published by the Free Software Foundation.
3204 + This program is distributed in the hope it will be useful, but WITHOUT
3205 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3206 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3209 + You should have received a copy of the GNU General Public License along with
3210 + this program; if not, write to the Free Software Foundation, Inc.,
3211 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3213 + The full GNU General Public License is included in this distribution in
3214 + the file called "COPYING".
3216 + Contact Information:
3217 + Linux NICS <linux.nics@intel.com>
3218 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
3219 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
3221 +*******************************************************************************/
3223 +#ifndef _E1000_82571_H_
3224 +#define _E1000_82571_H_
3226 +#define ID_LED_RESERVED_F746 0xF746
3227 +#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
3228 + (ID_LED_OFF1_ON2 << 8) | \
3229 + (ID_LED_DEF1_DEF2 << 4) | \
3230 + (ID_LED_DEF1_DEF2))
3232 +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
3234 +/* Intr Throttling - RW */
3235 +#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
3237 +#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
3238 +#define E1000_EIAC_MASK_82574 0x01F00000
3240 +#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
3242 +#define E1000_RXCFGL 0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
3244 +bool e1000_get_laa_state_82571(struct e1000_hw *hw);
3245 +void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);
3248 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_defines.h linux-2.6.22-10/drivers/net/e1000e/e1000_defines.h
3249 --- linux-2.6.22-0/drivers/net/e1000e/e1000_defines.h 1970-01-01 01:00:00.000000000 +0100
3250 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_defines.h 2008-10-14 01:51:32.000000000 +0200
3252 +/*******************************************************************************
3254 + Intel PRO/1000 Linux driver
3255 + Copyright(c) 1999 - 2008 Intel Corporation.
3257 + This program is free software; you can redistribute it and/or modify it
3258 + under the terms and conditions of the GNU General Public License,
3259 + version 2, as published by the Free Software Foundation.
3261 + This program is distributed in the hope it will be useful, but WITHOUT
3262 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3263 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3266 + You should have received a copy of the GNU General Public License along with
3267 + this program; if not, write to the Free Software Foundation, Inc.,
3268 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3270 + The full GNU General Public License is included in this distribution in
3271 + the file called "COPYING".
3273 + Contact Information:
3274 + Linux NICS <linux.nics@intel.com>
3275 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
3276 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
3278 +*******************************************************************************/
3280 +#ifndef _E1000_DEFINES_H_
3281 +#define _E1000_DEFINES_H_
3283 +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
3284 +#define REQ_TX_DESCRIPTOR_MULTIPLE 8
3285 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8
3287 +/* Definitions for power management and wakeup registers */
3288 +/* Wake Up Control */
3289 +#define E1000_WUC_APME 0x00000001 /* APM Enable */
3290 +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
3291 +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
3292 +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
3293 +#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
3294 +#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
3295 +#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
3296 +#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
3298 +/* Wake Up Filter Control */
3299 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
3300 +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
3301 +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
3302 +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
3303 +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
3304 +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
3305 +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
3306 +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
3307 +#define E1000_WUFC_IGNORE_TCO_BM 0x00000800 /* Ignore WakeOn TCO packets */
3308 +#define E1000_WUFC_FLX0_BM 0x00001000 /* Flexible Filter 0 Enable */
3309 +#define E1000_WUFC_FLX1_BM 0x00002000 /* Flexible Filter 1 Enable */
3310 +#define E1000_WUFC_FLX2_BM 0x00004000 /* Flexible Filter 2 Enable */
3311 +#define E1000_WUFC_FLX3_BM 0x00008000 /* Flexible Filter 3 Enable */
3312 +#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
3313 +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
3314 +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
3315 +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
3316 +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
3317 +#define E1000_WUFC_ALL_FILTERS_BM 0x0000F0FF /* Mask for all wakeup filters */
3318 +#define E1000_WUFC_FLX_OFFSET_BM 12 /* Offset to the Flexible Filters bits */
3319 +#define E1000_WUFC_FLX_FILTERS_BM 0x0000F000 /* Mask for the 4 flexible filters */
3320 +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
3321 +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
3322 +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
3324 +/* Wake Up Status */
3325 +#define E1000_WUS_LNKC E1000_WUFC_LNKC
3326 +#define E1000_WUS_MAG E1000_WUFC_MAG
3327 +#define E1000_WUS_EX E1000_WUFC_EX
3328 +#define E1000_WUS_MC E1000_WUFC_MC
3329 +#define E1000_WUS_BC E1000_WUFC_BC
3330 +#define E1000_WUS_ARP E1000_WUFC_ARP
3331 +#define E1000_WUS_IPV4 E1000_WUFC_IPV4
3332 +#define E1000_WUS_IPV6 E1000_WUFC_IPV6
3333 +#define E1000_WUS_FLX0_BM E1000_WUFC_FLX0_BM
3334 +#define E1000_WUS_FLX1_BM E1000_WUFC_FLX1_BM
3335 +#define E1000_WUS_FLX2_BM E1000_WUFC_FLX2_BM
3336 +#define E1000_WUS_FLX3_BM E1000_WUFC_FLX3_BM
3337 +#define E1000_WUS_FLX_FILTERS_BM E1000_WUFC_FLX_FILTERS_BM
3338 +#define E1000_WUS_FLX0 E1000_WUFC_FLX0
3339 +#define E1000_WUS_FLX1 E1000_WUFC_FLX1
3340 +#define E1000_WUS_FLX2 E1000_WUFC_FLX2
3341 +#define E1000_WUS_FLX3 E1000_WUFC_FLX3
3342 +#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
3344 +/* Wake Up Packet Length */
3345 +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
3347 +/* Four Flexible Filters are supported */
3348 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
3350 +/* Each Flexible Filter is at most 128 (0x80) bytes in length */
3351 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
3353 +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
3354 +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
3355 +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
3357 +/* Extended Device Control */
3358 +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
3359 +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
3360 +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
3361 +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
3362 +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
3363 +/* Reserved (bits 4,5) in >= 82575 */
3364 +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
3365 +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
3366 +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
3367 +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
3368 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
3369 +/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
3370 +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
3371 +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
3372 +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
3373 +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
3374 +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
3375 +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
3376 +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
3377 +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
3378 +#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
3379 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
3380 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
3381 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
3382 +#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
3383 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
3384 +#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
3385 +#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
3386 +#define E1000_CTRL_EXT_EIAME 0x01000000
3387 +#define E1000_CTRL_EXT_IRCA 0x00000001
3388 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
3389 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
3390 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
3391 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
3392 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
3393 +#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
3394 +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
3395 +/* IAME enable bit (27) was removed in >= 82575 */
3396 +#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
3397 +#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
3398 +#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
3399 +#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
3400 +#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
3401 +#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
3402 +#define E1000_CTRL_EXT_LSECCK 0x00001000
3403 +#define E1000_I2CCMD_REG_ADDR_SHIFT 16
3404 +#define E1000_I2CCMD_REG_ADDR 0x00FF0000
3405 +#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
3406 +#define E1000_I2CCMD_PHY_ADDR 0x07000000
3407 +#define E1000_I2CCMD_OPCODE_READ 0x08000000
3408 +#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
3409 +#define E1000_I2CCMD_RESET 0x10000000
3410 +#define E1000_I2CCMD_READY 0x20000000
3411 +#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
3412 +#define E1000_I2CCMD_ERROR 0x80000000
3413 +#define E1000_MAX_SGMII_PHY_REG_ADDR 255
3414 +#define E1000_I2CCMD_PHY_TIMEOUT 200
3416 +/* Receive Descriptor bit definitions */
3417 +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
3418 +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
3419 +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
3420 +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
3421 +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
3422 +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
3423 +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
3424 +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
3425 +#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
3426 +#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
3427 +#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
3428 +#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
3429 +#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
3430 +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
3431 +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
3432 +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
3433 +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
3434 +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
3435 +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
3436 +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
3437 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
3438 +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
3439 +#define E1000_RXD_SPC_PRI_SHIFT 13
3440 +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
3441 +#define E1000_RXD_SPC_CFI_SHIFT 12
3443 +#define E1000_RXDEXT_STATERR_CE 0x01000000
3444 +#define E1000_RXDEXT_STATERR_SE 0x02000000
3445 +#define E1000_RXDEXT_STATERR_SEQ 0x04000000
3446 +#define E1000_RXDEXT_STATERR_CXE 0x10000000
3447 +#define E1000_RXDEXT_STATERR_TCPE 0x20000000
3448 +#define E1000_RXDEXT_STATERR_IPE 0x40000000
3449 +#define E1000_RXDEXT_STATERR_RXE 0x80000000
3451 +#define E1000_RXDEXT_LSECH 0x01000000
3452 +#define E1000_RXDEXT_LSECE_MASK 0x60000000
3453 +#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000
3454 +#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000
3455 +#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
3456 +#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000
3458 +/* mask to determine if packets should be dropped due to frame errors */
3459 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
3460 + E1000_RXD_ERR_CE | \
3461 + E1000_RXD_ERR_SE | \
3462 + E1000_RXD_ERR_SEQ | \
3463 + E1000_RXD_ERR_CXE | \
3464 + E1000_RXD_ERR_RXE)
3466 +/* Same mask, but for extended and packet split descriptors */
3467 +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
3468 + E1000_RXDEXT_STATERR_CE | \
3469 + E1000_RXDEXT_STATERR_SE | \
3470 + E1000_RXDEXT_STATERR_SEQ | \
3471 + E1000_RXDEXT_STATERR_CXE | \
3472 + E1000_RXDEXT_STATERR_RXE)
3474 +#define E1000_MRQC_ENABLE_MASK 0x00000007
3475 +#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
3476 +#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
3477 +#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
3478 +#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
3479 +#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
3480 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
3481 +#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
3482 +#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
3483 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
3485 +#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
3486 +#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
3488 +/* Management Control */
3489 +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
3490 +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
3491 +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
3492 +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
3493 +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
3494 +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
3495 +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
3496 +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
3497 +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
3498 +/* Enable Neighbor Discovery Filtering */
3499 +#define E1000_MANC_NEIGHBOR_EN 0x00004000
3500 +#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
3501 +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
3502 +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
3503 +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
3504 +#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
3505 +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
3506 +/* Enable MAC address filtering */
3507 +#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
3508 +/* Enable MNG packets to host memory */
3509 +#define E1000_MANC_EN_MNG2HOST 0x00200000
3510 +/* Enable IP address filtering */
3511 +#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
3512 +#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
3513 +#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
3514 +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
3515 +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
3516 +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
3517 +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
3518 +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
3519 +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
3521 +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
3522 +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
3524 +/* Receive Control */
3525 +#define E1000_RCTL_RST 0x00000001 /* Software reset */
3526 +#define E1000_RCTL_EN 0x00000002 /* enable */
3527 +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
3528 +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
3529 +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
3530 +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
3531 +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
3532 +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
3533 +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
3534 +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
3535 +#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
3536 +#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
3537 +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
3538 +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
3539 +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
3540 +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
3541 +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
3542 +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
3543 +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
3544 +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
3545 +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
3546 +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
3547 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
3548 +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
3549 +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
3550 +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
3551 +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
3552 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
3553 +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
3554 +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
3555 +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
3556 +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
3557 +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
3558 +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
3559 +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
3560 +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
3561 +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
3562 +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
3563 +#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
3564 +#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
3567 + * Use byte values for the following shift parameters
3569 + * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
3570 + * E1000_PSRCTL_BSIZE0_MASK) |
3571 + * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
3572 + * E1000_PSRCTL_BSIZE1_MASK) |
3573 + * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
3574 + * E1000_PSRCTL_BSIZE2_MASK) |
3575 + * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
3576 + * E1000_PSRCTL_BSIZE3_MASK))
3577 + * where value0 = [128..16256], default=256
3578 + * value1 = [1024..64512], default=4096
3579 + * value2 = [0..64512], default=4096
3580 + * value3 = [0..64512], default=0
3583 +#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
3584 +#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
3585 +#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
3586 +#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
3588 +#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
3589 +#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
3590 +#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
3591 +#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
3593 +/* SWFW_SYNC Definitions */
3594 +#define E1000_SWFW_EEP_SM 0x1
3595 +#define E1000_SWFW_PHY0_SM 0x2
3596 +#define E1000_SWFW_PHY1_SM 0x4
3597 +#define E1000_SWFW_CSR_SM 0x8
3599 +/* FACTPS Definitions */
3600 +#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
3601 +/* Device Control */
3602 +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
3603 +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
3604 +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
3605 +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
3606 +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
3607 +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
3608 +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
3609 +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
3610 +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
3611 +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
3612 +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
3613 +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
3614 +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
3615 +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
3616 +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
3617 +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
3618 +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
3619 +#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
3620 +#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
3621 +#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
3622 +#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
3623 +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
3624 +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
3625 +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
3626 +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
3627 +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
3628 +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
3629 +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
3630 +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
3631 +#define E1000_CTRL_RST 0x04000000 /* Global reset */
3632 +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
3633 +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
3634 +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
3635 +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
3636 +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
3637 +#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
3638 +#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
3640 +/* Bit definitions for the Management Data IO (MDIO) and Management Data
3641 + * Clock (MDC) pins in the Device Control Register.
3643 +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
3644 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
3645 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
3646 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
3647 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
3648 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
3649 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
3650 +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
3652 +#define E1000_CONNSW_ENRGSRC 0x4
3653 +#define E1000_PCS_CFG_PCS_EN 8
3654 +#define E1000_PCS_LCTL_FLV_LINK_UP 1
3655 +#define E1000_PCS_LCTL_FSV_10 0
3656 +#define E1000_PCS_LCTL_FSV_100 2
3657 +#define E1000_PCS_LCTL_FSV_1000 4
3658 +#define E1000_PCS_LCTL_FDV_FULL 8
3659 +#define E1000_PCS_LCTL_FSD 0x10
3660 +#define E1000_PCS_LCTL_FORCE_LINK 0x20
3661 +#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
3662 +#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
3663 +#define E1000_PCS_LCTL_AN_ENABLE 0x10000
3664 +#define E1000_PCS_LCTL_AN_RESTART 0x20000
3665 +#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
3666 +#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
3667 +#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
3668 +#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
3669 +#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
3670 +#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
3671 +#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
3673 +#define E1000_PCS_LSTS_LINK_OK 1
3674 +#define E1000_PCS_LSTS_SPEED_10 0
3675 +#define E1000_PCS_LSTS_SPEED_100 2
3676 +#define E1000_PCS_LSTS_SPEED_1000 4
3677 +#define E1000_PCS_LSTS_DUPLEX_FULL 8
3678 +#define E1000_PCS_LSTS_SYNK_OK 0x10
3679 +#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
3680 +#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
3681 +#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
3682 +#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
3683 +#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
3685 +/* Device Status */
3686 +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
3687 +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
3688 +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
3689 +#define E1000_STATUS_FUNC_SHIFT 2
3690 +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
3691 +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
3692 +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
3693 +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
3694 +#define E1000_STATUS_SPEED_MASK 0x000000C0
3695 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
3696 +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
3697 +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
3698 +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
3699 +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
3700 +#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
3701 +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
3702 +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
3703 +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
3704 +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
3705 +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
3706 +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
3707 +#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
3708 +#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
3709 +#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
3710 +#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
3711 +#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
3712 +#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
3713 +#define E1000_STATUS_FUSE_8 0x04000000
3714 +#define E1000_STATUS_FUSE_9 0x08000000
3715 +#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
3716 +#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
3718 +/* Constants used to interpret the masked PCI-X bus speed. */
3719 +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
3720 +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
3721 +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
3723 +#define SPEED_10 10
3724 +#define SPEED_100 100
3725 +#define SPEED_1000 1000
3726 +#define HALF_DUPLEX 1
3727 +#define FULL_DUPLEX 2
3729 +#define PHY_FORCE_TIME 20
3731 +#define ADVERTISE_10_HALF 0x0001
3732 +#define ADVERTISE_10_FULL 0x0002
3733 +#define ADVERTISE_100_HALF 0x0004
3734 +#define ADVERTISE_100_FULL 0x0008
3735 +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
3736 +#define ADVERTISE_1000_FULL 0x0020
3738 +/* 1000/H is not supported, nor spec-compliant. */
3739 +#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
3740 + ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
3741 + ADVERTISE_1000_FULL)
3742 +#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
3743 + ADVERTISE_100_HALF | ADVERTISE_100_FULL)
3744 +#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
3745 +#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
3746 +#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
3747 + ADVERTISE_1000_FULL)
3748 +#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
3750 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
3753 +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
3754 +#define E1000_LEDCTL_LED0_MODE_SHIFT 0
3755 +#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
3756 +#define E1000_LEDCTL_LED0_IVRT 0x00000040
3757 +#define E1000_LEDCTL_LED0_BLINK 0x00000080
3758 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
3759 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8
3760 +#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
3761 +#define E1000_LEDCTL_LED1_IVRT 0x00004000
3762 +#define E1000_LEDCTL_LED1_BLINK 0x00008000
3763 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
3764 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16
3765 +#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
3766 +#define E1000_LEDCTL_LED2_IVRT 0x00400000
3767 +#define E1000_LEDCTL_LED2_BLINK 0x00800000
3768 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
3769 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24
3770 +#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
3771 +#define E1000_LEDCTL_LED3_IVRT 0x40000000
3772 +#define E1000_LEDCTL_LED3_BLINK 0x80000000
3774 +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
3775 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
3776 +#define E1000_LEDCTL_MODE_LINK_UP 0x2
3777 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3
3778 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
3779 +#define E1000_LEDCTL_MODE_LINK_10 0x5
3780 +#define E1000_LEDCTL_MODE_LINK_100 0x6
3781 +#define E1000_LEDCTL_MODE_LINK_1000 0x7
3782 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
3783 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
3784 +#define E1000_LEDCTL_MODE_COLLISION 0xA
3785 +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
3786 +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
3787 +#define E1000_LEDCTL_MODE_PAUSED 0xD
3788 +#define E1000_LEDCTL_MODE_LED_ON 0xE
3789 +#define E1000_LEDCTL_MODE_LED_OFF 0xF
3791 +/* Transmit Descriptor bit definitions */
3792 +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
3793 +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
3794 +#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
3795 +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
3796 +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
3797 +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
3798 +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
3799 +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
3800 +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
3801 +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
3802 +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
3803 +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
3804 +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
3805 +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
3806 +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
3807 +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
3808 +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
3809 +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
3810 +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
3811 +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
3812 +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
3813 +/* Extended desc bits for Linksec and timesync */
3814 +#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */
3815 +#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
3817 +/* Transmit Control */
3818 +#define E1000_TCTL_RST 0x00000001 /* software reset */
3819 +#define E1000_TCTL_EN 0x00000002 /* enable tx */
3820 +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
3821 +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
3822 +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
3823 +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
3824 +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
3825 +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
3826 +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
3827 +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
3828 +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
3830 +/* Transmit Arbitration Count */
3831 +#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
3833 +/* SerDes Control */
3834 +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
3836 +/* Receive Checksum Control */
3837 +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
3838 +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
3839 +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
3840 +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
3841 +#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
3842 +#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
3843 +#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
3845 +/* Header split receive */
3846 +#define E1000_RFCTL_ISCSI_DIS 0x00000001
3847 +#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
3848 +#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
3849 +#define E1000_RFCTL_NFSW_DIS 0x00000040
3850 +#define E1000_RFCTL_NFSR_DIS 0x00000080
3851 +#define E1000_RFCTL_NFS_VER_MASK 0x00000300
3852 +#define E1000_RFCTL_NFS_VER_SHIFT 8
3853 +#define E1000_RFCTL_IPV6_DIS 0x00000400
3854 +#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
3855 +#define E1000_RFCTL_ACK_DIS 0x00001000
3856 +#define E1000_RFCTL_ACKD_DIS 0x00002000
3857 +#define E1000_RFCTL_IPFRSP_DIS 0x00004000
3858 +#define E1000_RFCTL_EXTEN 0x00008000
3859 +#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
3860 +#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
3861 +#define E1000_RFCTL_LEF 0x00040000
3863 +/* Collision related configuration parameters */
3864 +#define E1000_COLLISION_THRESHOLD 15
3865 +#define E1000_CT_SHIFT 4
3866 +#define E1000_COLLISION_DISTANCE 63
3867 +#define E1000_COLD_SHIFT 12
3869 +/* Default values for the transmit IPG register */
3870 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9
3871 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
3873 +#define E1000_TIPG_IPGT_MASK 0x000003FF
3874 +#define E1000_TIPG_IPGR1_MASK 0x000FFC00
3875 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000
3877 +#define DEFAULT_82543_TIPG_IPGR1 8
3878 +#define E1000_TIPG_IPGR1_SHIFT 10
3880 +#define DEFAULT_82543_TIPG_IPGR2 6
3881 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
3882 +#define E1000_TIPG_IPGR2_SHIFT 20
3884 +/* Ethertype field values */
3885 +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
3887 +#define ETHERNET_FCS_SIZE 4
3888 +#define MAX_JUMBO_FRAME_SIZE 0x3F00
3890 +/* Extended Configuration Control and Size */
3891 +#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
3892 +#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
3893 +#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
3894 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
3895 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
3896 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
3897 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
3899 +#define E1000_PHY_CTRL_SPD_EN 0x00000001
3900 +#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
3901 +#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
3902 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
3903 +#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
3905 +#define E1000_KABGTXD_BGSQLBIAS 0x00050000
3907 +/* PBA constants */
3908 +#define E1000_PBA_6K 0x0006 /* 6KB */
3909 +#define E1000_PBA_8K 0x0008 /* 8KB */
3910 +#define E1000_PBA_12K 0x000C /* 12KB */
3911 +#define E1000_PBA_16K 0x0010 /* 16KB */
3912 +#define E1000_PBA_20K 0x0014
3913 +#define E1000_PBA_22K 0x0016
3914 +#define E1000_PBA_24K 0x0018
3915 +#define E1000_PBA_30K 0x001E
3916 +#define E1000_PBA_32K 0x0020
3917 +#define E1000_PBA_34K 0x0022
3918 +#define E1000_PBA_38K 0x0026
3919 +#define E1000_PBA_40K 0x0028
3920 +#define E1000_PBA_48K 0x0030 /* 48KB */
3921 +#define E1000_PBA_64K 0x0040 /* 64KB */
3923 +#define E1000_PBS_16K E1000_PBA_16K
3924 +#define E1000_PBS_24K E1000_PBA_24K
3928 +#define IFS_RATIO 4
3929 +#define IFS_STEP 10
3930 +#define MIN_NUM_XMITS 1000
3932 +/* SW Semaphore Register */
3933 +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
3934 +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
3935 +#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
3936 +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
3938 +/* Interrupt Cause Read */
3939 +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
3940 +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
3941 +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
3942 +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
3943 +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
3944 +#define E1000_ICR_RXO 0x00000040 /* rx overrun */
3945 +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
3946 +#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
3947 +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
3948 +#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
3949 +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
3950 +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
3951 +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
3952 +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
3953 +#define E1000_ICR_TXD_LOW 0x00008000
3954 +#define E1000_ICR_SRPD 0x00010000
3955 +#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
3956 +#define E1000_ICR_MNG 0x00040000 /* Manageability event */
3957 +#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
3958 +#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
3959 +#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
3960 +#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
3961 +#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
3962 +#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
3963 +#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
3964 +#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
3965 +#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
3966 +#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
3967 +#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
3968 +#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
3969 +#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
3970 +#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
3971 +#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
3972 +#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
3973 +#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
3975 +/* Extended Interrupt Cause Read */
3976 +#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
3977 +#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
3978 +#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
3979 +#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
3980 +#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
3981 +#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
3982 +#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
3983 +#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
3984 +#define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
3985 +#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
3987 +#define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
3988 +#define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
3989 +#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
3990 +#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
3993 + * This defines the bits that are set in the Interrupt Mask
3994 + * Set/Read Register. Each bit is documented below:
3995 + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
3996 + * o RXSEQ = Receive Sequence Error
3998 +#define POLL_IMS_ENABLE_MASK ( \
3999 + E1000_IMS_RXDMT0 | \
4003 + * This defines the bits that are set in the Interrupt Mask
4004 + * Set/Read Register. Each bit is documented below:
4005 + * o RXT0 = Receiver Timer Interrupt (ring 0)
4006 + * o TXDW = Transmit Descriptor Written Back
4007 + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
4008 + * o RXSEQ = Receive Sequence Error
4009 + * o LSC = Link Status Change
4011 +#define IMS_ENABLE_MASK ( \
4012 + E1000_IMS_RXT0 | \
4013 + E1000_IMS_TXDW | \
4014 + E1000_IMS_RXDMT0 | \
4015 + E1000_IMS_RXSEQ | \
4018 +/* Interrupt Mask Set */
4019 +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
4020 +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
4021 +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
4022 +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
4023 +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
4024 +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
4025 +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
4026 +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
4027 +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
4028 +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
4029 +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
4030 +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
4031 +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
4032 +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
4033 +#define E1000_IMS_SRPD E1000_ICR_SRPD
4034 +#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
4035 +#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
4036 +#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
4037 +#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
4038 +#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
4039 +#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
4040 +#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
4041 +#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
4042 +#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
4043 +#define E1000_IMS_DSW E1000_ICR_DSW
4044 +#define E1000_IMS_PHYINT E1000_ICR_PHYINT
4045 +#define E1000_IMS_EPRST E1000_ICR_EPRST
4046 +#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
4047 +#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
4048 +#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
4049 +#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
4050 +#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
4052 +/* Extended Interrupt Mask Set */
4053 +#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
4054 +#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
4055 +#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
4056 +#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
4057 +#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
4058 +#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
4059 +#define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
4060 +#define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
4061 +#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
4062 +#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
4064 +/* Interrupt Cause Set */
4065 +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
4066 +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
4067 +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
4068 +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
4069 +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
4070 +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
4071 +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
4072 +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
4073 +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
4074 +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
4075 +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
4076 +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
4077 +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
4078 +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
4079 +#define E1000_ICS_SRPD E1000_ICR_SRPD
4080 +#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
4081 +#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
4082 +#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
4083 +#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
4084 +#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
4085 +#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
4086 +#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
4087 +#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
4088 +#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
4089 +#define E1000_ICS_DSW E1000_ICR_DSW
4090 +#define E1000_ICS_PHYINT E1000_ICR_PHYINT
4091 +#define E1000_ICS_EPRST E1000_ICR_EPRST
4093 +/* Extended Interrupt Cause Set */
4094 +#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
4095 +#define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
4096 +#define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
4097 +#define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
4098 +#define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
4099 +#define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
4100 +#define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
4101 +#define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
4102 +#define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
4103 +#define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
4105 +/* Transmit Descriptor Control */
4106 +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
4107 +#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
4108 +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
4109 +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
4110 +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
4111 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
4112 +#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
4113 +/* Enable the counting of descriptors still to be processed. */
4114 +#define E1000_TXDCTL_COUNT_DESC 0x00400000
4116 +/* Flow Control Constants */
4117 +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
4118 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
4119 +#define FLOW_CONTROL_TYPE 0x8808
4121 +/* 802.1q VLAN Packet Size */
4122 +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
4123 +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
4125 +/* Receive Address */
4127 + * Number of high/low register pairs in the RAR. The RAR (Receive Address
4128 + * Registers) holds the directed and multicast addresses that we monitor.
4129 + * Technically, we have 16 spots. However, we reserve one of these spots
4130 + * (RAR[15]) for our directed address used by controllers with
4131 + * manageability enabled, allowing us room for 15 multicast addresses.
4133 +#define E1000_RAR_ENTRIES 15
4134 +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
4137 +#define E1000_SUCCESS 0
4138 +#define E1000_ERR_NVM 1
4139 +#define E1000_ERR_PHY 2
4140 +#define E1000_ERR_CONFIG 3
4141 +#define E1000_ERR_PARAM 4
4142 +#define E1000_ERR_MAC_INIT 5
4143 +#define E1000_ERR_PHY_TYPE 6
4144 +#define E1000_ERR_RESET 9
4145 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10
4146 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11
4147 +#define E1000_BLK_PHY_RESET 12
4148 +#define E1000_ERR_SWFW_SYNC 13
4149 +#define E1000_NOT_IMPLEMENTED 14
4151 +/* Loop limit on how long we wait for auto-negotiation to complete */
4152 +#define FIBER_LINK_UP_LIMIT 50
4153 +#define COPPER_LINK_UP_LIMIT 10
4154 +#define PHY_AUTO_NEG_LIMIT 45
4155 +#define PHY_FORCE_LIMIT 20
4156 +/* Number of 100 microseconds we wait for PCI Express master disable */
4157 +#define MASTER_DISABLE_TIMEOUT 800
4158 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */
4159 +#define PHY_CFG_TIMEOUT 100
4160 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
4161 +#define MDIO_OWNERSHIP_TIMEOUT 10
4162 +/* Number of milliseconds for NVM auto read done after MAC reset. */
4163 +#define AUTO_READ_DONE_TIMEOUT 10
4166 +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
4167 +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
4168 +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
4169 +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
4171 +/* Transmit Configuration Word */
4172 +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
4173 +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
4174 +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
4175 +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
4176 +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
4177 +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
4178 +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
4179 +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
4180 +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
4181 +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
4183 +/* Receive Configuration Word */
4184 +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
4185 +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
4186 +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
4187 +#define E1000_RXCW_CC 0x10000000 /* Receive config change */
4188 +#define E1000_RXCW_C 0x20000000 /* Receive config */
4189 +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
4190 +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
4192 +/* PCI Express Control */
4193 +#define E1000_GCR_RXD_NO_SNOOP 0x00000001
4194 +#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
4195 +#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
4196 +#define E1000_GCR_TXD_NO_SNOOP 0x00000008
4197 +#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
4198 +#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
4200 +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
4201 + E1000_GCR_RXDSCW_NO_SNOOP | \
4202 + E1000_GCR_RXDSCR_NO_SNOOP | \
4203 + E1000_GCR_TXD_NO_SNOOP | \
4204 + E1000_GCR_TXDSCW_NO_SNOOP | \
4205 + E1000_GCR_TXDSCR_NO_SNOOP)
4207 +/* PHY Control Register */
4208 +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
4209 +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
4210 +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
4211 +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
4212 +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
4213 +#define MII_CR_POWER_DOWN 0x0800 /* Power down */
4214 +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
4215 +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
4216 +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
4217 +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
4218 +#define MII_CR_SPEED_1000 0x0040
4219 +#define MII_CR_SPEED_100 0x2000
4220 +#define MII_CR_SPEED_10 0x0000
4222 +/* PHY Status Register */
4223 +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
4224 +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
4225 +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
4226 +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
4227 +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
4228 +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
4229 +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
4230 +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
4231 +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
4232 +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
4233 +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
4234 +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
4235 +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
4236 +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
4237 +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
4239 +/* Autoneg Advertisement Register */
4240 +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
4241 +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
4242 +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
4243 +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
4244 +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
4245 +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
4246 +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
4247 +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
4248 +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
4249 +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
4251 +/* Link Partner Ability Register (Base Page) */
4252 +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
4253 +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
4254 +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
4255 +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
4256 +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
4257 +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
4258 +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
4259 +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
4260 +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
4261 +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
4262 +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
4264 +/* Autoneg Expansion Register */
4265 +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
4266 +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
4267 +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
4268 +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
4269 +#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
4271 +/* 1000BASE-T Control Register */
4272 +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
4273 +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
4274 +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
4275 +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
4276 + /* 0=DTE device */
4277 +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
4278 + /* 0=Configure PHY as Slave */
4279 +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
4280 + /* 0=Automatic Master/Slave config */
4281 +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
4282 +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
4283 +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
4284 +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
4285 +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
4287 +/* 1000BASE-T Status Register */
4288 +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
4289 +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
4290 +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
4291 +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
4292 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
4293 +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
4294 +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
4295 +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
4297 +#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
4299 +/* PHY 1000 MII Register/Bit Definitions */
4300 +/* PHY Registers defined by IEEE */
4301 +#define PHY_CONTROL 0x00 /* Control Register */
4302 +#define PHY_STATUS 0x01 /* Status Register */
4303 +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
4304 +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
4305 +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
4306 +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
4307 +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
4308 +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
4309 +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
4310 +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
4311 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
4312 +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
4315 +#define E1000_EECD_SK 0x00000001 /* NVM Clock */
4316 +#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
4317 +#define E1000_EECD_DI 0x00000004 /* NVM Data In */
4318 +#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
4319 +#define E1000_EECD_FWE_MASK 0x00000030
4320 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
4321 +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
4322 +#define E1000_EECD_FWE_SHIFT 4
4323 +#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
4324 +#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
4325 +#define E1000_EECD_PRES 0x00000100 /* NVM Present */
4326 +#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
4327 +/* NVM Addressing bits based on type 0=small, 1=large */
4328 +#define E1000_EECD_ADDR_BITS 0x00000400
4329 +#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
4330 +#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
4331 +#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
4332 +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
4333 +#define E1000_EECD_SIZE_EX_SHIFT 11
4334 +#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
4335 +#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
4336 +#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
4337 +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
4338 +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
4339 +#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
4340 +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
4341 +#define E1000_EECD_SECVAL_SHIFT 22
4343 +#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
4344 +#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
4345 +#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
4346 +#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
4347 +#define E1000_NVM_RW_REG_START 1 /* Start operation */
4348 +#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
4349 +#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
4350 +#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
4351 +#define E1000_FLASH_UPDATES 2000
4353 +/* NVM Word Offsets */
4354 +#define NVM_COMPAT 0x0003
4355 +#define NVM_ID_LED_SETTINGS 0x0004
4356 +#define NVM_VERSION 0x0005
4357 +#define NVM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
4358 +#define NVM_PHY_CLASS_WORD 0x0007
4359 +#define NVM_INIT_CONTROL1_REG 0x000A
4360 +#define NVM_INIT_CONTROL2_REG 0x000F
4361 +#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
4362 +#define NVM_INIT_CONTROL3_PORT_B 0x0014
4363 +#define NVM_INIT_3GIO_3 0x001A
4364 +#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
4365 +#define NVM_INIT_CONTROL3_PORT_A 0x0024
4366 +#define NVM_CFG 0x0012
4367 +#define NVM_FLASH_VERSION 0x0032
4368 +#define NVM_ALT_MAC_ADDR_PTR 0x0037
4369 +#define NVM_CHECKSUM_REG 0x003F
4371 +#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
4372 +#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
4374 +/* Mask bits for fields in Word 0x0f of the NVM */
4375 +#define NVM_WORD0F_PAUSE_MASK 0x3000
4376 +#define NVM_WORD0F_PAUSE 0x1000
4377 +#define NVM_WORD0F_ASM_DIR 0x2000
4378 +#define NVM_WORD0F_ANE 0x0800
4379 +#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
4380 +#define NVM_WORD0F_LPLU 0x0001
4382 +/* Mask bits for fields in Word 0x1a of the NVM */
4383 +#define NVM_WORD1A_ASPM_MASK 0x000C
4385 +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
4386 +#define NVM_SUM 0xBABA
4388 +#define NVM_MAC_ADDR_OFFSET 0
4389 +#define NVM_PBA_OFFSET_0 8
4390 +#define NVM_PBA_OFFSET_1 9
4391 +#define NVM_RESERVED_WORD 0xFFFF
4392 +#define NVM_PHY_CLASS_A 0x8000
4393 +#define NVM_SERDES_AMPLITUDE_MASK 0x000F
4394 +#define NVM_SIZE_MASK 0x1C00
4395 +#define NVM_SIZE_SHIFT 10
4396 +#define NVM_WORD_SIZE_BASE_SHIFT 6
4397 +#define NVM_SWDPIO_EXT_SHIFT 4
4399 +/* NVM Commands - Microwire */
4400 +#define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
4401 +#define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
4402 +#define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
4403 +#define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
4404 +#define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
4406 +/* NVM Commands - SPI */
4407 +#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
4408 +#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
4409 +#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
4410 +#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
4411 +#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
4412 +#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
4413 +#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
4414 +#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
4416 +/* SPI NVM Status Register */
4417 +#define NVM_STATUS_RDY_SPI 0x01
4418 +#define NVM_STATUS_WEN_SPI 0x02
4419 +#define NVM_STATUS_BP0_SPI 0x04
4420 +#define NVM_STATUS_BP1_SPI 0x08
4421 +#define NVM_STATUS_WPEN_SPI 0x80
4423 +/* Word definitions for ID LED Settings */
4424 +#define ID_LED_RESERVED_0000 0x0000
4425 +#define ID_LED_RESERVED_FFFF 0xFFFF
4426 +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
4427 + (ID_LED_OFF1_OFF2 << 8) | \
4428 + (ID_LED_DEF1_DEF2 << 4) | \
4429 + (ID_LED_DEF1_DEF2))
4430 +#define ID_LED_DEF1_DEF2 0x1
4431 +#define ID_LED_DEF1_ON2 0x2
4432 +#define ID_LED_DEF1_OFF2 0x3
4433 +#define ID_LED_ON1_DEF2 0x4
4434 +#define ID_LED_ON1_ON2 0x5
4435 +#define ID_LED_ON1_OFF2 0x6
4436 +#define ID_LED_OFF1_DEF2 0x7
4437 +#define ID_LED_OFF1_ON2 0x8
4438 +#define ID_LED_OFF1_OFF2 0x9
4440 +#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
4441 +#define IGP_ACTIVITY_LED_ENABLE 0x0300
4442 +#define IGP_LED3_MODE 0x07000000
4444 +/* PCI/PCI-X/PCI-EX Config space */
4445 +#define PCIX_COMMAND_REGISTER 0xE6
4446 +#define PCIX_STATUS_REGISTER_LO 0xE8
4447 +#define PCIX_STATUS_REGISTER_HI 0xEA
4448 +#define PCI_HEADER_TYPE_REGISTER 0x0E
4449 +#define PCIE_LINK_STATUS 0x12
4451 +#define PCIX_COMMAND_MMRBC_MASK 0x000C
4452 +#define PCIX_COMMAND_MMRBC_SHIFT 0x2
4453 +#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
4454 +#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
4455 +#define PCIX_STATUS_HI_MMRBC_4K 0x3
4456 +#define PCIX_STATUS_HI_MMRBC_2K 0x2
4457 +#define PCIX_STATUS_LO_FUNC_MASK 0x7
4458 +#define PCI_HEADER_TYPE_MULTIFUNC 0x80
4459 +#define PCIE_LINK_WIDTH_MASK 0x3F0
4460 +#define PCIE_LINK_WIDTH_SHIFT 4
4462 +#ifndef ETH_ADDR_LEN
4463 +#define ETH_ADDR_LEN 6
4466 +#define PHY_REVISION_MASK 0xFFFFFFF0
4467 +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
4468 +#define MAX_PHY_MULTI_PAGE_REG 0xF
4470 +/* Bit definitions for valid PHY IDs. */
4475 +#define M88E1000_E_PHY_ID 0x01410C50
4476 +#define M88E1000_I_PHY_ID 0x01410C30
4477 +#define M88E1011_I_PHY_ID 0x01410C20
4478 +#define IGP01E1000_I_PHY_ID 0x02A80380
4479 +#define M88E1011_I_REV_4 0x04
4480 +#define M88E1111_I_PHY_ID 0x01410CC0
4481 +#define GG82563_E_PHY_ID 0x01410CA0
4482 +#define IGP03E1000_E_PHY_ID 0x02A80390
4483 +#define IFE_E_PHY_ID 0x02A80330
4484 +#define IFE_PLUS_E_PHY_ID 0x02A80320
4485 +#define IFE_C_E_PHY_ID 0x02A80310
4486 +#define BME1000_E_PHY_ID 0x01410CB0
4487 +#define BME1000_E_PHY_ID_R2 0x01410CB1
4488 +#define M88_VENDOR 0x0141
4490 +/* M88E1000 Specific Registers */
4491 +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
4492 +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
4493 +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
4494 +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
4495 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
4496 +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
4498 +#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
4499 +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
4500 +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
4501 +#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
4502 +#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
4504 +/* M88E1000 PHY Specific Control Register */
4505 +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
4506 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
4507 +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
4508 +/* 1=CLK125 low, 0=CLK125 toggling */
4509 +#define M88E1000_PSCR_CLK125_DISABLE 0x0010
4510 +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
4511 + /* Manual MDI configuration */
4512 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
4513 +/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
4514 +#define M88E1000_PSCR_AUTO_X_1000T 0x0040
4515 +/* Auto crossover enabled all speeds */
4516 +#define M88E1000_PSCR_AUTO_X_MODE 0x0060
4518 + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
4519 + * 0=Normal 10BASE-T Rx Threshold
4521 +#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
4522 +/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
4523 +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
4524 +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
4525 +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
4526 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
4528 +/* M88E1000 PHY Specific Status Register */
4529 +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
4530 +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
4531 +#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
4532 +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
4540 +#define M88E1000_PSSR_CABLE_LENGTH 0x0380
4541 +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
4542 +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
4543 +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
4544 +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
4545 +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
4546 +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
4547 +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
4548 +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
4550 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
4552 +/* M88E1000 Extended PHY Specific Control Register */
4553 +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
4555 + * 1 = Lost lock detect enabled.
4556 + * Will assert lost lock and bring
4557 + * link down if idle not seen
4558 + * within 1ms in 1000BASE-T
4560 +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
4562 + * Number of times we will attempt to autonegotiate before downshifting if we
4565 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
4566 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
4567 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
4568 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
4569 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
4571 + * Number of times we will attempt to autonegotiate before downshifting if we
4574 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
4575 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
4576 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
4577 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
4578 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
4579 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
4580 +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
4581 +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
4583 +/* M88EC018 Rev 2 specific DownShift settings */
4584 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
4585 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
4586 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
4587 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
4588 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
4589 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
4590 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
4591 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
4592 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
4594 +/* BME1000 PHY Specific Control Register */
4595 +#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
4600 + * 4-0: register offset
4602 +#define GG82563_PAGE_SHIFT 5
4603 +#define GG82563_REG(page, reg) \
4604 + (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
4605 +#define GG82563_MIN_ALT_REG 30
4607 +/* GG82563 Specific Registers */
4608 +#define GG82563_PHY_SPEC_CTRL \
4609 + GG82563_REG(0, 16) /* PHY Specific Control */
4610 +#define GG82563_PHY_SPEC_STATUS \
4611 + GG82563_REG(0, 17) /* PHY Specific Status */
4612 +#define GG82563_PHY_INT_ENABLE \
4613 + GG82563_REG(0, 18) /* Interrupt Enable */
4614 +#define GG82563_PHY_SPEC_STATUS_2 \
4615 + GG82563_REG(0, 19) /* PHY Specific Status 2 */
4616 +#define GG82563_PHY_RX_ERR_CNTR \
4617 + GG82563_REG(0, 21) /* Receive Error Counter */
4618 +#define GG82563_PHY_PAGE_SELECT \
4619 + GG82563_REG(0, 22) /* Page Select */
4620 +#define GG82563_PHY_SPEC_CTRL_2 \
4621 + GG82563_REG(0, 26) /* PHY Specific Control 2 */
4622 +#define GG82563_PHY_PAGE_SELECT_ALT \
4623 + GG82563_REG(0, 29) /* Alternate Page Select */
4624 +#define GG82563_PHY_TEST_CLK_CTRL \
4625 + GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
4627 +#define GG82563_PHY_MAC_SPEC_CTRL \
4628 + GG82563_REG(2, 21) /* MAC Specific Control Register */
4629 +#define GG82563_PHY_MAC_SPEC_CTRL_2 \
4630 + GG82563_REG(2, 26) /* MAC Specific Control 2 */
4632 +#define GG82563_PHY_DSP_DISTANCE \
4633 + GG82563_REG(5, 26) /* DSP Distance */
4635 +/* Page 193 - Port Control Registers */
4636 +#define GG82563_PHY_KMRN_MODE_CTRL \
4637 + GG82563_REG(193, 16) /* Kumeran Mode Control */
4638 +#define GG82563_PHY_PORT_RESET \
4639 + GG82563_REG(193, 17) /* Port Reset */
4640 +#define GG82563_PHY_REVISION_ID \
4641 + GG82563_REG(193, 18) /* Revision ID */
4642 +#define GG82563_PHY_DEVICE_ID \
4643 + GG82563_REG(193, 19) /* Device ID */
4644 +#define GG82563_PHY_PWR_MGMT_CTRL \
4645 + GG82563_REG(193, 20) /* Power Management Control */
4646 +#define GG82563_PHY_RATE_ADAPT_CTRL \
4647 + GG82563_REG(193, 25) /* Rate Adaptation Control */
4649 +/* Page 194 - KMRN Registers */
4650 +#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
4651 + GG82563_REG(194, 16) /* FIFO's Control/Status */
4652 +#define GG82563_PHY_KMRN_CTRL \
4653 + GG82563_REG(194, 17) /* Control */
4654 +#define GG82563_PHY_INBAND_CTRL \
4655 + GG82563_REG(194, 18) /* Inband Control */
4656 +#define GG82563_PHY_KMRN_DIAGNOSTIC \
4657 + GG82563_REG(194, 19) /* Diagnostic */
4658 +#define GG82563_PHY_ACK_TIMEOUTS \
4659 + GG82563_REG(194, 20) /* Acknowledge Timeouts */
4660 +#define GG82563_PHY_ADV_ABILITY \
4661 + GG82563_REG(194, 21) /* Advertised Ability */
4662 +#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
4663 + GG82563_REG(194, 23) /* Link Partner Advertised Ability */
4664 +#define GG82563_PHY_ADV_NEXT_PAGE \
4665 + GG82563_REG(194, 24) /* Advertised Next Page */
4666 +#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
4667 + GG82563_REG(194, 25) /* Link Partner Advertised Next page */
4668 +#define GG82563_PHY_KMRN_MISC \
4669 + GG82563_REG(194, 26) /* Misc. */
4672 +#define E1000_MDIC_DATA_MASK 0x0000FFFF
4673 +#define E1000_MDIC_REG_MASK 0x001F0000
4674 +#define E1000_MDIC_REG_SHIFT 16
4675 +#define E1000_MDIC_PHY_MASK 0x03E00000
4676 +#define E1000_MDIC_PHY_SHIFT 21
4677 +#define E1000_MDIC_OP_WRITE 0x04000000
4678 +#define E1000_MDIC_OP_READ 0x08000000
4679 +#define E1000_MDIC_READY 0x10000000
4680 +#define E1000_MDIC_INT_EN 0x20000000
4681 +#define E1000_MDIC_ERROR 0x40000000
4683 +/* SerDes Control */
4684 +#define E1000_GEN_CTL_READY 0x80000000
4685 +#define E1000_GEN_CTL_ADDRESS_SHIFT 8
4686 +#define E1000_GEN_POLL_TIMEOUT 640
4689 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000.h linux-2.6.22-10/drivers/net/e1000e/e1000.h
4690 --- linux-2.6.22-0/drivers/net/e1000e/e1000.h 1970-01-01 01:00:00.000000000 +0100
4691 +++ linux-2.6.22-10/drivers/net/e1000e/e1000.h 2008-10-14 01:51:32.000000000 +0200
4693 +/*******************************************************************************
4695 + Intel PRO/1000 Linux driver
4696 + Copyright(c) 1999 - 2008 Intel Corporation.
4698 + This program is free software; you can redistribute it and/or modify it
4699 + under the terms and conditions of the GNU General Public License,
4700 + version 2, as published by the Free Software Foundation.
4702 + This program is distributed in the hope it will be useful, but WITHOUT
4703 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4704 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4707 + You should have received a copy of the GNU General Public License along with
4708 + this program; if not, write to the Free Software Foundation, Inc.,
4709 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4711 + The full GNU General Public License is included in this distribution in
4712 + the file called "COPYING".
4714 + Contact Information:
4715 + Linux NICS <linux.nics@intel.com>
4716 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
4717 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
4719 +*******************************************************************************/
4721 +/* Linux PRO/1000 Ethernet Driver main header file */
4726 +#include <linux/types.h>
4727 +#include <linux/timer.h>
4728 +#include <asm/io.h>
4729 +#include <linux/netdevice.h>
4731 +#include "kcompat.h"
4733 +#include "e1000_hw.h"
4737 +#define e_printk(level, adapter, format, arg...) \
4738 + printk(level "%s: %s: " format, pci_name(adapter->pdev), \
4739 + (strchr(adapter->netdev->name, '%') ? "" : \
4740 + adapter->netdev->name), ## arg)
4742 +#define e_dbg(format, arg...) do { (void)(adapter); } while (0)
4744 +#define e_err(format, arg...) \
4745 + e_printk(KERN_ERR, adapter, format, ## arg)
4746 +#define e_info(format, arg...) \
4747 + e_printk(KERN_INFO, adapter, format, ## arg)
4748 +#define e_warn(format, arg...) \
4749 + e_printk(KERN_WARNING, adapter, format, ## arg)
4750 +#define e_notice(format, arg...) \
4751 + e_printk(KERN_NOTICE, adapter, format, ## arg)
4754 +#ifdef CONFIG_E1000E_MSIX
4755 +/* Interrupt modes, as used by the IntMode paramter */
4756 +#define E1000E_INT_MODE_LEGACY 0
4757 +#define E1000E_INT_MODE_MSI 1
4758 +#define E1000E_INT_MODE_MSIX 2
4760 +#endif /* CONFIG_E1000E_MSIX */
4762 +#define E1000_MAX_INTR 10
4764 +/* Tx/Rx descriptor defines */
4765 +#define E1000_DEFAULT_TXD 256
4766 +#define E1000_MAX_TXD 4096
4767 +#define E1000_MIN_TXD 80
4769 +#define E1000_DEFAULT_RXD 256
4770 +#define E1000_MAX_RXD 4096
4771 +#define E1000_MIN_RXD 80
4773 +#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
4774 +#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
4776 +/* Early Receive defines */
4777 +#define E1000_ERT_2048 0x100
4779 +#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
4781 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
4782 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
4783 +#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
4785 +#define AUTO_ALL_MODES 0
4786 +#define E1000_EEPROM_APME 0x0400
4788 +#define E1000_MNG_VLAN_NONE (-1)
4790 +/* Number of packet split data buffers (not including the header buffer) */
4791 +#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
4793 +enum e1000_boards {
4798 + board_80003es2lan,
4804 +struct e1000_queue_stats {
4809 +struct e1000_ps_page {
4810 + struct page *page;
4811 + u64 dma; /* must be u64 - written to hw */
4815 + * wrappers around a pointer to a socket buffer,
4816 + * so a DMA handle can be stored along with the buffer
4818 +struct e1000_buffer {
4820 + struct sk_buff *skb;
4824 + unsigned long time_stamp;
4826 + u16 next_to_watch;
4829 + /* arrays of page information for packet split */
4830 + struct e1000_ps_page *ps_pages;
4832 + struct page *page;
4835 +struct e1000_ring {
4836 + void *desc; /* pointer to ring memory */
4837 + dma_addr_t dma; /* phys address of ring */
4838 + unsigned int size; /* length of ring in bytes */
4839 + unsigned int count; /* number of desc. in ring */
4842 + u16 next_to_clean;
4847 + /* array of buffer information structs */
4848 + struct e1000_buffer *buffer_info;
4850 +#ifdef CONFIG_E1000E_MSIX
4851 + char name[IFNAMSIZ + 5];
4857 +#endif /* CONFIG_E1000E_MSIX */
4858 + struct sk_buff *rx_skb_top;
4860 + struct e1000_queue_stats stats;
4864 +/* PHY register snapshot values */
4865 +struct e1000_phy_regs {
4866 + u16 bmcr; /* basic mode control register */
4867 + u16 bmsr; /* basic mode status register */
4868 + u16 advertise; /* auto-negotiation advertisement */
4869 + u16 lpa; /* link partner ability register */
4870 + u16 expansion; /* auto-negotiation expansion reg */
4871 + u16 ctrl1000; /* 1000BASE-T control register */
4872 + u16 stat1000; /* 1000BASE-T status register */
4873 + u16 estatus; /* extended status register */
4877 +/* board specific private data structure */
4878 +struct e1000_adapter {
4879 + struct timer_list watchdog_timer;
4880 + struct timer_list phy_info_timer;
4881 + struct timer_list blink_timer;
4883 + struct work_struct reset_task;
4884 + struct work_struct watchdog_task;
4886 + const struct e1000_info *ei;
4888 + struct vlan_group *vlgrp;
4890 + u32 rx_buffer_len;
4895 + spinlock_t tx_queue_lock; /* prevent concurrent tail updates */
4897 + /* track device up/down/testing state */
4898 + unsigned long state;
4900 + /* Interrupt Throttle Rate */
4909 + struct e1000_ring *tx_ring /* One per active queue */
4910 + ____cacheline_aligned_in_smp;
4912 +#ifdef CONFIG_E1000E_NAPI
4913 + struct napi_struct napi;
4916 + unsigned long tx_queue_len;
4917 + unsigned int restart_queue;
4920 + bool detect_tx_hung;
4921 + u8 tx_timeout_factor;
4924 + u32 tx_abs_int_delay;
4926 + unsigned int total_tx_bytes;
4927 + unsigned int total_tx_packets;
4928 + unsigned int total_rx_bytes;
4929 + unsigned int total_rx_packets;
4936 + u32 tx_timeout_count;
4940 + u32 tx_dma_failed;
4945 +#ifdef CONFIG_E1000E_NAPI
4946 + bool (*clean_rx) (struct e1000_adapter *adapter,
4947 + int *work_done, int work_to_do)
4948 + ____cacheline_aligned_in_smp;
4950 + bool (*clean_rx) (struct e1000_adapter *adapter)
4951 + ____cacheline_aligned_in_smp;
4953 + void (*alloc_rx_buf) (struct e1000_adapter *adapter,
4954 + int cleaned_count);
4955 + struct e1000_ring *rx_ring;
4958 + u32 rx_abs_int_delay;
4966 + u32 alloc_rx_buff_failed;
4967 + u32 rx_dma_failed;
4969 + unsigned int rx_ps_pages;
4971 + u32 max_frame_size;
4972 + u32 min_frame_size;
4974 + /* OS defined structs */
4975 + struct net_device *netdev;
4976 + struct pci_dev *pdev;
4977 + struct net_device_stats net_stats;
4978 + spinlock_t stats_lock; /* prevent concurrent stats updates */
4980 + /* structs defined in e1000_hw.h */
4981 + struct e1000_hw hw;
4983 + struct e1000_hw_stats stats;
4984 + struct e1000_phy_info phy_info;
4985 + struct e1000_phy_stats phy_stats;
4988 + /* Snapshot of PHY registers */
4989 + struct e1000_phy_regs phy_regs;
4992 + struct e1000_ring test_tx_ring;
4993 + struct e1000_ring test_rx_ring;
4997 +#ifdef CONFIG_E1000E_MSIX
4998 + struct msix_entry *msix_entries;
5001 +#endif /* CONFIG_E1000E_MSIX */
5009 + unsigned long led_status;
5011 + unsigned int flags;
5012 + unsigned int flags2;
5013 + u32 *config_space;
5014 + u32 stats_freq_us; /* stats update freq (microseconds) */
5017 +struct e1000_info {
5018 + e1000_mac_type mac;
5019 + unsigned int flags;
5020 + unsigned int flags2;
5022 + void (*init_ops)(struct e1000_hw *);
5023 + s32 (*get_variants)(struct e1000_adapter *);
5026 +/* hardware capability, feature, and workaround flags */
5027 +#define FLAG_HAS_AMT (1 << 0)
5028 +#define FLAG_HAS_FLASH (1 << 1)
5029 +#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
5030 +#define FLAG_HAS_WOL (1 << 3)
5031 +#define FLAG_HAS_ERT (1 << 4)
5032 +#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
5033 +#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
5034 +#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
5035 +#define FLAG_HAS_ASPM (1 << 8)
5036 +#define FLAG_IS_ICH (1 << 9)
5037 +#define FLAG_HAS_MSIX (1 << 10)
5038 +#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
5039 +#define FLAG_IS_QUAD_PORT_A (1 << 12)
5040 +#define FLAG_IS_QUAD_PORT (1 << 13)
5041 +#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
5042 +#define FLAG_APME_IN_WUC (1 << 15)
5043 +#define FLAG_APME_IN_CTRL3 (1 << 16)
5044 +#define FLAG_APME_CHECK_PORT_B (1 << 17)
5045 +#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
5046 +#define FLAG_NO_WAKE_UCAST (1 << 19)
5047 +#define FLAG_MNG_PT_ENABLED (1 << 20)
5048 +#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
5049 +#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
5050 +#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
5051 +#define FLAG_RX_NEEDS_RESTART (1 << 24)
5052 +#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
5053 +#define FLAG_SMART_POWER_DOWN (1 << 26)
5054 +#define FLAG_MSI_ENABLED (1 << 27)
5055 +#define FLAG_RX_CSUM_ENABLED (1 << 28)
5056 +#define FLAG_TSO_FORCE (1 << 29)
5057 +#define FLAG_MSI_TEST_FAILED (1 << 30)
5058 +#define FLAG_RX_RESTART_NOW (1 << 31)
5060 +#define FLAG2_READ_ONLY_NVM (1 << 1)
5062 +#define E1000_RX_DESC_PS(R, i) \
5063 + (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5064 +#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
5065 +#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
5066 +#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
5067 +#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
5069 +enum e1000_state_t {
5071 + __E1000_RESETTING,
5075 +enum latency_range {
5076 + lowest_latency = 0,
5079 + latency_invalid = 255
5082 +extern char e1000e_driver_name[];
5083 +extern const char e1000e_driver_version[];
5085 +extern void e1000_check_options(struct e1000_adapter *adapter);
5086 +extern void e1000_set_ethtool_ops(struct net_device *netdev);
5087 +#ifdef ETHTOOL_OPS_COMPAT
5088 +extern int ethtool_ioctl(struct ifreq *ifr);
5091 +extern int e1000_up(struct e1000_adapter *adapter);
5092 +extern void e1000_down(struct e1000_adapter *adapter);
5093 +extern void e1000_reinit_locked(struct e1000_adapter *adapter);
5094 +extern void e1000_reset(struct e1000_adapter *adapter);
5095 +extern int e1000_setup_rx_resources(struct e1000_adapter *adapter);
5096 +extern int e1000_setup_tx_resources(struct e1000_adapter *adapter);
5097 +extern void e1000_free_rx_resources(struct e1000_adapter *adapter);
5098 +extern void e1000_free_tx_resources(struct e1000_adapter *adapter);
5099 +extern void e1000_update_stats(struct e1000_adapter *adapter);
5100 +#ifdef CONFIG_E1000E_MSIX
5101 +extern void e1000_set_interrupt_capability(struct e1000_adapter *adapter);
5102 +extern void e1000_reset_interrupt_capability(struct e1000_adapter *adapter);
5105 +extern unsigned int copybreak;
5107 +static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
5109 + return readl(hw->hw_addr + reg);
5112 +static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
5114 + writel(val, hw->hw_addr + reg);
5116 +#define er32(reg) E1000_READ_REG(hw, E1000_##reg)
5117 +#define ew32(reg,val) E1000_WRITE_REG(hw, E1000_##reg, (val))
5118 +#define e1e_flush() er32(STATUS)
5120 +extern void e1000_init_function_pointers_82571(struct e1000_hw *hw);
5121 +extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
5122 +extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
5124 +static inline s32 e1000_read_mac_addr(struct e1000_hw *hw)
5126 + if (hw->mac.ops.read_mac_addr)
5127 + return hw->mac.ops.read_mac_addr(hw);
5129 + return e1000_read_mac_addr_generic(hw);
5132 +static inline void e1000_power_up_phy(struct e1000_hw *hw)
5134 + if(hw->phy.ops.power_up)
5135 + hw->phy.ops.power_up(hw);
5136 + hw->mac.ops.setup_link(hw);
5139 +#endif /* _E1000_H_ */
5140 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_hw.h linux-2.6.22-10/drivers/net/e1000e/e1000_hw.h
5141 --- linux-2.6.22-0/drivers/net/e1000e/e1000_hw.h 1970-01-01 01:00:00.000000000 +0100
5142 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_hw.h 2008-10-14 01:51:32.000000000 +0200
5144 +/*******************************************************************************
5146 + Intel PRO/1000 Linux driver
5147 + Copyright(c) 1999 - 2008 Intel Corporation.
5149 + This program is free software; you can redistribute it and/or modify it
5150 + under the terms and conditions of the GNU General Public License,
5151 + version 2, as published by the Free Software Foundation.
5153 + This program is distributed in the hope it will be useful, but WITHOUT
5154 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5155 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5158 + You should have received a copy of the GNU General Public License along with
5159 + this program; if not, write to the Free Software Foundation, Inc.,
5160 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5162 + The full GNU General Public License is included in this distribution in
5163 + the file called "COPYING".
5165 + Contact Information:
5166 + Linux NICS <linux.nics@intel.com>
5167 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
5168 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
5170 +*******************************************************************************/
5172 +#ifndef _E1000_HW_H_
5173 +#define _E1000_HW_H_
5175 +#include "e1000_osdep.h"
5176 +#include "e1000_regs.h"
5177 +#include "e1000_defines.h"
5181 +#define E1000_DEV_ID_82571EB_COPPER 0x105E
5182 +#define E1000_DEV_ID_82571EB_FIBER 0x105F
5183 +#define E1000_DEV_ID_82571EB_SERDES 0x1060
5184 +#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
5185 +#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
5186 +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
5187 +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
5188 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
5189 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
5190 +#define E1000_DEV_ID_82572EI_COPPER 0x107D
5191 +#define E1000_DEV_ID_82572EI_FIBER 0x107E
5192 +#define E1000_DEV_ID_82572EI_SERDES 0x107F
5193 +#define E1000_DEV_ID_82572EI 0x10B9
5194 +#define E1000_DEV_ID_82573E 0x108B
5195 +#define E1000_DEV_ID_82573E_IAMT 0x108C
5196 +#define E1000_DEV_ID_82573L 0x109A
5197 +#define E1000_DEV_ID_82574L 0x10D3
5198 +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
5199 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
5200 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
5201 +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
5202 +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
5203 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
5204 +#define E1000_DEV_ID_ICH8_IGP_C 0x104B
5205 +#define E1000_DEV_ID_ICH8_IFE 0x104C
5206 +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
5207 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
5208 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D
5209 +#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
5210 +#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
5211 +#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
5212 +#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
5213 +#define E1000_DEV_ID_ICH9_BM 0x10E5
5214 +#define E1000_DEV_ID_ICH9_IGP_C 0x294C
5215 +#define E1000_DEV_ID_ICH9_IFE 0x10C0
5216 +#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
5217 +#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
5218 +#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
5219 +#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
5220 +#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
5221 +#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
5222 +#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
5224 +#define E1000_REVISION_0 0
5225 +#define E1000_REVISION_1 1
5226 +#define E1000_REVISION_2 2
5227 +#define E1000_REVISION_3 3
5228 +#define E1000_REVISION_4 4
5230 +#define E1000_FUNC_0 0
5231 +#define E1000_FUNC_1 1
5234 + e1000_undefined = 0,
5239 + e1000_80003es2lan,
5243 + e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
5247 + e1000_media_type_unknown = 0,
5248 + e1000_media_type_copper = 1,
5249 + e1000_media_type_fiber = 2,
5250 + e1000_media_type_internal_serdes = 3,
5251 + e1000_num_media_types
5252 +} e1000_media_type;
5255 + e1000_nvm_unknown = 0,
5257 + e1000_nvm_eeprom_spi,
5258 + e1000_nvm_eeprom_microwire,
5259 + e1000_nvm_flash_hw,
5260 + e1000_nvm_flash_sw
5264 + e1000_nvm_override_none = 0,
5265 + e1000_nvm_override_spi_small,
5266 + e1000_nvm_override_spi_large,
5267 + e1000_nvm_override_microwire_small,
5268 + e1000_nvm_override_microwire_large
5269 +} e1000_nvm_override;
5272 + e1000_phy_unknown = 0,
5277 + e1000_phy_gg82563,
5284 + e1000_bus_type_unknown = 0,
5285 + e1000_bus_type_pci,
5286 + e1000_bus_type_pcix,
5287 + e1000_bus_type_pci_express,
5288 + e1000_bus_type_reserved
5292 + e1000_bus_speed_unknown = 0,
5293 + e1000_bus_speed_33,
5294 + e1000_bus_speed_66,
5295 + e1000_bus_speed_100,
5296 + e1000_bus_speed_120,
5297 + e1000_bus_speed_133,
5298 + e1000_bus_speed_2500,
5299 + e1000_bus_speed_5000,
5300 + e1000_bus_speed_reserved
5304 + e1000_bus_width_unknown = 0,
5305 + e1000_bus_width_pcie_x1,
5306 + e1000_bus_width_pcie_x2,
5307 + e1000_bus_width_pcie_x4 = 4,
5308 + e1000_bus_width_pcie_x8 = 8,
5309 + e1000_bus_width_32,
5310 + e1000_bus_width_64,
5311 + e1000_bus_width_reserved
5315 + e1000_1000t_rx_status_not_ok = 0,
5316 + e1000_1000t_rx_status_ok,
5317 + e1000_1000t_rx_status_undefined = 0xFF
5318 +} e1000_1000t_rx_status;
5321 + e1000_rev_polarity_normal = 0,
5322 + e1000_rev_polarity_reversed,
5323 + e1000_rev_polarity_undefined = 0xFF
5324 +} e1000_rev_polarity;
5327 + e1000_fc_none = 0,
5328 + e1000_fc_rx_pause,
5329 + e1000_fc_tx_pause,
5331 + e1000_fc_default = 0xFF
5335 +/* Receive Descriptor */
5336 +struct e1000_rx_desc {
5337 + u64 buffer_addr; /* Address of the descriptor's data buffer */
5338 + u16 length; /* Length of data DMAed into data buffer */
5339 + u16 csum; /* Packet checksum */
5340 + u8 status; /* Descriptor status */
5341 + u8 errors; /* Descriptor Errors */
5345 +/* Receive Descriptor - Extended */
5346 +union e1000_rx_desc_extended {
5353 + u32 mrq; /* Multiple Rx Queues */
5355 + u32 rss; /* RSS Hash */
5357 + u16 ip_id; /* IP id */
5358 + u16 csum; /* Packet Checksum */
5363 + u32 status_error; /* ext status/error */
5365 + u16 vlan; /* VLAN tag */
5367 + } wb; /* writeback */
5370 +#define MAX_PS_BUFFERS 4
5371 +/* Receive Descriptor - Packet Split */
5372 +union e1000_rx_desc_packet_split {
5374 + /* one buffer for protocol header(s), three data buffers */
5375 + u64 buffer_addr[MAX_PS_BUFFERS];
5379 + u32 mrq; /* Multiple Rx Queues */
5381 + u32 rss; /* RSS Hash */
5383 + u16 ip_id; /* IP id */
5384 + u16 csum; /* Packet Checksum */
5389 + u32 status_error; /* ext status/error */
5390 + u16 length0; /* length of buffer 0 */
5391 + u16 vlan; /* VLAN tag */
5394 + u16 header_status;
5395 + u16 length[3]; /* length of buffers 1-3 */
5398 + } wb; /* writeback */
5401 +/* Transmit Descriptor */
5402 +struct e1000_tx_desc {
5403 + u64 buffer_addr; /* Address of the descriptor's data buffer */
5407 + u16 length; /* Data buffer length */
5408 + u8 cso; /* Checksum offset */
5409 + u8 cmd; /* Descriptor control */
5415 + u8 status; /* Descriptor status */
5416 + u8 css; /* Checksum start */
5422 +/* Offload Context Descriptor */
5423 +struct e1000_context_desc {
5427 + u8 ipcss; /* IP checksum start */
5428 + u8 ipcso; /* IP checksum offset */
5429 + u16 ipcse; /* IP checksum end */
5435 + u8 tucss; /* TCP checksum start */
5436 + u8 tucso; /* TCP checksum offset */
5437 + u16 tucse; /* TCP checksum end */
5440 + u32 cmd_and_length;
5444 + u8 status; /* Descriptor status */
5445 + u8 hdr_len; /* Header length */
5446 + u16 mss; /* Maximum segment size */
5451 +/* Offload data descriptor */
5452 +struct e1000_data_desc {
5453 + u64 buffer_addr; /* Address of the descriptor's buffer address */
5457 + u16 length; /* Data buffer length */
5465 + u8 status; /* Descriptor status */
5466 + u8 popts; /* Packet Options */
5472 +/* Statistics counters collected by the MAC */
5473 +struct e1000_hw_stats {
5551 +struct e1000_phy_stats {
5553 + u32 receive_errors;
5556 +struct e1000_host_mng_dhcp_cookie {
5567 +/* Host Interface "Rev 1" */
5568 +struct e1000_host_command_header {
5570 + u8 command_length;
5571 + u8 command_options;
5575 +#define E1000_HI_MAX_DATA_LENGTH 252
5576 +struct e1000_host_command_info {
5577 + struct e1000_host_command_header command_header;
5578 + u8 command_data[E1000_HI_MAX_DATA_LENGTH];
5581 +/* Host Interface "Rev 2" */
5582 +struct e1000_host_mng_command_header {
5587 + u16 command_length;
5590 +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
5591 +struct e1000_host_mng_command_info {
5592 + struct e1000_host_mng_command_header command_header;
5593 + u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
5596 +#include "e1000_mac.h"
5597 +#include "e1000_phy.h"
5598 +#include "e1000_nvm.h"
5599 +#include "e1000_manage.h"
5601 +struct e1000_mac_operations {
5602 + /* Function pointers for the MAC. */
5603 + s32 (*init_params)(struct e1000_hw *);
5604 + s32 (*blink_led)(struct e1000_hw *);
5605 + s32 (*check_for_link)(struct e1000_hw *);
5606 + bool (*check_mng_mode)(struct e1000_hw *hw);
5607 + s32 (*cleanup_led)(struct e1000_hw *);
5608 + void (*clear_hw_cntrs)(struct e1000_hw *);
5609 + void (*clear_vfta)(struct e1000_hw *);
5610 + s32 (*get_bus_info)(struct e1000_hw *);
5611 + s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
5612 + s32 (*led_on)(struct e1000_hw *);
5613 + s32 (*led_off)(struct e1000_hw *);
5614 + void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32,
5616 + void (*remove_device)(struct e1000_hw *);
5617 + s32 (*reset_hw)(struct e1000_hw *);
5618 + s32 (*init_hw)(struct e1000_hw *);
5619 + s32 (*setup_link)(struct e1000_hw *);
5620 + s32 (*setup_physical_interface)(struct e1000_hw *);
5621 + s32 (*setup_led)(struct e1000_hw *);
5622 + void (*write_vfta)(struct e1000_hw *, u32, u32);
5623 + void (*mta_set)(struct e1000_hw *, u32);
5624 + void (*config_collision_dist)(struct e1000_hw*);
5625 + void (*rar_set)(struct e1000_hw*, u8*, u32);
5626 + s32 (*read_mac_addr)(struct e1000_hw*);
5627 + s32 (*validate_mdi_setting)(struct e1000_hw*);
5628 + s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
5629 + s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
5630 + struct e1000_host_mng_command_header*);
5631 + s32 (*mng_enable_host_if)(struct e1000_hw*);
5632 + s32 (*wait_autoneg)(struct e1000_hw*);
5635 +struct e1000_phy_operations {
5636 + s32 (*init_params)(struct e1000_hw *);
5637 + s32 (*acquire)(struct e1000_hw *);
5638 + s32 (*cfg_on_link_up)(struct e1000_hw *);
5639 + s32 (*check_polarity)(struct e1000_hw *);
5640 + s32 (*check_reset_block)(struct e1000_hw *);
5641 + s32 (*commit)(struct e1000_hw *);
5642 + s32 (*force_speed_duplex)(struct e1000_hw *);
5643 + s32 (*get_cfg_done)(struct e1000_hw *hw);
5644 + s32 (*get_cable_length)(struct e1000_hw *);
5645 + s32 (*get_info)(struct e1000_hw *);
5646 + s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
5647 + void (*release)(struct e1000_hw *);
5648 + s32 (*reset)(struct e1000_hw *);
5649 + s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
5650 + s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
5651 + s32 (*write_reg)(struct e1000_hw *, u32, u16);
5652 + void (*power_up)(struct e1000_hw *);
5653 + void (*power_down)(struct e1000_hw *);
5656 +struct e1000_nvm_operations {
5657 + s32 (*init_params)(struct e1000_hw *);
5658 + s32 (*acquire)(struct e1000_hw *);
5659 + s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
5660 + void (*release)(struct e1000_hw *);
5661 + void (*reload)(struct e1000_hw *);
5662 + s32 (*update)(struct e1000_hw *);
5663 + s32 (*valid_led_default)(struct e1000_hw *, u16 *);
5664 + s32 (*validate)(struct e1000_hw *);
5665 + s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
5668 +struct e1000_mac_info {
5669 + struct e1000_mac_operations ops;
5673 + e1000_mac_type type;
5675 + u32 collision_delta;
5676 + u32 ledctl_default;
5679 + u32 mc_filter_type;
5680 + u32 tx_packet_delta;
5683 + u16 current_ifs_val;
5687 + u16 ifs_step_size;
5688 + u16 mta_reg_count;
5689 + u16 rar_entry_count;
5691 + u8 forced_speed_duplex;
5693 + bool adaptive_ifs;
5694 + bool arc_subsystem_valid;
5695 + bool asf_firmware_present;
5697 + bool autoneg_failed;
5699 + bool disable_hw_init_bits;
5700 + bool get_link_status;
5701 + bool ifs_params_forced;
5703 + bool report_tx_early;
5704 + bool serdes_has_link;
5705 + bool tx_pkt_filtering;
5708 +struct e1000_phy_info {
5709 + struct e1000_phy_operations ops;
5710 + e1000_phy_type type;
5712 + e1000_1000t_rx_status local_rx;
5713 + e1000_1000t_rx_status remote_rx;
5714 + e1000_ms_type ms_type;
5715 + e1000_ms_type original_ms_type;
5716 + e1000_rev_polarity cable_polarity;
5717 + e1000_smart_speed smart_speed;
5721 + u32 reset_delay_us; /* in usec */
5724 + e1000_media_type media_type;
5726 + u16 autoneg_advertised;
5729 + u16 max_cable_length;
5730 + u16 min_cable_length;
5734 + bool disable_polarity_correction;
5736 + bool polarity_correction;
5737 + bool reset_disable;
5738 + bool speed_downgraded;
5739 + bool autoneg_wait_to_complete;
5742 +struct e1000_nvm_info {
5743 + struct e1000_nvm_operations ops;
5744 + e1000_nvm_type type;
5745 + e1000_nvm_override override;
5747 + u32 flash_bank_size;
5748 + u32 flash_base_addr;
5749 + u32 semaphore_delay;
5758 +struct e1000_bus_info {
5759 + e1000_bus_type type;
5760 + e1000_bus_speed speed;
5761 + e1000_bus_width width;
5769 +struct e1000_fc_info {
5770 + u32 high_water; /* Flow control high-water mark */
5771 + u32 low_water; /* Flow control low-water mark */
5772 + u16 pause_time; /* Flow control pause timer */
5773 + bool send_xon; /* Flow control send XON */
5774 + bool strict_ieee; /* Strict IEEE mode */
5775 + e1000_fc_type type; /* Type of flow control */
5776 + e1000_fc_type original_type;
5783 + u8 __iomem *hw_addr;
5784 + u8 __iomem *flash_address;
5785 + unsigned long io_base;
5787 + struct e1000_mac_info mac;
5788 + struct e1000_fc_info fc;
5789 + struct e1000_phy_info phy;
5790 + struct e1000_nvm_info nvm;
5791 + struct e1000_bus_info bus;
5792 + struct e1000_host_mng_dhcp_cookie mng_cookie;
5794 + u32 dev_spec_size;
5797 + u16 subsystem_vendor_id;
5798 + u16 subsystem_device_id;
5804 +#include "e1000_82571.h"
5805 +#include "e1000_80003es2lan.h"
5806 +#include "e1000_ich8lan.h"
5808 +/* These functions must be implemented by drivers */
5809 +s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
5810 +s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
5811 +void e1000_free_dev_spec_struct(struct e1000_hw *hw);
5812 +void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
5815 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.c linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.c
5816 --- linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.c 1970-01-01 01:00:00.000000000 +0100
5817 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.c 2008-10-14 01:51:32.000000000 +0200
5819 +/*******************************************************************************
5821 + Intel PRO/1000 Linux driver
5822 + Copyright(c) 1999 - 2008 Intel Corporation.
5824 + This program is free software; you can redistribute it and/or modify it
5825 + under the terms and conditions of the GNU General Public License,
5826 + version 2, as published by the Free Software Foundation.
5828 + This program is distributed in the hope it will be useful, but WITHOUT
5829 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5830 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5833 + You should have received a copy of the GNU General Public License along with
5834 + this program; if not, write to the Free Software Foundation, Inc.,
5835 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5837 + The full GNU General Public License is included in this distribution in
5838 + the file called "COPYING".
5840 + Contact Information:
5841 + Linux NICS <linux.nics@intel.com>
5842 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
5843 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
5845 +*******************************************************************************/
5851 +#include "e1000_hw.h"
5853 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
5854 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
5855 +static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
5856 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
5857 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
5858 +static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
5859 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
5860 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
5861 +static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
5862 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
5863 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
5864 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
5866 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
5868 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
5869 + u16 words, u16 *data);
5870 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
5871 + u16 words, u16 *data);
5872 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
5873 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
5874 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
5876 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
5877 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
5878 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
5879 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
5880 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
5881 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
5882 + u16 *speed, u16 *duplex);
5883 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
5884 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
5885 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
5886 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
5887 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
5888 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
5889 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
5890 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
5891 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
5892 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
5893 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
5894 + u32 offset, u8* data);
5895 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
5896 + u8 size, u16* data);
5897 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
5898 + u32 offset, u16 *data);
5899 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
5900 + u32 offset, u8 byte);
5901 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
5902 + u32 offset, u8 data);
5903 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
5904 + u8 size, u16 data);
5905 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
5906 +static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
5908 +/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
5909 +/* Offset 04h HSFSTS */
5910 +union ich8_hws_flash_status {
5911 + struct ich8_hsfsts {
5912 + u16 flcdone :1; /* bit 0 Flash Cycle Done */
5913 + u16 flcerr :1; /* bit 1 Flash Cycle Error */
5914 + u16 dael :1; /* bit 2 Direct Access error Log */
5915 + u16 berasesz :2; /* bit 4:3 Sector Erase Size */
5916 + u16 flcinprog :1; /* bit 5 flash cycle in Progress */
5917 + u16 reserved1 :2; /* bit 13:6 Reserved */
5918 + u16 reserved2 :6; /* bit 13:6 Reserved */
5919 + u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
5920 + u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
5925 +/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
5926 +/* Offset 06h FLCTL */
5927 +union ich8_hws_flash_ctrl {
5928 + struct ich8_hsflctl {
5929 + u16 flcgo :1; /* 0 Flash Cycle Go */
5930 + u16 flcycle :2; /* 2:1 Flash Cycle */
5931 + u16 reserved :5; /* 7:3 Reserved */
5932 + u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
5933 + u16 flockdn :6; /* 15:10 Reserved */
5938 +/* ICH Flash Region Access Permissions */
5939 +union ich8_hws_flash_regacc {
5940 + struct ich8_flracc {
5941 + u32 grra :8; /* 0:7 GbE region Read Access */
5942 + u32 grwa :8; /* 8:15 GbE region Write Access */
5943 + u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
5944 + u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
5949 +struct e1000_shadow_ram {
5954 +struct e1000_dev_spec_ich8lan {
5955 + bool kmrn_lock_loss_workaround_enabled;
5956 + struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
5960 + * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
5961 + * @hw: pointer to the HW structure
5963 + * Initialize family-specific PHY parameters and function pointers.
5965 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
5967 + struct e1000_phy_info *phy = &hw->phy;
5968 + s32 ret_val = E1000_SUCCESS;
5971 + DEBUGFUNC("e1000_init_phy_params_ich8lan");
5974 + phy->reset_delay_us = 100;
5976 + phy->ops.acquire = e1000_acquire_swflag_ich8lan;
5977 + phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
5978 + phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
5979 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
5980 + phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
5981 + phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
5982 + phy->ops.get_info = e1000_get_phy_info_ich8lan;
5983 + phy->ops.read_reg = e1000_read_phy_reg_igp;
5984 + phy->ops.release = e1000_release_swflag_ich8lan;
5985 + phy->ops.reset = e1000_phy_hw_reset_ich8lan;
5986 + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
5987 + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
5988 + phy->ops.write_reg = e1000_write_phy_reg_igp;
5989 + phy->ops.power_up = e1000_power_up_phy_copper;
5990 + phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
5993 + * We may need to do this twice - once for IGP and if that fails,
5994 + * we'll set BM func pointers and try again
5996 + ret_val = e1000_determine_phy_address(hw);
5998 + phy->ops.write_reg = e1000_write_phy_reg_bm;
5999 + phy->ops.read_reg = e1000_read_phy_reg_bm;
6000 + ret_val = e1000_determine_phy_address(hw);
6002 + DEBUGOUT("Cannot determine PHY address. Erroring out\n");
6008 + while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
6011 + ret_val = e1000_get_phy_id(hw);
6016 + /* Verify phy id */
6017 + switch (phy->id) {
6018 + case IGP03E1000_E_PHY_ID:
6019 + phy->type = e1000_phy_igp_3;
6020 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
6022 + case IFE_E_PHY_ID:
6023 + case IFE_PLUS_E_PHY_ID:
6024 + case IFE_C_E_PHY_ID:
6025 + phy->type = e1000_phy_ife;
6026 + phy->autoneg_mask = E1000_ALL_NOT_GIG;
6028 + case BME1000_E_PHY_ID:
6029 + phy->type = e1000_phy_bm;
6030 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
6031 + phy->ops.read_reg = e1000_read_phy_reg_bm;
6032 + phy->ops.write_reg = e1000_write_phy_reg_bm;
6033 + phy->ops.commit = e1000_phy_sw_reset_generic;
6036 + ret_val = -E1000_ERR_PHY;
6045 + * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
6046 + * @hw: pointer to the HW structure
6048 + * Initialize family-specific NVM parameters and function
6051 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
6053 + struct e1000_nvm_info *nvm = &hw->nvm;
6054 + struct e1000_dev_spec_ich8lan *dev_spec;
6055 + u32 gfpreg, sector_base_addr, sector_end_addr;
6056 + s32 ret_val = E1000_SUCCESS;
6059 + DEBUGFUNC("e1000_init_nvm_params_ich8lan");
6061 + /* Can't read flash registers if the register set isn't mapped. */
6062 + if (!hw->flash_address) {
6063 + DEBUGOUT("ERROR: Flash registers not mapped\n");
6064 + ret_val = -E1000_ERR_CONFIG;
6068 + nvm->type = e1000_nvm_flash_sw;
6070 + gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
6073 + * sector_X_addr is a "sector"-aligned address (4096 bytes)
6074 + * Add 1 to sector_end_addr since this sector is included in
6075 + * the overall size.
6077 + sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
6078 + sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
6080 + /* flash_base_addr is byte-aligned */
6081 + nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
6084 + * find total size of the NVM, then cut in half since the total
6085 + * size represents two separate NVM banks.
6087 + nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
6088 + << FLASH_SECTOR_ADDR_SHIFT;
6089 + nvm->flash_bank_size /= 2;
6090 + /* Adjust to word count */
6091 + nvm->flash_bank_size /= sizeof(u16);
6093 + nvm->word_size = E1000_SHADOW_RAM_WORDS;
6095 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
6098 + DEBUGOUT("dev_spec pointer is set to NULL.\n");
6099 + ret_val = -E1000_ERR_CONFIG;
6103 + /* Clear shadow ram */
6104 + for (i = 0; i < nvm->word_size; i++) {
6105 + dev_spec->shadow_ram[i].modified = false;
6106 + dev_spec->shadow_ram[i].value = 0xFFFF;
6109 + /* Function Pointers */
6110 + nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
6111 + nvm->ops.read = e1000_read_nvm_ich8lan;
6112 + nvm->ops.release = e1000_release_swflag_ich8lan;
6113 + nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
6114 + nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
6115 + nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
6116 + nvm->ops.write = e1000_write_nvm_ich8lan;
6123 + * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
6124 + * @hw: pointer to the HW structure
6126 + * Initialize family-specific MAC parameters and function
6129 +static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
6131 + struct e1000_mac_info *mac = &hw->mac;
6132 + s32 ret_val = E1000_SUCCESS;
6134 + DEBUGFUNC("e1000_init_mac_params_ich8lan");
6136 + /* Set media type function pointer */
6137 + hw->phy.media_type = e1000_media_type_copper;
6139 + /* Set mta register count */
6140 + mac->mta_reg_count = 32;
6141 + /* Set rar entry count */
6142 + mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
6143 + if (mac->type == e1000_ich8lan)
6144 + mac->rar_entry_count--;
6145 + /* Set if part includes ASF firmware */
6146 + mac->asf_firmware_present = true;
6147 + /* Set if manageability features are enabled. */
6148 + mac->arc_subsystem_valid = true;
6150 + /* Function pointers */
6152 + /* bus type/speed/width */
6153 + mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
6155 + mac->ops.reset_hw = e1000_reset_hw_ich8lan;
6156 + /* hw initialization */
6157 + mac->ops.init_hw = e1000_init_hw_ich8lan;
6159 + mac->ops.setup_link = e1000_setup_link_ich8lan;
6160 + /* physical interface setup */
6161 + mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
6162 + /* check for link */
6163 + mac->ops.check_for_link = e1000_check_for_copper_link_generic;
6164 + /* check management mode */
6165 + mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
6167 + mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
6168 + /* multicast address update */
6169 + mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
6171 + mac->ops.mta_set = e1000_mta_set_generic;
6173 + mac->ops.blink_led = e1000_blink_led_generic;
6175 + mac->ops.setup_led = e1000_setup_led_generic;
6177 + mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
6178 + /* turn on/off LED */
6179 + mac->ops.led_on = e1000_led_on_ich8lan;
6180 + mac->ops.led_off = e1000_led_off_ich8lan;
6181 + /* remove device */
6182 + mac->ops.remove_device = e1000_remove_device_generic;
6183 + /* clear hardware counters */
6184 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
6186 + hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan);
6188 + /* Device-specific structure allocation */
6189 + ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
6193 + /* Enable PCS Lock-loss workaround for ICH8 */
6194 + if (mac->type == e1000_ich8lan)
6195 + e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
6203 + * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
6204 + * @hw: pointer to the HW structure
6206 + * Initialize family-specific function pointers for PHY, MAC, and NVM.
6208 +void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
6210 + DEBUGFUNC("e1000_init_function_pointers_ich8lan");
6212 + e1000_init_mac_ops_generic(hw);
6213 + e1000_init_nvm_ops_generic(hw);
6214 + hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
6215 + hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
6216 + hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
6220 + * e1000_acquire_swflag_ich8lan - Acquire software control flag
6221 + * @hw: pointer to the HW structure
6223 + * Acquires the software control flag for performing NVM and PHY
6224 + * operations. This is a function pointer entry point only called by
6225 + * read/write routines for the PHY and NVM parts.
6227 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
6229 + u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
6230 + s32 ret_val = E1000_SUCCESS;
6232 + DEBUGFUNC("e1000_acquire_swflag_ich8lan");
6235 + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
6236 + extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
6237 + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
6239 + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
6240 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
6242 + msec_delay_irq(1);
6247 + DEBUGOUT("FW or HW has locked the resource for too long.\n");
6248 + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
6249 + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
6250 + ret_val = -E1000_ERR_CONFIG;
6259 + * e1000_release_swflag_ich8lan - Release software control flag
6260 + * @hw: pointer to the HW structure
6262 + * Releases the software control flag for performing NVM and PHY operations.
6263 + * This is a function pointer entry point only called by read/write
6264 + * routines for the PHY and NVM parts.
6266 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
6270 + DEBUGFUNC("e1000_release_swflag_ich8lan");
6272 + extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
6273 + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
6274 + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
6280 + * e1000_check_mng_mode_ich8lan - Checks management mode
6281 + * @hw: pointer to the HW structure
6283 + * This checks if the adapter has manageability enabled.
6284 + * This is a function pointer entry point only called by read/write
6285 + * routines for the PHY and NVM parts.
6287 +static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
6291 + DEBUGFUNC("e1000_check_mng_mode_ich8lan");
6293 + fwsm = E1000_READ_REG(hw, E1000_FWSM);
6295 + return ((fwsm & E1000_FWSM_MODE_MASK) ==
6296 + (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
6300 + * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
6301 + * @hw: pointer to the HW structure
6303 + * Checks if firmware is blocking the reset of the PHY.
6304 + * This is a function pointer entry point only called by
6307 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
6311 + DEBUGFUNC("e1000_check_reset_block_ich8lan");
6313 + fwsm = E1000_READ_REG(hw, E1000_FWSM);
6315 + return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
6316 + : E1000_BLK_PHY_RESET;
6320 + * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
6321 + * @hw: pointer to the HW structure
6323 + * Forces the speed and duplex settings of the PHY.
6324 + * This is a function pointer entry point only called by
6325 + * PHY setup routines.
6327 +static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
6329 + struct e1000_phy_info *phy = &hw->phy;
6334 + DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
6336 + if (phy->type != e1000_phy_ife) {
6337 + ret_val = e1000_phy_force_speed_duplex_igp(hw);
6341 + ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
6345 + e1000_phy_force_speed_duplex_setup(hw, &data);
6347 + ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
6351 + /* Disable MDI-X support for 10/100 */
6352 + ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
6356 + data &= ~IFE_PMC_AUTO_MDIX;
6357 + data &= ~IFE_PMC_FORCE_MDIX;
6359 + ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
6363 + DEBUGOUT1("IFE PMC: %X\n", data);
6367 + if (phy->autoneg_wait_to_complete) {
6368 + DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
6370 + ret_val = e1000_phy_has_link_generic(hw,
6378 + DEBUGOUT("Link taking longer than expected.\n");
6381 + /* Try once more */
6382 + ret_val = e1000_phy_has_link_generic(hw,
6395 + * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
6396 + * @hw: pointer to the HW structure
6399 + * This is a function pointer entry point called by drivers
6400 + * or other shared routines.
6402 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
6404 + struct e1000_phy_info *phy = &hw->phy;
6405 + struct e1000_nvm_info *nvm = &hw->nvm;
6406 + u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
6408 + u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
6409 + u16 word_addr, reg_data, reg_addr, phy_page = 0;
6411 + DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
6413 + ret_val = e1000_phy_hw_reset_generic(hw);
6418 + * Initialize the PHY from the NVM on ICH platforms. This
6419 + * is needed due to an issue where the NVM configuration is
6420 + * not properly autoloaded after power transitions.
6421 + * Therefore, after each PHY reset, we will load the
6422 + * configuration data out of the NVM manually.
6424 + if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
6425 + /* Check if SW needs configure the PHY */
6426 + if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
6427 + (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
6428 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
6430 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
6432 + data = E1000_READ_REG(hw, E1000_FEXTNVM);
6433 + if (!(data & sw_cfg_mask))
6436 + /* Wait for basic configuration completes before proceeding*/
6438 + data = E1000_READ_REG(hw, E1000_STATUS);
6439 + data &= E1000_STATUS_LAN_INIT_DONE;
6441 + } while ((!data) && --loop);
6444 + * If basic configuration is incomplete before the above loop
6445 + * count reaches 0, loading the configuration from NVM will
6446 + * leave the PHY in a bad state possibly resulting in no link.
6449 + DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
6452 + /* Clear the Init Done bit for the next init event */
6453 + data = E1000_READ_REG(hw, E1000_STATUS);
6454 + data &= ~E1000_STATUS_LAN_INIT_DONE;
6455 + E1000_WRITE_REG(hw, E1000_STATUS, data);
6458 + * Make sure HW does not configure LCD from PHY
6459 + * extended configuration before SW configuration
6461 + data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
6462 + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
6465 + cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
6466 + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
6467 + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
6471 + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
6472 + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
6475 + * Configure LCD from extended configuration
6479 + /* cnf_base_addr is in DWORD */
6480 + word_addr = (u16)(cnf_base_addr << 1);
6482 + for (i = 0; i < cnf_size; i++) {
6483 + ret_val = nvm->ops.read(hw,
6484 + (word_addr + i * 2),
6490 + ret_val = nvm->ops.read(hw,
6491 + (word_addr + i * 2 + 1),
6497 + /* Save off the PHY page for future writes. */
6498 + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
6499 + phy_page = reg_data;
6503 + reg_addr |= phy_page;
6505 + ret_val = phy->ops.write_reg(hw,
6518 + * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
6519 + * @hw: pointer to the HW structure
6521 + * Wrapper for calling the get_phy_info routines for the appropriate phy type.
6522 + * This is a function pointer entry point called by drivers
6523 + * or other shared routines.
6525 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
6527 + s32 ret_val = -E1000_ERR_PHY_TYPE;
6529 + DEBUGFUNC("e1000_get_phy_info_ich8lan");
6531 + switch (hw->phy.type) {
6532 + case e1000_phy_ife:
6533 + ret_val = e1000_get_phy_info_ife_ich8lan(hw);
6535 + case e1000_phy_igp_3:
6536 + case e1000_phy_bm:
6537 + ret_val = e1000_get_phy_info_igp(hw);
6547 + * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
6548 + * @hw: pointer to the HW structure
6550 + * Populates "phy" structure with various feature states.
6551 + * This function is only called by other family-specific
6554 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
6556 + struct e1000_phy_info *phy = &hw->phy;
6561 + DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
6563 + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
6568 + DEBUGOUT("Phy info is only valid if link is up\n");
6569 + ret_val = -E1000_ERR_CONFIG;
6573 + ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
6576 + phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
6579 + if (phy->polarity_correction) {
6580 + ret_val = e1000_check_polarity_ife_ich8lan(hw);
6584 + /* Polarity is forced */
6585 + phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
6586 + ? e1000_rev_polarity_reversed
6587 + : e1000_rev_polarity_normal;
6590 + ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
6594 + phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
6596 + /* The following parameters are undefined for 10/100 operation. */
6597 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
6598 + phy->local_rx = e1000_1000t_rx_status_undefined;
6599 + phy->remote_rx = e1000_1000t_rx_status_undefined;
6606 + * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
6607 + * @hw: pointer to the HW structure
6609 + * Polarity is determined on the polarity reversal feature being enabled.
6610 + * This function is only called by other family-specific
6613 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
6615 + struct e1000_phy_info *phy = &hw->phy;
6617 + u16 phy_data, offset, mask;
6619 + DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
6622 + * Polarity is determined based on the reversal feature
6625 + if (phy->polarity_correction) {
6626 + offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
6627 + mask = IFE_PESC_POLARITY_REVERSED;
6629 + offset = IFE_PHY_SPECIAL_CONTROL;
6630 + mask = IFE_PSC_FORCE_POLARITY;
6633 + ret_val = phy->ops.read_reg(hw, offset, &phy_data);
6636 + phy->cable_polarity = (phy_data & mask)
6637 + ? e1000_rev_polarity_reversed
6638 + : e1000_rev_polarity_normal;
6644 + * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
6645 + * @hw: pointer to the HW structure
6646 + * @active: true to enable LPLU, false to disable
6648 + * Sets the LPLU D0 state according to the active flag. When
6649 + * activating LPLU this function also disables smart speed
6650 + * and vice versa. LPLU will not be activated unless the
6651 + * device autonegotiation advertisement meets standards of
6652 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
6653 + * This is a function pointer entry point only called by
6654 + * PHY setup routines.
6656 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
6659 + struct e1000_phy_info *phy = &hw->phy;
6661 + s32 ret_val = E1000_SUCCESS;
6664 + DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
6666 + if (phy->type == e1000_phy_ife)
6669 + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
6672 + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
6673 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
6676 + * Call gig speed drop workaround on LPLU before accessing
6677 + * any PHY registers
6679 + if ((hw->mac.type == e1000_ich8lan) &&
6680 + (hw->phy.type == e1000_phy_igp_3))
6681 + e1000_gig_downshift_workaround_ich8lan(hw);
6683 + /* When LPLU is enabled, we should disable SmartSpeed */
6684 + ret_val = phy->ops.read_reg(hw,
6685 + IGP01E1000_PHY_PORT_CONFIG,
6687 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6688 + ret_val = phy->ops.write_reg(hw,
6689 + IGP01E1000_PHY_PORT_CONFIG,
6694 + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
6695 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
6698 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
6699 + * during Dx states where the power conservation is most
6700 + * important. During driver activity we should enable
6701 + * SmartSpeed, so performance is maintained.
6703 + if (phy->smart_speed == e1000_smart_speed_on) {
6704 + ret_val = phy->ops.read_reg(hw,
6705 + IGP01E1000_PHY_PORT_CONFIG,
6710 + data |= IGP01E1000_PSCFR_SMART_SPEED;
6711 + ret_val = phy->ops.write_reg(hw,
6712 + IGP01E1000_PHY_PORT_CONFIG,
6716 + } else if (phy->smart_speed == e1000_smart_speed_off) {
6717 + ret_val = phy->ops.read_reg(hw,
6718 + IGP01E1000_PHY_PORT_CONFIG,
6723 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6724 + ret_val = phy->ops.write_reg(hw,
6725 + IGP01E1000_PHY_PORT_CONFIG,
6737 + * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
6738 + * @hw: pointer to the HW structure
6739 + * @active: true to enable LPLU, false to disable
6741 + * Sets the LPLU D3 state according to the active flag. When
6742 + * activating LPLU this function also disables smart speed
6743 + * and vice versa. LPLU will not be activated unless the
6744 + * device autonegotiation advertisement meets standards of
6745 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
6746 + * This is a function pointer entry point only called by
6747 + * PHY setup routines.
6749 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
6752 + struct e1000_phy_info *phy = &hw->phy;
6754 + s32 ret_val = E1000_SUCCESS;
6757 + DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
6759 + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
6762 + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
6763 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
6765 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
6766 + * during Dx states where the power conservation is most
6767 + * important. During driver activity we should enable
6768 + * SmartSpeed, so performance is maintained.
6770 + if (phy->smart_speed == e1000_smart_speed_on) {
6771 + ret_val = phy->ops.read_reg(hw,
6772 + IGP01E1000_PHY_PORT_CONFIG,
6777 + data |= IGP01E1000_PSCFR_SMART_SPEED;
6778 + ret_val = phy->ops.write_reg(hw,
6779 + IGP01E1000_PHY_PORT_CONFIG,
6783 + } else if (phy->smart_speed == e1000_smart_speed_off) {
6784 + ret_val = phy->ops.read_reg(hw,
6785 + IGP01E1000_PHY_PORT_CONFIG,
6790 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6791 + ret_val = phy->ops.write_reg(hw,
6792 + IGP01E1000_PHY_PORT_CONFIG,
6797 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
6798 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
6799 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
6800 + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
6801 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
6804 + * Call gig speed drop workaround on LPLU before accessing
6805 + * any PHY registers
6807 + if ((hw->mac.type == e1000_ich8lan) &&
6808 + (hw->phy.type == e1000_phy_igp_3))
6809 + e1000_gig_downshift_workaround_ich8lan(hw);
6811 + /* When LPLU is enabled, we should disable SmartSpeed */
6812 + ret_val = phy->ops.read_reg(hw,
6813 + IGP01E1000_PHY_PORT_CONFIG,
6818 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6819 + ret_val = phy->ops.write_reg(hw,
6820 + IGP01E1000_PHY_PORT_CONFIG,
6829 + * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
6830 + * @hw: pointer to the HW structure
6831 + * @bank: pointer to the variable that returns the active bank
6833 + * Reads signature byte from the NVM using the flash access registers.
6835 +static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
6837 + s32 ret_val = E1000_SUCCESS;
6838 + struct e1000_nvm_info *nvm = &hw->nvm;
6839 + /* flash bank size is in words */
6840 + u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
6841 + u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
6842 + u8 bank_high_byte = 0;
6844 + if (hw->mac.type != e1000_ich10lan) {
6845 + if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
6849 + } else if (hw->dev_spec != NULL) {
6851 + * Make sure the signature for bank 0 is valid,
6852 + * if not check for bank1
6854 + e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
6855 + if ((bank_high_byte & 0xC0) == 0x80) {
6859 + * find if segment 1 is valid by verifying
6860 + * bit 15:14 = 10b in word 0x13
6862 + e1000_read_flash_byte_ich8lan(hw,
6863 + act_offset + bank1_offset,
6866 + /* bank1 has a valid signature equivalent to SEC1V */
6867 + if ((bank_high_byte & 0xC0) == 0x80) {
6870 + DEBUGOUT("ERROR: EEPROM not present\n");
6871 + ret_val = -E1000_ERR_NVM;
6875 + DEBUGOUT("DEV SPEC is NULL\n");
6876 + ret_val = -E1000_ERR_NVM;
6883 + * e1000_read_nvm_ich8lan - Read word(s) from the NVM
6884 + * @hw: pointer to the HW structure
6885 + * @offset: The offset (in bytes) of the word(s) to read.
6886 + * @words: Size of data to read in words
6887 + * @data: Pointer to the word(s) to read at offset.
6889 + * Reads a word(s) from the NVM using the flash access registers.
6891 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
6894 + struct e1000_nvm_info *nvm = &hw->nvm;
6895 + struct e1000_dev_spec_ich8lan *dev_spec;
6897 + s32 ret_val = E1000_SUCCESS;
6901 + DEBUGFUNC("e1000_read_nvm_ich8lan");
6903 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
6906 + DEBUGOUT("dev_spec pointer is set to NULL.\n");
6907 + ret_val = -E1000_ERR_CONFIG;
6911 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
6913 + DEBUGOUT("nvm parameter(s) out of bounds\n");
6914 + ret_val = -E1000_ERR_NVM;
6918 + ret_val = nvm->ops.acquire(hw);
6922 + ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
6923 + if (ret_val != E1000_SUCCESS)
6926 + act_offset = (bank) ? nvm->flash_bank_size : 0;
6927 + act_offset += offset;
6929 + for (i = 0; i < words; i++) {
6930 + if ((dev_spec->shadow_ram) &&
6931 + (dev_spec->shadow_ram[offset+i].modified)) {
6932 + data[i] = dev_spec->shadow_ram[offset+i].value;
6934 + ret_val = e1000_read_flash_word_ich8lan(hw,
6943 + nvm->ops.release(hw);
6950 + * e1000_flash_cycle_init_ich8lan - Initialize flash
6951 + * @hw: pointer to the HW structure
6953 + * This function does initial flash setup so that a new read/write/erase cycle
6956 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
6958 + union ich8_hws_flash_status hsfsts;
6959 + s32 ret_val = -E1000_ERR_NVM;
6962 + DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
6964 + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
6966 + /* Check if the flash descriptor is valid */
6967 + if (hsfsts.hsf_status.fldesvalid == 0) {
6968 + DEBUGOUT("Flash descriptor invalid. "
6969 + "SW Sequencing must be used.");
6973 + /* Clear FCERR and DAEL in hw status by writing 1 */
6974 + hsfsts.hsf_status.flcerr = 1;
6975 + hsfsts.hsf_status.dael = 1;
6977 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
6980 + * Either we should have a hardware SPI cycle in progress
6981 + * bit to check against, in order to start a new cycle or
6982 + * FDONE bit should be changed in the hardware so that it
6983 + * is 1 after hardware reset, which can then be used as an
6984 + * indication whether a cycle is in progress or has been
6988 + if (hsfsts.hsf_status.flcinprog == 0) {
6990 + * There is no cycle running at present,
6991 + * so we can start a cycle.
6992 + * Begin by setting Flash Cycle Done.
6994 + hsfsts.hsf_status.flcdone = 1;
6995 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
6996 + ret_val = E1000_SUCCESS;
6999 + * Otherwise poll for sometime so the current
7000 + * cycle has a chance to end before giving up.
7002 + for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
7003 + hsfsts.regval = E1000_READ_FLASH_REG16(hw,
7004 + ICH_FLASH_HSFSTS);
7005 + if (hsfsts.hsf_status.flcinprog == 0) {
7006 + ret_val = E1000_SUCCESS;
7011 + if (ret_val == E1000_SUCCESS) {
7013 + * Successful in waiting for previous cycle to timeout,
7014 + * now set the Flash Cycle Done.
7016 + hsfsts.hsf_status.flcdone = 1;
7017 + E1000_WRITE_FLASH_REG16(hw,
7021 + DEBUGOUT("Flash controller busy, cannot get access");
7030 + * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
7031 + * @hw: pointer to the HW structure
7032 + * @timeout: maximum time to wait for completion
7034 + * This function starts a flash cycle and waits for its completion.
7036 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
7038 + union ich8_hws_flash_ctrl hsflctl;
7039 + union ich8_hws_flash_status hsfsts;
7040 + s32 ret_val = -E1000_ERR_NVM;
7043 + DEBUGFUNC("e1000_flash_cycle_ich8lan");
7045 + /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
7046 + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7047 + hsflctl.hsf_ctrl.flcgo = 1;
7048 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7050 + /* wait till FDONE bit is set to 1 */
7052 + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7053 + if (hsfsts.hsf_status.flcdone == 1)
7056 + } while (i++ < timeout);
7058 + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
7059 + ret_val = E1000_SUCCESS;
7065 + * e1000_read_flash_word_ich8lan - Read word from flash
7066 + * @hw: pointer to the HW structure
7067 + * @offset: offset to data location
7068 + * @data: pointer to the location for storing the data
7070 + * Reads the flash word at offset into data. Offset is converted
7071 + * to bytes before read.
7073 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
7078 + DEBUGFUNC("e1000_read_flash_word_ich8lan");
7081 + ret_val = -E1000_ERR_NVM;
7085 + /* Must convert offset into bytes. */
7088 + ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
7095 + * e1000_read_flash_byte_ich8lan - Read byte from flash
7096 + * @hw: pointer to the HW structure
7097 + * @offset: The offset of the byte to read.
7098 + * @data: Pointer to a byte to store the value read.
7100 + * Reads a single byte from the NVM using the flash access registers.
7102 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
7105 + s32 ret_val = E1000_SUCCESS;
7108 + ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
7119 + * e1000_read_flash_data_ich8lan - Read byte or word from NVM
7120 + * @hw: pointer to the HW structure
7121 + * @offset: The offset (in bytes) of the byte or word to read.
7122 + * @size: Size of data to read, 1=byte 2=word
7123 + * @data: Pointer to the word to store the value read.
7125 + * Reads a byte or word from the NVM using the flash access registers.
7127 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
7128 + u8 size, u16* data)
7130 + union ich8_hws_flash_status hsfsts;
7131 + union ich8_hws_flash_ctrl hsflctl;
7132 + u32 flash_linear_addr;
7133 + u32 flash_data = 0;
7134 + s32 ret_val = -E1000_ERR_NVM;
7137 + DEBUGFUNC("e1000_read_flash_data_ich8lan");
7139 + if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
7142 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7143 + hw->nvm.flash_base_addr;
7148 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7149 + if (ret_val != E1000_SUCCESS)
7152 + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7153 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7154 + hsflctl.hsf_ctrl.fldbcount = size - 1;
7155 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
7156 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7158 + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
7160 + ret_val = e1000_flash_cycle_ich8lan(hw,
7161 + ICH_FLASH_READ_COMMAND_TIMEOUT);
7164 + * Check if FCERR is set to 1, if set to 1, clear it
7165 + * and try the whole sequence a few more times, else
7166 + * read in (shift in) the Flash Data0, the order is
7167 + * least significant byte first msb to lsb
7169 + if (ret_val == E1000_SUCCESS) {
7170 + flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
7172 + *data = (u8)(flash_data & 0x000000FF);
7173 + } else if (size == 2) {
7174 + *data = (u16)(flash_data & 0x0000FFFF);
7179 + * If we've gotten here, then things are probably
7180 + * completely hosed, but if the error condition is
7181 + * detected, it won't hurt to give it another try...
7182 + * ICH_FLASH_CYCLE_REPEAT_COUNT times.
7184 + hsfsts.regval = E1000_READ_FLASH_REG16(hw,
7185 + ICH_FLASH_HSFSTS);
7186 + if (hsfsts.hsf_status.flcerr == 1) {
7187 + /* Repeat for some time before giving up. */
7189 + } else if (hsfsts.hsf_status.flcdone == 0) {
7190 + DEBUGOUT("Timeout error - flash cycle "
7191 + "did not complete.");
7195 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7202 + * e1000_write_nvm_ich8lan - Write word(s) to the NVM
7203 + * @hw: pointer to the HW structure
7204 + * @offset: The offset (in bytes) of the word(s) to write.
7205 + * @words: Size of data to write in words
7206 + * @data: Pointer to the word(s) to write at offset.
7208 + * Writes a byte or word to the NVM using the flash access registers.
7210 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
7213 + struct e1000_nvm_info *nvm = &hw->nvm;
7214 + struct e1000_dev_spec_ich8lan *dev_spec;
7215 + s32 ret_val = E1000_SUCCESS;
7218 + DEBUGFUNC("e1000_write_nvm_ich8lan");
7220 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
7223 + DEBUGOUT("dev_spec pointer is set to NULL.\n");
7224 + ret_val = -E1000_ERR_CONFIG;
7228 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
7230 + DEBUGOUT("nvm parameter(s) out of bounds\n");
7231 + ret_val = -E1000_ERR_NVM;
7235 + ret_val = nvm->ops.acquire(hw);
7239 + for (i = 0; i < words; i++) {
7240 + dev_spec->shadow_ram[offset+i].modified = true;
7241 + dev_spec->shadow_ram[offset+i].value = data[i];
7244 + nvm->ops.release(hw);
7251 + * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
7252 + * @hw: pointer to the HW structure
7254 + * The NVM checksum is updated by calling the generic update_nvm_checksum,
7255 + * which writes the checksum to the shadow ram. The changes in the shadow
7256 + * ram are then committed to the EEPROM by processing each bank at a time
7257 + * checking for the modified bit and writing only the pending changes.
7258 + * After a successful commit, the shadow ram is cleared and is ready for
7261 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
7263 + struct e1000_nvm_info *nvm = &hw->nvm;
7264 + struct e1000_dev_spec_ich8lan *dev_spec;
7265 + u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
7269 + DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
7271 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
7273 + ret_val = e1000_update_nvm_checksum_generic(hw);
7277 + if (nvm->type != e1000_nvm_flash_sw)
7280 + ret_val = nvm->ops.acquire(hw);
7285 + * We're writing to the opposite bank so if we're on bank 1,
7286 + * write to bank 0 etc. We also need to erase the segment that
7287 + * is going to be written
7289 + ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
7290 + if (ret_val != E1000_SUCCESS)
7294 + new_bank_offset = nvm->flash_bank_size;
7295 + old_bank_offset = 0;
7296 + e1000_erase_flash_bank_ich8lan(hw, 1);
7298 + old_bank_offset = nvm->flash_bank_size;
7299 + new_bank_offset = 0;
7300 + e1000_erase_flash_bank_ich8lan(hw, 0);
7303 + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7305 + * Determine whether to write the value stored
7306 + * in the other NVM bank or a modified value stored
7307 + * in the shadow RAM
7309 + if (dev_spec->shadow_ram[i].modified) {
7310 + data = dev_spec->shadow_ram[i].value;
7312 + e1000_read_flash_word_ich8lan(hw,
7313 + i + old_bank_offset,
7318 + * If the word is 0x13, then make sure the signature bits
7319 + * (15:14) are 11b until the commit has completed.
7320 + * This will allow us to write 10b which indicates the
7321 + * signature is valid. We want to do this after the write
7322 + * has completed so that we don't mark the segment valid
7323 + * while the write is still in progress
7325 + if (i == E1000_ICH_NVM_SIG_WORD)
7326 + data |= E1000_ICH_NVM_SIG_MASK;
7328 + /* Convert offset to bytes. */
7329 + act_offset = (i + new_bank_offset) << 1;
7332 + /* Write the bytes to the new bank. */
7333 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7340 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7348 + * Don't bother writing the segment valid bits if sector
7349 + * programming failed.
7352 + /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
7353 + DEBUGOUT("Flash commit failed.\n");
7354 + nvm->ops.release(hw);
7359 + * Finally validate the new segment by setting bit 15:14
7360 + * to 10b in word 0x13 , this can be done without an
7361 + * erase as well since these bits are 11 to start with
7362 + * and we need to change bit 14 to 0b
7364 + act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
7365 + e1000_read_flash_word_ich8lan(hw, act_offset, &data);
7367 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7368 + act_offset * 2 + 1,
7371 + nvm->ops.release(hw);
7376 + * And invalidate the previously valid segment by setting
7377 + * its signature word (0x13) high_byte to 0b. This can be
7378 + * done without an erase because flash erase sets all bits
7379 + * to 1's. We can write 1's to 0's without an erase
7381 + act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
7382 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
7384 + nvm->ops.release(hw);
7388 + /* Great! Everything worked, we can now clear the cached entries. */
7389 + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7390 + dev_spec->shadow_ram[i].modified = false;
7391 + dev_spec->shadow_ram[i].value = 0xFFFF;
7394 + nvm->ops.release(hw);
7397 + * Reload the EEPROM, or else modifications will not appear
7398 + * until after the next adapter reset.
7400 + nvm->ops.reload(hw);
7408 + * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
7409 + * @hw: pointer to the HW structure
7411 + * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
7412 + * If the bit is 0, that the EEPROM had been modified, but the checksum was
7413 + * not calculated, in which case we need to calculate the checksum and set
7416 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
7418 + s32 ret_val = E1000_SUCCESS;
7421 + DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
7424 + * Read 0x19 and check bit 6. If this bit is 0, the checksum
7425 + * needs to be fixed. This bit is an indication that the NVM
7426 + * was prepared by OEM software and did not calculate the
7427 + * checksum...a likely scenario.
7429 + ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
7433 + if ((data & 0x40) == 0) {
7435 + ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
7438 + ret_val = hw->nvm.ops.update(hw);
7443 + ret_val = e1000_validate_nvm_checksum_generic(hw);
7450 + * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
7451 + * @hw: pointer to the HW structure
7453 + * To prevent malicious write/erase of the NVM, set it to be read-only
7454 + * so that the hardware ignores all write/erase cycles of the NVM via
7455 + * the flash control registers. The shadow-ram copy of the NVM will
7456 + * still be updated, however any updates to this copy will not stick
7457 + * across driver reloads.
7459 +void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
7461 + union ich8_flash_protected_range pr0;
7462 + union ich8_hws_flash_status hsfsts;
7466 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7470 + gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
7472 + /* Write-protect GbE Sector of NVM */
7473 + pr0.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_PR0);
7474 + pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
7475 + pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
7476 + pr0.range.wpe = true;
7477 + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_PR0, pr0.regval);
7480 + * Lock down a subset of GbE Flash Control Registers, e.g.
7481 + * PR0 to prevent the write-protection from being lifted.
7482 + * Once FLOCKDN is set, the registers protected by it cannot
7483 + * be written until FLOCKDN is cleared by a hardware reset.
7485 + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7486 + hsfsts.hsf_status.flockdn = true;
7487 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
7489 + e1000_release_swflag_ich8lan(hw);
7493 + * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
7494 + * @hw: pointer to the HW structure
7495 + * @offset: The offset (in bytes) of the byte/word to read.
7496 + * @size: Size of data to read, 1=byte 2=word
7497 + * @data: The byte(s) to write to the NVM.
7499 + * Writes one/two bytes to the NVM using the flash access registers.
7501 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
7502 + u8 size, u16 data)
7504 + union ich8_hws_flash_status hsfsts;
7505 + union ich8_hws_flash_ctrl hsflctl;
7506 + u32 flash_linear_addr;
7507 + u32 flash_data = 0;
7508 + s32 ret_val = -E1000_ERR_NVM;
7511 + DEBUGFUNC("e1000_write_ich8_data");
7513 + if (size < 1 || size > 2 || data > size * 0xff ||
7514 + offset > ICH_FLASH_LINEAR_ADDR_MASK)
7517 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7518 + hw->nvm.flash_base_addr;
7523 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7524 + if (ret_val != E1000_SUCCESS)
7527 + hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7528 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7529 + hsflctl.hsf_ctrl.fldbcount = size -1;
7530 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
7531 + E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7533 + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
7536 + flash_data = (u32)data & 0x00FF;
7538 + flash_data = (u32)data;
7540 + E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
7543 + * check if FCERR is set to 1 , if set to 1, clear it
7544 + * and try the whole sequence a few more times else done
7546 + ret_val = e1000_flash_cycle_ich8lan(hw,
7547 + ICH_FLASH_WRITE_COMMAND_TIMEOUT);
7548 + if (ret_val == E1000_SUCCESS) {
7552 + * If we're here, then things are most likely
7553 + * completely hosed, but if the error condition
7554 + * is detected, it won't hurt to give it another
7555 + * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
7557 + hsfsts.regval = E1000_READ_FLASH_REG16(hw,
7558 + ICH_FLASH_HSFSTS);
7559 + if (hsfsts.hsf_status.flcerr == 1) {
7560 + /* Repeat for some time before giving up. */
7562 + } else if (hsfsts.hsf_status.flcdone == 0) {
7563 + DEBUGOUT("Timeout error - flash cycle "
7564 + "did not complete.");
7568 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7575 + * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
7576 + * @hw: pointer to the HW structure
7577 + * @offset: The index of the byte to read.
7578 + * @data: The byte to write to the NVM.
7580 + * Writes a single byte to the NVM using the flash access registers.
7582 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
7585 + u16 word = (u16)data;
7587 + DEBUGFUNC("e1000_write_flash_byte_ich8lan");
7589 + return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
7593 + * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
7594 + * @hw: pointer to the HW structure
7595 + * @offset: The offset of the byte to write.
7596 + * @byte: The byte to write to the NVM.
7598 + * Writes a single byte to the NVM using the flash access registers.
7599 + * Goes through a retry algorithm before giving up.
7601 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
7602 + u32 offset, u8 byte)
7605 + u16 program_retries;
7607 + DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
7609 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7610 + if (ret_val == E1000_SUCCESS)
7613 + for (program_retries = 0; program_retries < 100; program_retries++) {
7614 + DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
7616 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7617 + if (ret_val == E1000_SUCCESS)
7620 + if (program_retries == 100) {
7621 + ret_val = -E1000_ERR_NVM;
7630 + * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
7631 + * @hw: pointer to the HW structure
7632 + * @bank: 0 for first bank, 1 for second bank, etc.
7634 + * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
7635 + * bank N is 4096 * N + flash_reg_addr.
7637 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
7639 + struct e1000_nvm_info *nvm = &hw->nvm;
7640 + union ich8_hws_flash_status hsfsts;
7641 + union ich8_hws_flash_ctrl hsflctl;
7642 + u32 flash_linear_addr;
7643 + /* bank size is in 16bit words - adjust to bytes */
7644 + u32 flash_bank_size = nvm->flash_bank_size * 2;
7645 + s32 ret_val = E1000_SUCCESS;
7647 + s32 j, iteration, sector_size;
7649 + DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
7651 + hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7654 + * Determine HW Sector size: Read BERASE bits of hw flash status
7656 + * 00: The Hw sector is 256 bytes, hence we need to erase 16
7657 + * consecutive sectors. The start index for the nth Hw sector
7658 + * can be calculated as = bank * 4096 + n * 256
7659 + * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
7660 + * The start index for the nth Hw sector can be calculated
7661 + * as = bank * 4096
7662 + * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
7663 + * (ich9 only, otherwise error condition)
7664 + * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
7666 + switch (hsfsts.hsf_status.berasesz) {
7668 + /* Hw sector size 256 */
7669 + sector_size = ICH_FLASH_SEG_SIZE_256;
7670 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
7673 + sector_size = ICH_FLASH_SEG_SIZE_4K;
7674 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
7677 + if (hw->mac.type == e1000_ich9lan) {
7678 + sector_size = ICH_FLASH_SEG_SIZE_8K;
7679 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
7681 + ret_val = -E1000_ERR_NVM;
7686 + sector_size = ICH_FLASH_SEG_SIZE_64K;
7687 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
7690 + ret_val = -E1000_ERR_NVM;
7694 + /* Start with the base address, then add the sector offset. */
7695 + flash_linear_addr = hw->nvm.flash_base_addr;
7696 + flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
7698 + for (j = 0; j < iteration ; j++) {
7701 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7706 + * Write a value 11 (block Erase) in Flash
7707 + * Cycle field in hw flash control
7709 + hsflctl.regval = E1000_READ_FLASH_REG16(hw,
7710 + ICH_FLASH_HSFCTL);
7711 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
7712 + E1000_WRITE_FLASH_REG16(hw,
7717 + * Write the last 24 bits of an index within the
7718 + * block into Flash Linear address field in Flash
7721 + flash_linear_addr += (j * sector_size);
7722 + E1000_WRITE_FLASH_REG(hw,
7724 + flash_linear_addr);
7726 + ret_val = e1000_flash_cycle_ich8lan(hw,
7727 + ICH_FLASH_ERASE_COMMAND_TIMEOUT);
7728 + if (ret_val == E1000_SUCCESS) {
7732 + * Check if FCERR is set to 1. If 1,
7733 + * clear it and try the whole sequence
7734 + * a few more times else Done
7736 + hsfsts.regval = E1000_READ_FLASH_REG16(hw,
7737 + ICH_FLASH_HSFSTS);
7738 + if (hsfsts.hsf_status.flcerr == 1) {
7740 + * repeat for some time before
7744 + } else if (hsfsts.hsf_status.flcdone == 0)
7747 + } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
7755 + * e1000_valid_led_default_ich8lan - Set the default LED settings
7756 + * @hw: pointer to the HW structure
7757 + * @data: Pointer to the LED settings
7759 + * Reads the LED default settings from the NVM to data. If the NVM LED
7760 + * settings is all 0's or F's, set the LED default to a valid LED default
7763 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
7767 + DEBUGFUNC("e1000_valid_led_default_ich8lan");
7769 + ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
7771 + DEBUGOUT("NVM Read Error\n");
7775 + if (*data == ID_LED_RESERVED_0000 ||
7776 + *data == ID_LED_RESERVED_FFFF)
7777 + *data = ID_LED_DEFAULT_ICH8LAN;
7784 + * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
7785 + * @hw: pointer to the HW structure
7787 + * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
7788 + * register, so the the bus width is hard coded.
7790 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
7792 + struct e1000_bus_info *bus = &hw->bus;
7795 + DEBUGFUNC("e1000_get_bus_info_ich8lan");
7797 + ret_val = e1000_get_bus_info_pcie_generic(hw);
7800 + * ICH devices are "PCI Express"-ish. They have
7801 + * a configuration space, but do not contain
7802 + * PCI Express Capability registers, so bus width
7803 + * must be hardcoded.
7805 + if (bus->width == e1000_bus_width_unknown)
7806 + bus->width = e1000_bus_width_pcie_x1;
7812 + * e1000_reset_hw_ich8lan - Reset the hardware
7813 + * @hw: pointer to the HW structure
7815 + * Does a full reset of the hardware which includes a reset of the PHY and
7818 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
7820 + u32 ctrl, icr, kab;
7823 + DEBUGFUNC("e1000_reset_hw_ich8lan");
7826 + * Prevent the PCI-E bus from sticking if there is no TLP connection
7827 + * on the last TLP read/write transaction when MAC is reset.
7829 + ret_val = e1000_disable_pcie_master_generic(hw);
7831 + DEBUGOUT("PCI-E Master disable polling has failed.\n");
7834 + DEBUGOUT("Masking off all interrupts\n");
7835 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
7838 + * Disable the Transmit and Receive units. Then delay to allow
7839 + * any pending transactions to complete before we hit the MAC
7840 + * with the global reset.
7842 + E1000_WRITE_REG(hw, E1000_RCTL, 0);
7843 + E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
7844 + E1000_WRITE_FLUSH(hw);
7848 + /* Workaround for ICH8 bit corruption issue in FIFO memory */
7849 + if (hw->mac.type == e1000_ich8lan) {
7850 + /* Set Tx and Rx buffer allocation to 8k apiece. */
7851 + E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
7852 + /* Set Packet Buffer Size to 16k. */
7853 + E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
7856 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
7858 + if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
7860 + * PHY HW reset requires MAC CORE reset at the same
7861 + * time to make sure the interface between MAC and the
7862 + * external PHY is reset.
7864 + ctrl |= E1000_CTRL_PHY_RST;
7866 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7867 + DEBUGOUT("Issuing a global reset to ich8lan");
7868 + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
7871 + ret_val = e1000_get_auto_rd_done_generic(hw);
7874 + * When auto config read does not complete, do not
7875 + * return with an error. This can happen in situations
7876 + * where there is no eeprom and prevents getting link.
7878 + DEBUGOUT("Auto Read Done did not complete\n");
7881 + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
7882 + icr = E1000_READ_REG(hw, E1000_ICR);
7884 + kab = E1000_READ_REG(hw, E1000_KABGTXD);
7885 + kab |= E1000_KABGTXD_BGSQLBIAS;
7886 + E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
7892 + * e1000_init_hw_ich8lan - Initialize the hardware
7893 + * @hw: pointer to the HW structure
7895 + * Prepares the hardware for transmit and receive by doing the following:
7896 + * - initialize hardware bits
7897 + * - initialize LED identification
7898 + * - setup receive address registers
7899 + * - setup flow control
7900 + * - setup transmit descriptors
7901 + * - clear statistics
7903 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
7905 + struct e1000_mac_info *mac = &hw->mac;
7906 + u32 ctrl_ext, txdctl, snoop;
7910 + DEBUGFUNC("e1000_init_hw_ich8lan");
7912 + e1000_initialize_hw_bits_ich8lan(hw);
7914 + /* Initialize identification LED */
7915 + ret_val = e1000_id_led_init_generic(hw);
7917 + DEBUGOUT("Error initializing identification LED\n");
7918 + /* This is not fatal and we should not stop init due to this */
7921 + /* Setup the receive address. */
7922 + e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
7924 + /* Zero out the Multicast HASH table */
7925 + DEBUGOUT("Zeroing the MTA\n");
7926 + for (i = 0; i < mac->mta_reg_count; i++)
7927 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
7929 + /* Setup link and flow control */
7930 + ret_val = mac->ops.setup_link(hw);
7932 + /* Set the transmit descriptor write-back policy for both queues */
7933 + txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
7934 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
7935 + E1000_TXDCTL_FULL_TX_DESC_WB;
7936 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
7937 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
7938 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
7939 + txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
7940 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
7941 + E1000_TXDCTL_FULL_TX_DESC_WB;
7942 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
7943 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
7944 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
7947 + * ICH8 has opposite polarity of no_snoop bits.
7948 + * By default, we should use snoop behavior.
7950 + if (mac->type == e1000_ich8lan)
7951 + snoop = PCIE_ICH8_SNOOP_ALL;
7953 + snoop = (u32)~(PCIE_NO_SNOOP_ALL);
7954 + e1000_set_pcie_no_snoop_generic(hw, snoop);
7956 + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
7957 + ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
7958 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
7961 + * Clear all of the statistics registers (clear on read). It is
7962 + * important that we do this after we have tried to establish link
7963 + * because the symbol error count will increment wildly if there
7966 + e1000_clear_hw_cntrs_ich8lan(hw);
7971 + * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
7972 + * @hw: pointer to the HW structure
7974 + * Sets/Clears required hardware bits necessary for correctly setting up the
7975 + * hardware for transmit and receive.
7977 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
7981 + DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
7983 + if (hw->mac.disable_hw_init_bits)
7986 + /* Extended Device Control */
7987 + reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
7989 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
7991 + /* Transmit Descriptor Control 0 */
7992 + reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
7994 + E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
7996 + /* Transmit Descriptor Control 1 */
7997 + reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
7999 + E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
8001 + /* Transmit Arbitration Control 0 */
8002 + reg = E1000_READ_REG(hw, E1000_TARC(0));
8003 + if (hw->mac.type == e1000_ich8lan)
8004 + reg |= (1 << 28) | (1 << 29);
8005 + reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
8006 + E1000_WRITE_REG(hw, E1000_TARC(0), reg);
8008 + /* Transmit Arbitration Control 1 */
8009 + reg = E1000_READ_REG(hw, E1000_TARC(1));
8010 + if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
8011 + reg &= ~(1 << 28);
8014 + reg |= (1 << 24) | (1 << 26) | (1 << 30);
8015 + E1000_WRITE_REG(hw, E1000_TARC(1), reg);
8017 + /* Device Status */
8018 + if (hw->mac.type == e1000_ich8lan) {
8019 + reg = E1000_READ_REG(hw, E1000_STATUS);
8020 + reg &= ~(1 << 31);
8021 + E1000_WRITE_REG(hw, E1000_STATUS, reg);
8029 + * e1000_setup_link_ich8lan - Setup flow control and link settings
8030 + * @hw: pointer to the HW structure
8032 + * Determines which flow control settings to use, then configures flow
8033 + * control. Calls the appropriate media-specific link configuration
8034 + * function. Assuming the adapter has a valid link partner, a valid link
8035 + * should be established. Assumes the hardware has previously been reset
8036 + * and the transmitter and receiver are not enabled.
8038 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
8040 + s32 ret_val = E1000_SUCCESS;
8042 + DEBUGFUNC("e1000_setup_link_ich8lan");
8044 + if (hw->phy.ops.check_reset_block(hw))
8048 + * ICH parts do not have a word in the NVM to determine
8049 + * the default flow control setting, so we explicitly
8052 + if (hw->fc.type == e1000_fc_default)
8053 + hw->fc.type = e1000_fc_full;
8055 + hw->fc.original_type = hw->fc.type;
8057 + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
8059 + /* Continue to configure the copper link. */
8060 + ret_val = hw->mac.ops.setup_physical_interface(hw);
8064 + E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
8066 + ret_val = e1000_set_fc_watermarks_generic(hw);
8073 + * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
8074 + * @hw: pointer to the HW structure
8076 + * Configures the kumeran interface to the PHY to wait the appropriate time
8077 + * when polling the PHY, then call the generic setup_copper_link to finish
8078 + * configuring the copper link.
8080 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
8086 + DEBUGFUNC("e1000_setup_copper_link_ich8lan");
8088 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
8089 + ctrl |= E1000_CTRL_SLU;
8090 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
8091 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
8094 + * Set the mac to wait the maximum time between each iteration
8095 + * and increase the max iterations when polling the phy;
8096 + * this fixes erroneous timeouts at 10Mbps.
8098 + ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4),
8102 + ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
8107 + ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
8112 + if (hw->phy.type == e1000_phy_igp_3) {
8113 + ret_val = e1000_copper_link_setup_igp(hw);
8116 + } else if (hw->phy.type == e1000_phy_bm) {
8117 + ret_val = e1000_copper_link_setup_m88(hw);
8122 + if (hw->phy.type == e1000_phy_ife) {
8123 + ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
8128 + reg_data &= ~IFE_PMC_AUTO_MDIX;
8130 + switch (hw->phy.mdix) {
8132 + reg_data &= ~IFE_PMC_FORCE_MDIX;
8135 + reg_data |= IFE_PMC_FORCE_MDIX;
8139 + reg_data |= IFE_PMC_AUTO_MDIX;
8142 + ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
8147 + ret_val = e1000_setup_copper_link_generic(hw);
8154 + * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
8155 + * @hw: pointer to the HW structure
8156 + * @speed: pointer to store current link speed
8157 + * @duplex: pointer to store the current link duplex
8159 + * Calls the generic get_speed_and_duplex to retrieve the current link
8160 + * information and then calls the Kumeran lock loss workaround for links at
8163 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
8168 + DEBUGFUNC("e1000_get_link_up_info_ich8lan");
8170 + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
8174 + if ((hw->mac.type == e1000_ich8lan) &&
8175 + (hw->phy.type == e1000_phy_igp_3) &&
8176 + (*speed == SPEED_1000)) {
8177 + ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
8185 + * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
8186 + * @hw: pointer to the HW structure
8188 + * Work-around for 82566 Kumeran PCS lock loss:
8189 + * On link status change (i.e. PCI reset, speed change) and link is up and
8190 + * speed is gigabit-
8191 + * 0) if workaround is optionally disabled do nothing
8192 + * 1) wait 1ms for Kumeran link to come up
8193 + * 2) check Kumeran Diagnostic register PCS lock loss bit
8194 + * 3) if not set the link is locked (all is good), otherwise...
8195 + * 4) reset the PHY
8196 + * 5) repeat up to 10 times
8197 + * Note: this is only called for IGP3 copper when speed is 1gb.
8199 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
8201 + struct e1000_dev_spec_ich8lan *dev_spec;
8203 + s32 ret_val = E1000_SUCCESS;
8207 + DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
8209 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
8212 + DEBUGOUT("dev_spec pointer is set to NULL.\n");
8213 + ret_val = -E1000_ERR_CONFIG;
8217 + if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
8221 + * Make sure link is up before proceeding. If not just return.
8222 + * Attempting this while link is negotiating fouled up link
8225 + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
8227 + ret_val = E1000_SUCCESS;
8231 + for (i = 0; i < 10; i++) {
8232 + /* read once to clear */
8233 + ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
8236 + /* and again to get new status */
8237 + ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
8241 + /* check for PCS lock */
8242 + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
8243 + ret_val = E1000_SUCCESS;
8247 + /* Issue PHY reset */
8248 + hw->phy.ops.reset(hw);
8249 + msec_delay_irq(5);
8251 + /* Disable GigE link negotiation */
8252 + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
8253 + phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
8254 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8255 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
8258 + * Call gig speed drop workaround on Gig disable before accessing
8259 + * any PHY registers
8261 + e1000_gig_downshift_workaround_ich8lan(hw);
8263 + /* unable to acquire PCS lock */
8264 + ret_val = -E1000_ERR_PHY;
8271 + * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
8272 + * @hw: pointer to the HW structure
8273 + * @state: boolean value used to set the current Kumeran workaround state
8275 + * If ICH8, set the current Kumeran workaround state (enabled - true
8276 + * /disabled - false).
8278 +void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
8281 + struct e1000_dev_spec_ich8lan *dev_spec;
8283 + DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
8285 + if (hw->mac.type != e1000_ich8lan) {
8286 + DEBUGOUT("Workaround applies to ICH8 only.\n");
8290 + dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
8293 + DEBUGOUT("dev_spec pointer is set to NULL.\n");
8297 + dev_spec->kmrn_lock_loss_workaround_enabled = state;
8304 + * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
8305 + * @hw: pointer to the HW structure
8307 + * Workaround for 82566 power-down on D3 entry:
8308 + * 1) disable gigabit link
8309 + * 2) write VR power-down enable
8311 + * Continue if successful, else issue LCD reset and repeat
8313 +void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
8319 + DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
8321 + if (hw->phy.type != e1000_phy_igp_3)
8324 + /* Try the workaround twice (if needed) */
8326 + /* Disable link */
8327 + reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
8328 + reg |= (E1000_PHY_CTRL_GBE_DISABLE |
8329 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8330 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
8333 + * Call gig speed drop workaround on Gig disable before
8334 + * accessing any PHY registers
8336 + if (hw->mac.type == e1000_ich8lan)
8337 + e1000_gig_downshift_workaround_ich8lan(hw);
8339 + /* Write VR power-down enable */
8340 + hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
8341 + data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8342 + hw->phy.ops.write_reg(hw,
8344 + data | IGP3_VR_CTRL_MODE_SHUTDOWN);
8346 + /* Read it back and test */
8347 + hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
8348 + data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8349 + if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
8352 + /* Issue PHY reset and repeat at most one more time */
8353 + reg = E1000_READ_REG(hw, E1000_CTRL);
8354 + E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
8363 + * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
8364 + * @hw: pointer to the HW structure
8366 + * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
8367 + * LPLU, Gig disable, MDIC PHY reset):
8368 + * 1) Set Kumeran Near-end loopback
8369 + * 2) Clear Kumeran Near-end loopback
8370 + * Should only be called for ICH8[m] devices with IGP_3 Phy.
8372 +void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
8374 + s32 ret_val = E1000_SUCCESS;
8377 + DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
8379 + if ((hw->mac.type != e1000_ich8lan) ||
8380 + (hw->phy.type != e1000_phy_igp_3))
8383 + ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
8387 + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
8388 + ret_val = e1000_write_kmrn_reg_generic(hw,
8389 + E1000_KMRNCTRLSTA_DIAG_OFFSET,
8393 + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
8394 + ret_val = e1000_write_kmrn_reg_generic(hw,
8395 + E1000_KMRNCTRLSTA_DIAG_OFFSET,
8402 + * e1000_disable_gig_wol_ich8lan - disable gig during WoL
8403 + * @hw: pointer to the HW structure
8405 + * During S0 to Sx transition, it is possible the link remains at gig
8406 + * instead of negotiating to a lower speed. Before going to Sx, set
8407 + * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
8408 + * to a lower speed.
8410 + * Should only be called for ICH9 and ICH10 devices.
8412 +void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
8416 + if ((hw->mac.type == e1000_ich10lan) ||
8417 + (hw->mac.type == e1000_ich9lan)) {
8418 + phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
8419 + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
8420 + E1000_PHY_CTRL_GBE_DISABLE;
8421 + E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
8428 + * e1000_cleanup_led_ich8lan - Restore the default LED operation
8429 + * @hw: pointer to the HW structure
8431 + * Return the LED back to the default configuration.
8433 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
8435 + s32 ret_val = E1000_SUCCESS;
8437 + DEBUGFUNC("e1000_cleanup_led_ich8lan");
8439 + if (hw->phy.type == e1000_phy_ife)
8440 + ret_val = hw->phy.ops.write_reg(hw,
8441 + IFE_PHY_SPECIAL_CONTROL_LED,
8444 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
8450 + * e1000_led_on_ich8lan - Turn LEDs on
8451 + * @hw: pointer to the HW structure
8453 + * Turn on the LEDs.
8455 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
8457 + s32 ret_val = E1000_SUCCESS;
8459 + DEBUGFUNC("e1000_led_on_ich8lan");
8461 + if (hw->phy.type == e1000_phy_ife)
8462 + ret_val = hw->phy.ops.write_reg(hw,
8463 + IFE_PHY_SPECIAL_CONTROL_LED,
8464 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
8466 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
8472 + * e1000_led_off_ich8lan - Turn LEDs off
8473 + * @hw: pointer to the HW structure
8475 + * Turn off the LEDs.
8477 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
8479 + s32 ret_val = E1000_SUCCESS;
8481 + DEBUGFUNC("e1000_led_off_ich8lan");
8483 + if (hw->phy.type == e1000_phy_ife)
8484 + ret_val = hw->phy.ops.write_reg(hw,
8485 + IFE_PHY_SPECIAL_CONTROL_LED,
8486 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
8488 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
8494 + * e1000_get_cfg_done_ich8lan - Read config done bit
8495 + * @hw: pointer to the HW structure
8497 + * Read the management control register for the config done bit for
8498 + * completion status. NOTE: silicon which is EEPROM-less will fail trying
8499 + * to read the config done bit, so an error is *ONLY* logged and returns
8500 + * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
8501 + * would not be able to be reset or change link.
8503 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
8505 + s32 ret_val = E1000_SUCCESS;
8508 + e1000_get_cfg_done_generic(hw);
8510 + /* If EEPROM is not marked present, init the IGP 3 PHY manually */
8511 + if (hw->mac.type != e1000_ich10lan) {
8512 + if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
8513 + (hw->phy.type == e1000_phy_igp_3)) {
8514 + e1000_phy_init_script_igp3(hw);
8517 + if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
8518 + /* Maybe we should do a basic Boazman config */
8519 + DEBUGOUT("EEPROM not present\n");
8520 + ret_val = -E1000_ERR_CONFIG;
8528 + * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
8529 + * @hw: pointer to the HW structure
8531 + * In the case of a PHY power down to save power, or to turn off link during a
8532 + * driver unload, or wake on lan is not enabled, remove the link.
8534 +static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
8536 + struct e1000_phy_info *phy = &hw->phy;
8537 + struct e1000_mac_info *mac = &hw->mac;
8539 + /* If the management interface is not enabled, then power down */
8540 + if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
8541 + e1000_power_down_phy_copper(hw);
8547 + * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
8548 + * @hw: pointer to the HW structure
8550 + * Clears hardware counters specific to the silicon family and calls
8551 + * clear_hw_cntrs_generic to clear all general purpose counters.
8553 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
8555 + volatile u32 temp;
8557 + DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
8559 + e1000_clear_hw_cntrs_base_generic(hw);
8561 + temp = E1000_READ_REG(hw, E1000_ALGNERRC);
8562 + temp = E1000_READ_REG(hw, E1000_RXERRC);
8563 + temp = E1000_READ_REG(hw, E1000_TNCRS);
8564 + temp = E1000_READ_REG(hw, E1000_CEXTERR);
8565 + temp = E1000_READ_REG(hw, E1000_TSCTC);
8566 + temp = E1000_READ_REG(hw, E1000_TSCTFC);
8568 + temp = E1000_READ_REG(hw, E1000_MGTPRC);
8569 + temp = E1000_READ_REG(hw, E1000_MGTPDC);
8570 + temp = E1000_READ_REG(hw, E1000_MGTPTC);
8572 + temp = E1000_READ_REG(hw, E1000_IAC);
8573 + temp = E1000_READ_REG(hw, E1000_ICRXOC);
8576 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.h linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.h
8577 --- linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.h 1970-01-01 01:00:00.000000000 +0100
8578 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.h 2008-10-14 01:51:32.000000000 +0200
8580 +/*******************************************************************************
8582 + Intel PRO/1000 Linux driver
8583 + Copyright(c) 1999 - 2008 Intel Corporation.
8585 + This program is free software; you can redistribute it and/or modify it
8586 + under the terms and conditions of the GNU General Public License,
8587 + version 2, as published by the Free Software Foundation.
8589 + This program is distributed in the hope it will be useful, but WITHOUT
8590 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8591 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8594 + You should have received a copy of the GNU General Public License along with
8595 + this program; if not, write to the Free Software Foundation, Inc.,
8596 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8598 + The full GNU General Public License is included in this distribution in
8599 + the file called "COPYING".
8601 + Contact Information:
8602 + Linux NICS <linux.nics@intel.com>
8603 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
8604 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
8606 +*******************************************************************************/
8608 +#ifndef _E1000_ICH8LAN_H_
8609 +#define _E1000_ICH8LAN_H_
8611 +#define ICH_FLASH_GFPREG 0x0000
8612 +#define ICH_FLASH_HSFSTS 0x0004
8613 +#define ICH_FLASH_HSFCTL 0x0006
8614 +#define ICH_FLASH_FADDR 0x0008
8615 +#define ICH_FLASH_FDATA0 0x0010
8616 +#define ICH_FLASH_PR0 0x0074
8618 +#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
8619 +#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
8620 +#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
8621 +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
8622 +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
8624 +#define ICH_CYCLE_READ 0
8625 +#define ICH_CYCLE_WRITE 2
8626 +#define ICH_CYCLE_ERASE 3
8628 +#define FLASH_GFPREG_BASE_MASK 0x1FFF
8629 +#define FLASH_SECTOR_ADDR_SHIFT 12
8631 +#define E1000_SHADOW_RAM_WORDS 2048
8633 +#define ICH_FLASH_SEG_SIZE_256 256
8634 +#define ICH_FLASH_SEG_SIZE_4K 4096
8635 +#define ICH_FLASH_SEG_SIZE_8K 8192
8636 +#define ICH_FLASH_SEG_SIZE_64K 65536
8637 +#define ICH_FLASH_SECTOR_SIZE 4096
8639 +#define ICH_FLASH_REG_MAPSIZE 0x00A0
8641 +#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
8642 +#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
8643 +/* FW established a valid mode */
8644 +#define E1000_ICH_FWSM_FW_VALID 0x00008000
8646 +#define E1000_ICH_MNG_IAMT_MODE 0x2
8648 +#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
8649 + (ID_LED_DEF1_OFF2 << 8) | \
8650 + (ID_LED_DEF1_ON2 << 4) | \
8651 + (ID_LED_DEF1_DEF2))
8653 +#define E1000_ICH_NVM_SIG_WORD 0x13
8654 +#define E1000_ICH_NVM_SIG_MASK 0xC000
8656 +#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
8658 +#define E1000_FEXTNVM_SW_CONFIG 1
8659 +#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
8661 +#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
8663 +#define E1000_ICH_RAR_ENTRIES 7
8665 +#define PHY_PAGE_SHIFT 5
8666 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
8667 + ((reg) & MAX_PHY_REG_ADDRESS))
8668 +#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
8669 +#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
8670 +#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
8671 +#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
8673 +#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
8674 +#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
8675 +#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
8676 +#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
8679 + * Additional interrupts need to be handled for ICH family:
8680 + * DSW = The FW changed the status of the DISSW bit in FWSM
8681 + * PHYINT = The LAN connected device generates an interrupt
8682 + * EPRST = Manageability reset event
8684 +#define IMS_ICH_ENABLE_MASK (\
8686 + E1000_IMS_PHYINT | \
8689 +/* Additional interrupt register bit definitions */
8690 +#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
8691 +#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
8692 +#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
8694 +/* Security Processing bit Indication */
8695 +#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
8696 +#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
8697 +#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
8698 +#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
8699 +#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
8702 +/* ICH Flash Protected Region */
8703 +union ich8_flash_protected_range {
8705 + u32 base:13; /* 0:12 Protected Range Base */
8706 + u32 reserved1:2; /* 13:14 Reserved */
8707 + u32 rpe:1; /* 15 Read Protection Enable */
8708 + u32 limit:13; /* 16:28 Protected Range Limit */
8709 + u32 reserved2:2; /* 29:30 Reserved */
8710 + u32 wpe:1; /* 31 Write Protection Enable */
8715 +void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
8717 +void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
8719 +void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
8720 +void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
8721 +void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
8724 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c
8725 --- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c 1970-01-01 01:00:00.000000000 +0100
8726 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c 2008-10-14 01:51:32.000000000 +0200
8728 +/*******************************************************************************
8730 + Intel PRO/1000 Linux driver
8731 + Copyright(c) 1999 - 2008 Intel Corporation.
8733 + This program is free software; you can redistribute it and/or modify it
8734 + under the terms and conditions of the GNU General Public License,
8735 + version 2, as published by the Free Software Foundation.
8737 + This program is distributed in the hope it will be useful, but WITHOUT
8738 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8739 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8742 + You should have received a copy of the GNU General Public License along with
8743 + this program; if not, write to the Free Software Foundation, Inc.,
8744 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8746 + The full GNU General Public License is included in this distribution in
8747 + the file called "COPYING".
8749 + Contact Information:
8750 + Linux NICS <linux.nics@intel.com>
8751 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
8752 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
8754 +*******************************************************************************/
8756 +#include "e1000_hw.h"
8759 + * e1000_init_mac_ops_generic - Initialize MAC function pointers
8760 + * @hw: pointer to the HW structure
8762 + * Setups up the function pointers to no-op functions
8764 +void e1000_init_mac_ops_generic(struct e1000_hw *hw)
8766 + struct e1000_mac_info *mac = &hw->mac;
8767 + DEBUGFUNC("e1000_init_mac_ops_generic");
8769 + /* General Setup */
8770 + mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
8771 + mac->ops.remove_device = e1000_remove_device_generic;
8772 + mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
8774 + mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
8776 + mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
8777 + mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
8778 + mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
8779 + /* VLAN, MC, etc. */
8780 + mac->ops.rar_set = e1000_rar_set_generic;
8781 + mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
8785 + * e1000_remove_device_generic - Free device specific structure
8786 + * @hw: pointer to the HW structure
8788 + * If a device specific structure was allocated, this function will
8791 +void e1000_remove_device_generic(struct e1000_hw *hw)
8793 + DEBUGFUNC("e1000_remove_device_generic");
8795 + /* Freeing the dev_spec member of e1000_hw structure */
8796 + e1000_free_dev_spec_struct(hw);
8800 + * e1000_get_bus_info_pcie_generic - Get PCIe bus information
8801 + * @hw: pointer to the HW structure
8803 + * Determines and stores the system bus information for a particular
8804 + * network interface. The following bus information is determined and stored:
8805 + * bus speed, bus width, type (PCIe), and PCIe function.
8807 +s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
8809 + struct e1000_bus_info *bus = &hw->bus;
8812 + u16 pcie_link_status, pci_header_type;
8814 + DEBUGFUNC("e1000_get_bus_info_pcie_generic");
8816 + bus->type = e1000_bus_type_pci_express;
8817 + bus->speed = e1000_bus_speed_2500;
8819 + ret_val = e1000_read_pcie_cap_reg(hw,
8821 + &pcie_link_status);
8823 + bus->width = e1000_bus_width_unknown;
8825 + bus->width = (e1000_bus_width)((pcie_link_status &
8826 + PCIE_LINK_WIDTH_MASK) >>
8827 + PCIE_LINK_WIDTH_SHIFT);
8829 + e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
8830 + if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
8831 + status = E1000_READ_REG(hw, E1000_STATUS);
8832 + bus->func = (status & E1000_STATUS_FUNC_MASK)
8833 + >> E1000_STATUS_FUNC_SHIFT;
8838 + return E1000_SUCCESS;
8842 + * e1000_clear_vfta_generic - Clear VLAN filter table
8843 + * @hw: pointer to the HW structure
8845 + * Clears the register array which contains the VLAN filter table by
8846 + * setting all the values to 0.
8848 +void e1000_clear_vfta_generic(struct e1000_hw *hw)
8852 + DEBUGFUNC("e1000_clear_vfta_generic");
8854 + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
8855 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
8856 + E1000_WRITE_FLUSH(hw);
8861 + * e1000_write_vfta_generic - Write value to VLAN filter table
8862 + * @hw: pointer to the HW structure
8863 + * @offset: register offset in VLAN filter table
8864 + * @value: register value written to VLAN filter table
8866 + * Writes value at the given offset in the register array which stores
8867 + * the VLAN filter table.
8869 +void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
8871 + DEBUGFUNC("e1000_write_vfta_generic");
8873 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
8874 + E1000_WRITE_FLUSH(hw);
8878 + * e1000_init_rx_addrs_generic - Initialize receive address's
8879 + * @hw: pointer to the HW structure
8880 + * @rar_count: receive address registers
8882 + * Setups the receive address registers by setting the base receive address
8883 + * register to the devices MAC address and clearing all the other receive
8884 + * address registers to 0.
8886 +void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
8890 + DEBUGFUNC("e1000_init_rx_addrs_generic");
8892 + /* Setup the receive address */
8893 + DEBUGOUT("Programming MAC Address into RAR[0]\n");
8895 + hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
8897 + /* Zero out the other (rar_entry_count - 1) receive addresses */
8898 + DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
8899 + for (i = 1; i < rar_count; i++) {
8900 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
8901 + E1000_WRITE_FLUSH(hw);
8902 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
8903 + E1000_WRITE_FLUSH(hw);
8908 + * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
8909 + * @hw: pointer to the HW structure
8911 + * Checks the nvm for an alternate MAC address. An alternate MAC address
8912 + * can be setup by pre-boot software and must be treated like a permanent
8913 + * address and must override the actual permanent MAC address. If an
8914 + * alternate MAC address is found it is saved in the hw struct and
8915 + * programmed into RAR0 and the function returns success, otherwise the
8916 + * function returns an error.
8918 +s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
8921 + s32 ret_val = E1000_SUCCESS;
8922 + u16 offset, nvm_alt_mac_addr_offset, nvm_data;
8923 + u8 alt_mac_addr[ETH_ADDR_LEN];
8925 + DEBUGFUNC("e1000_check_alt_mac_addr_generic");
8927 + ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
8928 + &nvm_alt_mac_addr_offset);
8930 + DEBUGOUT("NVM Read Error\n");
8934 + if (nvm_alt_mac_addr_offset == 0xFFFF) {
8935 + ret_val = -(E1000_NOT_IMPLEMENTED);
8939 + if (hw->bus.func == E1000_FUNC_1)
8940 + nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16);
8942 + for (i = 0; i < ETH_ADDR_LEN; i += 2) {
8943 + offset = nvm_alt_mac_addr_offset + (i >> 1);
8944 + ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
8946 + DEBUGOUT("NVM Read Error\n");
8950 + alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
8951 + alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
8954 + /* if multicast bit is set, the alternate address will not be used */
8955 + if (alt_mac_addr[0] & 0x01) {
8956 + ret_val = -(E1000_NOT_IMPLEMENTED);
8960 + for (i = 0; i < ETH_ADDR_LEN; i++)
8961 + hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
8963 + hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0);
8970 + * e1000_rar_set_generic - Set receive address register
8971 + * @hw: pointer to the HW structure
8972 + * @addr: pointer to the receive address
8973 + * @index: receive address array register
8975 + * Sets the receive address array register at index to the address passed
8978 +void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
8980 + u32 rar_low, rar_high;
8982 + DEBUGFUNC("e1000_rar_set_generic");
8985 + * HW expects these in little endian so we reverse the byte order
8986 + * from network order (big endian) to little endian
8988 + rar_low = ((u32) addr[0] |
8989 + ((u32) addr[1] << 8) |
8990 + ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
8992 + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
8994 + /* If MAC address zero, no need to set the AV bit */
8995 + if (rar_low || rar_high) {
8996 + if (!hw->mac.disable_av)
8997 + rar_high |= E1000_RAH_AV;
9000 + E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
9001 + E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
9005 + * e1000_mta_set_generic - Set multicast filter table address
9006 + * @hw: pointer to the HW structure
9007 + * @hash_value: determines the MTA register and bit to set
9009 + * The multicast table address is a register array of 32-bit registers.
9010 + * The hash_value is used to determine what register the bit is in, the
9011 + * current value is read, the new bit is OR'd in and the new value is
9012 + * written back into the register.
9014 +void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
9016 + u32 hash_bit, hash_reg, mta;
9018 + DEBUGFUNC("e1000_mta_set_generic");
9020 + * The MTA is a register array of 32-bit registers. It is
9021 + * treated like an array of (32*mta_reg_count) bits. We want to
9022 + * set bit BitArray[hash_value]. So we figure out what register
9023 + * the bit is in, read it, OR in the new bit, then write
9024 + * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
9025 + * mask to bits 31:5 of the hash value which gives us the
9026 + * register we're modifying. The hash bit within that register
9027 + * is determined by the lower 5 bits of the hash value.
9029 + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
9030 + hash_bit = hash_value & 0x1F;
9032 + mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
9034 + mta |= (1 << hash_bit);
9036 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
9037 + E1000_WRITE_FLUSH(hw);
9041 + * e1000_update_mc_addr_list_generic - Update Multicast addresses
9042 + * @hw: pointer to the HW structure
9043 + * @mc_addr_list: array of multicast addresses to program
9044 + * @mc_addr_count: number of multicast addresses to program
9045 + * @rar_used_count: the first RAR register free to program
9046 + * @rar_count: total number of supported Receive Address Registers
9048 + * Updates the Receive Address Registers and Multicast Table Array.
9049 + * The caller must have a packed mc_addr_list of multicast addresses.
9050 + * The parameter rar_count will usually be hw->mac.rar_entry_count
9051 + * unless there are workarounds that change this.
9053 +void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
9054 + u8 *mc_addr_list, u32 mc_addr_count,
9055 + u32 rar_used_count, u32 rar_count)
9060 + DEBUGFUNC("e1000_update_mc_addr_list_generic");
9063 + * Load the first set of multicast addresses into the exact
9064 + * filters (RAR). If there are not enough to fill the RAR
9065 + * array, clear the filters.
9067 + for (i = rar_used_count; i < rar_count; i++) {
9068 + if (mc_addr_count) {
9069 + hw->mac.ops.rar_set(hw, mc_addr_list, i);
9071 + mc_addr_list += ETH_ADDR_LEN;
9073 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
9074 + E1000_WRITE_FLUSH(hw);
9075 + E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
9076 + E1000_WRITE_FLUSH(hw);
9080 + /* Clear the old settings from the MTA */
9081 + DEBUGOUT("Clearing MTA\n");
9082 + for (i = 0; i < hw->mac.mta_reg_count; i++) {
9083 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
9084 + E1000_WRITE_FLUSH(hw);
9087 + /* Load any remaining multicast addresses into the hash table. */
9088 + for (; mc_addr_count > 0; mc_addr_count--) {
9089 + hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
9090 + DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
9091 + hw->mac.ops.mta_set(hw, hash_value);
9092 + mc_addr_list += ETH_ADDR_LEN;
9097 + * e1000_hash_mc_addr_generic - Generate a multicast hash value
9098 + * @hw: pointer to the HW structure
9099 + * @mc_addr: pointer to a multicast address
9101 + * Generates a multicast address hash value which is used to determine
9102 + * the multicast filter table array address and new table value. See
9103 + * e1000_mta_set_generic()
9105 +u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
9107 + u32 hash_value, hash_mask;
9110 + DEBUGFUNC("e1000_hash_mc_addr_generic");
9112 + /* Register count multiplied by bits per register */
9113 + hash_mask = (hw->mac.mta_reg_count * 32) - 1;
9116 + * For a mc_filter_type of 0, bit_shift is the number of left-shifts
9117 + * where 0xFF would still fall within the hash mask.
9119 + while (hash_mask >> bit_shift != 0xFF)
9123 + * The portion of the address that is used for the hash table
9124 + * is determined by the mc_filter_type setting.
9125 + * The algorithm is such that there is a total of 8 bits of shifting.
9126 + * The bit_shift for a mc_filter_type of 0 represents the number of
9127 + * left-shifts where the MSB of mc_addr[5] would still fall within
9128 + * the hash_mask. Case 0 does this exactly. Since there are a total
9129 + * of 8 bits of shifting, then mc_addr[4] will shift right the
9130 + * remaining number of bits. Thus 8 - bit_shift. The rest of the
9131 + * cases are a variation of this algorithm...essentially raising the
9132 + * number of bits to shift mc_addr[5] left, while still keeping the
9133 + * 8-bit shifting total.
9135 + * For example, given the following Destination MAC Address and an
9136 + * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
9137 + * we can see that the bit_shift for case 0 is 4. These are the hash
9138 + * values resulting from each mc_filter_type...
9139 + * [0] [1] [2] [3] [4] [5]
9140 + * 01 AA 00 12 34 56
9143 + * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
9144 + * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
9145 + * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
9146 + * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
9148 + switch (hw->mac.mc_filter_type) {
9163 + hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
9164 + (((u16) mc_addr[5]) << bit_shift)));
9166 + return hash_value;
9170 + * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
9171 + * @hw: pointer to the HW structure
9173 + * Clears the base hardware counters by reading the counter registers.
9175 +void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
9177 + volatile u32 temp;
9179 + DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
9181 + temp = E1000_READ_REG(hw, E1000_CRCERRS);
9182 + temp = E1000_READ_REG(hw, E1000_SYMERRS);
9183 + temp = E1000_READ_REG(hw, E1000_MPC);
9184 + temp = E1000_READ_REG(hw, E1000_SCC);
9185 + temp = E1000_READ_REG(hw, E1000_ECOL);
9186 + temp = E1000_READ_REG(hw, E1000_MCC);
9187 + temp = E1000_READ_REG(hw, E1000_LATECOL);
9188 + temp = E1000_READ_REG(hw, E1000_COLC);
9189 + temp = E1000_READ_REG(hw, E1000_DC);
9190 + temp = E1000_READ_REG(hw, E1000_SEC);
9191 + temp = E1000_READ_REG(hw, E1000_RLEC);
9192 + temp = E1000_READ_REG(hw, E1000_XONRXC);
9193 + temp = E1000_READ_REG(hw, E1000_XONTXC);
9194 + temp = E1000_READ_REG(hw, E1000_XOFFRXC);
9195 + temp = E1000_READ_REG(hw, E1000_XOFFTXC);
9196 + temp = E1000_READ_REG(hw, E1000_FCRUC);
9197 + temp = E1000_READ_REG(hw, E1000_GPRC);
9198 + temp = E1000_READ_REG(hw, E1000_BPRC);
9199 + temp = E1000_READ_REG(hw, E1000_MPRC);
9200 + temp = E1000_READ_REG(hw, E1000_GPTC);
9201 + temp = E1000_READ_REG(hw, E1000_GORCL);
9202 + temp = E1000_READ_REG(hw, E1000_GORCH);
9203 + temp = E1000_READ_REG(hw, E1000_GOTCL);
9204 + temp = E1000_READ_REG(hw, E1000_GOTCH);
9205 + temp = E1000_READ_REG(hw, E1000_RNBC);
9206 + temp = E1000_READ_REG(hw, E1000_RUC);
9207 + temp = E1000_READ_REG(hw, E1000_RFC);
9208 + temp = E1000_READ_REG(hw, E1000_ROC);
9209 + temp = E1000_READ_REG(hw, E1000_RJC);
9210 + temp = E1000_READ_REG(hw, E1000_TORL);
9211 + temp = E1000_READ_REG(hw, E1000_TORH);
9212 + temp = E1000_READ_REG(hw, E1000_TOTL);
9213 + temp = E1000_READ_REG(hw, E1000_TOTH);
9214 + temp = E1000_READ_REG(hw, E1000_TPR);
9215 + temp = E1000_READ_REG(hw, E1000_TPT);
9216 + temp = E1000_READ_REG(hw, E1000_MPTC);
9217 + temp = E1000_READ_REG(hw, E1000_BPTC);
9221 + * e1000_check_for_copper_link_generic - Check for link (Copper)
9222 + * @hw: pointer to the HW structure
9224 + * Checks to see of the link status of the hardware has changed. If a
9225 + * change in link status has been detected, then we read the PHY registers
9226 + * to get the current speed/duplex if link exists.
9228 +s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
9230 + struct e1000_mac_info *mac = &hw->mac;
9234 + DEBUGFUNC("e1000_check_for_copper_link");
9237 + * We only want to go out to the PHY registers to see if Auto-Neg
9238 + * has completed and/or if our link status has changed. The
9239 + * get_link_status flag is set upon receiving a Link Status
9240 + * Change or Rx Sequence Error interrupt.
9242 + if (!mac->get_link_status) {
9243 + ret_val = E1000_SUCCESS;
9248 + * First we want to see if the MII Status Register reports
9249 + * link. If so, then we want to get the current speed/duplex
9252 + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
9257 + goto out; /* No link detected */
9259 + mac->get_link_status = false;
9262 + * Check if there was DownShift, must be checked
9263 + * immediately after link-up
9265 + e1000_check_downshift_generic(hw);
9268 + * If we are forcing speed/duplex, then we simply return since
9269 + * we have already determined whether we have link or not.
9271 + if (!mac->autoneg) {
9272 + ret_val = -E1000_ERR_CONFIG;
9277 + * Auto-Neg is enabled. Auto Speed Detection takes care
9278 + * of MAC speed/duplex configuration. So we only need to
9279 + * configure Collision Distance in the MAC.
9281 + e1000_config_collision_dist_generic(hw);
9284 + * Configure Flow Control now that Auto-Neg has completed.
9285 + * First, we need to restore the desired flow control
9286 + * settings because we may have had to re-autoneg with a
9287 + * different link partner.
9289 + ret_val = e1000_config_fc_after_link_up_generic(hw);
9291 + DEBUGOUT("Error configuring flow control\n");
9299 + * e1000_check_for_fiber_link_generic - Check for link (Fiber)
9300 + * @hw: pointer to the HW structure
9302 + * Checks for link up on the hardware. If link is not up and we have
9303 + * a signal, then we need to force link up.
9305 +s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
9307 + struct e1000_mac_info *mac = &hw->mac;
9311 + s32 ret_val = E1000_SUCCESS;
9313 + DEBUGFUNC("e1000_check_for_fiber_link_generic");
9315 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9316 + status = E1000_READ_REG(hw, E1000_STATUS);
9317 + rxcw = E1000_READ_REG(hw, E1000_RXCW);
9320 + * If we don't have link (auto-negotiation failed or link partner
9321 + * cannot auto-negotiate), the cable is plugged in (we have signal),
9322 + * and our link partner is not trying to auto-negotiate with us (we
9323 + * are receiving idles or data), we need to force link up. We also
9324 + * need to give auto-negotiation time to complete, in case the cable
9325 + * was just plugged in. The autoneg_failed flag does this.
9327 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9328 + if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
9329 + (!(rxcw & E1000_RXCW_C))) {
9330 + if (mac->autoneg_failed == 0) {
9331 + mac->autoneg_failed = 1;
9334 + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
9336 + /* Disable auto-negotiation in the TXCW register */
9337 + E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9339 + /* Force link-up and also force full-duplex. */
9340 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9341 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9342 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
9344 + /* Configure Flow Control after forcing link up. */
9345 + ret_val = e1000_config_fc_after_link_up_generic(hw);
9347 + DEBUGOUT("Error configuring flow control\n");
9350 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9352 + * If we are forcing link and we are receiving /C/ ordered
9353 + * sets, re-enable auto-negotiation in the TXCW register
9354 + * and disable forced link in the Device Control register
9355 + * in an attempt to auto-negotiate with our link partner.
9357 + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
9358 + E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
9359 + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
9361 + mac->serdes_has_link = true;
9369 + * e1000_check_for_serdes_link_generic - Check for link (Serdes)
9370 + * @hw: pointer to the HW structure
9372 + * Checks for link up on the hardware. If link is not up and we have
9373 + * a signal, then we need to force link up.
9375 +s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
9377 + struct e1000_mac_info *mac = &hw->mac;
9381 + s32 ret_val = E1000_SUCCESS;
9383 + DEBUGFUNC("e1000_check_for_serdes_link_generic");
9385 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9386 + status = E1000_READ_REG(hw, E1000_STATUS);
9387 + rxcw = E1000_READ_REG(hw, E1000_RXCW);
9390 + * If we don't have link (auto-negotiation failed or link partner
9391 + * cannot auto-negotiate), and our link partner is not trying to
9392 + * auto-negotiate with us (we are receiving idles or data),
9393 + * we need to force link up. We also need to give auto-negotiation
9394 + * time to complete.
9396 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9397 + if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
9398 + if (mac->autoneg_failed == 0) {
9399 + mac->autoneg_failed = 1;
9402 + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
9404 + /* Disable auto-negotiation in the TXCW register */
9405 + E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9407 + /* Force link-up and also force full-duplex. */
9408 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9409 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9410 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
9412 + /* Configure Flow Control after forcing link up. */
9413 + ret_val = e1000_config_fc_after_link_up_generic(hw);
9415 + DEBUGOUT("Error configuring flow control\n");
9418 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9420 + * If we are forcing link and we are receiving /C/ ordered
9421 + * sets, re-enable auto-negotiation in the TXCW register
9422 + * and disable forced link in the Device Control register
9423 + * in an attempt to auto-negotiate with our link partner.
9425 + DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
9426 + E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
9427 + E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
9429 + mac->serdes_has_link = true;
9430 + } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
9432 + * If we force link for non-auto-negotiation switch, check
9433 + * link status based on MAC synchronization for internal
9434 + * serdes media type.
9436 + /* SYNCH bit and IV bit are sticky. */
9438 + rxcw = E1000_READ_REG(hw, E1000_RXCW);
9439 + if (rxcw & E1000_RXCW_SYNCH) {
9440 + if (!(rxcw & E1000_RXCW_IV)) {
9441 + mac->serdes_has_link = true;
9442 + DEBUGOUT("SERDES: Link up - forced.\n");
9445 + mac->serdes_has_link = false;
9446 + DEBUGOUT("SERDES: Link down - force failed.\n");
9450 + if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
9451 + status = E1000_READ_REG(hw, E1000_STATUS);
9452 + if (status & E1000_STATUS_LU) {
9453 + /* SYNCH bit and IV bit are sticky, so reread rxcw. */
9455 + rxcw = E1000_READ_REG(hw, E1000_RXCW);
9456 + if (rxcw & E1000_RXCW_SYNCH) {
9457 + if (!(rxcw & E1000_RXCW_IV)) {
9458 + mac->serdes_has_link = TRUE;
9459 + DEBUGOUT("SERDES: Link up - autoneg "
9460 + "completed sucessfully.\n");
9462 + mac->serdes_has_link = FALSE;
9463 + DEBUGOUT("SERDES: Link down - invalid"
9464 + "codewords detected in autoneg.\n");
9467 + mac->serdes_has_link = FALSE;
9468 + DEBUGOUT("SERDES: Link down - no sync.\n");
9471 + mac->serdes_has_link = FALSE;
9472 + DEBUGOUT("SERDES: Link down - autoneg failed\n");
9481 + * e1000_setup_link_generic - Setup flow control and link settings
9482 + * @hw: pointer to the HW structure
9484 + * Determines which flow control settings to use, then configures flow
9485 + * control. Calls the appropriate media-specific link configuration
9486 + * function. Assuming the adapter has a valid link partner, a valid link
9487 + * should be established. Assumes the hardware has previously been reset
9488 + * and the transmitter and receiver are not enabled.
9490 +s32 e1000_setup_link_generic(struct e1000_hw *hw)
9492 + s32 ret_val = E1000_SUCCESS;
9494 + DEBUGFUNC("e1000_setup_link_generic");
9497 + * In the case of the phy reset being blocked, we already have a link.
9498 + * We do not need to set it up again.
9500 + if (hw->phy.ops.check_reset_block)
9501 + if (hw->phy.ops.check_reset_block(hw))
9505 + * If flow control is set to default, set flow control based on
9506 + * the EEPROM flow control settings.
9508 + if (hw->fc.type == e1000_fc_default) {
9509 + ret_val = e1000_set_default_fc_generic(hw);
9515 + * We want to save off the original Flow Control configuration just
9516 + * in case we get disconnected and then reconnected into a different
9517 + * hub or switch with different Flow Control capabilities.
9519 + hw->fc.original_type = hw->fc.type;
9521 + DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
9523 + /* Call the necessary media_type subroutine to configure the link. */
9524 + ret_val = hw->mac.ops.setup_physical_interface(hw);
9529 + * Initialize the flow control address, type, and PAUSE timer
9530 + * registers to their default values. This is done even if flow
9531 + * control is disabled, because it does not hurt anything to
9532 + * initialize these registers.
9534 + DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
9535 + E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
9536 + E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
9537 + E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
9539 + E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
9541 + ret_val = e1000_set_fc_watermarks_generic(hw);
9548 + * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
9549 + * @hw: pointer to the HW structure
9551 + * Configures collision distance and flow control for fiber and serdes
9552 + * links. Upon successful setup, poll for link.
9554 +s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
9557 + s32 ret_val = E1000_SUCCESS;
9559 + DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
9561 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9563 + /* Take the link out of reset */
9564 + ctrl &= ~E1000_CTRL_LRST;
9566 + e1000_config_collision_dist_generic(hw);
9568 + ret_val = e1000_commit_fc_settings_generic(hw);
9573 + * Since auto-negotiation is enabled, take the link out of reset (the
9574 + * link will be in reset, because we previously reset the chip). This
9575 + * will restart auto-negotiation. If auto-negotiation is successful
9576 + * then the link-up status bit will be set and the flow control enable
9577 + * bits (RFCE and TFCE) will be set according to their negotiated value.
9579 + DEBUGOUT("Auto-negotiation enabled\n");
9581 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
9582 + E1000_WRITE_FLUSH(hw);
9586 + * For these adapters, the SW definable pin 1 is set when the optics
9587 + * detect a signal. If we have a signal, then poll for a "Link-Up"
9590 + if (hw->phy.media_type == e1000_media_type_internal_serdes ||
9591 + (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
9592 + ret_val = e1000_poll_fiber_serdes_link_generic(hw);
9594 + DEBUGOUT("No signal detected\n");
9602 + * e1000_config_collision_dist_generic - Configure collision distance
9603 + * @hw: pointer to the HW structure
9605 + * Configures the collision distance to the default value and is used
9606 + * during link setup. Currently no func pointer exists and all
9607 + * implementations are handled in the generic version of this function.
9609 +void e1000_config_collision_dist_generic(struct e1000_hw *hw)
9613 + DEBUGFUNC("e1000_config_collision_dist_generic");
9615 + tctl = E1000_READ_REG(hw, E1000_TCTL);
9617 + tctl &= ~E1000_TCTL_COLD;
9618 + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
9620 + E1000_WRITE_REG(hw, E1000_TCTL, tctl);
9621 + E1000_WRITE_FLUSH(hw);
9625 + * e1000_poll_fiber_serdes_link_generic - Poll for link up
9626 + * @hw: pointer to the HW structure
9628 + * Polls for link up by reading the status register, if link fails to come
9629 + * up with auto-negotiation, then the link is forced if a signal is detected.
9631 +s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
9633 + struct e1000_mac_info *mac = &hw->mac;
9635 + s32 ret_val = E1000_SUCCESS;
9637 + DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
9640 + * If we have a signal (the cable is plugged in, or assumed true for
9641 + * serdes media) then poll for a "Link-Up" indication in the Device
9642 + * Status Register. Time-out if a link isn't seen in 500 milliseconds
9643 + * seconds (Auto-negotiation should complete in less than 500
9644 + * milliseconds even if the other end is doing it in SW).
9646 + for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
9648 + status = E1000_READ_REG(hw, E1000_STATUS);
9649 + if (status & E1000_STATUS_LU)
9652 + if (i == FIBER_LINK_UP_LIMIT) {
9653 + DEBUGOUT("Never got a valid link from auto-neg!!!\n");
9654 + mac->autoneg_failed = 1;
9656 + * AutoNeg failed to achieve a link, so we'll call
9657 + * mac->check_for_link. This routine will force the
9658 + * link up if we detect a signal. This will allow us to
9659 + * communicate with non-autonegotiating link partners.
9661 + ret_val = hw->mac.ops.check_for_link(hw);
9663 + DEBUGOUT("Error while checking for link\n");
9666 + mac->autoneg_failed = 0;
9668 + mac->autoneg_failed = 0;
9669 + DEBUGOUT("Valid Link Found\n");
9677 + * e1000_commit_fc_settings_generic - Configure flow control
9678 + * @hw: pointer to the HW structure
9680 + * Write the flow control settings to the Transmit Config Word Register (TXCW)
9681 + * base on the flow control settings in e1000_mac_info.
9683 +s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
9685 + struct e1000_mac_info *mac = &hw->mac;
9687 + s32 ret_val = E1000_SUCCESS;
9689 + DEBUGFUNC("e1000_commit_fc_settings_generic");
9692 + * Check for a software override of the flow control settings, and
9693 + * setup the device accordingly. If auto-negotiation is enabled, then
9694 + * software will have to set the "PAUSE" bits to the correct value in
9695 + * the Transmit Config Word Register (TXCW) and re-start auto-
9696 + * negotiation. However, if auto-negotiation is disabled, then
9697 + * software will have to manually configure the two flow control enable
9698 + * bits in the CTRL register.
9700 + * The possible values of the "fc" parameter are:
9701 + * 0: Flow control is completely disabled
9702 + * 1: Rx flow control is enabled (we can receive pause frames,
9703 + * but not send pause frames).
9704 + * 2: Tx flow control is enabled (we can send pause frames but we
9705 + * do not support receiving pause frames).
9706 + * 3: Both Rx and Tx flow control (symmetric) are enabled.
9708 + switch (hw->fc.type) {
9709 + case e1000_fc_none:
9710 + /* Flow control completely disabled by a software over-ride. */
9711 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
9713 + case e1000_fc_rx_pause:
9715 + * Rx Flow control is enabled and Tx Flow control is disabled
9716 + * by a software over-ride. Since there really isn't a way to
9717 + * advertise that we are capable of Rx Pause ONLY, we will
9718 + * advertise that we support both symmetric and asymmetric RX
9719 + * PAUSE. Later, we will disable the adapter's ability to send
9722 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9724 + case e1000_fc_tx_pause:
9726 + * Tx Flow control is enabled, and Rx Flow control is disabled,
9727 + * by a software over-ride.
9729 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
9731 + case e1000_fc_full:
9733 + * Flow control (both Rx and Tx) is enabled by a software
9736 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9739 + DEBUGOUT("Flow control param set incorrectly\n");
9740 + ret_val = -E1000_ERR_CONFIG;
9745 + E1000_WRITE_REG(hw, E1000_TXCW, txcw);
9753 + * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
9754 + * @hw: pointer to the HW structure
9756 + * Sets the flow control high/low threshold (watermark) registers. If
9757 + * flow control XON frame transmission is enabled, then set XON frame
9758 + * transmission as well.
9760 +s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
9762 + s32 ret_val = E1000_SUCCESS;
9763 + u32 fcrtl = 0, fcrth = 0;
9765 + DEBUGFUNC("e1000_set_fc_watermarks_generic");
9768 + * Set the flow control receive threshold registers. Normally,
9769 + * these registers will be set to a default threshold that may be
9770 + * adjusted later by the driver's runtime code. However, if the
9771 + * ability to transmit pause frames is not enabled, then these
9772 + * registers will be set to 0.
9774 + if (hw->fc.type & e1000_fc_tx_pause) {
9776 + * We need to set up the Receive Threshold high and low water
9777 + * marks as well as (optionally) enabling the transmission of
9780 + fcrtl = hw->fc.low_water;
9781 + if (hw->fc.send_xon)
9782 + fcrtl |= E1000_FCRTL_XONE;
9784 + fcrth = hw->fc.high_water;
9786 + E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
9787 + E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
9793 + * e1000_set_default_fc_generic - Set flow control default values
9794 + * @hw: pointer to the HW structure
9796 + * Read the EEPROM for the default values for flow control and store the
9799 +s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
9801 + s32 ret_val = E1000_SUCCESS;
9804 + DEBUGFUNC("e1000_set_default_fc_generic");
9807 + * Read and store word 0x0F of the EEPROM. This word contains bits
9808 + * that determine the hardware's default PAUSE (flow control) mode,
9809 + * a bit that determines whether the HW defaults to enabling or
9810 + * disabling auto-negotiation, and the direction of the
9811 + * SW defined pins. If there is no SW over-ride of the flow
9812 + * control setting, then the variable hw->fc will
9813 + * be initialized based on a value in the EEPROM.
9815 + ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
9818 + DEBUGOUT("NVM Read Error\n");
9822 + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
9823 + hw->fc.type = e1000_fc_none;
9824 + else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
9825 + NVM_WORD0F_ASM_DIR)
9826 + hw->fc.type = e1000_fc_tx_pause;
9828 + hw->fc.type = e1000_fc_full;
9835 + * e1000_force_mac_fc_generic - Force the MAC's flow control settings
9836 + * @hw: pointer to the HW structure
9838 + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
9839 + * device control register to reflect the adapter settings. TFCE and RFCE
9840 + * need to be explicitly set by software when a copper PHY is used because
9841 + * autonegotiation is managed by the PHY rather than the MAC. Software must
9842 + * also configure these bits when link is forced on a fiber connection.
9844 +s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
9847 + s32 ret_val = E1000_SUCCESS;
9849 + DEBUGFUNC("e1000_force_mac_fc_generic");
9851 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
9854 + * Because we didn't get link via the internal auto-negotiation
9855 + * mechanism (we either forced link or we got link via PHY
9856 + * auto-neg), we have to manually enable/disable transmit an
9857 + * receive flow control.
9859 + * The "Case" statement below enables/disable flow control
9860 + * according to the "hw->fc.type" parameter.
9862 + * The possible values of the "fc" parameter are:
9863 + * 0: Flow control is completely disabled
9864 + * 1: Rx flow control is enabled (we can receive pause
9865 + * frames but not send pause frames).
9866 + * 2: Tx flow control is enabled (we can send pause frames
9867 + * frames but we do not receive pause frames).
9868 + * 3: Both Rx and Tx flow control (symmetric) is enabled.
9869 + * other: No other values should be possible at this point.
9871 + DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type);
9873 + switch (hw->fc.type) {
9874 + case e1000_fc_none:
9875 + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
9877 + case e1000_fc_rx_pause:
9878 + ctrl &= (~E1000_CTRL_TFCE);
9879 + ctrl |= E1000_CTRL_RFCE;
9881 + case e1000_fc_tx_pause:
9882 + ctrl &= (~E1000_CTRL_RFCE);
9883 + ctrl |= E1000_CTRL_TFCE;
9885 + case e1000_fc_full:
9886 + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
9889 + DEBUGOUT("Flow control param set incorrectly\n");
9890 + ret_val = -E1000_ERR_CONFIG;
9894 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
9901 + * e1000_config_fc_after_link_up_generic - Configures flow control after link
9902 + * @hw: pointer to the HW structure
9904 + * Checks the status of auto-negotiation after link up to ensure that the
9905 + * speed and duplex were not forced. If the link needed to be forced, then
9906 + * flow control needs to be forced also. If auto-negotiation is enabled
9907 + * and did not fail, then we configure flow control based on our link
9910 +s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
9912 + struct e1000_mac_info *mac = &hw->mac;
9913 + struct e1000_phy_info *phy = &hw->phy;
9914 + s32 ret_val = E1000_SUCCESS;
9915 + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
9916 + u16 speed, duplex;
9918 + DEBUGFUNC("e1000_config_fc_after_link_up_generic");
9921 + * Check for the case where we have fiber media and auto-neg failed
9922 + * so we had to force link. In this case, we need to force the
9923 + * configuration of the MAC to match the "fc" parameter.
9925 + if (mac->autoneg_failed) {
9926 + if (hw->phy.media_type == e1000_media_type_fiber ||
9927 + hw->phy.media_type == e1000_media_type_internal_serdes)
9928 + ret_val = e1000_force_mac_fc_generic(hw);
9930 + if (hw->phy.media_type == e1000_media_type_copper)
9931 + ret_val = e1000_force_mac_fc_generic(hw);
9935 + DEBUGOUT("Error forcing flow control settings\n");
9940 + * Check for the case where we have copper media and auto-neg is
9941 + * enabled. In this case, we need to check and see if Auto-Neg
9942 + * has completed, and if so, how the PHY and link partner has
9943 + * flow control configured.
9945 + if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
9947 + * Read the MII Status Register and check to see if AutoNeg
9948 + * has completed. We read this twice because this reg has
9949 + * some "sticky" (latched) bits.
9951 + ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
9954 + ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
9958 + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
9959 + DEBUGOUT("Copper PHY and Auto Neg "
9960 + "has not completed.\n");
9965 + * The AutoNeg process has completed, so we now need to
9966 + * read both the Auto Negotiation Advertisement
9967 + * Register (Address 4) and the Auto_Negotiation Base
9968 + * Page Ability Register (Address 5) to determine how
9969 + * flow control was negotiated.
9971 + ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV,
9972 + &mii_nway_adv_reg);
9975 + ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY,
9976 + &mii_nway_lp_ability_reg);
9981 + * Two bits in the Auto Negotiation Advertisement Register
9982 + * (Address 4) and two bits in the Auto Negotiation Base
9983 + * Page Ability Register (Address 5) determine flow control
9984 + * for both the PHY and the link partner. The following
9985 + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
9986 + * 1999, describes these PAUSE resolution bits and how flow
9987 + * control is determined based upon these settings.
9988 + * NOTE: DC = Don't Care
9990 + * LOCAL DEVICE | LINK PARTNER
9991 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
9992 + *-------|---------|-------|---------|--------------------
9993 + * 0 | 0 | DC | DC | e1000_fc_none
9994 + * 0 | 1 | 0 | DC | e1000_fc_none
9995 + * 0 | 1 | 1 | 0 | e1000_fc_none
9996 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
9997 + * 1 | 0 | 0 | DC | e1000_fc_none
9998 + * 1 | DC | 1 | DC | e1000_fc_full
9999 + * 1 | 1 | 0 | 0 | e1000_fc_none
10000 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
10002 + * Are both PAUSE bits set to 1? If so, this implies
10003 + * Symmetric Flow Control is enabled at both ends. The
10004 + * ASM_DIR bits are irrelevant per the spec.
10006 + * For Symmetric Flow Control:
10008 + * LOCAL DEVICE | LINK PARTNER
10009 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10010 + *-------|---------|-------|---------|--------------------
10011 + * 1 | DC | 1 | DC | E1000_fc_full
10014 + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10015 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
10017 + * Now we need to check if the user selected Rx ONLY
10018 + * of pause frames. In this case, we had to advertise
10019 + * FULL flow control because we could not advertise RX
10020 + * ONLY. Hence, we must now check to see if we need to
10021 + * turn OFF the TRANSMISSION of PAUSE frames.
10023 + if (hw->fc.original_type == e1000_fc_full) {
10024 + hw->fc.type = e1000_fc_full;
10025 + DEBUGOUT("Flow Control = FULL.\r\n");
10027 + hw->fc.type = e1000_fc_rx_pause;
10028 + DEBUGOUT("Flow Control = "
10029 + "RX PAUSE frames only.\r\n");
10033 + * For receiving PAUSE frames ONLY.
10035 + * LOCAL DEVICE | LINK PARTNER
10036 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10037 + *-------|---------|-------|---------|--------------------
10038 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
10040 + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10041 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
10042 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
10043 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
10044 + hw->fc.type = e1000_fc_tx_pause;
10045 + DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
10048 + * For transmitting PAUSE frames ONLY.
10050 + * LOCAL DEVICE | LINK PARTNER
10051 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10052 + *-------|---------|-------|---------|--------------------
10053 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
10055 + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10056 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
10057 + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
10058 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
10059 + hw->fc.type = e1000_fc_rx_pause;
10060 + DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
10063 + * Per the IEEE spec, at this point flow control
10064 + * should be disabled.
10066 + hw->fc.type = e1000_fc_none;
10067 + DEBUGOUT("Flow Control = NONE.\r\n");
10071 + * Now we need to do one last check... If we auto-
10072 + * negotiated to HALF DUPLEX, flow control should not be
10073 + * enabled per IEEE 802.3 spec.
10075 + ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
10077 + DEBUGOUT("Error getting link speed and duplex\n");
10081 + if (duplex == HALF_DUPLEX)
10082 + hw->fc.type = e1000_fc_none;
10085 + * Now we call a subroutine to actually force the MAC
10086 + * controller to use the correct flow control settings.
10088 + ret_val = e1000_force_mac_fc_generic(hw);
10090 + DEBUGOUT("Error forcing flow control settings\n");
10100 + * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
10101 + * @hw: pointer to the HW structure
10102 + * @speed: stores the current speed
10103 + * @duplex: stores the current duplex
10105 + * Read the status register for the current speed/duplex and store the current
10106 + * speed and duplex for copper connections.
10108 +s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
10113 + DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
10115 + status = E1000_READ_REG(hw, E1000_STATUS);
10116 + if (status & E1000_STATUS_SPEED_1000) {
10117 + *speed = SPEED_1000;
10118 + DEBUGOUT("1000 Mbs, ");
10119 + } else if (status & E1000_STATUS_SPEED_100) {
10120 + *speed = SPEED_100;
10121 + DEBUGOUT("100 Mbs, ");
10123 + *speed = SPEED_10;
10124 + DEBUGOUT("10 Mbs, ");
10127 + if (status & E1000_STATUS_FD) {
10128 + *duplex = FULL_DUPLEX;
10129 + DEBUGOUT("Full Duplex\n");
10131 + *duplex = HALF_DUPLEX;
10132 + DEBUGOUT("Half Duplex\n");
10135 + return E1000_SUCCESS;
10139 + * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
10140 + * @hw: pointer to the HW structure
10141 + * @speed: stores the current speed
10142 + * @duplex: stores the current duplex
10144 + * Sets the speed and duplex to gigabit full duplex (the only possible option)
10145 + * for fiber/serdes links.
10147 +s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
10148 + u16 *speed, u16 *duplex)
10150 + DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
10152 + *speed = SPEED_1000;
10153 + *duplex = FULL_DUPLEX;
10155 + return E1000_SUCCESS;
10159 + * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
10160 + * @hw: pointer to the HW structure
10162 + * Acquire the HW semaphore to access the PHY or NVM
10164 +s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
10167 + s32 ret_val = E1000_SUCCESS;
10168 + s32 timeout = hw->nvm.word_size + 1;
10171 + DEBUGFUNC("e1000_get_hw_semaphore_generic");
10173 + /* Get the SW semaphore */
10174 + while (i < timeout) {
10175 + swsm = E1000_READ_REG(hw, E1000_SWSM);
10176 + if (!(swsm & E1000_SWSM_SMBI))
10183 + if (i == timeout) {
10184 + DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
10185 + ret_val = -E1000_ERR_NVM;
10189 + /* Get the FW semaphore. */
10190 + for (i = 0; i < timeout; i++) {
10191 + swsm = E1000_READ_REG(hw, E1000_SWSM);
10192 + E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
10194 + /* Semaphore acquired if bit latched */
10195 + if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
10201 + if (i == timeout) {
10202 + /* Release semaphores */
10203 + e1000_put_hw_semaphore_generic(hw);
10204 + DEBUGOUT("Driver can't access the NVM\n");
10205 + ret_val = -E1000_ERR_NVM;
10214 + * e1000_put_hw_semaphore_generic - Release hardware semaphore
10215 + * @hw: pointer to the HW structure
10217 + * Release hardware semaphore used to access the PHY or NVM
10219 +void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
10223 + DEBUGFUNC("e1000_put_hw_semaphore_generic");
10225 + swsm = E1000_READ_REG(hw, E1000_SWSM);
10227 + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
10229 + E1000_WRITE_REG(hw, E1000_SWSM, swsm);
10233 + * e1000_get_auto_rd_done_generic - Check for auto read completion
10234 + * @hw: pointer to the HW structure
10236 + * Check EEPROM for Auto Read done bit.
10238 +s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
10241 + s32 ret_val = E1000_SUCCESS;
10243 + DEBUGFUNC("e1000_get_auto_rd_done_generic");
10245 + while (i < AUTO_READ_DONE_TIMEOUT) {
10246 + if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
10252 + if (i == AUTO_READ_DONE_TIMEOUT) {
10253 + DEBUGOUT("Auto read by HW from NVM has not completed.\n");
10254 + ret_val = -E1000_ERR_RESET;
10263 + * e1000_valid_led_default_generic - Verify a valid default LED config
10264 + * @hw: pointer to the HW structure
10265 + * @data: pointer to the NVM (EEPROM)
10267 + * Read the EEPROM for the current default LED configuration. If the
10268 + * LED configuration is not valid, set to a valid LED configuration.
10270 +s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
10274 + DEBUGFUNC("e1000_valid_led_default_generic");
10276 + ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
10278 + DEBUGOUT("NVM Read Error\n");
10282 + if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
10283 + *data = ID_LED_DEFAULT;
10290 + * e1000_id_led_init_generic -
10291 + * @hw: pointer to the HW structure
10294 +s32 e1000_id_led_init_generic(struct e1000_hw * hw)
10296 + struct e1000_mac_info *mac = &hw->mac;
10298 + const u32 ledctl_mask = 0x000000FF;
10299 + const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
10300 + const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
10301 + u16 data, i, temp;
10302 + const u16 led_mask = 0x0F;
10304 + DEBUGFUNC("e1000_id_led_init_generic");
10306 + ret_val = hw->nvm.ops.valid_led_default(hw, &data);
10310 + mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
10311 + mac->ledctl_mode1 = mac->ledctl_default;
10312 + mac->ledctl_mode2 = mac->ledctl_default;
10314 + for (i = 0; i < 4; i++) {
10315 + temp = (data >> (i << 2)) & led_mask;
10317 + case ID_LED_ON1_DEF2:
10318 + case ID_LED_ON1_ON2:
10319 + case ID_LED_ON1_OFF2:
10320 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10321 + mac->ledctl_mode1 |= ledctl_on << (i << 3);
10323 + case ID_LED_OFF1_DEF2:
10324 + case ID_LED_OFF1_ON2:
10325 + case ID_LED_OFF1_OFF2:
10326 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10327 + mac->ledctl_mode1 |= ledctl_off << (i << 3);
10334 + case ID_LED_DEF1_ON2:
10335 + case ID_LED_ON1_ON2:
10336 + case ID_LED_OFF1_ON2:
10337 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10338 + mac->ledctl_mode2 |= ledctl_on << (i << 3);
10340 + case ID_LED_DEF1_OFF2:
10341 + case ID_LED_ON1_OFF2:
10342 + case ID_LED_OFF1_OFF2:
10343 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10344 + mac->ledctl_mode2 |= ledctl_off << (i << 3);
10357 + * e1000_setup_led_generic - Configures SW controllable LED
10358 + * @hw: pointer to the HW structure
10360 + * This prepares the SW controllable LED for use and saves the current state
10361 + * of the LED so it can be later restored.
10363 +s32 e1000_setup_led_generic(struct e1000_hw *hw)
10366 + s32 ret_val = E1000_SUCCESS;
10368 + DEBUGFUNC("e1000_setup_led_generic");
10370 + if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
10371 + ret_val = -E1000_ERR_CONFIG;
10375 + if (hw->phy.media_type == e1000_media_type_fiber) {
10376 + ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
10377 + hw->mac.ledctl_default = ledctl;
10378 + /* Turn off LED0 */
10379 + ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
10380 + E1000_LEDCTL_LED0_BLINK |
10381 + E1000_LEDCTL_LED0_MODE_MASK);
10382 + ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
10383 + E1000_LEDCTL_LED0_MODE_SHIFT);
10384 + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
10385 + } else if (hw->phy.media_type == e1000_media_type_copper) {
10386 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
10394 + * e1000_cleanup_led_generic - Set LED config to default operation
10395 + * @hw: pointer to the HW structure
10397 + * Remove the current LED configuration and set the LED configuration
10398 + * to the default value, saved from the EEPROM.
10400 +s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
10402 + s32 ret_val = E1000_SUCCESS;
10404 + DEBUGFUNC("e1000_cleanup_led_generic");
10406 + if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
10407 + ret_val = -E1000_ERR_CONFIG;
10411 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
10418 + * e1000_blink_led_generic - Blink LED
10419 + * @hw: pointer to the HW structure
10421 + * Blink the LEDs which are set to be on.
10423 +s32 e1000_blink_led_generic(struct e1000_hw *hw)
10425 + u32 ledctl_blink = 0;
10428 + DEBUGFUNC("e1000_blink_led_generic");
10430 + if (hw->phy.media_type == e1000_media_type_fiber) {
10431 + /* always blink LED0 for PCI-E fiber */
10432 + ledctl_blink = E1000_LEDCTL_LED0_BLINK |
10433 + (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
10436 + * set the blink bit for each LED that's "on" (0x0E)
10437 + * in ledctl_mode2
10439 + ledctl_blink = hw->mac.ledctl_mode2;
10440 + for (i = 0; i < 4; i++)
10441 + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
10442 + E1000_LEDCTL_MODE_LED_ON)
10443 + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
10447 + E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
10449 + return E1000_SUCCESS;
10453 + * e1000_led_on_generic - Turn LED on
10454 + * @hw: pointer to the HW structure
10458 +s32 e1000_led_on_generic(struct e1000_hw *hw)
10462 + DEBUGFUNC("e1000_led_on_generic");
10464 + switch (hw->phy.media_type) {
10465 + case e1000_media_type_fiber:
10466 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
10467 + ctrl &= ~E1000_CTRL_SWDPIN0;
10468 + ctrl |= E1000_CTRL_SWDPIO0;
10469 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
10471 + case e1000_media_type_copper:
10472 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
10478 + return E1000_SUCCESS;
10482 + * e1000_led_off_generic - Turn LED off
10483 + * @hw: pointer to the HW structure
10487 +s32 e1000_led_off_generic(struct e1000_hw *hw)
10491 + DEBUGFUNC("e1000_led_off_generic");
10493 + switch (hw->phy.media_type) {
10494 + case e1000_media_type_fiber:
10495 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
10496 + ctrl |= E1000_CTRL_SWDPIN0;
10497 + ctrl |= E1000_CTRL_SWDPIO0;
10498 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
10500 + case e1000_media_type_copper:
10501 + E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
10507 + return E1000_SUCCESS;
10511 + * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
10512 + * @hw: pointer to the HW structure
10513 + * @no_snoop: bitmap of snoop events
10515 + * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
10517 +void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
10521 + DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
10523 + if (hw->bus.type != e1000_bus_type_pci_express)
10527 + gcr = E1000_READ_REG(hw, E1000_GCR);
10528 + gcr &= ~(PCIE_NO_SNOOP_ALL);
10530 + E1000_WRITE_REG(hw, E1000_GCR, gcr);
10537 + * e1000_disable_pcie_master_generic - Disables PCI-express master access
10538 + * @hw: pointer to the HW structure
10540 + * Returns 0 (E1000_SUCCESS) if successful, else returns -10
10541 + * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
10542 + * the master requests to be disabled.
10544 + * Disables PCI-Express master access and verifies there are no pending
10547 +s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
10550 + s32 timeout = MASTER_DISABLE_TIMEOUT;
10551 + s32 ret_val = E1000_SUCCESS;
10553 + DEBUGFUNC("e1000_disable_pcie_master_generic");
10555 + if (hw->bus.type != e1000_bus_type_pci_express)
10558 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
10559 + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
10560 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
10562 + while (timeout) {
10563 + if (!(E1000_READ_REG(hw, E1000_STATUS) &
10564 + E1000_STATUS_GIO_MASTER_ENABLE))
10571 + DEBUGOUT("Master requests are pending.\n");
10572 + ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
10581 + * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
10582 + * @hw: pointer to the HW structure
10584 + * Reset the Adaptive Interframe Spacing throttle to default values.
10586 +void e1000_reset_adaptive_generic(struct e1000_hw *hw)
10588 + struct e1000_mac_info *mac = &hw->mac;
10590 + DEBUGFUNC("e1000_reset_adaptive_generic");
10592 + if (!mac->adaptive_ifs) {
10593 + DEBUGOUT("Not in Adaptive IFS mode!\n");
10597 + if (!mac->ifs_params_forced) {
10598 + mac->current_ifs_val = 0;
10599 + mac->ifs_min_val = IFS_MIN;
10600 + mac->ifs_max_val = IFS_MAX;
10601 + mac->ifs_step_size = IFS_STEP;
10602 + mac->ifs_ratio = IFS_RATIO;
10605 + mac->in_ifs_mode = false;
10606 + E1000_WRITE_REG(hw, E1000_AIT, 0);
10612 + * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
10613 + * @hw: pointer to the HW structure
10615 + * Update the Adaptive Interframe Spacing Throttle value based on the
10616 + * time between transmitted packets and time between collisions.
10618 +void e1000_update_adaptive_generic(struct e1000_hw *hw)
10620 + struct e1000_mac_info *mac = &hw->mac;
10622 + DEBUGFUNC("e1000_update_adaptive_generic");
10624 + if (!mac->adaptive_ifs) {
10625 + DEBUGOUT("Not in Adaptive IFS mode!\n");
10629 + if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
10630 + if (mac->tx_packet_delta > MIN_NUM_XMITS) {
10631 + mac->in_ifs_mode = true;
10632 + if (mac->current_ifs_val < mac->ifs_max_val) {
10633 + if (!mac->current_ifs_val)
10634 + mac->current_ifs_val = mac->ifs_min_val;
10636 + mac->current_ifs_val +=
10637 + mac->ifs_step_size;
10638 + E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
10642 + if (mac->in_ifs_mode &&
10643 + (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
10644 + mac->current_ifs_val = 0;
10645 + mac->in_ifs_mode = false;
10646 + E1000_WRITE_REG(hw, E1000_AIT, 0);
10654 + * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
10655 + * @hw: pointer to the HW structure
10657 + * Verify that when not using auto-negotiation that MDI/MDIx is correctly
10658 + * set, which is forced to MDI mode only.
10660 +s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
10662 + s32 ret_val = E1000_SUCCESS;
10664 + DEBUGFUNC("e1000_validate_mdi_setting_generic");
10666 + if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
10667 + DEBUGOUT("Invalid MDI setting detected\n");
10668 + hw->phy.mdix = 1;
10669 + ret_val = -E1000_ERR_CONFIG;
10678 + * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
10679 + * @hw: pointer to the HW structure
10680 + * @reg: 32bit register offset such as E1000_SCTL
10681 + * @offset: register offset to write to
10682 + * @data: data to write at register offset
10684 + * Writes an address/data control type register. There are several of these
10685 + * and they all have the format address << 8 | data and bit 31 is polled for
10688 +s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
10689 + u32 offset, u8 data)
10691 + u32 i, regvalue = 0;
10692 + s32 ret_val = E1000_SUCCESS;
10694 + DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
10696 + /* Set up the address and data */
10697 + regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
10698 + E1000_WRITE_REG(hw, reg, regvalue);
10700 + /* Poll the ready bit to see if the MDI read completed */
10701 + for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
10703 + regvalue = E1000_READ_REG(hw, reg);
10704 + if (regvalue & E1000_GEN_CTL_READY)
10707 + if (!(regvalue & E1000_GEN_CTL_READY)) {
10708 + DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
10709 + ret_val = -E1000_ERR_PHY;
10716 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h
10717 --- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h 1970-01-01 01:00:00.000000000 +0100
10718 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h 2008-10-14 01:51:32.000000000 +0200
10720 +/*******************************************************************************
10722 + Intel PRO/1000 Linux driver
10723 + Copyright(c) 1999 - 2008 Intel Corporation.
10725 + This program is free software; you can redistribute it and/or modify it
10726 + under the terms and conditions of the GNU General Public License,
10727 + version 2, as published by the Free Software Foundation.
10729 + This program is distributed in the hope it will be useful, but WITHOUT
10730 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10731 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10734 + You should have received a copy of the GNU General Public License along with
10735 + this program; if not, write to the Free Software Foundation, Inc.,
10736 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
10738 + The full GNU General Public License is included in this distribution in
10739 + the file called "COPYING".
10741 + Contact Information:
10742 + Linux NICS <linux.nics@intel.com>
10743 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
10744 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10746 +*******************************************************************************/
10748 +#ifndef _E1000_MAC_H_
10749 +#define _E1000_MAC_H_
10752 + * Functions that should not be called directly from drivers but can be used
10753 + * by other files in this 'shared code'
10755 +void e1000_init_mac_ops_generic(struct e1000_hw *hw);
10756 +s32 e1000_blink_led_generic(struct e1000_hw *hw);
10757 +s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);
10758 +s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
10759 +s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw);
10760 +s32 e1000_cleanup_led_generic(struct e1000_hw *hw);
10761 +s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);
10762 +s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw);
10763 +s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw);
10764 +s32 e1000_force_mac_fc_generic(struct e1000_hw *hw);
10765 +s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw);
10766 +s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw);
10767 +s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw);
10768 +s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
10770 +s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
10771 + u16 *speed, u16 *duplex);
10772 +s32 e1000_id_led_init_generic(struct e1000_hw *hw);
10773 +s32 e1000_led_on_generic(struct e1000_hw *hw);
10774 +s32 e1000_led_off_generic(struct e1000_hw *hw);
10775 +void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
10776 + u8 *mc_addr_list, u32 mc_addr_count,
10777 + u32 rar_used_count, u32 rar_count);
10778 +s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
10779 +s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
10780 +s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw);
10781 +s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
10782 +s32 e1000_setup_led_generic(struct e1000_hw *hw);
10783 +s32 e1000_setup_link_generic(struct e1000_hw *hw);
10784 +s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
10785 +s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
10786 + u32 offset, u8 data);
10788 +u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
10790 +void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
10791 +void e1000_clear_vfta_generic(struct e1000_hw *hw);
10792 +void e1000_config_collision_dist_generic(struct e1000_hw *hw);
10793 +void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
10794 +void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
10795 +void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
10796 +void e1000_put_hw_semaphore_generic(struct e1000_hw *hw);
10797 +void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
10798 +s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
10799 +void e1000_remove_device_generic(struct e1000_hw *hw);
10800 +void e1000_reset_adaptive_generic(struct e1000_hw *hw);
10801 +void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
10802 +void e1000_update_adaptive_generic(struct e1000_hw *hw);
10803 +void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
10806 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c
10807 --- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c 1970-01-01 01:00:00.000000000 +0100
10808 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c 2008-10-14 01:51:32.000000000 +0200
10810 +/*******************************************************************************
10812 + Intel PRO/1000 Linux driver
10813 + Copyright(c) 1999 - 2008 Intel Corporation.
10815 + This program is free software; you can redistribute it and/or modify it
10816 + under the terms and conditions of the GNU General Public License,
10817 + version 2, as published by the Free Software Foundation.
10819 + This program is distributed in the hope it will be useful, but WITHOUT
10820 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10821 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10824 + You should have received a copy of the GNU General Public License along with
10825 + this program; if not, write to the Free Software Foundation, Inc.,
10826 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
10828 + The full GNU General Public License is included in this distribution in
10829 + the file called "COPYING".
10831 + Contact Information:
10832 + Linux NICS <linux.nics@intel.com>
10833 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
10834 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10836 +*******************************************************************************/
10838 +#include "e1000_hw.h"
10840 +static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
10843 + * e1000_calculate_checksum - Calculate checksum for buffer
10844 + * @buffer: pointer to EEPROM
10845 + * @length: size of EEPROM to calculate a checksum for
10847 + * Calculates the checksum for some buffer on a specified length. The
10848 + * checksum calculated is returned.
10850 +static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
10855 + DEBUGFUNC("e1000_calculate_checksum");
10860 + for (i = 0; i < length; i++)
10861 + sum += buffer[i];
10863 + return (u8) (0 - sum);
10867 + * e1000_mng_enable_host_if_generic - Checks host interface is enabled
10868 + * @hw: pointer to the HW structure
10870 + * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
10872 + * This function checks whether the HOST IF is enabled for command operation
10873 + * and also checks whether the previous command is completed. It busy waits
10874 + * in case of previous command is not completed.
10876 +s32 e1000_mng_enable_host_if_generic(struct e1000_hw * hw)
10879 + s32 ret_val = E1000_SUCCESS;
10882 + DEBUGFUNC("e1000_mng_enable_host_if_generic");
10884 + /* Check that the host interface is enabled. */
10885 + hicr = E1000_READ_REG(hw, E1000_HICR);
10886 + if ((hicr & E1000_HICR_EN) == 0) {
10887 + DEBUGOUT("E1000_HOST_EN bit disabled.\n");
10888 + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
10891 + /* check the previous command is completed */
10892 + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
10893 + hicr = E1000_READ_REG(hw, E1000_HICR);
10894 + if (!(hicr & E1000_HICR_C))
10896 + msec_delay_irq(1);
10899 + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
10900 + DEBUGOUT("Previous command timeout failed .\n");
10901 + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
10910 + * e1000_check_mng_mode_generic - Generic check management mode
10911 + * @hw: pointer to the HW structure
10913 + * Reads the firmware semaphore register and returns true (>0) if
10914 + * manageability is enabled, else false (0).
10916 +bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
10920 + DEBUGFUNC("e1000_check_mng_mode_generic");
10922 + fwsm = E1000_READ_REG(hw, E1000_FWSM);
10924 + return ((fwsm & E1000_FWSM_MODE_MASK) ==
10925 + (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
10929 + * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
10930 + * @hw: pointer to the HW structure
10932 + * Enables packet filtering on transmit packets if manageability is enabled
10933 + * and host interface is enabled.
10935 +bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
10937 + struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
10938 + u32 *buffer = (u32 *)&hw->mng_cookie;
10940 + s32 ret_val, hdr_csum, csum;
10942 + bool tx_filter = true;
10944 + DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
10946 + /* No manageability, no filtering */
10947 + if (!hw->mac.ops.check_mng_mode(hw)) {
10948 + tx_filter = false;
10953 + * If we can't read from the host interface for whatever
10954 + * reason, disable filtering.
10956 + ret_val = hw->mac.ops.mng_enable_host_if(hw);
10957 + if (ret_val != E1000_SUCCESS) {
10958 + tx_filter = false;
10962 + /* Read in the header. Length and offset are in dwords. */
10963 + len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
10964 + offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
10965 + for (i = 0; i < len; i++) {
10966 + *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
10970 + hdr_csum = hdr->checksum;
10971 + hdr->checksum = 0;
10972 + csum = e1000_calculate_checksum((u8 *)hdr,
10973 + E1000_MNG_DHCP_COOKIE_LENGTH);
10975 + * If either the checksums or signature don't match, then
10976 + * the cookie area isn't considered valid, in which case we
10977 + * take the safe route of assuming Tx filtering is enabled.
10979 + if (hdr_csum != csum)
10981 + if (hdr->signature != E1000_IAMT_SIGNATURE)
10984 + /* Cookie area is valid, make the final check for filtering. */
10985 + if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
10986 + tx_filter = false;
10989 + hw->mac.tx_pkt_filtering = tx_filter;
10990 + return tx_filter;
10994 + * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
10995 + * @hw: pointer to the HW structure
10996 + * @buffer: pointer to the host interface
10997 + * @length: size of the buffer
10999 + * Writes the DHCP information to the host interface.
11001 +s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw * hw, u8 *buffer,
11004 + struct e1000_host_mng_command_header hdr;
11008 + DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
11010 + hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
11011 + hdr.command_length = length;
11012 + hdr.reserved1 = 0;
11013 + hdr.reserved2 = 0;
11014 + hdr.checksum = 0;
11016 + /* Enable the host interface */
11017 + ret_val = hw->mac.ops.mng_enable_host_if(hw);
11021 + /* Populate the host interface with the contents of "buffer". */
11022 + ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
11023 + sizeof(hdr), &(hdr.checksum));
11027 + /* Write the manageability command header */
11028 + ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
11032 + /* Tell the ARC a new command is pending. */
11033 + hicr = E1000_READ_REG(hw, E1000_HICR);
11034 + E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
11041 + * e1000_mng_write_cmd_header_generic - Writes manageability command header
11042 + * @hw: pointer to the HW structure
11043 + * @hdr: pointer to the host interface command header
11045 + * Writes the command header after does the checksum calculation.
11047 +s32 e1000_mng_write_cmd_header_generic(struct e1000_hw * hw,
11048 + struct e1000_host_mng_command_header * hdr)
11050 + u16 i, length = sizeof(struct e1000_host_mng_command_header);
11052 + DEBUGFUNC("e1000_mng_write_cmd_header_generic");
11054 + /* Write the whole command header structure with new checksum. */
11056 + hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
11059 + /* Write the relevant command block into the ram area. */
11060 + for (i = 0; i < length; i++) {
11061 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
11062 + *((u32 *) hdr + i));
11063 + E1000_WRITE_FLUSH(hw);
11066 + return E1000_SUCCESS;
11070 + * e1000_mng_host_if_write_generic - Write to the manageability host interface
11071 + * @hw: pointer to the HW structure
11072 + * @buffer: pointer to the host interface buffer
11073 + * @length: size of the buffer
11074 + * @offset: location in the buffer to write to
11075 + * @sum: sum of the data (not checksum)
11077 + * This function writes the buffer content at the offset given on the host if.
11078 + * It also does alignment considerations to do the writes in most efficient
11079 + * way. Also fills up the sum of the buffer in *buffer parameter.
11081 +s32 e1000_mng_host_if_write_generic(struct e1000_hw * hw, u8 *buffer,
11082 + u16 length, u16 offset, u8 *sum)
11085 + u8 *bufptr = buffer;
11087 + s32 ret_val = E1000_SUCCESS;
11088 + u16 remaining, i, j, prev_bytes;
11090 + DEBUGFUNC("e1000_mng_host_if_write_generic");
11092 + /* sum = only sum of the data and it is not checksum */
11094 + if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
11095 + ret_val = -E1000_ERR_PARAM;
11099 + tmp = (u8 *)&data;
11100 + prev_bytes = offset & 0x3;
11103 + if (prev_bytes) {
11104 + data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
11105 + for (j = prev_bytes; j < sizeof(u32); j++) {
11106 + *(tmp + j) = *bufptr++;
11107 + *sum += *(tmp + j);
11109 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
11110 + length -= j - prev_bytes;
11114 + remaining = length & 0x3;
11115 + length -= remaining;
11117 + /* Calculate length in DWORDs */
11121 + * The device driver writes the relevant command block into the
11124 + for (i = 0; i < length; i++) {
11125 + for (j = 0; j < sizeof(u32); j++) {
11126 + *(tmp + j) = *bufptr++;
11127 + *sum += *(tmp + j);
11130 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
11133 + for (j = 0; j < sizeof(u32); j++) {
11134 + if (j < remaining)
11135 + *(tmp + j) = *bufptr++;
11139 + *sum += *(tmp + j);
11141 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
11149 + * e1000_enable_mng_pass_thru - Enable processing of ARP's
11150 + * @hw: pointer to the HW structure
11152 + * Verifies the hardware needs to allow ARPs to be processed by the host.
11154 +bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
11157 + u32 fwsm, factps;
11158 + bool ret_val = false;
11160 + DEBUGFUNC("e1000_enable_mng_pass_thru");
11162 + if (!hw->mac.asf_firmware_present)
11165 + manc = E1000_READ_REG(hw, E1000_MANC);
11167 + if (!(manc & E1000_MANC_RCV_TCO_EN) ||
11168 + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
11171 + if (hw->mac.arc_subsystem_valid) {
11172 + fwsm = E1000_READ_REG(hw, E1000_FWSM);
11173 + factps = E1000_READ_REG(hw, E1000_FACTPS);
11175 + if (!(factps & E1000_FACTPS_MNGCG) &&
11176 + ((fwsm & E1000_FWSM_MODE_MASK) ==
11177 + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
11182 + if ((manc & E1000_MANC_SMBUS_EN) &&
11183 + !(manc & E1000_MANC_ASF_EN)) {
11193 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h
11194 --- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h 1970-01-01 01:00:00.000000000 +0100
11195 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h 2008-10-14 01:51:32.000000000 +0200
11197 +/*******************************************************************************
11199 + Intel PRO/1000 Linux driver
11200 + Copyright(c) 1999 - 2008 Intel Corporation.
11202 + This program is free software; you can redistribute it and/or modify it
11203 + under the terms and conditions of the GNU General Public License,
11204 + version 2, as published by the Free Software Foundation.
11206 + This program is distributed in the hope it will be useful, but WITHOUT
11207 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11208 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11211 + You should have received a copy of the GNU General Public License along with
11212 + this program; if not, write to the Free Software Foundation, Inc.,
11213 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11215 + The full GNU General Public License is included in this distribution in
11216 + the file called "COPYING".
11218 + Contact Information:
11219 + Linux NICS <linux.nics@intel.com>
11220 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11221 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11223 +*******************************************************************************/
11225 +#ifndef _E1000_MANAGE_H_
11226 +#define _E1000_MANAGE_H_
11228 +bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
11229 +bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
11230 +s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
11231 +s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
11232 + u16 length, u16 offset, u8 *sum);
11233 +s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
11234 + struct e1000_host_mng_command_header *hdr);
11235 +s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
11236 + u8 *buffer, u16 length);
11237 +bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
11240 + e1000_mng_mode_none = 0,
11241 + e1000_mng_mode_asf,
11242 + e1000_mng_mode_pt,
11243 + e1000_mng_mode_ipmi,
11244 + e1000_mng_mode_host_if_only
11247 +#define E1000_FACTPS_MNGCG 0x20000000
11249 +#define E1000_FWSM_MODE_MASK 0xE
11250 +#define E1000_FWSM_MODE_SHIFT 1
11252 +#define E1000_MNG_IAMT_MODE 0x3
11253 +#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
11254 +#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
11255 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
11256 +#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
11257 +#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
11258 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
11260 +#define E1000_VFTA_ENTRY_SHIFT 5
11261 +#define E1000_VFTA_ENTRY_MASK 0x7F
11262 +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
11264 +#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
11265 +#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
11266 +#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
11268 +#define E1000_HICR_EN 0x01 /* Enable bit - RO */
11269 +/* Driver sets this bit when done to put command in RAM */
11270 +#define E1000_HICR_C 0x02
11271 +#define E1000_HICR_SV 0x04 /* Status Validity */
11272 +#define E1000_HICR_FW_RESET_ENABLE 0x40
11273 +#define E1000_HICR_FW_RESET 0x80
11275 +/* Intel(R) Active Management Technology signature */
11276 +#define E1000_IAMT_SIGNATURE 0x544D4149
11279 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c
11280 --- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c 1970-01-01 01:00:00.000000000 +0100
11281 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c 2008-10-14 01:51:32.000000000 +0200
11283 +/*******************************************************************************
11285 + Intel PRO/1000 Linux driver
11286 + Copyright(c) 1999 - 2008 Intel Corporation.
11288 + This program is free software; you can redistribute it and/or modify it
11289 + under the terms and conditions of the GNU General Public License,
11290 + version 2, as published by the Free Software Foundation.
11292 + This program is distributed in the hope it will be useful, but WITHOUT
11293 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11294 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11297 + You should have received a copy of the GNU General Public License along with
11298 + this program; if not, write to the Free Software Foundation, Inc.,
11299 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11301 + The full GNU General Public License is included in this distribution in
11302 + the file called "COPYING".
11304 + Contact Information:
11305 + Linux NICS <linux.nics@intel.com>
11306 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11307 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11309 +*******************************************************************************/
11311 +#include "e1000_hw.h"
11314 + * e1000_init_nvm_ops_generic - Initialize NVM function pointers
11315 + * @hw: pointer to the HW structure
11317 + * Setups up the function pointers to no-op functions
11319 +void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
11321 + struct e1000_nvm_info *nvm = &hw->nvm;
11322 + DEBUGFUNC("e1000_init_nvm_ops_generic");
11324 + /* Initialize function pointers */
11325 + nvm->ops.reload = e1000_reload_nvm_generic;
11329 + * e1000_raise_eec_clk - Raise EEPROM clock
11330 + * @hw: pointer to the HW structure
11331 + * @eecd: pointer to the EEPROM
11333 + * Enable/Raise the EEPROM clock bit.
11335 +static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
11337 + *eecd = *eecd | E1000_EECD_SK;
11338 + E1000_WRITE_REG(hw, E1000_EECD, *eecd);
11339 + E1000_WRITE_FLUSH(hw);
11340 + usec_delay(hw->nvm.delay_usec);
11344 + * e1000_lower_eec_clk - Lower EEPROM clock
11345 + * @hw: pointer to the HW structure
11346 + * @eecd: pointer to the EEPROM
11348 + * Clear/Lower the EEPROM clock bit.
11350 +static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
11352 + *eecd = *eecd & ~E1000_EECD_SK;
11353 + E1000_WRITE_REG(hw, E1000_EECD, *eecd);
11354 + E1000_WRITE_FLUSH(hw);
11355 + usec_delay(hw->nvm.delay_usec);
11359 + * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
11360 + * @hw: pointer to the HW structure
11361 + * @data: data to send to the EEPROM
11362 + * @count: number of bits to shift out
11364 + * We need to shift 'count' bits out to the EEPROM. So, the value in the
11365 + * "data" parameter will be shifted out to the EEPROM one bit at a time.
11366 + * In order to do this, "data" must be broken down into bits.
11368 +static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
11370 + struct e1000_nvm_info *nvm = &hw->nvm;
11371 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
11374 + DEBUGFUNC("e1000_shift_out_eec_bits");
11376 + mask = 0x01 << (count - 1);
11377 + if (nvm->type == e1000_nvm_eeprom_microwire)
11378 + eecd &= ~E1000_EECD_DO;
11379 + else if (nvm->type == e1000_nvm_eeprom_spi)
11380 + eecd |= E1000_EECD_DO;
11383 + eecd &= ~E1000_EECD_DI;
11386 + eecd |= E1000_EECD_DI;
11388 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11389 + E1000_WRITE_FLUSH(hw);
11391 + usec_delay(nvm->delay_usec);
11393 + e1000_raise_eec_clk(hw, &eecd);
11394 + e1000_lower_eec_clk(hw, &eecd);
11399 + eecd &= ~E1000_EECD_DI;
11400 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11404 + * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
11405 + * @hw: pointer to the HW structure
11406 + * @count: number of bits to shift in
11408 + * In order to read a register from the EEPROM, we need to shift 'count' bits
11409 + * in from the EEPROM. Bits are "shifted in" by raising the clock input to
11410 + * the EEPROM (setting the SK bit), and then reading the value of the data out
11411 + * "DO" bit. During this "shifting in" process the data in "DI" bit should
11412 + * always be clear.
11414 +static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
11420 + DEBUGFUNC("e1000_shift_in_eec_bits");
11422 + eecd = E1000_READ_REG(hw, E1000_EECD);
11424 + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
11427 + for (i = 0; i < count; i++) {
11429 + e1000_raise_eec_clk(hw, &eecd);
11431 + eecd = E1000_READ_REG(hw, E1000_EECD);
11433 + eecd &= ~E1000_EECD_DI;
11434 + if (eecd & E1000_EECD_DO)
11437 + e1000_lower_eec_clk(hw, &eecd);
11444 + * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
11445 + * @hw: pointer to the HW structure
11446 + * @ee_reg: EEPROM flag for polling
11448 + * Polls the EEPROM status bit for either read or write completion based
11449 + * upon the value of 'ee_reg'.
11451 +s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
11453 + u32 attempts = 100000;
11455 + s32 ret_val = -E1000_ERR_NVM;
11457 + DEBUGFUNC("e1000_poll_eerd_eewr_done");
11459 + for (i = 0; i < attempts; i++) {
11460 + if (ee_reg == E1000_NVM_POLL_READ)
11461 + reg = E1000_READ_REG(hw, E1000_EERD);
11463 + reg = E1000_READ_REG(hw, E1000_EEWR);
11465 + if (reg & E1000_NVM_RW_REG_DONE) {
11466 + ret_val = E1000_SUCCESS;
11477 + * e1000_acquire_nvm_generic - Generic request for access to EEPROM
11478 + * @hw: pointer to the HW structure
11480 + * Set the EEPROM access request bit and wait for EEPROM access grant bit.
11481 + * Return successful if access grant bit set, else clear the request for
11482 + * EEPROM access and return -E1000_ERR_NVM (-1).
11484 +s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
11486 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
11487 + s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
11488 + s32 ret_val = E1000_SUCCESS;
11490 + DEBUGFUNC("e1000_acquire_nvm_generic");
11492 + E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
11493 + eecd = E1000_READ_REG(hw, E1000_EECD);
11495 + while (timeout) {
11496 + if (eecd & E1000_EECD_GNT)
11499 + eecd = E1000_READ_REG(hw, E1000_EECD);
11504 + eecd &= ~E1000_EECD_REQ;
11505 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11506 + DEBUGOUT("Could not acquire NVM grant\n");
11507 + ret_val = -E1000_ERR_NVM;
11514 + * e1000_standby_nvm - Return EEPROM to standby state
11515 + * @hw: pointer to the HW structure
11517 + * Return the EEPROM to a standby state.
11519 +static void e1000_standby_nvm(struct e1000_hw *hw)
11521 + struct e1000_nvm_info *nvm = &hw->nvm;
11522 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
11524 + DEBUGFUNC("e1000_standby_nvm");
11526 + if (nvm->type == e1000_nvm_eeprom_microwire) {
11527 + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
11528 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11529 + E1000_WRITE_FLUSH(hw);
11530 + usec_delay(nvm->delay_usec);
11532 + e1000_raise_eec_clk(hw, &eecd);
11534 + /* Select EEPROM */
11535 + eecd |= E1000_EECD_CS;
11536 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11537 + E1000_WRITE_FLUSH(hw);
11538 + usec_delay(nvm->delay_usec);
11540 + e1000_lower_eec_clk(hw, &eecd);
11541 + } else if (nvm->type == e1000_nvm_eeprom_spi) {
11542 + /* Toggle CS to flush commands */
11543 + eecd |= E1000_EECD_CS;
11544 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11545 + E1000_WRITE_FLUSH(hw);
11546 + usec_delay(nvm->delay_usec);
11547 + eecd &= ~E1000_EECD_CS;
11548 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11549 + E1000_WRITE_FLUSH(hw);
11550 + usec_delay(nvm->delay_usec);
11555 + * e1000_stop_nvm - Terminate EEPROM command
11556 + * @hw: pointer to the HW structure
11558 + * Terminates the current command by inverting the EEPROM's chip select pin.
11560 +void e1000_stop_nvm(struct e1000_hw *hw)
11564 + DEBUGFUNC("e1000_stop_nvm");
11566 + eecd = E1000_READ_REG(hw, E1000_EECD);
11567 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
11568 + /* Pull CS high */
11569 + eecd |= E1000_EECD_CS;
11570 + e1000_lower_eec_clk(hw, &eecd);
11571 + } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
11572 + /* CS on Microwire is active-high */
11573 + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
11574 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11575 + e1000_raise_eec_clk(hw, &eecd);
11576 + e1000_lower_eec_clk(hw, &eecd);
11581 + * e1000_release_nvm_generic - Release exclusive access to EEPROM
11582 + * @hw: pointer to the HW structure
11584 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
11586 +void e1000_release_nvm_generic(struct e1000_hw *hw)
11590 + DEBUGFUNC("e1000_release_nvm_generic");
11592 + e1000_stop_nvm(hw);
11594 + eecd = E1000_READ_REG(hw, E1000_EECD);
11595 + eecd &= ~E1000_EECD_REQ;
11596 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11600 + * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
11601 + * @hw: pointer to the HW structure
11603 + * Setups the EEPROM for reading and writing.
11605 +static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
11607 + struct e1000_nvm_info *nvm = &hw->nvm;
11608 + u32 eecd = E1000_READ_REG(hw, E1000_EECD);
11609 + s32 ret_val = E1000_SUCCESS;
11613 + DEBUGFUNC("e1000_ready_nvm_eeprom");
11615 + if (nvm->type == e1000_nvm_eeprom_microwire) {
11616 + /* Clear SK and DI */
11617 + eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
11618 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11620 + eecd |= E1000_EECD_CS;
11621 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11622 + } else if (nvm->type == e1000_nvm_eeprom_spi) {
11623 + /* Clear SK and CS */
11624 + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
11625 + E1000_WRITE_REG(hw, E1000_EECD, eecd);
11627 + timeout = NVM_MAX_RETRY_SPI;
11630 + * Read "Status Register" repeatedly until the LSB is cleared.
11631 + * The EEPROM will signal that the command has been completed
11632 + * by clearing bit 0 of the internal status register. If it's
11633 + * not cleared within 'timeout', then error out.
11635 + while (timeout) {
11636 + e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
11637 + hw->nvm.opcode_bits);
11638 + spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
11639 + if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
11643 + e1000_standby_nvm(hw);
11648 + DEBUGOUT("SPI NVM Status error\n");
11649 + ret_val = -E1000_ERR_NVM;
11659 + * e1000_read_nvm_spi - Read EEPROM's using SPI
11660 + * @hw: pointer to the HW structure
11661 + * @offset: offset of word in the EEPROM to read
11662 + * @words: number of words to read
11663 + * @data: word read from the EEPROM
11665 + * Reads a 16 bit word from the EEPROM.
11667 +s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
11669 + struct e1000_nvm_info *nvm = &hw->nvm;
11673 + u8 read_opcode = NVM_READ_OPCODE_SPI;
11675 + DEBUGFUNC("e1000_read_nvm_spi");
11678 + * A check for invalid values: offset too large, too many words,
11679 + * and not enough words.
11681 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11683 + DEBUGOUT("nvm parameter(s) out of bounds\n");
11684 + ret_val = -E1000_ERR_NVM;
11688 + ret_val = nvm->ops.acquire(hw);
11692 + ret_val = e1000_ready_nvm_eeprom(hw);
11696 + e1000_standby_nvm(hw);
11698 + if ((nvm->address_bits == 8) && (offset >= 128))
11699 + read_opcode |= NVM_A8_OPCODE_SPI;
11701 + /* Send the READ command (opcode + addr) */
11702 + e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
11703 + e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
11706 + * Read the data. SPI NVMs increment the address with each byte
11707 + * read and will roll over if reading beyond the end. This allows
11708 + * us to read the whole NVM from any offset
11710 + for (i = 0; i < words; i++) {
11711 + word_in = e1000_shift_in_eec_bits(hw, 16);
11712 + data[i] = (word_in >> 8) | (word_in << 8);
11716 + nvm->ops.release(hw);
11723 + * e1000_read_nvm_microwire - Reads EEPROM's using microwire
11724 + * @hw: pointer to the HW structure
11725 + * @offset: offset of word in the EEPROM to read
11726 + * @words: number of words to read
11727 + * @data: word read from the EEPROM
11729 + * Reads a 16 bit word from the EEPROM.
11731 +s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
11734 + struct e1000_nvm_info *nvm = &hw->nvm;
11737 + u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
11739 + DEBUGFUNC("e1000_read_nvm_microwire");
11742 + * A check for invalid values: offset too large, too many words,
11743 + * and not enough words.
11745 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11747 + DEBUGOUT("nvm parameter(s) out of bounds\n");
11748 + ret_val = -E1000_ERR_NVM;
11752 + ret_val = nvm->ops.acquire(hw);
11756 + ret_val = e1000_ready_nvm_eeprom(hw);
11760 + for (i = 0; i < words; i++) {
11761 + /* Send the READ command (opcode + addr) */
11762 + e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
11763 + e1000_shift_out_eec_bits(hw, (u16)(offset + i),
11764 + nvm->address_bits);
11767 + * Read the data. For microwire, each word requires the
11768 + * overhead of setup and tear-down.
11770 + data[i] = e1000_shift_in_eec_bits(hw, 16);
11771 + e1000_standby_nvm(hw);
11775 + nvm->ops.release(hw);
11782 + * e1000_read_nvm_eerd - Reads EEPROM using EERD register
11783 + * @hw: pointer to the HW structure
11784 + * @offset: offset of word in the EEPROM to read
11785 + * @words: number of words to read
11786 + * @data: word read from the EEPROM
11788 + * Reads a 16 bit word from the EEPROM using the EERD register.
11790 +s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
11792 + struct e1000_nvm_info *nvm = &hw->nvm;
11794 + s32 ret_val = E1000_SUCCESS;
11796 + DEBUGFUNC("e1000_read_nvm_eerd");
11799 + * A check for invalid values: offset too large, too many words,
11800 + * too many words for the offset, and not enough words.
11802 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11804 + DEBUGOUT("nvm parameter(s) out of bounds\n");
11805 + ret_val = -E1000_ERR_NVM;
11809 + for (i = 0; i < words; i++) {
11810 + eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
11811 + E1000_NVM_RW_REG_START;
11813 + E1000_WRITE_REG(hw, E1000_EERD, eerd);
11814 + ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
11818 + data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
11819 + E1000_NVM_RW_REG_DATA);
11827 + * e1000_write_nvm_spi - Write to EEPROM using SPI
11828 + * @hw: pointer to the HW structure
11829 + * @offset: offset within the EEPROM to be written to
11830 + * @words: number of words to write
11831 + * @data: 16 bit word(s) to be written to the EEPROM
11833 + * Writes data to EEPROM at offset using SPI interface.
11835 + * If e1000_update_nvm_checksum is not called after this function , the
11836 + * EEPROM will most likely contain an invalid checksum.
11838 +s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
11840 + struct e1000_nvm_info *nvm = &hw->nvm;
11844 + DEBUGFUNC("e1000_write_nvm_spi");
11847 + * A check for invalid values: offset too large, too many words,
11848 + * and not enough words.
11850 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11852 + DEBUGOUT("nvm parameter(s) out of bounds\n");
11853 + ret_val = -E1000_ERR_NVM;
11857 + ret_val = nvm->ops.acquire(hw);
11861 + while (widx < words) {
11862 + u8 write_opcode = NVM_WRITE_OPCODE_SPI;
11864 + ret_val = e1000_ready_nvm_eeprom(hw);
11868 + e1000_standby_nvm(hw);
11870 + /* Send the WRITE ENABLE command (8 bit opcode) */
11871 + e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
11872 + nvm->opcode_bits);
11874 + e1000_standby_nvm(hw);
11877 + * Some SPI eeproms use the 8th address bit embedded in the
11880 + if ((nvm->address_bits == 8) && (offset >= 128))
11881 + write_opcode |= NVM_A8_OPCODE_SPI;
11883 + /* Send the Write command (8-bit opcode + addr) */
11884 + e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
11885 + e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
11886 + nvm->address_bits);
11888 + /* Loop to allow for up to whole page write of eeprom */
11889 + while (widx < words) {
11890 + u16 word_out = data[widx];
11891 + word_out = (word_out >> 8) | (word_out << 8);
11892 + e1000_shift_out_eec_bits(hw, word_out, 16);
11895 + if ((((offset + widx) * 2) % nvm->page_size) == 0) {
11896 + e1000_standby_nvm(hw);
11902 + msec_delay(nvm->semaphore_delay);
11904 + nvm->ops.release(hw);
11911 + * e1000_write_nvm_microwire - Writes EEPROM using microwire
11912 + * @hw: pointer to the HW structure
11913 + * @offset: offset within the EEPROM to be written to
11914 + * @words: number of words to write
11915 + * @data: 16 bit word(s) to be written to the EEPROM
11917 + * Writes data to EEPROM at offset using microwire interface.
11919 + * If e1000_update_nvm_checksum is not called after this function , the
11920 + * EEPROM will most likely contain an invalid checksum.
11922 +s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
11925 + struct e1000_nvm_info *nvm = &hw->nvm;
11928 + u16 words_written = 0;
11931 + DEBUGFUNC("e1000_write_nvm_microwire");
11934 + * A check for invalid values: offset too large, too many words,
11935 + * and not enough words.
11937 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11939 + DEBUGOUT("nvm parameter(s) out of bounds\n");
11940 + ret_val = -E1000_ERR_NVM;
11944 + ret_val = nvm->ops.acquire(hw);
11948 + ret_val = e1000_ready_nvm_eeprom(hw);
11952 + e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
11953 + (u16)(nvm->opcode_bits + 2));
11955 + e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
11957 + e1000_standby_nvm(hw);
11959 + while (words_written < words) {
11960 + e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
11961 + nvm->opcode_bits);
11963 + e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
11964 + nvm->address_bits);
11966 + e1000_shift_out_eec_bits(hw, data[words_written], 16);
11968 + e1000_standby_nvm(hw);
11970 + for (widx = 0; widx < 200; widx++) {
11971 + eecd = E1000_READ_REG(hw, E1000_EECD);
11972 + if (eecd & E1000_EECD_DO)
11977 + if (widx == 200) {
11978 + DEBUGOUT("NVM Write did not complete\n");
11979 + ret_val = -E1000_ERR_NVM;
11983 + e1000_standby_nvm(hw);
11988 + e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
11989 + (u16)(nvm->opcode_bits + 2));
11991 + e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
11994 + nvm->ops.release(hw);
12001 + * e1000_read_pba_num_generic - Read device part number
12002 + * @hw: pointer to the HW structure
12003 + * @pba_num: pointer to device part number
12005 + * Reads the product board assembly (PBA) number from the EEPROM and stores
12006 + * the value in pba_num.
12008 +s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
12013 + DEBUGFUNC("e1000_read_pba_num_generic");
12015 + ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
12017 + DEBUGOUT("NVM Read Error\n");
12020 + *pba_num = (u32)(nvm_data << 16);
12022 + ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
12024 + DEBUGOUT("NVM Read Error\n");
12027 + *pba_num |= nvm_data;
12034 + * e1000_read_mac_addr_generic - Read device MAC address
12035 + * @hw: pointer to the HW structure
12037 + * Reads the device MAC address from the EEPROM and stores the value.
12038 + * Since devices with two ports use the same EEPROM, we increment the
12039 + * last bit in the MAC address for the second port.
12041 +s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
12043 + s32 ret_val = E1000_SUCCESS;
12044 + u16 offset, nvm_data, i;
12046 + DEBUGFUNC("e1000_read_mac_addr");
12048 + for (i = 0; i < ETH_ADDR_LEN; i += 2) {
12050 + ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
12052 + DEBUGOUT("NVM Read Error\n");
12055 + hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
12056 + hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
12059 + /* Flip last bit of mac address if we're on second port */
12060 + if (hw->bus.func == E1000_FUNC_1)
12061 + hw->mac.perm_addr[5] ^= 1;
12063 + for (i = 0; i < ETH_ADDR_LEN; i++)
12064 + hw->mac.addr[i] = hw->mac.perm_addr[i];
12071 + * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
12072 + * @hw: pointer to the HW structure
12074 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
12075 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
12077 +s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
12079 + s32 ret_val = E1000_SUCCESS;
12080 + u16 checksum = 0;
12083 + DEBUGFUNC("e1000_validate_nvm_checksum_generic");
12085 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
12086 + ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
12088 + DEBUGOUT("NVM Read Error\n");
12091 + checksum += nvm_data;
12094 + if (checksum != (u16) NVM_SUM) {
12095 + DEBUGOUT("NVM Checksum Invalid\n");
12096 + ret_val = -E1000_ERR_NVM;
12105 + * e1000_update_nvm_checksum_generic - Update EEPROM checksum
12106 + * @hw: pointer to the HW structure
12108 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
12109 + * up to the checksum. Then calculates the EEPROM checksum and writes the
12110 + * value to the EEPROM.
12112 +s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
12115 + u16 checksum = 0;
12118 + DEBUGFUNC("e1000_update_nvm_checksum");
12120 + for (i = 0; i < NVM_CHECKSUM_REG; i++) {
12121 + ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
12123 + DEBUGOUT("NVM Read Error while updating checksum.\n");
12126 + checksum += nvm_data;
12128 + checksum = (u16) NVM_SUM - checksum;
12129 + ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
12131 + DEBUGOUT("NVM Write Error while updating checksum.\n");
12139 + * e1000_reload_nvm_generic - Reloads EEPROM
12140 + * @hw: pointer to the HW structure
12142 + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
12143 + * extended control register.
12145 +void e1000_reload_nvm_generic(struct e1000_hw *hw)
12149 + DEBUGFUNC("e1000_reload_nvm_generic");
12152 + ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
12153 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
12154 + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
12155 + E1000_WRITE_FLUSH(hw);
12158 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h
12159 --- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h 1970-01-01 01:00:00.000000000 +0100
12160 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h 2008-10-14 01:51:32.000000000 +0200
12162 +/*******************************************************************************
12164 + Intel PRO/1000 Linux driver
12165 + Copyright(c) 1999 - 2008 Intel Corporation.
12167 + This program is free software; you can redistribute it and/or modify it
12168 + under the terms and conditions of the GNU General Public License,
12169 + version 2, as published by the Free Software Foundation.
12171 + This program is distributed in the hope it will be useful, but WITHOUT
12172 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12173 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12176 + You should have received a copy of the GNU General Public License along with
12177 + this program; if not, write to the Free Software Foundation, Inc.,
12178 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
12180 + The full GNU General Public License is included in this distribution in
12181 + the file called "COPYING".
12183 + Contact Information:
12184 + Linux NICS <linux.nics@intel.com>
12185 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
12186 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12188 +*******************************************************************************/
12190 +#ifndef _E1000_NVM_H_
12191 +#define _E1000_NVM_H_
12193 +void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
12194 +s32 e1000_acquire_nvm_generic(struct e1000_hw *hw);
12196 +s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
12197 +s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
12198 +s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
12199 +s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
12200 +s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
12201 + u16 words, u16 *data);
12202 +s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
12204 +s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
12205 +s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);
12206 +s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
12207 + u16 words, u16 *data);
12208 +s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,
12209 + u16 words, u16 *data);
12210 +s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
12212 +s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
12213 +void e1000_stop_nvm(struct e1000_hw *hw);
12214 +void e1000_release_nvm_generic(struct e1000_hw *hw);
12215 +void e1000_reload_nvm_generic(struct e1000_hw *hw);
12217 +#define E1000_STM_OPCODE 0xDB00
12220 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_osdep.h linux-2.6.22-10/drivers/net/e1000e/e1000_osdep.h
12221 --- linux-2.6.22-0/drivers/net/e1000e/e1000_osdep.h 1970-01-01 01:00:00.000000000 +0100
12222 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_osdep.h 2008-10-14 01:51:32.000000000 +0200
12224 +/*******************************************************************************
12226 + Intel PRO/1000 Linux driver
12227 + Copyright(c) 1999 - 2008 Intel Corporation.
12229 + This program is free software; you can redistribute it and/or modify it
12230 + under the terms and conditions of the GNU General Public License,
12231 + version 2, as published by the Free Software Foundation.
12233 + This program is distributed in the hope it will be useful, but WITHOUT
12234 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12235 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12238 + You should have received a copy of the GNU General Public License along with
12239 + this program; if not, write to the Free Software Foundation, Inc.,
12240 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
12242 + The full GNU General Public License is included in this distribution in
12243 + the file called "COPYING".
12245 + Contact Information:
12246 + Linux NICS <linux.nics@intel.com>
12247 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
12248 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12250 +*******************************************************************************/
12253 +/* glue for the OS-dependent part of e1000
12254 + * includes register access macros
12257 +#ifndef _E1000_OSDEP_H_
12258 +#define _E1000_OSDEP_H_
12260 +#include <linux/pci.h>
12261 +#include <linux/delay.h>
12262 +#include <linux/interrupt.h>
12263 +#include <linux/if_ether.h>
12265 +#include "kcompat.h"
12267 +#define usec_delay(x) udelay(x)
12268 +#ifndef msec_delay
12269 +#define msec_delay(x) do { if(in_interrupt()) { \
12270 + /* Don't sleep in interrupt context! */ \
12276 +/* Some workarounds require millisecond delays and are run during interrupt
12277 + * context. Most notably, when establishing link, the phy may need tweaking
12278 + * but cannot process phy register reads/writes faster than millisecond
12279 + * intervals...and we establish link due to a "link status change" interrupt.
12281 +#define msec_delay_irq(x) mdelay(x)
12284 +#define PCI_COMMAND_REGISTER PCI_COMMAND
12285 +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
12286 +#define ETH_ADDR_LEN ETH_ALEN
12289 +#define DEBUGOUT(S)
12290 +#define DEBUGOUT1(S, A...)
12292 +#define DEBUGFUNC(F) DEBUGOUT(F "\n")
12293 +#define DEBUGOUT2 DEBUGOUT1
12294 +#define DEBUGOUT3 DEBUGOUT2
12295 +#define DEBUGOUT7 DEBUGOUT3
12297 +#define E1000_WRITE_REG(a, reg, value) ( \
12298 + writel((value), ((a)->hw_addr + reg)))
12300 +#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
12302 +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
12303 + writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
12305 +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
12306 + readl((a)->hw_addr + reg + ((offset) << 2)))
12308 +#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
12309 +#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
12311 +#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
12312 + writew((value), ((a)->hw_addr + reg + ((offset) << 1))))
12314 +#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
12315 + readw((a)->hw_addr + reg + ((offset) << 1)))
12317 +#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
12318 + writeb((value), ((a)->hw_addr + reg + (offset))))
12320 +#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
12321 + readb((a)->hw_addr + reg + (offset)))
12323 +#define E1000_WRITE_REG_IO(a, reg, offset) do { \
12324 + outl(reg, ((a)->io_base)); \
12325 + outl(offset, ((a)->io_base + 4)); } while(0)
12327 +#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
12329 +#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
12330 + writel((value), ((a)->flash_address + reg)))
12332 +#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
12333 + writew((value), ((a)->flash_address + reg)))
12335 +#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
12337 +#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
12339 +#endif /* _E1000_OSDEP_H_ */
12340 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c
12341 --- linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c 1970-01-01 01:00:00.000000000 +0100
12342 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c 2008-10-14 01:51:32.000000000 +0200
12344 +/*******************************************************************************
12346 + Intel PRO/1000 Linux driver
12347 + Copyright(c) 1999 - 2008 Intel Corporation.
12349 + This program is free software; you can redistribute it and/or modify it
12350 + under the terms and conditions of the GNU General Public License,
12351 + version 2, as published by the Free Software Foundation.
12353 + This program is distributed in the hope it will be useful, but WITHOUT
12354 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12355 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12358 + You should have received a copy of the GNU General Public License along with
12359 + this program; if not, write to the Free Software Foundation, Inc.,
12360 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
12362 + The full GNU General Public License is included in this distribution in
12363 + the file called "COPYING".
12365 + Contact Information:
12366 + Linux NICS <linux.nics@intel.com>
12367 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
12368 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12370 +*******************************************************************************/
12372 +#include "e1000_hw.h"
12374 +static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
12375 +/* Cable length tables */
12376 +static const u16 e1000_m88_cable_length_table[] =
12377 + { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
12378 +#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
12379 + (sizeof(e1000_m88_cable_length_table) / \
12380 + sizeof(e1000_m88_cable_length_table[0]))
12382 +static const u16 e1000_igp_2_cable_length_table[] =
12383 + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
12384 + 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
12385 + 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
12386 + 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
12387 + 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
12388 + 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
12389 + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
12390 + 104, 109, 114, 118, 121, 124};
12391 +#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
12392 + (sizeof(e1000_igp_2_cable_length_table) / \
12393 + sizeof(e1000_igp_2_cable_length_table[0]))
12396 + * e1000_check_reset_block_generic - Check if PHY reset is blocked
12397 + * @hw: pointer to the HW structure
12399 + * Read the PHY management control register and check whether a PHY reset
12400 + * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
12401 + * return E1000_BLK_PHY_RESET (12).
12403 +s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
12407 + DEBUGFUNC("e1000_check_reset_block");
12409 + manc = E1000_READ_REG(hw, E1000_MANC);
12411 + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
12412 + E1000_BLK_PHY_RESET : E1000_SUCCESS;
12416 + * e1000_get_phy_id - Retrieve the PHY ID and revision
12417 + * @hw: pointer to the HW structure
12419 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
12420 + * revision in the hardware structure.
12422 +s32 e1000_get_phy_id(struct e1000_hw *hw)
12424 + struct e1000_phy_info *phy = &hw->phy;
12425 + s32 ret_val = E1000_SUCCESS;
12428 + DEBUGFUNC("e1000_get_phy_id");
12430 + if (!(phy->ops.read_reg))
12433 + ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
12437 + phy->id = (u32)(phy_id << 16);
12439 + ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
12443 + phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
12444 + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
12451 + * e1000_phy_reset_dsp_generic - Reset PHY DSP
12452 + * @hw: pointer to the HW structure
12454 + * Reset the digital signal processor.
12456 +s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
12458 + s32 ret_val = E1000_SUCCESS;
12460 + DEBUGFUNC("e1000_phy_reset_dsp_generic");
12462 + if (!(hw->phy.ops.write_reg))
12465 + ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
12469 + ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
12476 + * e1000_read_phy_reg_mdic - Read MDI control register
12477 + * @hw: pointer to the HW structure
12478 + * @offset: register offset to be read
12479 + * @data: pointer to the read data
12481 + * Reads the MDI control register in the PHY at offset and stores the
12482 + * information read to data.
12484 +s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
12486 + struct e1000_phy_info *phy = &hw->phy;
12488 + s32 ret_val = E1000_SUCCESS;
12490 + DEBUGFUNC("e1000_read_phy_reg_mdic");
12493 + * Set up Op-code, Phy Address, and register offset in the MDI
12494 + * Control register. The MAC will take care of interfacing with the
12495 + * PHY to retrieve the desired data.
12497 + mdic = ((offset << E1000_MDIC_REG_SHIFT) |
12498 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
12499 + (E1000_MDIC_OP_READ));
12501 + E1000_WRITE_REG(hw, E1000_MDIC, mdic);
12504 + * Poll the ready bit to see if the MDI read completed
12505 + * Increasing the time out as testing showed failures with
12506 + * the lower time out
12508 + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
12510 + mdic = E1000_READ_REG(hw, E1000_MDIC);
12511 + if (mdic & E1000_MDIC_READY)
12514 + if (!(mdic & E1000_MDIC_READY)) {
12515 + DEBUGOUT("MDI Read did not complete\n");
12516 + ret_val = -E1000_ERR_PHY;
12519 + if (mdic & E1000_MDIC_ERROR) {
12520 + DEBUGOUT("MDI Error\n");
12521 + ret_val = -E1000_ERR_PHY;
12524 + *data = (u16) mdic;
12531 + * e1000_write_phy_reg_mdic - Write MDI control register
12532 + * @hw: pointer to the HW structure
12533 + * @offset: register offset to write to
12534 + * @data: data to write to register at offset
12536 + * Writes data to MDI control register in the PHY at offset.
12538 +s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
12540 + struct e1000_phy_info *phy = &hw->phy;
12542 + s32 ret_val = E1000_SUCCESS;
12544 + DEBUGFUNC("e1000_write_phy_reg_mdic");
12547 + * Set up Op-code, Phy Address, and register offset in the MDI
12548 + * Control register. The MAC will take care of interfacing with the
12549 + * PHY to retrieve the desired data.
12551 + mdic = (((u32)data) |
12552 + (offset << E1000_MDIC_REG_SHIFT) |
12553 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
12554 + (E1000_MDIC_OP_WRITE));
12556 + E1000_WRITE_REG(hw, E1000_MDIC, mdic);
12559 + * Poll the ready bit to see if the MDI read completed
12560 + * Increasing the time out as testing showed failures with
12561 + * the lower time out
12563 + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
12565 + mdic = E1000_READ_REG(hw, E1000_MDIC);
12566 + if (mdic & E1000_MDIC_READY)
12569 + if (!(mdic & E1000_MDIC_READY)) {
12570 + DEBUGOUT("MDI Write did not complete\n");
12571 + ret_val = -E1000_ERR_PHY;
12574 + if (mdic & E1000_MDIC_ERROR) {
12575 + DEBUGOUT("MDI Error\n");
12576 + ret_val = -E1000_ERR_PHY;
12585 + * e1000_read_phy_reg_m88 - Read m88 PHY register
12586 + * @hw: pointer to the HW structure
12587 + * @offset: register offset to be read
12588 + * @data: pointer to the read data
12590 + * Acquires semaphore, if necessary, then reads the PHY register at offset
12591 + * and storing the retrieved information in data. Release any acquired
12592 + * semaphores before exiting.
12594 +s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
12596 + s32 ret_val = E1000_SUCCESS;
12598 + DEBUGFUNC("e1000_read_phy_reg_m88");
12600 + if (!(hw->phy.ops.acquire))
12603 + ret_val = hw->phy.ops.acquire(hw);
12607 + ret_val = e1000_read_phy_reg_mdic(hw,
12608 + MAX_PHY_REG_ADDRESS & offset,
12611 + hw->phy.ops.release(hw);
12618 + * e1000_write_phy_reg_m88 - Write m88 PHY register
12619 + * @hw: pointer to the HW structure
12620 + * @offset: register offset to write to
12621 + * @data: data to write at register offset
12623 + * Acquires semaphore, if necessary, then writes the data to PHY register
12624 + * at the offset. Release any acquired semaphores before exiting.
12626 +s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
12628 + s32 ret_val = E1000_SUCCESS;
12630 + DEBUGFUNC("e1000_write_phy_reg_m88");
12632 + if (!(hw->phy.ops.acquire))
12635 + ret_val = hw->phy.ops.acquire(hw);
12639 + ret_val = e1000_write_phy_reg_mdic(hw,
12640 + MAX_PHY_REG_ADDRESS & offset,
12643 + hw->phy.ops.release(hw);
12650 + * e1000_read_phy_reg_igp - Read igp PHY register
12651 + * @hw: pointer to the HW structure
12652 + * @offset: register offset to be read
12653 + * @data: pointer to the read data
12655 + * Acquires semaphore, if necessary, then reads the PHY register at offset
12656 + * and storing the retrieved information in data. Release any acquired
12657 + * semaphores before exiting.
12659 +s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
12661 + s32 ret_val = E1000_SUCCESS;
12663 + DEBUGFUNC("e1000_read_phy_reg_igp");
12665 + if (!(hw->phy.ops.acquire))
12668 + ret_val = hw->phy.ops.acquire(hw);
12672 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
12673 + ret_val = e1000_write_phy_reg_mdic(hw,
12674 + IGP01E1000_PHY_PAGE_SELECT,
12677 + hw->phy.ops.release(hw);
12682 + ret_val = e1000_read_phy_reg_mdic(hw,
12683 + MAX_PHY_REG_ADDRESS & offset,
12686 + hw->phy.ops.release(hw);
12693 + * e1000_write_phy_reg_igp - Write igp PHY register
12694 + * @hw: pointer to the HW structure
12695 + * @offset: register offset to write to
12696 + * @data: data to write at register offset
12698 + * Acquires semaphore, if necessary, then writes the data to PHY register
12699 + * at the offset. Release any acquired semaphores before exiting.
12701 +s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
12703 + s32 ret_val = E1000_SUCCESS;
12705 + DEBUGFUNC("e1000_write_phy_reg_igp");
12707 + if (!(hw->phy.ops.acquire))
12710 + ret_val = hw->phy.ops.acquire(hw);
12714 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
12715 + ret_val = e1000_write_phy_reg_mdic(hw,
12716 + IGP01E1000_PHY_PAGE_SELECT,
12719 + hw->phy.ops.release(hw);
12724 + ret_val = e1000_write_phy_reg_mdic(hw,
12725 + MAX_PHY_REG_ADDRESS & offset,
12728 + hw->phy.ops.release(hw);
12735 + * e1000_read_kmrn_reg_generic - Read kumeran register
12736 + * @hw: pointer to the HW structure
12737 + * @offset: register offset to be read
12738 + * @data: pointer to the read data
12740 + * Acquires semaphore, if necessary. Then reads the PHY register at offset
12741 + * using the kumeran interface. The information retrieved is stored in data.
12742 + * Release any acquired semaphores before exiting.
12744 +s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
12747 + s32 ret_val = E1000_SUCCESS;
12749 + DEBUGFUNC("e1000_read_kmrn_reg_generic");
12751 + if (!(hw->phy.ops.acquire))
12754 + ret_val = hw->phy.ops.acquire(hw);
12758 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
12759 + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
12760 + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
12764 + kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
12765 + *data = (u16)kmrnctrlsta;
12767 + hw->phy.ops.release(hw);
12774 + * e1000_write_kmrn_reg_generic - Write kumeran register
12775 + * @hw: pointer to the HW structure
12776 + * @offset: register offset to write to
12777 + * @data: data to write at register offset
12779 + * Acquires semaphore, if necessary. Then write the data to PHY register
12780 + * at the offset using the kumeran interface. Release any acquired semaphores
12781 + * before exiting.
12783 +s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
12786 + s32 ret_val = E1000_SUCCESS;
12788 + DEBUGFUNC("e1000_write_kmrn_reg_generic");
12790 + if (!(hw->phy.ops.acquire))
12793 + ret_val = hw->phy.ops.acquire(hw);
12797 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
12798 + E1000_KMRNCTRLSTA_OFFSET) | data;
12799 + E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
12802 + hw->phy.ops.release(hw);
12809 + * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
12810 + * @hw: pointer to the HW structure
12812 + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
12813 + * and downshift values are set also.
12815 +s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
12817 + struct e1000_phy_info *phy = &hw->phy;
12821 + DEBUGFUNC("e1000_copper_link_setup_m88");
12823 + if (phy->reset_disable) {
12824 + ret_val = E1000_SUCCESS;
12828 + /* Enable CRS on TX. This must be set for half-duplex operation. */
12829 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
12833 + /* For newer PHYs this bit is downshift enable */
12834 + if (phy->type == e1000_phy_m88)
12835 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
12839 + * MDI/MDI-X = 0 (default)
12840 + * 0 - Auto for all speeds
12843 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
12845 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
12847 + switch (phy->mdix) {
12849 + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
12852 + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
12855 + phy_data |= M88E1000_PSCR_AUTO_X_1000T;
12859 + phy_data |= M88E1000_PSCR_AUTO_X_MODE;
12865 + * disable_polarity_correction = 0 (default)
12866 + * Automatic Correction for Reversed Cable Polarity
12870 + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
12871 + if (phy->disable_polarity_correction == 1)
12872 + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
12874 + /* Enable downshift on BM (disabled by default) */
12875 + if (phy->type == e1000_phy_bm)
12876 + phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
12878 + ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
12882 + if ((phy->type == e1000_phy_m88) &&
12883 + (phy->revision < E1000_REVISION_4) &&
12884 + (phy->id != BME1000_E_PHY_ID_R2)) {
12886 + * Force TX_CLK in the Extended PHY Specific Control Register
12887 + * to 25MHz clock.
12889 + ret_val = phy->ops.read_reg(hw,
12890 + M88E1000_EXT_PHY_SPEC_CTRL,
12895 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
12897 + if ((phy->revision == E1000_REVISION_2) &&
12898 + (phy->id == M88E1111_I_PHY_ID)) {
12899 + /* 82573L PHY - set the downshift counter to 5x. */
12900 + phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
12901 + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
12903 + /* Configure Master and Slave downshift values */
12904 + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
12905 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
12906 + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
12907 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
12909 + ret_val = phy->ops.write_reg(hw,
12910 + M88E1000_EXT_PHY_SPEC_CTRL,
12916 + if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
12917 + /* Set PHY page 0, register 29 to 0x0003 */
12918 + ret_val = phy->ops.write_reg(hw, 29, 0x0003);
12922 + /* Set PHY page 0, register 30 to 0x0000 */
12923 + ret_val = phy->ops.write_reg(hw, 30, 0x0000);
12928 + /* Commit the changes. */
12929 + ret_val = phy->ops.commit(hw);
12931 + DEBUGOUT("Error committing the PHY changes\n");
12940 + * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
12941 + * @hw: pointer to the HW structure
12943 + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
12946 +s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
12948 + struct e1000_phy_info *phy = &hw->phy;
12952 + DEBUGFUNC("e1000_copper_link_setup_igp");
12954 + if (phy->reset_disable) {
12955 + ret_val = E1000_SUCCESS;
12959 + ret_val = hw->phy.ops.reset(hw);
12961 + DEBUGOUT("Error resetting the PHY.\n");
12966 + * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
12967 + * timeout issues when LFS is enabled.
12972 + * The NVM settings will configure LPLU in D3 for
12975 + if (phy->type == e1000_phy_igp) {
12976 + /* disable lplu d3 during driver init */
12977 + ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
12979 + DEBUGOUT("Error Disabling LPLU D3\n");
12984 + /* disable lplu d0 during driver init */
12985 + if (hw->phy.ops.set_d0_lplu_state) {
12986 + ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
12988 + DEBUGOUT("Error Disabling LPLU D0\n");
12992 + /* Configure mdi-mdix settings */
12993 + ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
12997 + data &= ~IGP01E1000_PSCR_AUTO_MDIX;
12999 + switch (phy->mdix) {
13001 + data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
13004 + data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
13008 + data |= IGP01E1000_PSCR_AUTO_MDIX;
13011 + ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
13015 + /* set auto-master slave resolution settings */
13016 + if (hw->mac.autoneg) {
13018 + * when autonegotiation advertisement is only 1000Mbps then we
13019 + * should disable SmartSpeed and enable Auto MasterSlave
13020 + * resolution as hardware default.
13022 + if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
13023 + /* Disable SmartSpeed */
13024 + ret_val = phy->ops.read_reg(hw,
13025 + IGP01E1000_PHY_PORT_CONFIG,
13030 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
13031 + ret_val = phy->ops.write_reg(hw,
13032 + IGP01E1000_PHY_PORT_CONFIG,
13037 + /* Set auto Master/Slave resolution process */
13038 + ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
13042 + data &= ~CR_1000T_MS_ENABLE;
13043 + ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
13048 + ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
13052 + /* load defaults for future use */
13053 + phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
13054 + ((data & CR_1000T_MS_VALUE) ?
13055 + e1000_ms_force_master :
13056 + e1000_ms_force_slave) :
13059 + switch (phy->ms_type) {
13060 + case e1000_ms_force_master:
13061 + data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
13063 + case e1000_ms_force_slave:
13064 + data |= CR_1000T_MS_ENABLE;
13065 + data &= ~(CR_1000T_MS_VALUE);
13067 + case e1000_ms_auto:
13068 + data &= ~CR_1000T_MS_ENABLE;
13072 + ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
13082 + * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
13083 + * @hw: pointer to the HW structure
13085 + * Performs initial bounds checking on autoneg advertisement parameter, then
13086 + * configure to advertise the full capability. Setup the PHY to autoneg
13087 + * and restart the negotiation process between the link partner. If
13088 + * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
13090 +s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
13092 + struct e1000_phy_info *phy = &hw->phy;
13096 + DEBUGFUNC("e1000_copper_link_autoneg");
13099 + * Perform some bounds checking on the autoneg advertisement
13102 + phy->autoneg_advertised &= phy->autoneg_mask;
13105 + * If autoneg_advertised is zero, we assume it was not defaulted
13106 + * by the calling code so we set to advertise full capability.
13108 + if (phy->autoneg_advertised == 0)
13109 + phy->autoneg_advertised = phy->autoneg_mask;
13111 + DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
13112 + ret_val = e1000_phy_setup_autoneg(hw);
13114 + DEBUGOUT("Error Setting up Auto-Negotiation\n");
13117 + DEBUGOUT("Restarting Auto-Neg\n");
13120 + * Restart auto-negotiation by setting the Auto Neg Enable bit and
13121 + * the Auto Neg Restart bit in the PHY control register.
13123 + ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
13127 + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
13128 + ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
13133 + * Does the user want to wait for Auto-Neg to complete here, or
13134 + * check at a later time (for example, callback routine).
13136 + if (phy->autoneg_wait_to_complete) {
13137 + ret_val = hw->mac.ops.wait_autoneg(hw);
13139 + DEBUGOUT("Error while waiting for "
13140 + "autoneg to complete\n");
13145 + hw->mac.get_link_status = true;
13152 + * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
13153 + * @hw: pointer to the HW structure
13155 + * Reads the MII auto-neg advertisement register and/or the 1000T control
13156 + * register and if the PHY is already setup for auto-negotiation, then
13157 + * return successful. Otherwise, setup advertisement and flow control to
13158 + * the appropriate values for the wanted auto-negotiation.
13160 +s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
13162 + struct e1000_phy_info *phy = &hw->phy;
13164 + u16 mii_autoneg_adv_reg;
13165 + u16 mii_1000t_ctrl_reg = 0;
13167 + DEBUGFUNC("e1000_phy_setup_autoneg");
13169 + phy->autoneg_advertised &= phy->autoneg_mask;
13171 + /* Read the MII Auto-Neg Advertisement Register (Address 4). */
13172 + ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
13176 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
13177 + /* Read the MII 1000Base-T Control Register (Address 9). */
13178 + ret_val = phy->ops.read_reg(hw,
13180 + &mii_1000t_ctrl_reg);
13186 + * Need to parse both autoneg_advertised and fc and set up
13187 + * the appropriate PHY registers. First we will parse for
13188 + * autoneg_advertised software override. Since we can advertise
13189 + * a plethora of combinations, we need to check each bit
13194 + * First we clear all the 10/100 mb speed bits in the Auto-Neg
13195 + * Advertisement Register (Address 4) and the 1000 mb speed bits in
13196 + * the 1000Base-T Control Register (Address 9).
13198 + mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
13199 + NWAY_AR_100TX_HD_CAPS |
13200 + NWAY_AR_10T_FD_CAPS |
13201 + NWAY_AR_10T_HD_CAPS);
13202 + mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
13204 + DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
13206 + /* Do we want to advertise 10 Mb Half Duplex? */
13207 + if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
13208 + DEBUGOUT("Advertise 10mb Half duplex\n");
13209 + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
13212 + /* Do we want to advertise 10 Mb Full Duplex? */
13213 + if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
13214 + DEBUGOUT("Advertise 10mb Full duplex\n");
13215 + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
13218 + /* Do we want to advertise 100 Mb Half Duplex? */
13219 + if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
13220 + DEBUGOUT("Advertise 100mb Half duplex\n");
13221 + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
13224 + /* Do we want to advertise 100 Mb Full Duplex? */
13225 + if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
13226 + DEBUGOUT("Advertise 100mb Full duplex\n");
13227 + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
13230 + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
13231 + if (phy->autoneg_advertised & ADVERTISE_1000_HALF) {
13232 + DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
13235 + /* Do we want to advertise 1000 Mb Full Duplex? */
13236 + if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
13237 + DEBUGOUT("Advertise 1000mb Full duplex\n");
13238 + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
13242 + * Check for a software override of the flow control settings, and
13243 + * setup the PHY advertisement registers accordingly. If
13244 + * auto-negotiation is enabled, then software will have to set the
13245 + * "PAUSE" bits to the correct value in the Auto-Negotiation
13246 + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
13249 + * The possible values of the "fc" parameter are:
13250 + * 0: Flow control is completely disabled
13251 + * 1: Rx flow control is enabled (we can receive pause frames
13252 + * but not send pause frames).
13253 + * 2: Tx flow control is enabled (we can send pause frames
13254 + * but we do not support receiving pause frames).
13255 + * 3: Both Rx and Tx flow control (symmetric) are enabled.
13256 + * other: No software override. The flow control configuration
13257 + * in the EEPROM is used.
13259 + switch (hw->fc.type) {
13260 + case e1000_fc_none:
13262 + * Flow control (Rx & Tx) is completely disabled by a
13263 + * software over-ride.
13265 + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
13267 + case e1000_fc_rx_pause:
13269 + * Rx Flow control is enabled, and Tx Flow control is
13270 + * disabled, by a software over-ride.
13272 + * Since there really isn't a way to advertise that we are
13273 + * capable of Rx Pause ONLY, we will advertise that we
13274 + * support both symmetric and asymmetric Rx PAUSE. Later
13275 + * (in e1000_config_fc_after_link_up) we will disable the
13276 + * hw's ability to send PAUSE frames.
13278 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
13280 + case e1000_fc_tx_pause:
13282 + * Tx Flow control is enabled, and Rx Flow control is
13283 + * disabled, by a software over-ride.
13285 + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
13286 + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
13288 + case e1000_fc_full:
13290 + * Flow control (both Rx and Tx) is enabled by a software
13293 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
13296 + DEBUGOUT("Flow control param set incorrectly\n");
13297 + ret_val = -E1000_ERR_CONFIG;
13301 + ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
13305 + DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
13307 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
13308 + ret_val = phy->ops.write_reg(hw,
13310 + mii_1000t_ctrl_reg);
13320 + * e1000_setup_copper_link_generic - Configure copper link settings
13321 + * @hw: pointer to the HW structure
13323 + * Calls the appropriate function to configure the link for auto-neg or forced
13324 + * speed and duplex. Then we check for link, once link is established calls
13325 + * to configure collision distance and flow control are called. If link is
13326 + * not established, we return -E1000_ERR_PHY (-2).
13328 +s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
13333 + DEBUGFUNC("e1000_setup_copper_link_generic");
13335 + if (hw->mac.autoneg) {
13337 + * Setup autoneg and flow control advertisement and perform
13338 + * autonegotiation.
13340 + ret_val = e1000_copper_link_autoneg(hw);
13345 + * PHY will be set to 10H, 10F, 100H or 100F
13346 + * depending on user settings.
13348 + DEBUGOUT("Forcing Speed and Duplex\n");
13349 + ret_val = hw->phy.ops.force_speed_duplex(hw);
13351 + DEBUGOUT("Error Forcing Speed and Duplex\n");
13357 + * Check link status. Wait up to 100 microseconds for link to become
13360 + ret_val = e1000_phy_has_link_generic(hw,
13361 + COPPER_LINK_UP_LIMIT,
13368 + DEBUGOUT("Valid link established!!!\n");
13369 + e1000_config_collision_dist_generic(hw);
13370 + ret_val = e1000_config_fc_after_link_up_generic(hw);
13372 + DEBUGOUT("Unable to establish link!!!\n");
13380 + * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
13381 + * @hw: pointer to the HW structure
13383 + * Calls the PHY setup function to force speed and duplex. Clears the
13384 + * auto-crossover to force MDI manually. Waits for link and returns
13385 + * successful if link up is successful, else -E1000_ERR_PHY (-2).
13387 +s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
13389 + struct e1000_phy_info *phy = &hw->phy;
13394 + DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
13396 + ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
13400 + e1000_phy_force_speed_duplex_setup(hw, &phy_data);
13402 + ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
13407 + * Clear Auto-Crossover to force MDI manually. IGP requires MDI
13408 + * forced whenever speed and duplex are forced.
13410 + ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
13414 + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
13415 + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
13417 + ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
13421 + DEBUGOUT1("IGP PSCR: %X\n", phy_data);
13425 + if (phy->autoneg_wait_to_complete) {
13426 + DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
13428 + ret_val = e1000_phy_has_link_generic(hw,
13436 + DEBUGOUT("Link taking longer than expected.\n");
13439 + /* Try once more */
13440 + ret_val = e1000_phy_has_link_generic(hw,
13453 + * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
13454 + * @hw: pointer to the HW structure
13456 + * Calls the PHY setup function to force speed and duplex. Clears the
13457 + * auto-crossover to force MDI manually. Resets the PHY to commit the
13458 + * changes. If time expires while waiting for link up, we reset the DSP.
13459 + * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
13460 + * successful completion, else return corresponding error code.
13462 +s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
13464 + struct e1000_phy_info *phy = &hw->phy;
13469 + DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
13472 + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
13473 + * forced whenever speed and duplex are forced.
13475 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
13479 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
13480 + ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
13484 + DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
13486 + ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
13490 + e1000_phy_force_speed_duplex_setup(hw, &phy_data);
13492 + /* Reset the phy to commit changes. */
13493 + phy_data |= MII_CR_RESET;
13495 + ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
13501 + if (phy->autoneg_wait_to_complete) {
13502 + DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
13504 + ret_val = e1000_phy_has_link_generic(hw,
13513 + * We didn't get link.
13514 + * Reset the DSP and cross our fingers.
13516 + ret_val = phy->ops.write_reg(hw,
13517 + M88E1000_PHY_PAGE_SELECT,
13521 + ret_val = e1000_phy_reset_dsp_generic(hw);
13526 + /* Try once more */
13527 + ret_val = e1000_phy_has_link_generic(hw,
13535 + ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
13540 + * Resetting the phy means we need to re-force TX_CLK in the
13541 + * Extended PHY Specific Control Register to 25MHz clock from
13542 + * the reset value of 2.5MHz.
13544 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
13545 + ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
13550 + * In addition, we must re-enable CRS on Tx for both half and full
13553 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
13557 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
13558 + ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
13565 + * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
13566 + * @hw: pointer to the HW structure
13567 + * @phy_ctrl: pointer to current value of PHY_CONTROL
13569 + * Forces speed and duplex on the PHY by doing the following: disable flow
13570 + * control, force speed/duplex on the MAC, disable auto speed detection,
13571 + * disable auto-negotiation, configure duplex, configure speed, configure
13572 + * the collision distance, write configuration to CTRL register. The
13573 + * caller must write to the PHY_CONTROL register for these settings to
13576 +void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
13578 + struct e1000_mac_info *mac = &hw->mac;
13581 + DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
13583 + /* Turn off flow control when forcing speed/duplex */
13584 + hw->fc.type = e1000_fc_none;
13586 + /* Force speed/duplex on the mac */
13587 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
13588 + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
13589 + ctrl &= ~E1000_CTRL_SPD_SEL;
13591 + /* Disable Auto Speed Detection */
13592 + ctrl &= ~E1000_CTRL_ASDE;
13594 + /* Disable autoneg on the phy */
13595 + *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
13597 + /* Forcing Full or Half Duplex? */
13598 + if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
13599 + ctrl &= ~E1000_CTRL_FD;
13600 + *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
13601 + DEBUGOUT("Half Duplex\n");
13603 + ctrl |= E1000_CTRL_FD;
13604 + *phy_ctrl |= MII_CR_FULL_DUPLEX;
13605 + DEBUGOUT("Full Duplex\n");
13608 + /* Forcing 10mb or 100mb? */
13609 + if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
13610 + ctrl |= E1000_CTRL_SPD_100;
13611 + *phy_ctrl |= MII_CR_SPEED_100;
13612 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
13613 + DEBUGOUT("Forcing 100mb\n");
13615 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
13616 + *phy_ctrl |= MII_CR_SPEED_10;
13617 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
13618 + DEBUGOUT("Forcing 10mb\n");
13621 + e1000_config_collision_dist_generic(hw);
13623 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
13627 + * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
13628 + * @hw: pointer to the HW structure
13629 + * @active: boolean used to enable/disable lplu
13631 + * Success returns 0, Failure returns 1
13633 + * The low power link up (lplu) state is set to the power management level D3
13634 + * and SmartSpeed is disabled when active is true, else clear lplu for D3
13635 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
13636 + * is used during Dx states where the power conservation is most important.
13637 + * During driver activity, SmartSpeed should be enabled so performance is
13640 +s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
13642 + struct e1000_phy_info *phy = &hw->phy;
13643 + s32 ret_val = E1000_SUCCESS;
13646 + DEBUGFUNC("e1000_set_d3_lplu_state_generic");
13648 + if (!(hw->phy.ops.read_reg))
13651 + ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
13656 + data &= ~IGP02E1000_PM_D3_LPLU;
13657 + ret_val = phy->ops.write_reg(hw,
13658 + IGP02E1000_PHY_POWER_MGMT,
13663 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
13664 + * during Dx states where the power conservation is most
13665 + * important. During driver activity we should enable
13666 + * SmartSpeed, so performance is maintained.
13668 + if (phy->smart_speed == e1000_smart_speed_on) {
13669 + ret_val = phy->ops.read_reg(hw,
13670 + IGP01E1000_PHY_PORT_CONFIG,
13675 + data |= IGP01E1000_PSCFR_SMART_SPEED;
13676 + ret_val = phy->ops.write_reg(hw,
13677 + IGP01E1000_PHY_PORT_CONFIG,
13681 + } else if (phy->smart_speed == e1000_smart_speed_off) {
13682 + ret_val = phy->ops.read_reg(hw,
13683 + IGP01E1000_PHY_PORT_CONFIG,
13688 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
13689 + ret_val = phy->ops.write_reg(hw,
13690 + IGP01E1000_PHY_PORT_CONFIG,
13695 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
13696 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
13697 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
13698 + data |= IGP02E1000_PM_D3_LPLU;
13699 + ret_val = phy->ops.write_reg(hw,
13700 + IGP02E1000_PHY_POWER_MGMT,
13705 + /* When LPLU is enabled, we should disable SmartSpeed */
13706 + ret_val = phy->ops.read_reg(hw,
13707 + IGP01E1000_PHY_PORT_CONFIG,
13712 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
13713 + ret_val = phy->ops.write_reg(hw,
13714 + IGP01E1000_PHY_PORT_CONFIG,
13723 + * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
13724 + * @hw: pointer to the HW structure
13726 + * Success returns 0, Failure returns 1
13728 + * A downshift is detected by querying the PHY link health.
13730 +s32 e1000_check_downshift_generic(struct e1000_hw *hw)
13732 + struct e1000_phy_info *phy = &hw->phy;
13734 + u16 phy_data, offset, mask;
13736 + DEBUGFUNC("e1000_check_downshift_generic");
13738 + switch (phy->type) {
13739 + case e1000_phy_m88:
13740 + case e1000_phy_gg82563:
13741 + case e1000_phy_bm:
13742 + offset = M88E1000_PHY_SPEC_STATUS;
13743 + mask = M88E1000_PSSR_DOWNSHIFT;
13745 + case e1000_phy_igp_2:
13746 + case e1000_phy_igp:
13747 + case e1000_phy_igp_3:
13748 + offset = IGP01E1000_PHY_LINK_HEALTH;
13749 + mask = IGP01E1000_PLHR_SS_DOWNGRADE;
13752 + /* speed downshift not supported */
13753 + phy->speed_downgraded = false;
13754 + ret_val = E1000_SUCCESS;
13758 + ret_val = phy->ops.read_reg(hw, offset, &phy_data);
13761 + phy->speed_downgraded = (phy_data & mask) ? true : false;
13768 + * e1000_check_polarity_m88 - Checks the polarity.
13769 + * @hw: pointer to the HW structure
13771 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
13773 + * Polarity is determined based on the PHY specific status register.
13775 +s32 e1000_check_polarity_m88(struct e1000_hw *hw)
13777 + struct e1000_phy_info *phy = &hw->phy;
13781 + DEBUGFUNC("e1000_check_polarity_m88");
13783 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
13786 + phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
13787 + ? e1000_rev_polarity_reversed
13788 + : e1000_rev_polarity_normal;
13794 + * e1000_check_polarity_igp - Checks the polarity.
13795 + * @hw: pointer to the HW structure
13797 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
13799 + * Polarity is determined based on the PHY port status register, and the
13800 + * current speed (since there is no polarity at 100Mbps).
13802 +s32 e1000_check_polarity_igp(struct e1000_hw *hw)
13804 + struct e1000_phy_info *phy = &hw->phy;
13806 + u16 data, offset, mask;
13808 + DEBUGFUNC("e1000_check_polarity_igp");
13811 + * Polarity is determined based on the speed of
13812 + * our connection.
13814 + ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
13818 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
13819 + IGP01E1000_PSSR_SPEED_1000MBPS) {
13820 + offset = IGP01E1000_PHY_PCS_INIT_REG;
13821 + mask = IGP01E1000_PHY_POLARITY_MASK;
13824 + * This really only applies to 10Mbps since
13825 + * there is no polarity for 100Mbps (always 0).
13827 + offset = IGP01E1000_PHY_PORT_STATUS;
13828 + mask = IGP01E1000_PSSR_POLARITY_REVERSED;
13831 + ret_val = phy->ops.read_reg(hw, offset, &data);
13834 + phy->cable_polarity = (data & mask)
13835 + ? e1000_rev_polarity_reversed
13836 + : e1000_rev_polarity_normal;
13843 + * e1000_wait_autoneg_generic - Wait for auto-neg completion
13844 + * @hw: pointer to the HW structure
13846 + * Waits for auto-negotiation to complete or for the auto-negotiation time
13847 + * limit to expire, which ever happens first.
13849 +s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
13851 + s32 ret_val = E1000_SUCCESS;
13852 + u16 i, phy_status;
13854 + DEBUGFUNC("e1000_wait_autoneg_generic");
13856 + if (!(hw->phy.ops.read_reg))
13857 + return E1000_SUCCESS;
13859 + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
13860 + for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
13861 + ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
13864 + ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
13867 + if (phy_status & MII_SR_AUTONEG_COMPLETE)
13873 + * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
13880 + * e1000_phy_has_link_generic - Polls PHY for link
13881 + * @hw: pointer to the HW structure
13882 + * @iterations: number of times to poll for link
13883 + * @usec_interval: delay between polling attempts
13884 + * @success: pointer to whether polling was successful or not
13886 + * Polls the PHY status register for link, 'iterations' number of times.
13888 +s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
13889 + u32 usec_interval, bool *success)
13891 + s32 ret_val = E1000_SUCCESS;
13892 + u16 i, phy_status;
13894 + DEBUGFUNC("e1000_phy_has_link_generic");
13896 + if (!(hw->phy.ops.read_reg))
13897 + return E1000_SUCCESS;
13899 + for (i = 0; i < iterations; i++) {
13901 + * Some PHYs require the PHY_STATUS register to be read
13902 + * twice due to the link bit being sticky. No harm doing
13903 + * it across the board.
13905 + ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
13908 + ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
13911 + if (phy_status & MII_SR_LINK_STATUS)
13913 + if (usec_interval >= 1000)
13914 + msec_delay_irq(usec_interval/1000);
13916 + usec_delay(usec_interval);
13919 + *success = (i < iterations) ? true : false;
13925 + * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
13926 + * @hw: pointer to the HW structure
13928 + * Reads the PHY specific status register to retrieve the cable length
13929 + * information. The cable length is determined by averaging the minimum and
13930 + * maximum values to get the "average" cable length. The m88 PHY has four
13931 + * possible cable length values, which are:
13932 + * Register Value Cable Length
13934 + * 1 50 - 80 meters
13935 + * 2 80 - 110 meters
13936 + * 3 110 - 140 meters
13939 +s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
13941 + struct e1000_phy_info *phy = &hw->phy;
13943 + u16 phy_data, index;
13945 + DEBUGFUNC("e1000_get_cable_length_m88");
13947 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
13951 + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
13952 + M88E1000_PSSR_CABLE_LENGTH_SHIFT;
13953 + phy->min_cable_length = e1000_m88_cable_length_table[index];
13954 + phy->max_cable_length = e1000_m88_cable_length_table[index+1];
13956 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
13963 + * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
13964 + * @hw: pointer to the HW structure
13966 + * The automatic gain control (agc) normalizes the amplitude of the
13967 + * received signal, adjusting for the attenuation produced by the
13968 + * cable. By reading the AGC registers, which represent the
13969 + * combination of coarse and fine gain value, the value can be put
13970 + * into a lookup table to obtain the approximate cable length
13971 + * for each channel.
13973 +s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
13975 + struct e1000_phy_info *phy = &hw->phy;
13976 + s32 ret_val = E1000_SUCCESS;
13977 + u16 phy_data, i, agc_value = 0;
13978 + u16 cur_agc_index, max_agc_index = 0;
13979 + u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
13980 + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
13981 + {IGP02E1000_PHY_AGC_A,
13982 + IGP02E1000_PHY_AGC_B,
13983 + IGP02E1000_PHY_AGC_C,
13984 + IGP02E1000_PHY_AGC_D};
13986 + DEBUGFUNC("e1000_get_cable_length_igp_2");
13988 + /* Read the AGC registers for all channels */
13989 + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
13990 + ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
13995 + * Getting bits 15:9, which represent the combination of
13996 + * coarse and fine gain values. The result is a number
13997 + * that can be put into the lookup table to obtain the
13998 + * approximate cable length.
14000 + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
14001 + IGP02E1000_AGC_LENGTH_MASK;
14003 + /* Array index bound check. */
14004 + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
14005 + (cur_agc_index == 0)) {
14006 + ret_val = -E1000_ERR_PHY;
14010 + /* Remove min & max AGC values from calculation. */
14011 + if (e1000_igp_2_cable_length_table[min_agc_index] >
14012 + e1000_igp_2_cable_length_table[cur_agc_index])
14013 + min_agc_index = cur_agc_index;
14014 + if (e1000_igp_2_cable_length_table[max_agc_index] <
14015 + e1000_igp_2_cable_length_table[cur_agc_index])
14016 + max_agc_index = cur_agc_index;
14018 + agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
14021 + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
14022 + e1000_igp_2_cable_length_table[max_agc_index]);
14023 + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
14025 + /* Calculate cable length with the error range of +/- 10 meters. */
14026 + phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
14027 + (agc_value - IGP02E1000_AGC_RANGE) : 0;
14028 + phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
14030 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
14037 + * e1000_get_phy_info_m88 - Retrieve PHY information
14038 + * @hw: pointer to the HW structure
14040 + * Valid for only copper links. Read the PHY status register (sticky read)
14041 + * to verify that link is up. Read the PHY special control register to
14042 + * determine the polarity and 10base-T extended distance. Read the PHY
14043 + * special status register to determine MDI/MDIx and current speed. If
14044 + * speed is 1000, then determine cable length, local and remote receiver.
14046 +s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
14048 + struct e1000_phy_info *phy = &hw->phy;
14053 + DEBUGFUNC("e1000_get_phy_info_m88");
14055 + if (hw->phy.media_type != e1000_media_type_copper) {
14056 + DEBUGOUT("Phy info is only valid for copper media\n");
14057 + ret_val = -E1000_ERR_CONFIG;
14061 + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
14066 + DEBUGOUT("Phy info is only valid if link is up\n");
14067 + ret_val = -E1000_ERR_CONFIG;
14071 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
14075 + phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
14079 + ret_val = e1000_check_polarity_m88(hw);
14083 + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
14087 + phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
14089 + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
14090 + ret_val = hw->phy.ops.get_cable_length(hw);
14094 + ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
14098 + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
14099 + ? e1000_1000t_rx_status_ok
14100 + : e1000_1000t_rx_status_not_ok;
14102 + phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
14103 + ? e1000_1000t_rx_status_ok
14104 + : e1000_1000t_rx_status_not_ok;
14106 + /* Set values to "undefined" */
14107 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
14108 + phy->local_rx = e1000_1000t_rx_status_undefined;
14109 + phy->remote_rx = e1000_1000t_rx_status_undefined;
14117 + * e1000_get_phy_info_igp - Retrieve igp PHY information
14118 + * @hw: pointer to the HW structure
14120 + * Read PHY status to determine if link is up. If link is up, then
14121 + * set/determine 10base-T extended distance and polarity correction. Read
14122 + * PHY port status to determine MDI/MDIx and speed. Based on the speed,
14123 + * determine on the cable length, local and remote receiver.
14125 +s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
14127 + struct e1000_phy_info *phy = &hw->phy;
14132 + DEBUGFUNC("e1000_get_phy_info_igp");
14134 + ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
14139 + DEBUGOUT("Phy info is only valid if link is up\n");
14140 + ret_val = -E1000_ERR_CONFIG;
14144 + phy->polarity_correction = true;
14146 + ret_val = e1000_check_polarity_igp(hw);
14150 + ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
14154 + phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
14156 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
14157 + IGP01E1000_PSSR_SPEED_1000MBPS) {
14158 + ret_val = hw->phy.ops.get_cable_length(hw);
14162 + ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
14166 + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
14167 + ? e1000_1000t_rx_status_ok
14168 + : e1000_1000t_rx_status_not_ok;
14170 + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
14171 + ? e1000_1000t_rx_status_ok
14172 + : e1000_1000t_rx_status_not_ok;
14174 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
14175 + phy->local_rx = e1000_1000t_rx_status_undefined;
14176 + phy->remote_rx = e1000_1000t_rx_status_undefined;
14184 + * e1000_phy_sw_reset_generic - PHY software reset
14185 + * @hw: pointer to the HW structure
14187 + * Does a software reset of the PHY by reading the PHY control register and
14188 + * setting/write the control register reset bit to the PHY.
14190 +s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
14192 + s32 ret_val = E1000_SUCCESS;
14195 + DEBUGFUNC("e1000_phy_sw_reset_generic");
14197 + if (!(hw->phy.ops.read_reg))
14200 + ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
14204 + phy_ctrl |= MII_CR_RESET;
14205 + ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
14216 + * e1000_phy_hw_reset_generic - PHY hardware reset
14217 + * @hw: pointer to the HW structure
14219 + * Verify the reset block is not blocking us from resetting. Acquire
14220 + * semaphore (if necessary) and read/set/write the device control reset
14221 + * bit in the PHY. Wait the appropriate delay time for the device to
14222 + * reset and release the semaphore (if necessary).
14224 +s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
14226 + struct e1000_phy_info *phy = &hw->phy;
14227 + s32 ret_val = E1000_SUCCESS;
14230 + DEBUGFUNC("e1000_phy_hw_reset_generic");
14232 + ret_val = phy->ops.check_reset_block(hw);
14234 + ret_val = E1000_SUCCESS;
14238 + ret_val = phy->ops.acquire(hw);
14242 + ctrl = E1000_READ_REG(hw, E1000_CTRL);
14243 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
14244 + E1000_WRITE_FLUSH(hw);
14246 + usec_delay(phy->reset_delay_us);
14248 + E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
14249 + E1000_WRITE_FLUSH(hw);
14253 + phy->ops.release(hw);
14255 + ret_val = phy->ops.get_cfg_done(hw);
14262 + * e1000_get_cfg_done_generic - Generic configuration done
14263 + * @hw: pointer to the HW structure
14265 + * Generic function to wait 10 milli-seconds for configuration to complete
14266 + * and return success.
14268 +s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
14270 + DEBUGFUNC("e1000_get_cfg_done_generic");
14272 + msec_delay_irq(10);
14274 + return E1000_SUCCESS;
14278 + * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
14279 + * @hw: pointer to the HW structure
14281 + * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
14283 +s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
14285 + DEBUGOUT("Running IGP 3 PHY init script\n");
14287 + /* PHY init IGP 3 */
14288 + /* Enable rise/fall, 10-mode work in class-A */
14289 + hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
14290 + /* Remove all caps from Replica path filter */
14291 + hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
14292 + /* Bias trimming for ADC, AFE and Driver (Default) */
14293 + hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
14294 + /* Increase Hybrid poly bias */
14295 + hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
14296 + /* Add 4% to Tx amplitude in Gig mode */
14297 + hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
14298 + /* Disable trimming (TTT) */
14299 + hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
14300 + /* Poly DC correction to 94.6% + 2% for all channels */
14301 + hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
14302 + /* ABS DC correction to 95.9% */
14303 + hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
14304 + /* BG temp curve trim */
14305 + hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
14306 + /* Increasing ADC OPAMP stage 1 currents to max */
14307 + hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
14308 + /* Force 1000 ( required for enabling PHY regs configuration) */
14309 + hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
14310 + /* Set upd_freq to 6 */
14311 + hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
14312 + /* Disable NPDFE */
14313 + hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
14314 + /* Disable adaptive fixed FFE (Default) */
14315 + hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
14316 + /* Enable FFE hysteresis */
14317 + hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
14318 + /* Fixed FFE for short cable lengths */
14319 + hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
14320 + /* Fixed FFE for medium cable lengths */
14321 + hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
14322 + /* Fixed FFE for long cable lengths */
14323 + hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
14324 + /* Enable Adaptive Clip Threshold */
14325 + hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
14326 + /* AHT reset limit to 1 */
14327 + hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
14328 + /* Set AHT master delay to 127 msec */
14329 + hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
14330 + /* Set scan bits for AHT */
14331 + hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
14332 + /* Set AHT Preset bits */
14333 + hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
14334 + /* Change integ_factor of channel A to 3 */
14335 + hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
14336 + /* Change prop_factor of channels BCD to 8 */
14337 + hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
14338 + /* Change cg_icount + enable integbp for channels BCD */
14339 + hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
14341 + * Change cg_icount + enable integbp + change prop_factor_master
14342 + * to 8 for channel A
14344 + hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
14345 + /* Disable AHT in Slave mode on channel A */
14346 + hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
14348 + * Enable LPLU and disable AN to 1000 in non-D0a states,
14351 + hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
14352 + /* Enable restart AN on an1000_dis change */
14353 + hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
14354 + /* Enable wh_fifo read clock in 10/100 modes */
14355 + hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
14356 + /* Restart AN, Speed selection is 1000 */
14357 + hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
14359 + return E1000_SUCCESS;
14363 + * e1000_get_phy_type_from_id - Get PHY type from id
14364 + * @phy_id: phy_id read from the phy
14366 + * Returns the phy type from the id.
14368 +e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
14370 + e1000_phy_type phy_type = e1000_phy_unknown;
14372 + switch (phy_id) {
14373 + case M88E1000_I_PHY_ID:
14374 + case M88E1000_E_PHY_ID:
14375 + case M88E1111_I_PHY_ID:
14376 + case M88E1011_I_PHY_ID:
14377 + phy_type = e1000_phy_m88;
14379 + case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
14380 + phy_type = e1000_phy_igp_2;
14382 + case GG82563_E_PHY_ID:
14383 + phy_type = e1000_phy_gg82563;
14385 + case IGP03E1000_E_PHY_ID:
14386 + phy_type = e1000_phy_igp_3;
14388 + case IFE_E_PHY_ID:
14389 + case IFE_PLUS_E_PHY_ID:
14390 + case IFE_C_E_PHY_ID:
14391 + phy_type = e1000_phy_ife;
14393 + case BME1000_E_PHY_ID:
14394 + case BME1000_E_PHY_ID_R2:
14395 + phy_type = e1000_phy_bm;
14398 + phy_type = e1000_phy_unknown;
14405 + * e1000_determine_phy_address - Determines PHY address.
14406 + * @hw: pointer to the HW structure
14408 + * This uses a trial and error method to loop through possible PHY
14409 + * addresses. It tests each by reading the PHY ID registers and
14410 + * checking for a match.
14412 +s32 e1000_determine_phy_address(struct e1000_hw* hw)
14414 + s32 ret_val = -E1000_ERR_PHY_TYPE;
14417 + e1000_phy_type phy_type = e1000_phy_unknown;
14419 + for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
14420 + hw->phy.addr = phy_addr;
14424 + e1000_get_phy_id(hw);
14425 + phy_type = e1000_get_phy_type_from_id(hw->phy.id);
14428 + * If phy_type is valid, break - we found our
14431 + if (phy_type != e1000_phy_unknown) {
14432 + ret_val = E1000_SUCCESS;
14437 + } while (i < 10);
14445 + * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
14446 + * @page: page to access
14448 + * Returns the phy address for the page requested.
14450 +static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
14452 + u32 phy_addr = 2;
14454 + if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
14461 + * e1000_write_phy_reg_bm - Write BM PHY register
14462 + * @hw: pointer to the HW structure
14463 + * @offset: register offset to write to
14464 + * @data: data to write at register offset
14466 + * Acquires semaphore, if necessary, then writes the data to PHY register
14467 + * at the offset. Release any acquired semaphores before exiting.
14469 +s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
14472 + u32 page_select = 0;
14473 + u32 page = offset >> IGP_PAGE_SHIFT;
14474 + u32 page_shift = 0;
14476 + DEBUGFUNC("e1000_write_phy_reg_bm");
14478 + /* Page 800 works differently than the rest so it has its own func */
14479 + if (page == BM_WUC_PAGE) {
14480 + ret_val = e1000_access_phy_wakeup_reg_bm(hw,
14481 + offset, &data, false);
14485 + ret_val = hw->phy.ops.acquire(hw);
14489 + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
14491 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14493 + * Page select is register 31 for phy address 1 and 22 for
14494 + * phy address 2 and 3. Page select is shifted only for
14497 + if (hw->phy.addr == 1) {
14498 + page_shift = IGP_PAGE_SHIFT;
14499 + page_select = IGP01E1000_PHY_PAGE_SELECT;
14502 + page_select = BM_PHY_PAGE_SELECT;
14505 + /* Page is shifted left, PHY expects (page x 32) */
14506 + ret_val = e1000_write_phy_reg_mdic(hw, page_select,
14507 + (page << page_shift));
14509 + hw->phy.ops.release(hw);
14514 + ret_val = e1000_write_phy_reg_mdic(hw,
14515 + MAX_PHY_REG_ADDRESS & offset,
14518 + hw->phy.ops.release(hw);
14525 + * e1000_read_phy_reg_bm - Read BM PHY register
14526 + * @hw: pointer to the HW structure
14527 + * @offset: register offset to be read
14528 + * @data: pointer to the read data
14530 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14531 + * and storing the retrieved information in data. Release any acquired
14532 + * semaphores before exiting.
14534 +s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
14537 + u32 page_select = 0;
14538 + u32 page = offset >> IGP_PAGE_SHIFT;
14539 + u32 page_shift = 0;
14541 + DEBUGFUNC("e1000_read_phy_reg_bm");
14543 + /* Page 800 works differently than the rest so it has its own func */
14544 + if (page == BM_WUC_PAGE) {
14545 + ret_val = e1000_access_phy_wakeup_reg_bm(hw,
14546 + offset, data, true);
14550 + ret_val = hw->phy.ops.acquire(hw);
14554 + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
14556 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14558 + * Page select is register 31 for phy address 1 and 22 for
14559 + * phy address 2 and 3. Page select is shifted only for
14562 + if (hw->phy.addr == 1) {
14563 + page_shift = IGP_PAGE_SHIFT;
14564 + page_select = IGP01E1000_PHY_PAGE_SELECT;
14567 + page_select = BM_PHY_PAGE_SELECT;
14570 + /* Page is shifted left, PHY expects (page x 32) */
14571 + ret_val = e1000_write_phy_reg_mdic(hw, page_select,
14572 + (page << page_shift));
14574 + hw->phy.ops.release(hw);
14579 + ret_val = e1000_read_phy_reg_mdic(hw,
14580 + MAX_PHY_REG_ADDRESS & offset,
14582 + hw->phy.ops.release(hw);
14589 + * e1000_read_phy_reg_bm2 - Read BM PHY register
14590 + * @hw: pointer to the HW structure
14591 + * @offset: register offset to be read
14592 + * @data: pointer to the read data
14594 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14595 + * and storing the retrieved information in data. Release any acquired
14596 + * semaphores before exiting.
14598 +s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
14601 + u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
14603 + DEBUGFUNC("e1000_write_phy_reg_bm2");
14605 + /* Page 800 works differently than the rest so it has its own func */
14606 + if (page == BM_WUC_PAGE) {
14607 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
14612 + ret_val = hw->phy.ops.acquire(hw);
14616 + hw->phy.addr = 1;
14618 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14620 + /* Page is shifted left, PHY expects (page x 32) */
14621 + ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
14625 + hw->phy.ops.release(hw);
14630 + ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14632 + hw->phy.ops.release(hw);
14639 + * e1000_write_phy_reg_bm2 - Write BM PHY register
14640 + * @hw: pointer to the HW structure
14641 + * @offset: register offset to write to
14642 + * @data: data to write at register offset
14644 + * Acquires semaphore, if necessary, then writes the data to PHY register
14645 + * at the offset. Release any acquired semaphores before exiting.
14647 +s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
14650 + u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
14652 + DEBUGFUNC("e1000_write_phy_reg_bm2");
14654 + /* Page 800 works differently than the rest so it has its own func */
14655 + if (page == BM_WUC_PAGE) {
14656 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
14661 + ret_val = hw->phy.ops.acquire(hw);
14665 + hw->phy.addr = 1;
14667 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14668 + /* Page is shifted left, PHY expects (page x 32) */
14669 + ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
14673 + hw->phy.ops.release(hw);
14678 + ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14681 + hw->phy.ops.release(hw);
14688 + * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
14689 + * @hw: pointer to the HW structure
14690 + * @offset: register offset to be read or written
14691 + * @data: pointer to the data to read or write
14692 + * @read: determines if operation is read or write
14694 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14695 + * and storing the retrieved information in data. Release any acquired
14696 + * semaphores before exiting. Note that procedure to read the wakeup
14697 + * registers are different. It works as such:
14698 + * 1) Set page 769, register 17, bit 2 = 1
14699 + * 2) Set page to 800 for host (801 if we were manageability)
14700 + * 3) Write the address using the address opcode (0x11)
14701 + * 4) Read or write the data using the data opcode (0x12)
14702 + * 5) Restore 769_17.2 to its original value
14704 +s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw,
14705 + u32 offset, u16 *data, bool read)
14708 + u16 reg = ((u16)offset);
14710 + u8 phy_acquired = 1;
14712 + DEBUGFUNC("e1000_read_phy_wakeup_reg_bm");
14714 + ret_val = hw->phy.ops.acquire(hw);
14716 + DEBUGOUT("Could not acquire PHY\n");
14717 + phy_acquired = 0;
14721 + /* All operations in this function are phy address 1 */
14722 + hw->phy.addr = 1;
14724 + /* Set page 769 */
14725 + e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
14726 + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
14728 + ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
14730 + DEBUGOUT("Could not read PHY page 769\n");
14734 + /* First clear bit 4 to avoid a power state change */
14735 + phy_reg &= ~(BM_WUC_HOST_WU_BIT);
14736 + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
14738 + DEBUGOUT("Could not clear PHY page 769 bit 4\n");
14742 + /* Write bit 2 = 1, and clear bit 4 to 769_17 */
14743 + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
14744 + phy_reg | BM_WUC_ENABLE_BIT);
14746 + DEBUGOUT("Could not write PHY page 769 bit 2\n");
14750 + /* Select page 800 */
14751 + ret_val = e1000_write_phy_reg_mdic(hw,
14752 + IGP01E1000_PHY_PAGE_SELECT,
14753 + (BM_WUC_PAGE << IGP_PAGE_SHIFT));
14755 + /* Write the page 800 offset value using opcode 0x11 */
14756 + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
14758 + DEBUGOUT("Could not write address opcode to page 800\n");
14763 + /* Read the page 800 value using opcode 0x12 */
14764 + ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
14767 + /* Read the page 800 value using opcode 0x12 */
14768 + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
14773 + DEBUGOUT("Could not read data value from page 800\n");
14778 + * Restore 769_17.2 to its original value
14781 + e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
14782 + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
14784 + /* Clear 769_17.2 */
14785 + ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
14787 + DEBUGOUT("Could not clear PHY page 769 bit 2\n");
14792 + if (phy_acquired == 1)
14793 + hw->phy.ops.release(hw);
14798 + * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
14799 + * @hw: pointer to the HW structure
14801 + * In the case of a PHY power down to save power, or to turn off link during a
14802 + * driver unload, or wake on lan is not enabled, restore the link to previous
14805 +void e1000_power_up_phy_copper(struct e1000_hw *hw)
14809 + /* The PHY will retain its settings across a power down/up cycle */
14810 + hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
14811 + mii_reg &= ~MII_CR_POWER_DOWN;
14812 + hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
14816 + * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
14817 + * @hw: pointer to the HW structure
14819 + * In the case of a PHY power down to save power, or to turn off link during a
14820 + * driver unload, or wake on lan is not enabled, restore the link to previous
14823 +void e1000_power_down_phy_copper(struct e1000_hw *hw)
14827 + /* The PHY will retain its settings across a power down/up cycle */
14828 + hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
14829 + mii_reg |= MII_CR_POWER_DOWN;
14830 + hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
14833 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_phy.h linux-2.6.22-10/drivers/net/e1000e/e1000_phy.h
14834 --- linux-2.6.22-0/drivers/net/e1000e/e1000_phy.h 1970-01-01 01:00:00.000000000 +0100
14835 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_phy.h 2008-10-14 01:51:32.000000000 +0200
14837 +/*******************************************************************************
14839 + Intel PRO/1000 Linux driver
14840 + Copyright(c) 1999 - 2008 Intel Corporation.
14842 + This program is free software; you can redistribute it and/or modify it
14843 + under the terms and conditions of the GNU General Public License,
14844 + version 2, as published by the Free Software Foundation.
14846 + This program is distributed in the hope it will be useful, but WITHOUT
14847 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14848 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14851 + You should have received a copy of the GNU General Public License along with
14852 + this program; if not, write to the Free Software Foundation, Inc.,
14853 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
14855 + The full GNU General Public License is included in this distribution in
14856 + the file called "COPYING".
14858 + Contact Information:
14859 + Linux NICS <linux.nics@intel.com>
14860 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
14861 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
14863 +*******************************************************************************/
14865 +#ifndef _E1000_PHY_H_
14866 +#define _E1000_PHY_H_
14869 + e1000_ms_hw_default = 0,
14870 + e1000_ms_force_master,
14871 + e1000_ms_force_slave,
14876 + e1000_smart_speed_default = 0,
14877 + e1000_smart_speed_on,
14878 + e1000_smart_speed_off
14879 +} e1000_smart_speed;
14881 +void e1000_init_phy_ops_generic(struct e1000_hw *hw);
14882 +s32 e1000_check_downshift_generic(struct e1000_hw *hw);
14883 +s32 e1000_check_polarity_m88(struct e1000_hw *hw);
14884 +s32 e1000_check_polarity_igp(struct e1000_hw *hw);
14885 +s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
14886 +s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
14887 +s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
14888 +s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
14889 +s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
14890 +s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
14891 +s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
14892 +s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
14893 +s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
14894 +s32 e1000_get_phy_id(struct e1000_hw *hw);
14895 +s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
14896 +s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
14897 +s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
14898 +void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
14899 +s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
14900 +s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
14901 +s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
14902 +s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
14903 +s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
14904 +s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
14905 +s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
14906 +s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
14907 +s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
14908 +s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
14909 +s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
14910 +s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
14911 +s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
14912 +s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
14913 + u32 usec_interval, bool *success);
14914 +s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
14915 +e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
14916 +s32 e1000_determine_phy_address(struct e1000_hw* hw);
14917 +s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
14918 +s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
14919 +s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data,
14921 +s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
14922 +s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
14923 +void e1000_power_up_phy_copper(struct e1000_hw *hw);
14924 +void e1000_power_down_phy_copper(struct e1000_hw *hw);
14925 +s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
14926 +s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
14928 +#define E1000_MAX_PHY_ADDR 4
14930 +/* IGP01E1000 Specific Registers */
14931 +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
14932 +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
14933 +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
14934 +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
14935 +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
14936 +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
14937 +#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
14938 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
14939 +#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
14940 +#define IGP_PAGE_SHIFT 5
14941 +#define PHY_REG_MASK 0x1F
14943 +#define BM_WUC_PAGE 800
14944 +#define BM_WUC_ADDRESS_OPCODE 0x11
14945 +#define BM_WUC_DATA_OPCODE 0x12
14946 +#define BM_WUC_ENABLE_PAGE 769
14947 +#define BM_WUC_ENABLE_REG 17
14948 +#define BM_WUC_ENABLE_BIT (1 << 2)
14949 +#define BM_WUC_HOST_WU_BIT (1 << 4)
14951 +/* BM PHY Copper Specific Control 1 */
14952 +#define BM_CS_CTRL1 16
14953 +#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */
14955 +/* BM PHY Copper Specific States */
14956 +#define BM_CS_STATUS 17
14957 +#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */
14959 +#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
14960 +#define IGP01E1000_PHY_POLARITY_MASK 0x0078
14962 +#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
14963 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
14965 +#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
14967 +/* Enable flexible speed on link-up */
14968 +#define IGP01E1000_GMII_FLEX_SPD 0x0010
14969 +#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
14971 +#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
14972 +#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
14973 +#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
14975 +#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
14977 +#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
14978 +#define IGP01E1000_PSSR_MDIX 0x0008
14979 +#define IGP01E1000_PSSR_SPEED_MASK 0xC000
14980 +#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
14982 +#define IGP02E1000_PHY_CHANNEL_NUM 4
14983 +#define IGP02E1000_PHY_AGC_A 0x11B1
14984 +#define IGP02E1000_PHY_AGC_B 0x12B1
14985 +#define IGP02E1000_PHY_AGC_C 0x14B1
14986 +#define IGP02E1000_PHY_AGC_D 0x18B1
14988 +#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
14989 +#define IGP02E1000_AGC_LENGTH_MASK 0x7F
14990 +#define IGP02E1000_AGC_RANGE 15
14992 +#define IGP03E1000_PHY_MISC_CTRL 0x1B
14993 +#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
14995 +#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
14997 +#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
14998 +#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
14999 +#define E1000_KMRNCTRLSTA_REN 0x00200000
15000 +#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
15001 +#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
15003 +#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
15004 +#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
15005 +#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
15006 +#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
15008 +/* IFE PHY Extended Status Control */
15009 +#define IFE_PESC_POLARITY_REVERSED 0x0100
15011 +/* IFE PHY Special Control */
15012 +#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
15013 +#define IFE_PSC_FORCE_POLARITY 0x0020
15014 +#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
15016 +/* IFE PHY Special Control and LED Control */
15017 +#define IFE_PSCL_PROBE_MODE 0x0020
15018 +#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
15019 +#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
15021 +/* IFE PHY MDIX Control */
15022 +#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
15023 +#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
15024 +#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
15027 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_regs.h linux-2.6.22-10/drivers/net/e1000e/e1000_regs.h
15028 --- linux-2.6.22-0/drivers/net/e1000e/e1000_regs.h 1970-01-01 01:00:00.000000000 +0100
15029 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_regs.h 2008-10-14 01:51:32.000000000 +0200
15031 +/*******************************************************************************
15033 + Intel PRO/1000 Linux driver
15034 + Copyright(c) 1999 - 2008 Intel Corporation.
15036 + This program is free software; you can redistribute it and/or modify it
15037 + under the terms and conditions of the GNU General Public License,
15038 + version 2, as published by the Free Software Foundation.
15040 + This program is distributed in the hope it will be useful, but WITHOUT
15041 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15042 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15045 + You should have received a copy of the GNU General Public License along with
15046 + this program; if not, write to the Free Software Foundation, Inc.,
15047 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
15049 + The full GNU General Public License is included in this distribution in
15050 + the file called "COPYING".
15052 + Contact Information:
15053 + Linux NICS <linux.nics@intel.com>
15054 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
15055 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15057 +*******************************************************************************/
15059 +#ifndef _E1000_REGS_H_
15060 +#define _E1000_REGS_H_
15062 +#define E1000_CTRL 0x00000 /* Device Control - RW */
15063 +#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
15064 +#define E1000_STATUS 0x00008 /* Device Status - RO */
15065 +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
15066 +#define E1000_EERD 0x00014 /* EEPROM Read - RW */
15067 +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
15068 +#define E1000_FLA 0x0001C /* Flash Access - RW */
15069 +#define E1000_MDIC 0x00020 /* MDI Control - RW */
15070 +#define E1000_SCTL 0x00024 /* SerDes Control - RW */
15071 +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
15072 +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
15073 +#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
15074 +#define E1000_FCT 0x00030 /* Flow Control Type - RW */
15075 +#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
15076 +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
15077 +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
15078 +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
15079 +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
15080 +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
15081 +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
15082 +#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
15083 +#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
15084 +#define E1000_RCTL 0x00100 /* Rx Control - RW */
15085 +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
15086 +#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
15087 +#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
15088 +#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
15089 +#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
15090 +#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
15091 +#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
15092 +#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15093 +#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
15094 +#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
15095 +#define E1000_TCTL 0x00400 /* Tx Control - RW */
15096 +#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
15097 +#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
15098 +#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
15099 +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
15100 +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
15101 +#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
15102 +#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
15103 +#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
15104 +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
15105 +#define E1000_PBS 0x01008 /* Packet Buffer Size */
15106 +#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
15107 +#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
15108 +#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
15109 +#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
15110 +#define E1000_FLSWCTL 0x01030 /* FLASH control register */
15111 +#define E1000_FLSWDATA 0x01034 /* FLASH data register */
15112 +#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
15113 +#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
15114 +#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
15115 +#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
15116 +#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
15117 +#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
15118 +#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
15119 +#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
15120 +#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
15121 +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
15122 +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
15123 +#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
15124 +#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
15125 +#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
15126 +#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
15127 +/* Split and Replication Rx Control - RW */
15128 +#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
15129 +#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
15130 +#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
15131 +#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
15132 +#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
15133 +#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
15134 +#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
15136 + * Convenience macros
15138 + * Note: "_n" is the queue number of the register to be written to.
15141 + * E1000_RDBAL_REG(current_rx_queue)
15143 +#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : (0x0C000 + ((_n) * 0x40)))
15144 +#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : (0x0C004 + ((_n) * 0x40)))
15145 +#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : (0x0C008 + ((_n) * 0x40)))
15146 +#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : (0x0C00C + ((_n) * 0x40)))
15147 +#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : (0x0C010 + ((_n) * 0x40)))
15148 +#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : (0x0C018 + ((_n) * 0x40)))
15149 +#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : (0x0C028 + ((_n) * 0x40)))
15150 +#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : (0x0E000 + ((_n) * 0x40)))
15151 +#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : (0x0E004 + ((_n) * 0x40)))
15152 +#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : (0x0E008 + ((_n) * 0x40)))
15153 +#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : (0x0E010 + ((_n) * 0x40)))
15154 +#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : (0x0E018 + ((_n) * 0x40)))
15155 +#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : (0x0E028 + ((_n) * 0x40)))
15156 +#define E1000_TARC(_n) (0x03840 + (_n << 8))
15157 +#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
15158 +#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
15159 +#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : (0x0E038 + ((_n) * 0x40)))
15160 +#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : (0x0E03C + ((_n) * 0x40)))
15161 +#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
15162 +#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
15163 +#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
15164 +#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
15165 +#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
15166 +#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x054E0 + ((_i - 16) * 8)))
15167 +#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x054E4 + ((_i - 16) * 8)))
15168 +#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
15169 +#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
15170 +#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
15171 +#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
15172 +#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
15173 +#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
15174 +#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
15175 +#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
15176 +#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
15177 +#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
15178 +#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
15179 +#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
15180 +#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
15181 +#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
15182 +#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
15183 +#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
15184 +#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
15185 +#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
15186 +#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
15187 +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
15188 +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
15189 +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
15190 +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
15191 +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
15192 +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
15193 +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
15194 +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
15195 +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
15196 +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
15197 +#define E1000_COLC 0x04028 /* Collision Count - R/clr */
15198 +#define E1000_DC 0x04030 /* Defer Count - R/clr */
15199 +#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
15200 +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
15201 +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
15202 +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
15203 +#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
15204 +#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
15205 +#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
15206 +#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
15207 +#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
15208 +#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
15209 +#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
15210 +#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
15211 +#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
15212 +#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
15213 +#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
15214 +#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
15215 +#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
15216 +#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
15217 +#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
15218 +#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
15219 +#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
15220 +#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
15221 +#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
15222 +#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
15223 +#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
15224 +#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
15225 +#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
15226 +#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
15227 +#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
15228 +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
15229 +#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
15230 +#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
15231 +#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
15232 +#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
15233 +#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
15234 +#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
15235 +#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
15236 +#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
15237 +#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
15238 +#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
15239 +#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
15240 +#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
15241 +#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
15242 +#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
15243 +#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
15244 +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
15245 +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
15246 +#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
15247 +#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
15248 +#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
15249 +#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
15250 +#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
15251 +#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
15252 +#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
15253 +#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
15254 +#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
15256 +#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
15257 +#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
15258 +#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
15259 +#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
15260 +#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
15261 +#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
15262 +#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
15263 +#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
15264 +#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
15265 +#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
15266 +#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
15267 +#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
15268 +#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
15269 +#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
15270 +#define E1000_LENERRS 0x04138 /* Length Errors Count */
15271 +#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
15272 +#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
15273 +#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
15274 +#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
15275 +#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
15276 +#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
15277 +#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */
15278 +#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
15279 +#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
15280 +#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
15281 +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
15282 +#define E1000_RA 0x05400 /* Receive Address - RW Array */
15283 +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
15284 +#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */
15285 +#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
15286 +#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
15287 +#define E1000_WUC 0x05800 /* Wakeup Control - RW */
15288 +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
15289 +#define E1000_WUS 0x05810 /* Wakeup Status - RO */
15290 +#define E1000_MANC 0x05820 /* Management Control - RW */
15291 +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
15292 +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
15293 +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
15294 +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
15295 +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
15296 +#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
15297 +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
15298 +#define E1000_HOST_IF 0x08800 /* Host Interface */
15299 +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
15300 +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
15302 +#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
15303 +#define E1000_MDPHYA 0x0003C /* PHY address - RW */
15304 +#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
15305 +#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
15306 +#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
15307 +#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
15308 +#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
15309 +#define E1000_GCR 0x05B00 /* PCI-Ex Control */
15310 +#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
15311 +#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
15312 +#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
15313 +#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
15314 +#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
15315 +#define E1000_SWSM 0x05B50 /* SW Semaphore */
15316 +#define E1000_FWSM 0x05B54 /* FW Semaphore */
15317 +#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
15318 +#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
15319 +#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
15320 +#define E1000_HICR 0x08F00 /* Host Interface Control */
15322 +/* RSS registers */
15323 +#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
15324 +#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
15325 +#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
15326 +#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
15327 +#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
15328 +#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register (_i) - RW */
15329 +#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr low reg 0 - RW */
15330 +#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr upper reg 0 - RW */
15331 +#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry message reg 0 - RW */
15332 +#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry vector ctrl reg 0 - RW */
15333 +#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
15334 +#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW Array */
15335 +#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
15336 +#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
15337 +#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
15338 +#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Message Type - RW */
15339 +#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
15341 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/ethtool.c linux-2.6.22-10/drivers/net/e1000e/ethtool.c
15342 --- linux-2.6.22-0/drivers/net/e1000e/ethtool.c 1970-01-01 01:00:00.000000000 +0100
15343 +++ linux-2.6.22-10/drivers/net/e1000e/ethtool.c 2008-10-14 01:51:32.000000000 +0200
15345 +/*******************************************************************************
15347 + Intel PRO/1000 Linux driver
15348 + Copyright(c) 1999 - 2008 Intel Corporation.
15350 + This program is free software; you can redistribute it and/or modify it
15351 + under the terms and conditions of the GNU General Public License,
15352 + version 2, as published by the Free Software Foundation.
15354 + This program is distributed in the hope it will be useful, but WITHOUT
15355 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15356 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15359 + You should have received a copy of the GNU General Public License along with
15360 + this program; if not, write to the Free Software Foundation, Inc.,
15361 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
15363 + The full GNU General Public License is included in this distribution in
15364 + the file called "COPYING".
15366 + Contact Information:
15367 + Linux NICS <linux.nics@intel.com>
15368 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
15369 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15371 +*******************************************************************************/
15373 +/* ethtool support for e1000 */
15375 +#include <linux/netdevice.h>
15376 +#ifdef SIOCETHTOOL
15377 +#include <linux/ethtool.h>
15378 +#include <linux/pci.h>
15379 +#include <linux/delay.h>
15381 +#include "e1000.h"
15382 +#ifdef NETIF_F_HW_VLAN_TX
15383 +#include <linux/if_vlan.h>
15386 +#ifdef ETHTOOL_OPS_COMPAT
15387 +#include "kcompat_ethtool.c"
15390 +struct e1000_stats {
15391 + char stat_string[ETH_GSTRING_LEN];
15396 +#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
15397 + offsetof(struct e1000_adapter, m)
15398 +static const struct e1000_stats e1000_gstrings_stats[] = {
15399 + { "rx_packets", E1000_STAT(stats.gprc) },
15400 + { "tx_packets", E1000_STAT(stats.gptc) },
15401 + { "rx_bytes", E1000_STAT(stats.gorc) },
15402 + { "tx_bytes", E1000_STAT(stats.gotc) },
15403 + { "rx_broadcast", E1000_STAT(stats.bprc) },
15404 + { "tx_broadcast", E1000_STAT(stats.bptc) },
15405 + { "rx_multicast", E1000_STAT(stats.mprc) },
15406 + { "tx_multicast", E1000_STAT(stats.mptc) },
15407 + { "rx_errors", E1000_STAT(net_stats.rx_errors) },
15408 + { "tx_errors", E1000_STAT(net_stats.tx_errors) },
15409 + { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
15410 + { "multicast", E1000_STAT(stats.mprc) },
15411 + { "collisions", E1000_STAT(stats.colc) },
15412 + { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
15413 + { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
15414 + { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
15415 + { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
15416 + { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
15417 + { "rx_missed_errors", E1000_STAT(stats.mpc) },
15418 + { "tx_aborted_errors", E1000_STAT(stats.ecol) },
15419 + { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
15420 + { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
15421 + { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
15422 + { "tx_window_errors", E1000_STAT(stats.latecol) },
15423 + { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
15424 + { "tx_deferred_ok", E1000_STAT(stats.dc) },
15425 + { "tx_single_coll_ok", E1000_STAT(stats.scc) },
15426 + { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
15427 + { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
15428 + { "tx_restart_queue", E1000_STAT(restart_queue) },
15429 + { "rx_long_length_errors", E1000_STAT(stats.roc) },
15430 + { "rx_short_length_errors", E1000_STAT(stats.ruc) },
15431 + { "rx_align_errors", E1000_STAT(stats.algnerrc) },
15432 + { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
15433 + { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
15434 + { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
15435 + { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
15436 + { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
15437 + { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
15438 + { "rx_long_byte_count", E1000_STAT(stats.gorc) },
15439 + { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
15440 + { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
15441 + { "rx_header_split", E1000_STAT(rx_hdr_split) },
15442 + { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
15443 + { "tx_smbus", E1000_STAT(stats.mgptc) },
15444 + { "rx_smbus", E1000_STAT(stats.mgprc) },
15445 + { "dropped_smbus", E1000_STAT(stats.mgpdc) },
15446 + { "rx_dma_failed", E1000_STAT(rx_dma_failed) },
15447 + { "tx_dma_failed", E1000_STAT(tx_dma_failed) },
15450 +#define E1000_GLOBAL_STATS_LEN \
15451 + sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
15452 +#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN)
15453 +static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
15454 + "Register test (offline)", "Eeprom test (offline)",
15455 + "Interrupt test (offline)", "Loopback test (offline)",
15456 + "Link test (on/offline)"
15458 +#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
15460 +static int e1000_get_settings(struct net_device *netdev,
15461 + struct ethtool_cmd *ecmd)
15463 + struct e1000_adapter *adapter = netdev_priv(netdev);
15464 + struct e1000_hw *hw = &adapter->hw;
15467 + if (hw->phy.media_type == e1000_media_type_copper) {
15469 + ecmd->supported = (SUPPORTED_10baseT_Half |
15470 + SUPPORTED_10baseT_Full |
15471 + SUPPORTED_100baseT_Half |
15472 + SUPPORTED_100baseT_Full |
15473 + SUPPORTED_1000baseT_Full |
15474 + SUPPORTED_Autoneg |
15476 + if (hw->phy.type == e1000_phy_ife)
15477 + ecmd->supported &= ~SUPPORTED_1000baseT_Full;
15478 + ecmd->advertising = ADVERTISED_TP;
15480 + if (hw->mac.autoneg == 1) {
15481 + ecmd->advertising |= ADVERTISED_Autoneg;
15482 + /* the e1000 autoneg seems to match ethtool nicely */
15483 + ecmd->advertising |= hw->phy.autoneg_advertised;
15486 + ecmd->port = PORT_TP;
15487 + ecmd->phy_address = hw->phy.addr;
15488 + ecmd->transceiver = XCVR_INTERNAL;
15491 + ecmd->supported = (SUPPORTED_1000baseT_Full |
15492 + SUPPORTED_FIBRE |
15493 + SUPPORTED_Autoneg);
15495 + ecmd->advertising = (ADVERTISED_1000baseT_Full |
15496 + ADVERTISED_FIBRE |
15497 + ADVERTISED_Autoneg);
15499 + ecmd->port = PORT_FIBRE;
15500 + ecmd->transceiver = XCVR_EXTERNAL;
15503 + status = er32(STATUS);
15504 + if (status & E1000_STATUS_LU) {
15505 + if (status & E1000_STATUS_SPEED_1000)
15506 + ecmd->speed = 1000;
15507 + else if (status & E1000_STATUS_SPEED_100)
15508 + ecmd->speed = 100;
15510 + ecmd->speed = 10;
15512 + if (status & E1000_STATUS_FD)
15513 + ecmd->duplex = DUPLEX_FULL;
15515 + ecmd->duplex = DUPLEX_HALF;
15517 + ecmd->speed = -1;
15518 + ecmd->duplex = -1;
15521 + ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
15522 + hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
15526 +static u32 e1000_get_link(struct net_device *netdev)
15528 + struct e1000_adapter *adapter = netdev_priv(netdev);
15529 + struct e1000_hw *hw = &adapter->hw;
15532 + status = er32(STATUS);
15533 + return (status & E1000_STATUS_LU);
15536 +static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
15538 + struct e1000_mac_info *mac = &adapter->hw.mac;
15540 + mac->autoneg = 0;
15542 + /* Fiber NICs only allow 1000 gbps Full duplex */
15543 + if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
15544 + spddplx != (SPEED_1000 + DUPLEX_FULL)) {
15545 + e_err("Unsupported Speed/Duplex configuration\n");
15549 + switch (spddplx) {
15550 + case SPEED_10 + DUPLEX_HALF:
15551 + mac->forced_speed_duplex = ADVERTISE_10_HALF;
15553 + case SPEED_10 + DUPLEX_FULL:
15554 + mac->forced_speed_duplex = ADVERTISE_10_FULL;
15556 + case SPEED_100 + DUPLEX_HALF:
15557 + mac->forced_speed_duplex = ADVERTISE_100_HALF;
15559 + case SPEED_100 + DUPLEX_FULL:
15560 + mac->forced_speed_duplex = ADVERTISE_100_FULL;
15562 + case SPEED_1000 + DUPLEX_FULL:
15563 + mac->autoneg = 1;
15564 + adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
15566 + case SPEED_1000 + DUPLEX_HALF: /* not supported */
15568 + e_err("Unsupported Speed/Duplex configuration\n");
15574 +static int e1000_set_settings(struct net_device *netdev,
15575 + struct ethtool_cmd *ecmd)
15577 + struct e1000_adapter *adapter = netdev_priv(netdev);
15578 + struct e1000_hw *hw = &adapter->hw;
15581 + * When SoL/IDER sessions are active, autoneg/speed/duplex
15582 + * cannot be changed
15584 + if (hw->phy.ops.check_reset_block &&
15585 + hw->phy.ops.check_reset_block(&adapter->hw)) {
15586 + e_err("Cannot change link characteristics when SoL/IDER"
15587 + " is active.\n");
15591 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
15594 + if (ecmd->autoneg == AUTONEG_ENABLE) {
15595 + hw->mac.autoneg = 1;
15596 + if (hw->phy.media_type == e1000_media_type_fiber)
15597 + hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
15598 + ADVERTISED_FIBRE |
15599 + ADVERTISED_Autoneg;
15601 + hw->phy.autoneg_advertised = ecmd->advertising |
15603 + ADVERTISED_Autoneg;
15604 + ecmd->advertising = hw->phy.autoneg_advertised;
15605 + if (adapter->fc_autoneg)
15606 + hw->fc.original_type = e1000_fc_default;
15608 + if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
15609 + clear_bit(__E1000_RESETTING, &adapter->state);
15614 + /* reset the link */
15616 + if (netif_running(adapter->netdev)) {
15617 + e1000_down(adapter);
15618 + e1000_up(adapter);
15620 + e1000_reset(adapter);
15623 + clear_bit(__E1000_RESETTING, &adapter->state);
15627 +static void e1000_get_pauseparam(struct net_device *netdev,
15628 + struct ethtool_pauseparam *pause)
15630 + struct e1000_adapter *adapter = netdev_priv(netdev);
15631 + struct e1000_hw *hw = &adapter->hw;
15634 + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
15636 + if (hw->fc.type == e1000_fc_rx_pause) {
15637 + pause->rx_pause = 1;
15638 + } else if (hw->fc.type == e1000_fc_tx_pause) {
15639 + pause->tx_pause = 1;
15640 + } else if (hw->fc.type == e1000_fc_full) {
15641 + pause->rx_pause = 1;
15642 + pause->tx_pause = 1;
15646 +static int e1000_set_pauseparam(struct net_device *netdev,
15647 + struct ethtool_pauseparam *pause)
15649 + struct e1000_adapter *adapter = netdev_priv(netdev);
15650 + struct e1000_hw *hw = &adapter->hw;
15653 + adapter->fc_autoneg = pause->autoneg;
15655 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
15658 + if (pause->rx_pause && pause->tx_pause)
15659 + hw->fc.type = e1000_fc_full;
15660 + else if (pause->rx_pause && !pause->tx_pause)
15661 + hw->fc.type = e1000_fc_rx_pause;
15662 + else if (!pause->rx_pause && pause->tx_pause)
15663 + hw->fc.type = e1000_fc_tx_pause;
15664 + else if (!pause->rx_pause && !pause->tx_pause)
15665 + hw->fc.type = e1000_fc_none;
15667 + hw->fc.original_type = hw->fc.type;
15669 + if (adapter->fc_autoneg == AUTONEG_ENABLE) {
15670 + hw->fc.type = e1000_fc_default;
15671 + if (netif_running(adapter->netdev)) {
15672 + e1000_down(adapter);
15673 + e1000_up(adapter);
15675 + e1000_reset(adapter);
15678 + retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
15679 + hw->mac.ops.setup_link(hw) :
15680 + e1000_force_mac_fc_generic(hw));
15683 + clear_bit(__E1000_RESETTING, &adapter->state);
15687 +static u32 e1000_get_rx_csum(struct net_device *netdev)
15689 + struct e1000_adapter *adapter = netdev_priv(netdev);
15690 + return (adapter->flags & FLAG_RX_CSUM_ENABLED);
15693 +static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
15695 + struct e1000_adapter *adapter = netdev_priv(netdev);
15698 + adapter->flags |= FLAG_RX_CSUM_ENABLED;
15700 + adapter->flags &= ~FLAG_RX_CSUM_ENABLED;
15702 + if (netif_running(netdev))
15703 + e1000_reinit_locked(adapter);
15705 + e1000_reset(adapter);
15709 +static u32 e1000_get_tx_csum(struct net_device *netdev)
15711 + return ((netdev->features & NETIF_F_HW_CSUM) != 0);
15714 +static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
15717 + netdev->features |= NETIF_F_HW_CSUM;
15719 + netdev->features &= ~NETIF_F_HW_CSUM;
15724 +#ifdef NETIF_F_TSO
15725 +static int e1000_set_tso(struct net_device *netdev, u32 data)
15727 + struct e1000_adapter *adapter = netdev_priv(netdev);
15729 + struct net_device *v_netdev;
15732 + netdev->features |= NETIF_F_TSO;
15733 +#ifdef NETIF_F_TSO6
15734 + netdev->features |= NETIF_F_TSO6;
15737 + netdev->features &= ~NETIF_F_TSO;
15738 +#ifdef NETIF_F_TSO6
15739 + netdev->features &= ~NETIF_F_TSO6;
15741 +#ifdef NETIF_F_HW_VLAN_TX
15742 + /* disable TSO on all VLANs if they're present */
15743 + if (!adapter->vlgrp)
15745 + for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
15746 + v_netdev = vlan_group_get_device(adapter->vlgrp, i);
15750 + v_netdev->features &= ~NETIF_F_TSO;
15751 +#ifdef NETIF_F_TSO6
15752 + v_netdev->features &= ~NETIF_F_TSO6;
15754 + vlan_group_set_device(adapter->vlgrp, i, v_netdev);
15760 + e_info("TSO is %s\n", data ? "Enabled" : "Disabled");
15761 + adapter->flags |= FLAG_TSO_FORCE;
15766 +static u32 e1000_get_msglevel(struct net_device *netdev)
15768 + struct e1000_adapter *adapter = netdev_priv(netdev);
15769 + return adapter->msg_enable;
15772 +static void e1000_set_msglevel(struct net_device *netdev, u32 data)
15774 + struct e1000_adapter *adapter = netdev_priv(netdev);
15775 + adapter->msg_enable = data;
15778 +static int e1000_get_regs_len(struct net_device *netdev)
15780 +#define E1000_REGS_LEN 32 /* overestimate */
15781 + return E1000_REGS_LEN * sizeof(u32);
15784 +static void e1000_get_regs(struct net_device *netdev,
15785 + struct ethtool_regs *regs, void *p)
15787 + struct e1000_adapter *adapter = netdev_priv(netdev);
15788 + struct e1000_hw *hw = &adapter->hw;
15789 + u32 *regs_buff = p;
15793 + memset(p, 0, E1000_REGS_LEN * sizeof(u32));
15795 + pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id);
15797 + regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device;
15799 + regs_buff[0] = er32(CTRL);
15800 + regs_buff[1] = er32(STATUS);
15802 + regs_buff[2] = er32(RCTL);
15803 + regs_buff[3] = er32(RDLEN(0));
15804 + regs_buff[4] = er32(RDH(0));
15805 + regs_buff[5] = er32(RDT(0));
15806 + regs_buff[6] = er32(RDTR);
15808 + regs_buff[7] = er32(TCTL);
15809 + regs_buff[8] = er32(TDLEN(0));
15810 + regs_buff[9] = er32(TDH(0));
15811 + regs_buff[10] = er32(TDT(0));
15812 + regs_buff[11] = er32(TIDV);
15814 + regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
15815 + if (hw->phy.type == e1000_phy_m88) {
15816 + hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
15817 + regs_buff[13] = (u32)phy_data; /* cable length */
15818 + regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
15819 + regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
15820 + regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
15821 + hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
15822 + regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
15823 + regs_buff[18] = regs_buff[13]; /* cable polarity */
15824 + regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
15825 + regs_buff[20] = regs_buff[17]; /* polarity correction */
15826 + /* phy receive errors */
15827 + regs_buff[22] = adapter->phy_stats.receive_errors;
15828 + regs_buff[23] = regs_buff[13]; /* mdix mode */
15830 + regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
15831 + hw->phy.ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
15832 + regs_buff[24] = (u32)phy_data; /* phy local receiver status */
15833 + regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
15836 +static int e1000_get_eeprom_len(struct net_device *netdev)
15838 + struct e1000_adapter *adapter = netdev_priv(netdev);
15839 + return adapter->hw.nvm.word_size * 2;
15842 +static int e1000_get_eeprom(struct net_device *netdev,
15843 + struct ethtool_eeprom *eeprom, u8 *bytes)
15845 + struct e1000_adapter *adapter = netdev_priv(netdev);
15846 + struct e1000_hw *hw = &adapter->hw;
15847 + u16 *eeprom_buff;
15853 + if (eeprom->len == 0)
15856 + eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16);
15858 + first_word = eeprom->offset >> 1;
15859 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
15861 + eeprom_buff = kmalloc(sizeof(u16) *
15862 + (last_word - first_word + 1), GFP_KERNEL);
15863 + if (!eeprom_buff)
15866 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
15867 + ret_val = hw->nvm.ops.read(hw, first_word,
15868 + last_word - first_word + 1,
15871 + for (i = 0; i < last_word - first_word + 1; i++) {
15872 + ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
15873 + &eeprom_buff[i]);
15879 + /* Device's eeprom is always little-endian, word addressable */
15880 + for (i = 0; i < last_word - first_word + 1; i++)
15881 + le16_to_cpus(&eeprom_buff[i]);
15883 + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
15884 + kfree(eeprom_buff);
15889 +static int e1000_set_eeprom(struct net_device *netdev,
15890 + struct ethtool_eeprom *eeprom, u8 *bytes)
15892 + struct e1000_adapter *adapter = netdev_priv(netdev);
15893 + struct e1000_hw *hw = &adapter->hw;
15894 + u16 *eeprom_buff;
15902 + if (eeprom->len == 0)
15903 + return -EOPNOTSUPP;
15905 + if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16)))
15908 + if (adapter->flags2 & FLAG2_READ_ONLY_NVM)
15911 + max_len = hw->nvm.word_size * 2;
15913 + first_word = eeprom->offset >> 1;
15914 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
15915 + eeprom_buff = kmalloc(max_len, GFP_KERNEL);
15916 + if (!eeprom_buff)
15919 + ptr = (void *)eeprom_buff;
15921 + if (eeprom->offset & 1) {
15922 + /* need read/modify/write of first changed EEPROM word */
15923 + /* only the second byte of the word is being modified */
15924 + ret_val = hw->nvm.ops.read(hw, first_word, 1, &eeprom_buff[0]);
15927 + if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0))
15928 + /* need read/modify/write of last changed EEPROM word */
15929 + /* only the first byte of the word is being modified */
15930 + ret_val = hw->nvm.ops.read(hw, last_word, 1,
15931 + &eeprom_buff[last_word - first_word]);
15933 + /* Device's eeprom is always little-endian, word addressable */
15934 + for (i = 0; i < last_word - first_word + 1; i++)
15935 + le16_to_cpus(&eeprom_buff[i]);
15937 + memcpy(ptr, bytes, eeprom->len);
15939 + for (i = 0; i < last_word - first_word + 1; i++)
15940 + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
15942 + ret_val = hw->nvm.ops.write(hw, first_word, last_word - first_word + 1,
15946 + * Update the checksum over the first part of the EEPROM if needed
15947 + * and flush shadow RAM for 82573 controllers
15949 + if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) ||
15950 + (hw->mac.type == e1000_82574) ||
15951 + (hw->mac.type == e1000_82573)))
15952 + hw->nvm.ops.update(hw);
15954 + kfree(eeprom_buff);
15958 +static void e1000_get_drvinfo(struct net_device *netdev,
15959 + struct ethtool_drvinfo *drvinfo)
15961 + struct e1000_adapter *adapter = netdev_priv(netdev);
15962 + struct e1000_hw *hw = &adapter->hw;
15963 + char firmware_version[32];
15966 + strncpy(drvinfo->driver, e1000e_driver_name, 32);
15967 + strncpy(drvinfo->version, e1000e_driver_version, 32);
15970 + * EEPROM image version # is reported as firmware version # for
15971 + * PCI-E controllers
15973 + hw->nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
15974 + sprintf(firmware_version, "%d.%d-%d",
15975 + (eeprom_data & 0xF000) >> 12,
15976 + (eeprom_data & 0x0FF0) >> 4,
15977 + eeprom_data & 0x000F);
15979 + strncpy(drvinfo->fw_version, firmware_version, 32);
15980 + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
15981 + drvinfo->regdump_len = e1000_get_regs_len(netdev);
15982 + drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
15985 +static void e1000_get_ringparam(struct net_device *netdev,
15986 + struct ethtool_ringparam *ring)
15988 + struct e1000_adapter *adapter = netdev_priv(netdev);
15989 + struct e1000_ring *tx_ring = adapter->tx_ring;
15990 + struct e1000_ring *rx_ring = adapter->rx_ring;
15992 + ring->rx_max_pending = E1000_MAX_RXD;
15993 + ring->tx_max_pending = E1000_MAX_TXD;
15994 + ring->rx_mini_max_pending = 0;
15995 + ring->rx_jumbo_max_pending = 0;
15996 + ring->rx_pending = rx_ring->count;
15997 + ring->tx_pending = tx_ring->count;
15998 + ring->rx_mini_pending = 0;
15999 + ring->rx_jumbo_pending = 0;
16002 +static int e1000_set_ringparam(struct net_device *netdev,
16003 + struct ethtool_ringparam *ring)
16005 + struct e1000_adapter *adapter = netdev_priv(netdev);
16006 + struct e1000_ring *tx_ring, *tx_old;
16007 + struct e1000_ring *rx_ring, *rx_old;
16010 + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
16013 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
16016 + if (netif_running(adapter->netdev))
16017 + e1000_down(adapter);
16019 + tx_old = adapter->tx_ring;
16020 + rx_old = adapter->rx_ring;
16023 + tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
16025 + goto err_alloc_tx;
16027 + * use a memcpy to save any previously configured
16028 + * items like napi structs from having to be
16031 + memcpy(tx_ring, tx_old, sizeof(struct e1000_ring));
16033 + rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
16035 + goto err_alloc_rx;
16036 + memcpy(rx_ring, rx_old, sizeof(struct e1000_ring));
16038 + adapter->tx_ring = tx_ring;
16039 + adapter->rx_ring = rx_ring;
16041 + rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
16042 + rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD));
16043 + rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
16045 + tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
16046 + tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD));
16047 + tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
16049 + if (netif_running(adapter->netdev)) {
16050 + /* Try to get new resources before deleting old */
16051 + err = e1000_setup_rx_resources(adapter);
16053 + goto err_setup_rx;
16054 + err = e1000_setup_tx_resources(adapter);
16056 + goto err_setup_tx;
16059 + * restore the old in order to free it,
16060 + * then add in the new
16062 + adapter->rx_ring = rx_old;
16063 + adapter->tx_ring = tx_old;
16064 + e1000_free_rx_resources(adapter);
16065 + e1000_free_tx_resources(adapter);
16068 + adapter->rx_ring = rx_ring;
16069 + adapter->tx_ring = tx_ring;
16070 + err = e1000_up(adapter);
16075 + clear_bit(__E1000_RESETTING, &adapter->state);
16078 + e1000_free_rx_resources(adapter);
16080 + adapter->rx_ring = rx_old;
16081 + adapter->tx_ring = tx_old;
16086 + e1000_up(adapter);
16088 + clear_bit(__E1000_RESETTING, &adapter->state);
16092 +static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
16093 + int reg, int offset, u32 mask, u32 write)
16096 + static const u32 test[] =
16097 + {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
16098 + for (pat = 0; pat < ARRAY_SIZE(test); pat++) {
16099 + E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset,
16100 + (test[pat] & write));
16101 + val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
16102 + if (val != (test[pat] & write & mask)) {
16103 + e_err("pattern test reg %04X failed: got "
16104 + "0x%08X expected 0x%08X\n",
16106 + val, (test[pat] & write & mask));
16114 +static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
16115 + int reg, u32 mask, u32 write)
16118 + __ew32(&adapter->hw, reg, write & mask);
16119 + val = __er32(&adapter->hw, reg);
16120 + if ((write & mask) != (val & mask)) {
16121 + e_err("set/check reg %04X test failed: got 0x%08X"
16122 + "expected 0x%08X\n", reg, (val & mask), (write & mask));
16128 +#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write) \
16130 + if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \
16133 +#define REG_PATTERN_TEST(reg, mask, write) \
16134 + REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
16136 +#define REG_SET_AND_CHECK(reg, mask, write) \
16138 + if (reg_set_and_check(adapter, data, reg, mask, write)) \
16142 +static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
16144 + struct e1000_hw *hw = &adapter->hw;
16145 + struct e1000_mac_info *mac = &adapter->hw.mac;
16153 + * The status register is Read Only, so a write should fail.
16154 + * Some bits that get toggled are ignored.
16156 + switch (mac->type) {
16157 + /* there are several bits on newer hardware that are r/w */
16158 + case e1000_82571:
16159 + case e1000_82572:
16160 + case e1000_80003es2lan:
16161 + toggle = 0x7FFFF3FF;
16163 + case e1000_82573:
16164 + case e1000_82574:
16165 + case e1000_ich8lan:
16166 + case e1000_ich9lan:
16167 + case e1000_ich10lan:
16168 + toggle = 0x7FFFF033;
16171 + toggle = 0xFFFFF833;
16175 + before = er32(STATUS);
16176 + value = (er32(STATUS) & toggle);
16177 + ew32(STATUS, toggle);
16178 + after = er32(STATUS) & toggle;
16179 + if (value != after) {
16180 + e_err("failed STATUS register test got: "
16181 + "0x%08X expected: 0x%08X\n", after, value);
16185 + /* restore previous status */
16186 + ew32(STATUS, before);
16188 + if (!(adapter->flags & FLAG_IS_ICH)) {
16189 + REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
16190 + REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
16191 + REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
16192 + REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
16195 + REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
16196 + REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
16197 + REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF);
16198 + REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF);
16199 + REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF);
16200 + REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
16201 + REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
16202 + REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
16203 + REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
16204 + REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF);
16206 + REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
16208 + before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
16209 + REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
16210 + REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
16212 + REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
16213 + REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
16214 + if (!(adapter->flags & FLAG_IS_ICH))
16215 + REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
16216 + REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
16217 + REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
16218 + for (i = 0; i < mac->rar_entry_count; i++)
16219 + REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
16220 + ((mac->type == e1000_ich10lan) ?
16221 + 0x8007FFFF : 0x8003FFFF),
16224 + for (i = 0; i < mac->mta_reg_count; i++)
16225 + REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
16231 +static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
16233 + struct e1000_hw *hw = &adapter->hw;
16235 + u16 checksum = 0;
16239 + /* Read and add up the contents of the EEPROM */
16240 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
16241 + if ((hw->nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
16245 + checksum += temp;
16248 + /* If Checksum is not Correct return error else test passed */
16249 + if ((checksum != (u16) NVM_SUM) && !(*data))
16255 +static irqreturn_t e1000_test_intr(int irq, void *data)
16257 + struct net_device *netdev = (struct net_device *) data;
16258 + struct e1000_adapter *adapter = netdev_priv(netdev);
16259 + struct e1000_hw *hw = &adapter->hw;
16261 + adapter->test_icr |= er32(ICR);
16263 + return IRQ_HANDLED;
16266 +static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
16268 + struct net_device *netdev = adapter->netdev;
16269 + struct e1000_hw *hw = &adapter->hw;
16271 + u32 shared_int = 1;
16272 + u32 irq = adapter->pdev->irq;
16274 +#ifdef CONFIG_E1000E_MSIX
16276 + int int_mode = E1000E_INT_MODE_LEGACY;
16281 + /* NOTE: we don't test MSI/MSI-X interrupts here, yet */
16282 +#ifdef CONFIG_E1000E_MSIX
16283 + if (adapter->int_mode == E1000E_INT_MODE_MSIX) {
16284 + int_mode = adapter->int_mode;
16285 + e1000_reset_interrupt_capability(adapter);
16286 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
16287 + e1000_set_interrupt_capability(adapter);
16290 + /* Hook up test interrupt handler just for this test */
16291 + if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
16294 + } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
16295 + netdev->name, netdev)) {
16297 +#ifdef CONFIG_E1000E_MSIX
16304 + e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared"));
16306 + /* Disable all the interrupts */
16307 + ew32(IMC, 0xFFFFFFFF);
16310 + /* Test each interrupt */
16311 + for (i = 0; i < 10; i++) {
16312 + /* Interrupt to test */
16315 + if (adapter->flags & FLAG_IS_ICH) {
16317 + case E1000_ICR_RXSEQ:
16320 + if (adapter->hw.mac.type == e1000_ich8lan ||
16321 + adapter->hw.mac.type == e1000_ich9lan)
16329 + if (!shared_int) {
16331 + * Disable the interrupt to be reported in
16332 + * the cause register and then force the same
16333 + * interrupt and see if one gets posted. If
16334 + * an interrupt was posted to the bus, the
16337 + adapter->test_icr = 0;
16342 + if (adapter->test_icr & mask) {
16349 + * Enable the interrupt to be reported in
16350 + * the cause register and then force the same
16351 + * interrupt and see if one gets posted. If
16352 + * an interrupt was not posted to the bus, the
16355 + adapter->test_icr = 0;
16360 + if (!(adapter->test_icr & mask)) {
16365 + if (!shared_int) {
16367 + * Disable the other interrupts to be reported in
16368 + * the cause register and then force the other
16369 + * interrupts and see if any get posted. If
16370 + * an interrupt was posted to the bus, the
16373 + adapter->test_icr = 0;
16374 + ew32(IMC, ~mask & 0x00007FFF);
16375 + ew32(ICS, ~mask & 0x00007FFF);
16378 + if (adapter->test_icr) {
16385 + /* Disable all the interrupts */
16386 + ew32(IMC, 0xFFFFFFFF);
16389 + /* Unhook test interrupt handler */
16390 + free_irq(irq, netdev);
16392 +#ifdef CONFIG_E1000E_MSIX
16394 + if (int_mode == E1000E_INT_MODE_MSIX) {
16395 + e1000_reset_interrupt_capability(adapter);
16396 + adapter->int_mode = int_mode;
16397 + e1000_set_interrupt_capability(adapter);
16406 +static void e1000_free_desc_rings(struct e1000_adapter *adapter)
16408 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
16409 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
16410 + struct pci_dev *pdev = adapter->pdev;
16413 + if (tx_ring->desc && tx_ring->buffer_info) {
16414 + for (i = 0; i < tx_ring->count; i++) {
16415 + if (tx_ring->buffer_info[i].dma)
16416 + pci_unmap_single(pdev,
16417 + tx_ring->buffer_info[i].dma,
16418 + tx_ring->buffer_info[i].length,
16419 + PCI_DMA_TODEVICE);
16420 + if (tx_ring->buffer_info[i].skb)
16421 + dev_kfree_skb(tx_ring->buffer_info[i].skb);
16425 + if (rx_ring->desc && rx_ring->buffer_info) {
16426 + for (i = 0; i < rx_ring->count; i++) {
16427 + if (rx_ring->buffer_info[i].dma)
16428 + pci_unmap_single(pdev,
16429 + rx_ring->buffer_info[i].dma,
16430 + 2048, PCI_DMA_FROMDEVICE);
16431 + if (rx_ring->buffer_info[i].skb)
16432 + dev_kfree_skb(rx_ring->buffer_info[i].skb);
16436 + if (tx_ring->desc) {
16437 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
16439 + tx_ring->desc = NULL;
16441 + if (rx_ring->desc) {
16442 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
16444 + rx_ring->desc = NULL;
16447 + kfree(tx_ring->buffer_info);
16448 + tx_ring->buffer_info = NULL;
16449 + kfree(rx_ring->buffer_info);
16450 + rx_ring->buffer_info = NULL;
16453 +static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
16455 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
16456 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
16457 + struct pci_dev *pdev = adapter->pdev;
16458 + struct e1000_hw *hw = &adapter->hw;
16463 + /* Setup Tx descriptor ring and Tx buffers */
16465 + if (!tx_ring->count)
16466 + tx_ring->count = E1000_DEFAULT_TXD;
16468 + if (!(tx_ring->buffer_info = kcalloc(tx_ring->count,
16469 + sizeof(struct e1000_buffer),
16475 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
16476 + tx_ring->size = ALIGN(tx_ring->size, 4096);
16477 + tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
16478 + &tx_ring->dma, GFP_KERNEL);
16479 + if (!tx_ring->desc) {
16483 + tx_ring->next_to_use = 0;
16484 + tx_ring->next_to_clean = 0;
16486 + ew32(TDBAL(0), ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
16487 + ew32(TDBAH(0), ((u64) tx_ring->dma >> 32));
16488 + ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc));
16491 + ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR |
16492 + E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
16493 + E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
16495 + for (i = 0; i < tx_ring->count; i++) {
16496 + struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
16497 + struct sk_buff *skb;
16498 + unsigned int skb_size = 1024;
16500 + skb = alloc_skb(skb_size, GFP_KERNEL);
16505 + skb_put(skb, skb_size);
16506 + tx_ring->buffer_info[i].skb = skb;
16507 + tx_ring->buffer_info[i].length = skb->len;
16508 + tx_ring->buffer_info[i].dma =
16509 + pci_map_single(pdev, skb->data, skb->len,
16510 + PCI_DMA_TODEVICE);
16511 + if (pci_dma_mapping_error(pdev, tx_ring->buffer_info[i].dma)) {
16515 + tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
16516 + tx_desc->lower.data = cpu_to_le32(skb->len);
16517 + tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
16518 + E1000_TXD_CMD_IFCS |
16519 + E1000_TXD_CMD_RS);
16520 + tx_desc->upper.data = 0;
16523 + /* Setup Rx descriptor ring and Rx buffers */
16525 + if (!rx_ring->count)
16526 + rx_ring->count = E1000_DEFAULT_RXD;
16528 + if (!(rx_ring->buffer_info = kcalloc(rx_ring->count,
16529 + sizeof(struct e1000_buffer),
16535 + rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
16536 + rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
16537 + &rx_ring->dma, GFP_KERNEL);
16538 + if (!rx_ring->desc) {
16542 + rx_ring->next_to_use = 0;
16543 + rx_ring->next_to_clean = 0;
16545 + rctl = er32(RCTL);
16546 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
16547 + ew32(RDBAL(0), ((u64) rx_ring->dma & 0xFFFFFFFF));
16548 + ew32(RDBAH(0), ((u64) rx_ring->dma >> 32));
16549 + ew32(RDLEN(0), rx_ring->size);
16552 + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
16553 + E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE |
16554 + E1000_RCTL_SBP | E1000_RCTL_SECRC |
16555 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
16556 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
16557 + ew32(RCTL, rctl);
16559 + for (i = 0; i < rx_ring->count; i++) {
16560 + struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
16561 + struct sk_buff *skb;
16563 + skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL);
16568 + skb_reserve(skb, NET_IP_ALIGN);
16569 + rx_ring->buffer_info[i].skb = skb;
16570 + rx_ring->buffer_info[i].dma =
16571 + pci_map_single(pdev, skb->data, 2048,
16572 + PCI_DMA_FROMDEVICE);
16573 + if (pci_dma_mapping_error(pdev, rx_ring->buffer_info[i].dma)) {
16577 + rx_desc->buffer_addr =
16578 + cpu_to_le64(rx_ring->buffer_info[i].dma);
16579 + memset(skb->data, 0x00, skb->len);
16585 + e1000_free_desc_rings(adapter);
16589 +static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
16591 + /* Write out to PHY registers 29 and 30 to disable the Receiver. */
16592 + adapter->hw.phy.ops.write_reg(&adapter->hw, 29, 0x001F);
16593 + adapter->hw.phy.ops.write_reg(&adapter->hw, 30, 0x8FFC);
16594 + adapter->hw.phy.ops.write_reg(&adapter->hw, 29, 0x001A);
16595 + adapter->hw.phy.ops.write_reg(&adapter->hw, 30, 0x8FF0);
16598 +static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
16600 + struct e1000_hw *hw = &adapter->hw;
16601 + u32 ctrl_reg = 0;
16602 + u32 stat_reg = 0;
16605 + hw->mac.autoneg = 0;
16607 + if (hw->phy.type == e1000_phy_m88) {
16608 + /* Auto-MDI/MDIX Off */
16609 + hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
16610 + /* reset to update Auto-MDI/MDIX */
16611 + hw->phy.ops.write_reg(hw, PHY_CONTROL, 0x9140);
16612 + /* autoneg off */
16613 + hw->phy.ops.write_reg(hw, PHY_CONTROL, 0x8140);
16614 + } else if (hw->phy.type == e1000_phy_gg82563)
16615 + hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
16617 + ctrl_reg = er32(CTRL);
16619 + switch (hw->phy.type) {
16620 + case e1000_phy_ife:
16621 + /* force 100, set loopback */
16622 + hw->phy.ops.write_reg(hw, PHY_CONTROL, 0x6100);
16624 + /* Now set up the MAC to the same speed/duplex as the PHY. */
16625 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
16626 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
16627 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
16628 + E1000_CTRL_SPD_100 |/* Force Speed to 100 */
16629 + E1000_CTRL_FD); /* Force Duplex to FULL */
16631 + case e1000_phy_bm:
16632 + /* Set Default MAC Interface speed to 1GB */
16633 + hw->phy.ops.read_reg(hw, PHY_REG(2, 21), &phy_reg);
16634 + phy_reg &= ~0x0007;
16635 + phy_reg |= 0x006;
16636 + hw->phy.ops.write_reg(hw, PHY_REG(2, 21), phy_reg);
16637 + /* Assert SW reset for above settings to take effect */
16638 + hw->phy.ops.commit(hw);
16640 + /* Force Full Duplex */
16641 + hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &phy_reg);
16642 + hw->phy.ops.write_reg(hw, PHY_REG(769, 16), phy_reg | 0x000C);
16643 + /* Set Link Up (in force link) */
16644 + hw->phy.ops.read_reg(hw, PHY_REG(776, 16), &phy_reg);
16645 + hw->phy.ops.write_reg(hw, PHY_REG(776, 16), phy_reg | 0x0040);
16647 + hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &phy_reg);
16648 + hw->phy.ops.write_reg(hw, PHY_REG(769, 16), phy_reg | 0x0040);
16649 + /* Set Early Link Enable */
16650 + hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
16651 + hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | 0x0400);
16652 + /* fall through */
16654 + /* force 1000, set loopback */
16655 + hw->phy.ops.write_reg(hw, PHY_CONTROL, 0x4140);
16658 + /* Now set up the MAC to the same speed/duplex as the PHY. */
16659 + ctrl_reg = er32(CTRL);
16660 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
16661 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
16662 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
16663 + E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
16664 + E1000_CTRL_FD); /* Force Duplex to FULL */
16666 + if (adapter->flags & FLAG_IS_ICH)
16667 + ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */
16670 + if (hw->phy.media_type == e1000_media_type_copper &&
16671 + hw->phy.type == e1000_phy_m88) {
16672 + ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
16675 + * Set the ILOS bit on the fiber Nic if half duplex link is
16678 + stat_reg = er32(STATUS);
16679 + if ((stat_reg & E1000_STATUS_FD) == 0)
16680 + ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
16683 + ew32(CTRL, ctrl_reg);
16686 + * Disable the receiver on the PHY so when a cable is plugged in, the
16687 + * PHY does not begin to autoneg when a cable is reconnected to the NIC.
16689 + if (hw->phy.type == e1000_phy_m88)
16690 + e1000_phy_disable_receiver(adapter);
16697 +static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
16699 + struct e1000_hw *hw = &adapter->hw;
16700 + u32 ctrl = er32(CTRL);
16703 + /* special requirements for 82571/82572 fiber adapters */
16706 + * jump through hoops to make sure link is up because serdes
16707 + * link is hardwired up
16709 + ctrl |= E1000_CTRL_SLU;
16710 + ew32(CTRL, ctrl);
16712 + /* disable autoneg */
16713 + ctrl = er32(TXCW);
16714 + ctrl &= ~(1 << 31);
16715 + ew32(TXCW, ctrl);
16717 + link = (er32(STATUS) & E1000_STATUS_LU);
16720 + /* set invert loss of signal */
16721 + ctrl = er32(CTRL);
16722 + ctrl |= E1000_CTRL_ILOS;
16723 + ew32(CTRL, ctrl);
16727 + * special write to serdes control register to enable SerDes analog
16730 +#define E1000_SERDES_LB_ON 0x410
16731 + ew32(SCTL, E1000_SERDES_LB_ON);
16737 +/* only call this for fiber/serdes connections to es2lan */
16738 +static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
16740 + struct e1000_hw *hw = &adapter->hw;
16741 + u32 ctrlext = er32(CTRL_EXT);
16742 + u32 ctrl = er32(CTRL);
16745 + * save CTRL_EXT to restore later, reuse an empty variable (unused
16746 + * on mac_type 80003es2lan)
16748 + adapter->tx_fifo_head = ctrlext;
16750 + /* clear the serdes mode bits, putting the device into mac loopback */
16751 + ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
16752 + ew32(CTRL_EXT, ctrlext);
16754 + /* force speed to 1000/FD, link up */
16755 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
16756 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
16757 + E1000_CTRL_SPD_1000 | E1000_CTRL_FD);
16758 + ew32(CTRL, ctrl);
16760 + /* set mac loopback */
16761 + ctrl = er32(RCTL);
16762 + ctrl |= E1000_RCTL_LBM_MAC;
16763 + ew32(RCTL, ctrl);
16765 + /* set testing mode parameters (no need to reset later) */
16766 +#define KMRNCTRLSTA_OPMODE (0x1F << 16)
16767 +#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582
16768 + ew32(KMRNCTRLSTA,
16769 + (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII));
16774 +static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
16776 + struct e1000_hw *hw = &adapter->hw;
16779 + if (hw->phy.media_type == e1000_media_type_fiber ||
16780 + hw->phy.media_type == e1000_media_type_internal_serdes) {
16781 + switch (hw->mac.type) {
16782 + case e1000_80003es2lan:
16783 + return e1000_set_es2lan_mac_loopback(adapter);
16785 + case e1000_82571:
16786 + case e1000_82572:
16787 + return e1000_set_82571_fiber_loopback(adapter);
16790 + rctl = er32(RCTL);
16791 + rctl |= E1000_RCTL_LBM_TCVR;
16792 + ew32(RCTL, rctl);
16795 + } else if (hw->phy.media_type == e1000_media_type_copper) {
16796 + return e1000_integrated_phy_loopback(adapter);
16802 +static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
16804 + struct e1000_hw *hw = &adapter->hw;
16808 + rctl = er32(RCTL);
16809 + rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
16810 + ew32(RCTL, rctl);
16812 + switch (hw->mac.type) {
16813 + case e1000_80003es2lan:
16814 + if (hw->phy.media_type == e1000_media_type_fiber ||
16815 + hw->phy.media_type == e1000_media_type_internal_serdes) {
16816 + /* restore CTRL_EXT, stealing space from tx_fifo_head */
16817 + ew32(CTRL_EXT, adapter->tx_fifo_head);
16818 + adapter->tx_fifo_head = 0;
16820 + /* fall through */
16821 + case e1000_82571:
16822 + case e1000_82572:
16823 + if (hw->phy.media_type == e1000_media_type_fiber ||
16824 + hw->phy.media_type == e1000_media_type_internal_serdes) {
16825 +#define E1000_SERDES_LB_OFF 0x400
16826 + ew32(SCTL, E1000_SERDES_LB_OFF);
16830 + /* Fall Through */
16832 + hw->mac.autoneg = 1;
16833 + if (hw->phy.type == e1000_phy_gg82563)
16834 + hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
16836 + if(hw->phy.ops.read_reg)
16837 + hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_reg);
16838 + if (phy_reg & MII_CR_LOOPBACK) {
16839 + phy_reg &= ~MII_CR_LOOPBACK;
16840 + hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_reg);
16841 + if (hw->phy.ops.commit)
16842 + hw->phy.ops.commit(hw);
16848 +static void e1000_create_lbtest_frame(struct sk_buff *skb,
16849 + unsigned int frame_size)
16851 + memset(skb->data, 0xFF, frame_size);
16852 + frame_size &= ~1;
16853 + memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
16854 + memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
16855 + memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
16858 +static int e1000_check_lbtest_frame(struct sk_buff *skb,
16859 + unsigned int frame_size)
16861 + frame_size &= ~1;
16862 + if (*(skb->data + 3) == 0xFF)
16863 + if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
16864 + (*(skb->data + frame_size / 2 + 12) == 0xAF))
16869 +static int e1000_run_loopback_test(struct e1000_adapter *adapter)
16871 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
16872 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
16873 + struct pci_dev *pdev = adapter->pdev;
16874 + struct e1000_hw *hw = &adapter->hw;
16879 + unsigned long time;
16881 + ew32(RDT(0), rx_ring->count - 1);
16884 + * Calculate the loop count based on the largest descriptor ring
16885 + * The idea is to wrap the largest ring a number of times using 64
16886 + * send/receive pairs during each loop
16889 + if (rx_ring->count <= tx_ring->count)
16890 + lc = ((tx_ring->count / 64) * 2) + 1;
16892 + lc = ((rx_ring->count / 64) * 2) + 1;
16896 + for (j = 0; j <= lc; j++) { /* loop count loop */
16897 + for (i = 0; i < 64; i++) { /* send the packets */
16898 + e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb,
16900 + pci_dma_sync_single_for_device(pdev,
16901 + tx_ring->buffer_info[k].dma,
16902 + tx_ring->buffer_info[k].length,
16903 + PCI_DMA_TODEVICE);
16905 + if (k == tx_ring->count)
16910 + time = jiffies; /* set the start time for the receive */
16912 + do { /* receive the sent packets */
16913 + pci_dma_sync_single_for_cpu(pdev,
16914 + rx_ring->buffer_info[l].dma, 2048,
16915 + PCI_DMA_FROMDEVICE);
16917 + ret_val = e1000_check_lbtest_frame(
16918 + rx_ring->buffer_info[l].skb, 1024);
16922 + if (l == rx_ring->count)
16925 + * time + 20 msecs (200 msecs on 2.4) is more than
16926 + * enough time to complete the receives, if it's
16927 + * exceeded, break and error off
16929 + } while ((good_cnt < 64) && !time_after(jiffies, time + 20));
16930 + if (good_cnt != 64) {
16931 + ret_val = 13; /* ret_val is the same as mis-compare */
16934 + if (jiffies >= (time + 20)) {
16935 + ret_val = 14; /* error code for time out error */
16938 + } /* end loop count loop */
16942 +static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
16944 + struct e1000_hw *hw = &adapter->hw;
16946 + * PHY loopback cannot be performed if SoL/IDER
16947 + * sessions are active
16949 + if (hw->phy.ops.check_reset_block &&
16950 + hw->phy.ops.check_reset_block(&adapter->hw)) {
16951 + e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
16956 + *data = e1000_setup_desc_rings(adapter);
16960 + *data = e1000_setup_loopback_test(adapter);
16962 + goto err_loopback;
16964 + *data = e1000_run_loopback_test(adapter);
16965 + e1000_loopback_cleanup(adapter);
16968 + e1000_free_desc_rings(adapter);
16973 +static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
16975 + struct e1000_hw *hw = &adapter->hw;
16978 + if (hw->phy.media_type == e1000_media_type_internal_serdes) {
16980 + hw->mac.serdes_has_link = 0;
16983 + * On some blade server designs, link establishment
16984 + * could take as long as 2-3 minutes
16987 + hw->mac.ops.check_for_link(hw);
16988 + if (hw->mac.serdes_has_link)
16991 + } while (i++ < 3750);
16995 + hw->mac.ops.check_for_link(hw);
16996 + if (hw->mac.autoneg)
16999 + if (!(er32(STATUS) &
17000 + E1000_STATUS_LU))
17006 +static int e1000_get_self_test_count(struct net_device *netdev)
17008 + return E1000_TEST_LEN;
17011 +static int e1000_get_stats_count(struct net_device *netdev)
17013 + return E1000_STATS_LEN;
17016 +static void e1000_diag_test(struct net_device *netdev,
17017 + struct ethtool_test *eth_test, u64 *data)
17019 + struct e1000_adapter *adapter = netdev_priv(netdev);
17020 + u16 autoneg_advertised;
17021 + u8 forced_speed_duplex;
17023 + bool if_running = netif_running(netdev);
17025 + set_bit(__E1000_TESTING, &adapter->state);
17026 + if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
17027 + /* Offline tests */
17029 + /* save speed, duplex, autoneg settings */
17030 + autoneg_advertised = adapter->hw.phy.autoneg_advertised;
17031 + forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
17032 + autoneg = adapter->hw.mac.autoneg;
17034 + e_info("offline testing starting\n");
17037 + * Link test performed before hardware reset so autoneg doesn't
17038 + * interfere with test result
17040 + if (e1000_link_test(adapter, &data[4]))
17041 + eth_test->flags |= ETH_TEST_FL_FAILED;
17044 + /* indicate we're in test mode */
17045 + dev_close(netdev);
17047 + e1000_reset(adapter);
17049 + if (e1000_reg_test(adapter, &data[0]))
17050 + eth_test->flags |= ETH_TEST_FL_FAILED;
17052 + e1000_reset(adapter);
17053 + if (e1000_eeprom_test(adapter, &data[1]))
17054 + eth_test->flags |= ETH_TEST_FL_FAILED;
17056 + e1000_reset(adapter);
17057 + if (e1000_intr_test(adapter, &data[2]))
17058 + eth_test->flags |= ETH_TEST_FL_FAILED;
17060 + e1000_reset(adapter);
17061 + /* make sure the phy is powered up */
17062 + e1000_power_up_phy(&adapter->hw);
17063 + if (e1000_loopback_test(adapter, &data[3]))
17064 + eth_test->flags |= ETH_TEST_FL_FAILED;
17066 + /* restore speed, duplex, autoneg settings */
17067 + adapter->hw.phy.autoneg_advertised = autoneg_advertised;
17068 + adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
17069 + adapter->hw.mac.autoneg = autoneg;
17071 + /* force this routine to wait until autoneg complete/timeout */
17072 + adapter->hw.phy.autoneg_wait_to_complete = 1;
17073 + e1000_reset(adapter);
17074 + adapter->hw.phy.autoneg_wait_to_complete = 0;
17076 + clear_bit(__E1000_TESTING, &adapter->state);
17078 + dev_open(netdev);
17080 + e_info("online testing starting\n");
17081 + /* Online tests */
17082 + if (e1000_link_test(adapter, &data[4]))
17083 + eth_test->flags |= ETH_TEST_FL_FAILED;
17085 + /* Online tests aren't run; pass by default */
17091 + clear_bit(__E1000_TESTING, &adapter->state);
17093 + msleep_interruptible(4 * 1000);
17096 +static void e1000_get_wol(struct net_device *netdev,
17097 + struct ethtool_wolinfo *wol)
17099 + struct e1000_adapter *adapter = netdev_priv(netdev);
17101 + wol->supported = 0;
17102 + wol->wolopts = 0;
17104 + if (!(adapter->flags & FLAG_HAS_WOL))
17107 + wol->supported = WAKE_UCAST | WAKE_MCAST |
17108 + WAKE_BCAST | WAKE_MAGIC |
17109 + WAKE_PHY | WAKE_ARP;
17111 + /* apply any specific unsupported masks here */
17112 + if (adapter->flags & FLAG_NO_WAKE_UCAST) {
17113 + wol->supported &= ~WAKE_UCAST;
17115 + if (adapter->wol & E1000_WUFC_EX)
17116 + e_err("Interface does not support directed (unicast)"
17117 + " frame wake-up packets\n");
17120 + if (adapter->wol & E1000_WUFC_EX)
17121 + wol->wolopts |= WAKE_UCAST;
17122 + if (adapter->wol & E1000_WUFC_MC)
17123 + wol->wolopts |= WAKE_MCAST;
17124 + if (adapter->wol & E1000_WUFC_BC)
17125 + wol->wolopts |= WAKE_BCAST;
17126 + if (adapter->wol & E1000_WUFC_MAG)
17127 + wol->wolopts |= WAKE_MAGIC;
17128 + if (adapter->wol & E1000_WUFC_LNKC)
17129 + wol->wolopts |= WAKE_PHY;
17130 + if (adapter->wol & E1000_WUFC_ARP)
17131 + wol->wolopts |= WAKE_ARP;
17134 +static int e1000_set_wol(struct net_device *netdev,
17135 + struct ethtool_wolinfo *wol)
17137 + struct e1000_adapter *adapter = netdev_priv(netdev);
17139 + if (wol->wolopts & WAKE_MAGICSECURE)
17140 + return -EOPNOTSUPP;
17142 + if (!(adapter->flags & FLAG_HAS_WOL))
17143 + return wol->wolopts ? -EOPNOTSUPP : 0;
17145 + /* these settings will always override what we currently have */
17146 + adapter->wol = 0;
17148 + if (wol->wolopts & WAKE_UCAST)
17149 + adapter->wol |= E1000_WUFC_EX;
17150 + if (wol->wolopts & WAKE_MCAST)
17151 + adapter->wol |= E1000_WUFC_MC;
17152 + if (wol->wolopts & WAKE_BCAST)
17153 + adapter->wol |= E1000_WUFC_BC;
17154 + if (wol->wolopts & WAKE_MAGIC)
17155 + adapter->wol |= E1000_WUFC_MAG;
17156 + if (wol->wolopts & WAKE_PHY)
17157 + adapter->wol |= E1000_WUFC_LNKC;
17158 + if (wol->wolopts & WAKE_ARP)
17159 + adapter->wol |= E1000_WUFC_ARP;
17164 +/* toggle LED 4 times per second = 2 "blinks" per second */
17165 +#define E1000_ID_INTERVAL (HZ/4)
17167 +/* bit defines for adapter->led_status */
17168 +#define E1000_LED_ON 0
17170 +static void e1000_led_blink_callback(unsigned long data)
17172 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
17174 + if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
17175 + adapter->hw.mac.ops.led_off(&adapter->hw);
17177 + adapter->hw.mac.ops.led_on(&adapter->hw);
17179 + mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
17182 +static int e1000_phys_id(struct net_device *netdev, u32 data)
17184 + struct e1000_adapter *adapter = netdev_priv(netdev);
17185 + struct e1000_hw *hw = &adapter->hw;
17190 + if ((hw->phy.type == e1000_phy_ife) ||
17191 + (hw->mac.type == e1000_82574)) {
17192 + if (!adapter->blink_timer.function) {
17193 + init_timer(&adapter->blink_timer);
17194 + adapter->blink_timer.function =
17195 + e1000_led_blink_callback;
17196 + adapter->blink_timer.data = (unsigned long) adapter;
17198 + mod_timer(&adapter->blink_timer, jiffies);
17199 + msleep_interruptible(data * 1000);
17200 + del_timer_sync(&adapter->blink_timer);
17201 + if (hw->phy.type == e1000_phy_ife)
17202 + hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
17205 + hw->mac.ops.blink_led(hw);
17206 + msleep_interruptible(data * 1000);
17209 + hw->mac.ops.led_off(hw);
17210 + clear_bit(E1000_LED_ON, &adapter->led_status);
17211 + hw->mac.ops.cleanup_led(hw);
17216 +static int e1000_get_coalesce(struct net_device *netdev,
17217 + struct ethtool_coalesce *ec)
17219 + struct e1000_adapter *adapter = netdev_priv(netdev);
17221 + if (adapter->itr_setting <= 3)
17222 + ec->rx_coalesce_usecs = adapter->itr_setting;
17224 + ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
17226 + ec->stats_block_coalesce_usecs = adapter->stats_freq_us;
17231 +static int e1000_set_coalesce(struct net_device *netdev,
17232 + struct ethtool_coalesce *ec)
17234 + struct e1000_adapter *adapter = netdev_priv(netdev);
17235 + struct e1000_hw *hw = &adapter->hw;
17237 + if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) ||
17238 + ((ec->rx_coalesce_usecs > 3) &&
17239 + (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) ||
17240 + (ec->rx_coalesce_usecs == 2) ||
17241 + (ec->stats_block_coalesce_usecs > (10 * 1000000)))
17244 + adapter->stats_freq_us = ec->stats_block_coalesce_usecs;
17246 + if (ec->rx_coalesce_usecs <= 3) {
17247 + adapter->itr = 20000;
17248 + adapter->itr_setting = ec->rx_coalesce_usecs;
17250 + adapter->itr = (1000000 / ec->rx_coalesce_usecs);
17251 + adapter->itr_setting = adapter->itr & ~3;
17254 + if (adapter->itr_setting != 0)
17255 + ew32(ITR, 1000000000 / (adapter->itr * 256));
17262 +static int e1000_nway_reset(struct net_device *netdev)
17264 + struct e1000_adapter *adapter = netdev_priv(netdev);
17265 + if (netif_running(netdev))
17266 + e1000_reinit_locked(adapter);
17270 +static void e1000_get_ethtool_stats(struct net_device *netdev,
17271 + struct ethtool_stats *stats,
17274 + struct e1000_adapter *adapter = netdev_priv(netdev);
17277 + e1000_update_stats(adapter);
17278 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
17279 + char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
17280 + data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
17281 + sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
17285 +static void e1000_get_strings(struct net_device *netdev, u32 stringset,
17291 + switch (stringset) {
17292 + case ETH_SS_TEST:
17293 + memcpy(data, *e1000_gstrings_test, sizeof(e1000_gstrings_test));
17295 + case ETH_SS_STATS:
17296 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
17297 + memcpy(p, e1000_gstrings_stats[i].stat_string,
17298 + ETH_GSTRING_LEN);
17299 + p += ETH_GSTRING_LEN;
17305 +static const struct ethtool_ops e1000_ethtool_ops = {
17306 + .get_settings = e1000_get_settings,
17307 + .set_settings = e1000_set_settings,
17308 + .get_drvinfo = e1000_get_drvinfo,
17309 + .get_regs_len = e1000_get_regs_len,
17310 + .get_regs = e1000_get_regs,
17311 + .get_wol = e1000_get_wol,
17312 + .set_wol = e1000_set_wol,
17313 + .get_msglevel = e1000_get_msglevel,
17314 + .set_msglevel = e1000_set_msglevel,
17315 + .nway_reset = e1000_nway_reset,
17316 + .get_link = e1000_get_link,
17317 + .get_eeprom_len = e1000_get_eeprom_len,
17318 + .get_eeprom = e1000_get_eeprom,
17319 + .set_eeprom = e1000_set_eeprom,
17320 + .get_ringparam = e1000_get_ringparam,
17321 + .set_ringparam = e1000_set_ringparam,
17322 + .get_pauseparam = e1000_get_pauseparam,
17323 + .set_pauseparam = e1000_set_pauseparam,
17324 + .get_rx_csum = e1000_get_rx_csum,
17325 + .set_rx_csum = e1000_set_rx_csum,
17326 + .get_tx_csum = e1000_get_tx_csum,
17327 + .set_tx_csum = e1000_set_tx_csum,
17328 + .get_sg = ethtool_op_get_sg,
17329 + .set_sg = ethtool_op_set_sg,
17330 +#ifdef NETIF_F_TSO
17331 + .get_tso = ethtool_op_get_tso,
17332 + .set_tso = e1000_set_tso,
17334 + .self_test = e1000_diag_test,
17335 + .get_strings = e1000_get_strings,
17336 + .phys_id = e1000_phys_id,
17337 + .get_ethtool_stats = e1000_get_ethtool_stats,
17338 + .self_test_count = e1000_get_self_test_count,
17339 + .get_stats_count = e1000_get_stats_count,
17340 + .get_coalesce = e1000_get_coalesce,
17341 + .set_coalesce = e1000_set_coalesce,
17344 +void e1000_set_ethtool_ops(struct net_device *netdev)
17346 + /* have to "undeclare" const on this struct to remove warnings */
17347 + SET_ETHTOOL_OPS(netdev, (struct ethtool_ops *)&e1000_ethtool_ops);
17349 +#endif /* SIOCETHTOOL */
17350 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat.c linux-2.6.22-10/drivers/net/e1000e/kcompat.c
17351 --- linux-2.6.22-0/drivers/net/e1000e/kcompat.c 1970-01-01 01:00:00.000000000 +0100
17352 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat.c 2008-11-10 17:29:35.000000000 +0100
17354 +/*******************************************************************************
17356 + Intel PRO/1000 Linux driver
17357 + Copyright(c) 1999 - 2008 Intel Corporation.
17359 + This program is free software; you can redistribute it and/or modify it
17360 + under the terms and conditions of the GNU General Public License,
17361 + version 2, as published by the Free Software Foundation.
17363 + This program is distributed in the hope it will be useful, but WITHOUT
17364 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17365 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17368 + You should have received a copy of the GNU General Public License along with
17369 + this program; if not, write to the Free Software Foundation, Inc.,
17370 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17372 + The full GNU General Public License is included in this distribution in
17373 + the file called "COPYING".
17375 + Contact Information:
17376 + Linux NICS <linux.nics@intel.com>
17377 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
17378 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17380 +*******************************************************************************/
17383 +#define DRIVER_E1000E
17385 +#ifdef DRIVER_E1000E
17386 +#include "e1000.h"
17392 +#include "kcompat.h"
17394 +/*****************************************************************************/
17395 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )
17397 +/**************************************/
17398 +/* PCI DMA MAPPING */
17400 +#if defined(CONFIG_HIGHMEM)
17402 +#ifndef PCI_DRAM_OFFSET
17403 +#define PCI_DRAM_OFFSET 0
17407 +_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,
17408 + size_t size, int direction)
17410 + return (((u64) (page - mem_map) << PAGE_SHIFT) + offset +
17411 + PCI_DRAM_OFFSET);
17414 +#else /* CONFIG_HIGHMEM */
17417 +_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,
17418 + size_t size, int direction)
17420 + return pci_map_single(dev, (void *)page_address(page) + offset, size,
17424 +#endif /* CONFIG_HIGHMEM */
17427 +_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size,
17430 + return pci_unmap_single(dev, dma_addr, size, direction);
17433 +#endif /* 2.4.13 => 2.4.3 */
17435 +/*****************************************************************************/
17436 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )
17438 +/**************************************/
17439 +/* PCI DRIVER API */
17442 +_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask)
17444 + if (!pci_dma_supported(dev, mask))
17446 + dev->dma_mask = mask;
17451 +_kc_pci_request_regions(struct pci_dev *dev, char *res_name)
17455 + for (i = 0; i < 6; i++) {
17456 + if (pci_resource_len(dev, i) == 0)
17459 + if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
17460 + if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {
17461 + pci_release_regions(dev);
17464 + } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) {
17465 + if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {
17466 + pci_release_regions(dev);
17475 +_kc_pci_release_regions(struct pci_dev *dev)
17479 + for (i = 0; i < 6; i++) {
17480 + if (pci_resource_len(dev, i) == 0)
17483 + if (pci_resource_flags(dev, i) & IORESOURCE_IO)
17484 + release_region(pci_resource_start(dev, i), pci_resource_len(dev, i));
17486 + else if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
17487 + release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i));
17491 +/**************************************/
17492 +/* NETWORK DRIVER API */
17494 +struct net_device *
17495 +_kc_alloc_etherdev(int sizeof_priv)
17497 + struct net_device *dev;
17500 + alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31;
17501 + dev = kmalloc(alloc_size, GFP_KERNEL);
17504 + memset(dev, 0, alloc_size);
17507 + dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31);
17508 + dev->name[0] = '\0';
17509 + ether_setup(dev);
17515 +_kc_is_valid_ether_addr(u8 *addr)
17517 + const char zaddr[6] = { 0, };
17519 + return !(addr[0] & 1) && memcmp(addr, zaddr, 6);
17522 +#endif /* 2.4.3 => 2.4.0 */
17524 +/*****************************************************************************/
17525 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )
17528 +_kc_pci_set_power_state(struct pci_dev *dev, int state)
17534 +_kc_pci_save_state(struct pci_dev *dev, u32 *buffer)
17540 +_kc_pci_restore_state(struct pci_dev *pdev, u32 *buffer)
17546 +_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable)
17551 +#endif /* 2.4.6 => 2.4.3 */
17553 +/*****************************************************************************/
17554 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
17555 +void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page,
17556 + int off, int size)
17558 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
17559 + frag->page = page;
17560 + frag->page_offset = off;
17561 + frag->size = size;
17562 + skb_shinfo(skb)->nr_frags = i + 1;
17566 + * Original Copyright:
17567 + * find_next_bit.c: fallback find next bit implementation
17569 + * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
17570 + * Written by David Howells (dhowells@redhat.com)
17574 + * find_next_bit - find the next set bit in a memory region
17575 + * @addr: The address to base the search on
17576 + * @offset: The bitnumber to start searching at
17577 + * @size: The maximum size to search
17579 +unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
17580 + unsigned long offset)
17582 + const unsigned long *p = addr + BITOP_WORD(offset);
17583 + unsigned long result = offset & ~(BITS_PER_LONG-1);
17584 + unsigned long tmp;
17586 + if (offset >= size)
17589 + offset %= BITS_PER_LONG;
17592 + tmp &= (~0UL << offset);
17593 + if (size < BITS_PER_LONG)
17594 + goto found_first;
17596 + goto found_middle;
17597 + size -= BITS_PER_LONG;
17598 + result += BITS_PER_LONG;
17600 + while (size & ~(BITS_PER_LONG-1)) {
17601 + if ((tmp = *(p++)))
17602 + goto found_middle;
17603 + result += BITS_PER_LONG;
17604 + size -= BITS_PER_LONG;
17611 + tmp &= (~0UL >> (BITS_PER_LONG - size));
17612 + if (tmp == 0UL) /* Are any bits set? */
17613 + return result + size; /* Nope. */
17615 + return result + ffs(tmp);
17618 +#endif /* 2.6.0 => 2.4.6 */
17620 +/*****************************************************************************/
17621 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )
17622 +void *_kc_kzalloc(size_t size, int flags)
17624 + void *ret = kmalloc(size, flags);
17626 + memset(ret, 0, size);
17629 +#endif /* <= 2.6.13 */
17631 +/*****************************************************************************/
17632 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )
17633 +struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev,
17634 + unsigned int length)
17636 + /* 16 == NET_PAD_SKB */
17637 + struct sk_buff *skb;
17638 + skb = alloc_skb(length + 16, GFP_ATOMIC);
17639 + if (likely(skb != NULL)) {
17640 + skb_reserve(skb, 16);
17645 +#endif /* <= 2.6.17 */
17647 +/*****************************************************************************/
17648 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )
17649 +#endif /* < 2.6.23 */
17651 +/*****************************************************************************/
17652 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
17654 +int __kc_adapter_clean(struct net_device *netdev, int *budget)
17657 + int work_to_do = min(*budget, netdev->quota);
17658 + struct adapter_struct *adapter = netdev_priv(netdev);
17659 +#ifdef DRIVER_E1000E
17660 + struct napi_struct *napi = &adapter->napi;
17662 + struct napi_struct *napi = &adapter->rx_ring[0].napi;
17665 + work_done = napi->poll(napi, work_to_do);
17666 + *budget -= work_done;
17667 + netdev->quota -= work_done;
17668 + return work_done ? 1 : 0;
17671 +#endif /* <= 2.6.24 */
17673 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat_ethtool.c linux-2.6.22-10/drivers/net/e1000e/kcompat_ethtool.c
17674 --- linux-2.6.22-0/drivers/net/e1000e/kcompat_ethtool.c 1970-01-01 01:00:00.000000000 +0100
17675 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat_ethtool.c 2008-10-14 01:51:32.000000000 +0200
17677 +/*******************************************************************************
17679 + Intel PRO/1000 Linux driver
17680 + Copyright(c) 1999 - 2008 Intel Corporation.
17682 + This program is free software; you can redistribute it and/or modify it
17683 + under the terms and conditions of the GNU General Public License,
17684 + version 2, as published by the Free Software Foundation.
17686 + This program is distributed in the hope it will be useful, but WITHOUT
17687 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17688 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17691 + You should have received a copy of the GNU General Public License along with
17692 + this program; if not, write to the Free Software Foundation, Inc.,
17693 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17695 + The full GNU General Public License is included in this distribution in
17696 + the file called "COPYING".
17698 + Contact Information:
17699 + Linux NICS <linux.nics@intel.com>
17700 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
17701 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17703 +*******************************************************************************/
17706 + * net/core/ethtool.c - Ethtool ioctl handler
17707 + * Copyright (c) 2003 Matthew Wilcox <matthew@wil.cx>
17709 + * This file is where we call all the ethtool_ops commands to get
17710 + * the information ethtool needs. We fall back to calling do_ioctl()
17711 + * for drivers which haven't been converted to ethtool_ops yet.
17713 + * It's GPL, stupid.
17715 + * Modification by sfeldma@pobox.com to work as backward compat
17716 + * solution for pre-ethtool_ops kernels.
17717 + * - copied struct ethtool_ops from ethtool.h
17718 + * - defined SET_ETHTOOL_OPS
17719 + * - put in some #ifndef NETIF_F_xxx wrappers
17720 + * - changes refs to dev->ethtool_ops to ethtool_ops
17721 + * - changed dev_ethtool to ethtool_ioctl
17722 + * - remove EXPORT_SYMBOL()s
17723 + * - added _kc_ prefix in built-in ethtool_op_xxx ops.
17726 +#include <linux/module.h>
17727 +#include <linux/types.h>
17728 +#include <linux/errno.h>
17729 +#include <linux/mii.h>
17730 +#include <linux/ethtool.h>
17731 +#include <linux/netdevice.h>
17732 +#include <asm/uaccess.h>
17734 +#include "kcompat.h"
17736 +#undef SUPPORTED_10000baseT_Full
17737 +#define SUPPORTED_10000baseT_Full (1 << 12)
17738 +#undef ADVERTISED_10000baseT_Full
17739 +#define ADVERTISED_10000baseT_Full (1 << 12)
17740 +#undef SPEED_10000
17741 +#define SPEED_10000 10000
17743 +#undef ethtool_ops
17744 +#define ethtool_ops _kc_ethtool_ops
17746 +struct _kc_ethtool_ops {
17747 + int (*get_settings)(struct net_device *, struct ethtool_cmd *);
17748 + int (*set_settings)(struct net_device *, struct ethtool_cmd *);
17749 + void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
17750 + int (*get_regs_len)(struct net_device *);
17751 + void (*get_regs)(struct net_device *, struct ethtool_regs *, void *);
17752 + void (*get_wol)(struct net_device *, struct ethtool_wolinfo *);
17753 + int (*set_wol)(struct net_device *, struct ethtool_wolinfo *);
17754 + u32 (*get_msglevel)(struct net_device *);
17755 + void (*set_msglevel)(struct net_device *, u32);
17756 + int (*nway_reset)(struct net_device *);
17757 + u32 (*get_link)(struct net_device *);
17758 + int (*get_eeprom_len)(struct net_device *);
17759 + int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
17760 + int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
17761 + int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *);
17762 + int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *);
17763 + void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *);
17764 + int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *);
17765 + void (*get_pauseparam)(struct net_device *,
17766 + struct ethtool_pauseparam*);
17767 + int (*set_pauseparam)(struct net_device *,
17768 + struct ethtool_pauseparam*);
17769 + u32 (*get_rx_csum)(struct net_device *);
17770 + int (*set_rx_csum)(struct net_device *, u32);
17771 + u32 (*get_tx_csum)(struct net_device *);
17772 + int (*set_tx_csum)(struct net_device *, u32);
17773 + u32 (*get_sg)(struct net_device *);
17774 + int (*set_sg)(struct net_device *, u32);
17775 + u32 (*get_tso)(struct net_device *);
17776 + int (*set_tso)(struct net_device *, u32);
17777 + int (*self_test_count)(struct net_device *);
17778 + void (*self_test)(struct net_device *, struct ethtool_test *, u64 *);
17779 + void (*get_strings)(struct net_device *, u32 stringset, u8 *);
17780 + int (*phys_id)(struct net_device *, u32);
17781 + int (*get_stats_count)(struct net_device *);
17782 + void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *,
17784 +} *ethtool_ops = NULL;
17786 +#undef SET_ETHTOOL_OPS
17787 +#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops))
17790 + * Some useful ethtool_ops methods that are device independent. If we find that
17791 + * all drivers want to do the same thing here, we can turn these into dev_()
17792 + * function calls.
17795 +#undef ethtool_op_get_link
17796 +#define ethtool_op_get_link _kc_ethtool_op_get_link
17797 +u32 _kc_ethtool_op_get_link(struct net_device *dev)
17799 + return netif_carrier_ok(dev) ? 1 : 0;
17802 +#undef ethtool_op_get_tx_csum
17803 +#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum
17804 +u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev)
17806 +#ifdef NETIF_F_IP_CSUM
17807 + return (dev->features & NETIF_F_IP_CSUM) != 0;
17813 +#undef ethtool_op_set_tx_csum
17814 +#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum
17815 +int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
17817 +#ifdef NETIF_F_IP_CSUM
17819 +#ifdef NETIF_F_IPV6_CSUM
17820 + dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
17822 + dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
17824 + dev->features |= NETIF_F_IP_CSUM;
17826 + dev->features &= ~NETIF_F_IP_CSUM;
17833 +#undef ethtool_op_get_sg
17834 +#define ethtool_op_get_sg _kc_ethtool_op_get_sg
17835 +u32 _kc_ethtool_op_get_sg(struct net_device *dev)
17838 + return (dev->features & NETIF_F_SG) != 0;
17844 +#undef ethtool_op_set_sg
17845 +#define ethtool_op_set_sg _kc_ethtool_op_set_sg
17846 +int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data)
17850 + dev->features |= NETIF_F_SG;
17852 + dev->features &= ~NETIF_F_SG;
17858 +#undef ethtool_op_get_tso
17859 +#define ethtool_op_get_tso _kc_ethtool_op_get_tso
17860 +u32 _kc_ethtool_op_get_tso(struct net_device *dev)
17862 +#ifdef NETIF_F_TSO
17863 + return (dev->features & NETIF_F_TSO) != 0;
17869 +#undef ethtool_op_set_tso
17870 +#define ethtool_op_set_tso _kc_ethtool_op_set_tso
17871 +int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data)
17873 +#ifdef NETIF_F_TSO
17875 + dev->features |= NETIF_F_TSO;
17877 + dev->features &= ~NETIF_F_TSO;
17883 +/* Handlers for each ethtool command */
17885 +static int ethtool_get_settings(struct net_device *dev, void *useraddr)
17887 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
17890 + if (!ethtool_ops->get_settings)
17891 + return -EOPNOTSUPP;
17893 + err = ethtool_ops->get_settings(dev, &cmd);
17897 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
17902 +static int ethtool_set_settings(struct net_device *dev, void *useraddr)
17904 + struct ethtool_cmd cmd;
17906 + if (!ethtool_ops->set_settings)
17907 + return -EOPNOTSUPP;
17909 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
17912 + return ethtool_ops->set_settings(dev, &cmd);
17915 +static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr)
17917 + struct ethtool_drvinfo info;
17918 + struct ethtool_ops *ops = ethtool_ops;
17920 + if (!ops->get_drvinfo)
17921 + return -EOPNOTSUPP;
17923 + memset(&info, 0, sizeof(info));
17924 + info.cmd = ETHTOOL_GDRVINFO;
17925 + ops->get_drvinfo(dev, &info);
17927 + if (ops->self_test_count)
17928 + info.testinfo_len = ops->self_test_count(dev);
17929 + if (ops->get_stats_count)
17930 + info.n_stats = ops->get_stats_count(dev);
17931 + if (ops->get_regs_len)
17932 + info.regdump_len = ops->get_regs_len(dev);
17933 + if (ops->get_eeprom_len)
17934 + info.eedump_len = ops->get_eeprom_len(dev);
17936 + if (copy_to_user(useraddr, &info, sizeof(info)))
17941 +static int ethtool_get_regs(struct net_device *dev, char *useraddr)
17943 + struct ethtool_regs regs;
17944 + struct ethtool_ops *ops = ethtool_ops;
17948 + if (!ops->get_regs || !ops->get_regs_len)
17949 + return -EOPNOTSUPP;
17951 + if (copy_from_user(®s, useraddr, sizeof(regs)))
17954 + reglen = ops->get_regs_len(dev);
17955 + if (regs.len > reglen)
17956 + regs.len = reglen;
17958 + regbuf = kmalloc(reglen, GFP_USER);
17962 + ops->get_regs(dev, ®s, regbuf);
17965 + if (copy_to_user(useraddr, ®s, sizeof(regs)))
17967 + useraddr += offsetof(struct ethtool_regs, data);
17968 + if (copy_to_user(useraddr, regbuf, reglen))
17977 +static int ethtool_get_wol(struct net_device *dev, char *useraddr)
17979 + struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
17981 + if (!ethtool_ops->get_wol)
17982 + return -EOPNOTSUPP;
17984 + ethtool_ops->get_wol(dev, &wol);
17986 + if (copy_to_user(useraddr, &wol, sizeof(wol)))
17991 +static int ethtool_set_wol(struct net_device *dev, char *useraddr)
17993 + struct ethtool_wolinfo wol;
17995 + if (!ethtool_ops->set_wol)
17996 + return -EOPNOTSUPP;
17998 + if (copy_from_user(&wol, useraddr, sizeof(wol)))
18001 + return ethtool_ops->set_wol(dev, &wol);
18004 +static int ethtool_get_msglevel(struct net_device *dev, char *useraddr)
18006 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
18008 + if (!ethtool_ops->get_msglevel)
18009 + return -EOPNOTSUPP;
18011 + edata.data = ethtool_ops->get_msglevel(dev);
18013 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18018 +static int ethtool_set_msglevel(struct net_device *dev, char *useraddr)
18020 + struct ethtool_value edata;
18022 + if (!ethtool_ops->set_msglevel)
18023 + return -EOPNOTSUPP;
18025 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
18028 + ethtool_ops->set_msglevel(dev, edata.data);
18032 +static int ethtool_nway_reset(struct net_device *dev)
18034 + if (!ethtool_ops->nway_reset)
18035 + return -EOPNOTSUPP;
18037 + return ethtool_ops->nway_reset(dev);
18040 +static int ethtool_get_link(struct net_device *dev, void *useraddr)
18042 + struct ethtool_value edata = { ETHTOOL_GLINK };
18044 + if (!ethtool_ops->get_link)
18045 + return -EOPNOTSUPP;
18047 + edata.data = ethtool_ops->get_link(dev);
18049 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18054 +static int ethtool_get_eeprom(struct net_device *dev, void *useraddr)
18056 + struct ethtool_eeprom eeprom;
18057 + struct ethtool_ops *ops = ethtool_ops;
18061 + if (!ops->get_eeprom || !ops->get_eeprom_len)
18062 + return -EOPNOTSUPP;
18064 + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
18067 + /* Check for wrap and zero */
18068 + if (eeprom.offset + eeprom.len <= eeprom.offset)
18071 + /* Check for exceeding total eeprom len */
18072 + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))
18075 + data = kmalloc(eeprom.len, GFP_USER);
18080 + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))
18083 + ret = ops->get_eeprom(dev, &eeprom, data);
18088 + if (copy_to_user(useraddr, &eeprom, sizeof(eeprom)))
18090 + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))
18099 +static int ethtool_set_eeprom(struct net_device *dev, void *useraddr)
18101 + struct ethtool_eeprom eeprom;
18102 + struct ethtool_ops *ops = ethtool_ops;
18106 + if (!ops->set_eeprom || !ops->get_eeprom_len)
18107 + return -EOPNOTSUPP;
18109 + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
18112 + /* Check for wrap and zero */
18113 + if (eeprom.offset + eeprom.len <= eeprom.offset)
18116 + /* Check for exceeding total eeprom len */
18117 + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))
18120 + data = kmalloc(eeprom.len, GFP_USER);
18125 + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))
18128 + ret = ops->set_eeprom(dev, &eeprom, data);
18132 + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))
18140 +static int ethtool_get_coalesce(struct net_device *dev, void *useraddr)
18142 + struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE };
18144 + if (!ethtool_ops->get_coalesce)
18145 + return -EOPNOTSUPP;
18147 + ethtool_ops->get_coalesce(dev, &coalesce);
18149 + if (copy_to_user(useraddr, &coalesce, sizeof(coalesce)))
18154 +static int ethtool_set_coalesce(struct net_device *dev, void *useraddr)
18156 + struct ethtool_coalesce coalesce;
18158 + if (!ethtool_ops->get_coalesce)
18159 + return -EOPNOTSUPP;
18161 + if (copy_from_user(&coalesce, useraddr, sizeof(coalesce)))
18164 + return ethtool_ops->set_coalesce(dev, &coalesce);
18167 +static int ethtool_get_ringparam(struct net_device *dev, void *useraddr)
18169 + struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM };
18171 + if (!ethtool_ops->get_ringparam)
18172 + return -EOPNOTSUPP;
18174 + ethtool_ops->get_ringparam(dev, &ringparam);
18176 + if (copy_to_user(useraddr, &ringparam, sizeof(ringparam)))
18181 +static int ethtool_set_ringparam(struct net_device *dev, void *useraddr)
18183 + struct ethtool_ringparam ringparam;
18185 + if (!ethtool_ops->get_ringparam)
18186 + return -EOPNOTSUPP;
18188 + if (copy_from_user(&ringparam, useraddr, sizeof(ringparam)))
18191 + return ethtool_ops->set_ringparam(dev, &ringparam);
18194 +static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr)
18196 + struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM };
18198 + if (!ethtool_ops->get_pauseparam)
18199 + return -EOPNOTSUPP;
18201 + ethtool_ops->get_pauseparam(dev, &pauseparam);
18203 + if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam)))
18208 +static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr)
18210 + struct ethtool_pauseparam pauseparam;
18212 + if (!ethtool_ops->get_pauseparam)
18213 + return -EOPNOTSUPP;
18215 + if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam)))
18218 + return ethtool_ops->set_pauseparam(dev, &pauseparam);
18221 +static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr)
18223 + struct ethtool_value edata = { ETHTOOL_GRXCSUM };
18225 + if (!ethtool_ops->get_rx_csum)
18226 + return -EOPNOTSUPP;
18228 + edata.data = ethtool_ops->get_rx_csum(dev);
18230 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18235 +static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr)
18237 + struct ethtool_value edata;
18239 + if (!ethtool_ops->set_rx_csum)
18240 + return -EOPNOTSUPP;
18242 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
18245 + ethtool_ops->set_rx_csum(dev, edata.data);
18249 +static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr)
18251 + struct ethtool_value edata = { ETHTOOL_GTXCSUM };
18253 + if (!ethtool_ops->get_tx_csum)
18254 + return -EOPNOTSUPP;
18256 + edata.data = ethtool_ops->get_tx_csum(dev);
18258 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18263 +static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr)
18265 + struct ethtool_value edata;
18267 + if (!ethtool_ops->set_tx_csum)
18268 + return -EOPNOTSUPP;
18270 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
18273 + return ethtool_ops->set_tx_csum(dev, edata.data);
18276 +static int ethtool_get_sg(struct net_device *dev, char *useraddr)
18278 + struct ethtool_value edata = { ETHTOOL_GSG };
18280 + if (!ethtool_ops->get_sg)
18281 + return -EOPNOTSUPP;
18283 + edata.data = ethtool_ops->get_sg(dev);
18285 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18290 +static int ethtool_set_sg(struct net_device *dev, char *useraddr)
18292 + struct ethtool_value edata;
18294 + if (!ethtool_ops->set_sg)
18295 + return -EOPNOTSUPP;
18297 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
18300 + return ethtool_ops->set_sg(dev, edata.data);
18303 +static int ethtool_get_tso(struct net_device *dev, char *useraddr)
18305 + struct ethtool_value edata = { ETHTOOL_GTSO };
18307 + if (!ethtool_ops->get_tso)
18308 + return -EOPNOTSUPP;
18310 + edata.data = ethtool_ops->get_tso(dev);
18312 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
18317 +static int ethtool_set_tso(struct net_device *dev, char *useraddr)
18319 + struct ethtool_value edata;
18321 + if (!ethtool_ops->set_tso)
18322 + return -EOPNOTSUPP;
18324 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
18327 + return ethtool_ops->set_tso(dev, edata.data);
18330 +static int ethtool_self_test(struct net_device *dev, char *useraddr)
18332 + struct ethtool_test test;
18333 + struct ethtool_ops *ops = ethtool_ops;
18337 + if (!ops->self_test || !ops->self_test_count)
18338 + return -EOPNOTSUPP;
18340 + if (copy_from_user(&test, useraddr, sizeof(test)))
18343 + test.len = ops->self_test_count(dev);
18344 + data = kmalloc(test.len * sizeof(u64), GFP_USER);
18348 + ops->self_test(dev, &test, data);
18351 + if (copy_to_user(useraddr, &test, sizeof(test)))
18353 + useraddr += sizeof(test);
18354 + if (copy_to_user(useraddr, data, test.len * sizeof(u64)))
18363 +static int ethtool_get_strings(struct net_device *dev, void *useraddr)
18365 + struct ethtool_gstrings gstrings;
18366 + struct ethtool_ops *ops = ethtool_ops;
18370 + if (!ops->get_strings)
18371 + return -EOPNOTSUPP;
18373 + if (copy_from_user(&gstrings, useraddr, sizeof(gstrings)))
18376 + switch (gstrings.string_set) {
18377 + case ETH_SS_TEST:
18378 + if (!ops->self_test_count)
18379 + return -EOPNOTSUPP;
18380 + gstrings.len = ops->self_test_count(dev);
18382 + case ETH_SS_STATS:
18383 + if (!ops->get_stats_count)
18384 + return -EOPNOTSUPP;
18385 + gstrings.len = ops->get_stats_count(dev);
18391 + data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER);
18395 + ops->get_strings(dev, gstrings.string_set, data);
18398 + if (copy_to_user(useraddr, &gstrings, sizeof(gstrings)))
18400 + useraddr += sizeof(gstrings);
18401 + if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN))
18410 +static int ethtool_phys_id(struct net_device *dev, void *useraddr)
18412 + struct ethtool_value id;
18414 + if (!ethtool_ops->phys_id)
18415 + return -EOPNOTSUPP;
18417 + if (copy_from_user(&id, useraddr, sizeof(id)))
18420 + return ethtool_ops->phys_id(dev, id.data);
18423 +static int ethtool_get_stats(struct net_device *dev, void *useraddr)
18425 + struct ethtool_stats stats;
18426 + struct ethtool_ops *ops = ethtool_ops;
18430 + if (!ops->get_ethtool_stats || !ops->get_stats_count)
18431 + return -EOPNOTSUPP;
18433 + if (copy_from_user(&stats, useraddr, sizeof(stats)))
18436 + stats.n_stats = ops->get_stats_count(dev);
18437 + data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER);
18441 + ops->get_ethtool_stats(dev, &stats, data);
18444 + if (copy_to_user(useraddr, &stats, sizeof(stats)))
18446 + useraddr += sizeof(stats);
18447 + if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64)))
18456 +/* The main entry point in this file. Called from net/core/dev.c */
18458 +#define ETHTOOL_OPS_COMPAT
18459 +int ethtool_ioctl(struct ifreq *ifr)
18461 + struct net_device *dev = __dev_get_by_name(ifr->ifr_name);
18462 + void *useraddr = (void *) ifr->ifr_data;
18466 + * XXX: This can be pushed down into the ethtool_* handlers that
18467 + * need it. Keep existing behavior for the moment.
18469 + if (!capable(CAP_NET_ADMIN))
18472 + if (!dev || !netif_device_present(dev))
18475 + if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
18478 + switch (ethcmd) {
18479 + case ETHTOOL_GSET:
18480 + return ethtool_get_settings(dev, useraddr);
18481 + case ETHTOOL_SSET:
18482 + return ethtool_set_settings(dev, useraddr);
18483 + case ETHTOOL_GDRVINFO:
18484 + return ethtool_get_drvinfo(dev, useraddr);
18485 + case ETHTOOL_GREGS:
18486 + return ethtool_get_regs(dev, useraddr);
18487 + case ETHTOOL_GWOL:
18488 + return ethtool_get_wol(dev, useraddr);
18489 + case ETHTOOL_SWOL:
18490 + return ethtool_set_wol(dev, useraddr);
18491 + case ETHTOOL_GMSGLVL:
18492 + return ethtool_get_msglevel(dev, useraddr);
18493 + case ETHTOOL_SMSGLVL:
18494 + return ethtool_set_msglevel(dev, useraddr);
18495 + case ETHTOOL_NWAY_RST:
18496 + return ethtool_nway_reset(dev);
18497 + case ETHTOOL_GLINK:
18498 + return ethtool_get_link(dev, useraddr);
18499 + case ETHTOOL_GEEPROM:
18500 + return ethtool_get_eeprom(dev, useraddr);
18501 + case ETHTOOL_SEEPROM:
18502 + return ethtool_set_eeprom(dev, useraddr);
18503 + case ETHTOOL_GCOALESCE:
18504 + return ethtool_get_coalesce(dev, useraddr);
18505 + case ETHTOOL_SCOALESCE:
18506 + return ethtool_set_coalesce(dev, useraddr);
18507 + case ETHTOOL_GRINGPARAM:
18508 + return ethtool_get_ringparam(dev, useraddr);
18509 + case ETHTOOL_SRINGPARAM:
18510 + return ethtool_set_ringparam(dev, useraddr);
18511 + case ETHTOOL_GPAUSEPARAM:
18512 + return ethtool_get_pauseparam(dev, useraddr);
18513 + case ETHTOOL_SPAUSEPARAM:
18514 + return ethtool_set_pauseparam(dev, useraddr);
18515 + case ETHTOOL_GRXCSUM:
18516 + return ethtool_get_rx_csum(dev, useraddr);
18517 + case ETHTOOL_SRXCSUM:
18518 + return ethtool_set_rx_csum(dev, useraddr);
18519 + case ETHTOOL_GTXCSUM:
18520 + return ethtool_get_tx_csum(dev, useraddr);
18521 + case ETHTOOL_STXCSUM:
18522 + return ethtool_set_tx_csum(dev, useraddr);
18523 + case ETHTOOL_GSG:
18524 + return ethtool_get_sg(dev, useraddr);
18525 + case ETHTOOL_SSG:
18526 + return ethtool_set_sg(dev, useraddr);
18527 + case ETHTOOL_GTSO:
18528 + return ethtool_get_tso(dev, useraddr);
18529 + case ETHTOOL_STSO:
18530 + return ethtool_set_tso(dev, useraddr);
18531 + case ETHTOOL_TEST:
18532 + return ethtool_self_test(dev, useraddr);
18533 + case ETHTOOL_GSTRINGS:
18534 + return ethtool_get_strings(dev, useraddr);
18535 + case ETHTOOL_PHYS_ID:
18536 + return ethtool_phys_id(dev, useraddr);
18537 + case ETHTOOL_GSTATS:
18538 + return ethtool_get_stats(dev, useraddr);
18540 + return -EOPNOTSUPP;
18543 + return -EOPNOTSUPP;
18546 +#define mii_if_info _kc_mii_if_info
18547 +struct _kc_mii_if_info {
18551 + int reg_num_mask;
18553 + unsigned int full_duplex : 1; /* is full duplex? */
18554 + unsigned int force_media : 1; /* is autoneg. disabled? */
18556 + struct net_device *dev;
18557 + int (*mdio_read) (struct net_device *dev, int phy_id, int location);
18558 + void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val);
18561 +struct ethtool_cmd;
18562 +struct mii_ioctl_data;
18564 +#undef mii_link_ok
18565 +#define mii_link_ok _kc_mii_link_ok
18566 +#undef mii_nway_restart
18567 +#define mii_nway_restart _kc_mii_nway_restart
18568 +#undef mii_ethtool_gset
18569 +#define mii_ethtool_gset _kc_mii_ethtool_gset
18570 +#undef mii_ethtool_sset
18571 +#define mii_ethtool_sset _kc_mii_ethtool_sset
18572 +#undef mii_check_link
18573 +#define mii_check_link _kc_mii_check_link
18574 +#undef generic_mii_ioctl
18575 +#define generic_mii_ioctl _kc_generic_mii_ioctl
18576 +extern int _kc_mii_link_ok (struct mii_if_info *mii);
18577 +extern int _kc_mii_nway_restart (struct mii_if_info *mii);
18578 +extern int _kc_mii_ethtool_gset(struct mii_if_info *mii,
18579 + struct ethtool_cmd *ecmd);
18580 +extern int _kc_mii_ethtool_sset(struct mii_if_info *mii,
18581 + struct ethtool_cmd *ecmd);
18582 +extern void _kc_mii_check_link (struct mii_if_info *mii);
18583 +extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if,
18584 + struct mii_ioctl_data *mii_data, int cmd,
18585 + unsigned int *duplex_changed);
18588 +struct _kc_pci_dev_ext {
18589 + struct pci_dev *dev;
18590 + void *pci_drvdata;
18591 + struct pci_driver *driver;
18594 +struct _kc_net_dev_ext {
18595 + struct net_device *dev;
18596 + unsigned int carrier;
18600 +/**************************************/
18603 +int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
18605 + struct net_device *dev = mii->dev;
18606 + u32 advert, bmcr, lpa, nego;
18608 + ecmd->supported =
18609 + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
18610 + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
18611 + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
18613 + /* only supports twisted-pair */
18614 + ecmd->port = PORT_MII;
18616 + /* only supports internal transceiver */
18617 + ecmd->transceiver = XCVR_INTERNAL;
18619 + /* this isn't fully supported at higher layers */
18620 + ecmd->phy_address = mii->phy_id;
18622 + ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
18623 + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
18624 + if (advert & ADVERTISE_10HALF)
18625 + ecmd->advertising |= ADVERTISED_10baseT_Half;
18626 + if (advert & ADVERTISE_10FULL)
18627 + ecmd->advertising |= ADVERTISED_10baseT_Full;
18628 + if (advert & ADVERTISE_100HALF)
18629 + ecmd->advertising |= ADVERTISED_100baseT_Half;
18630 + if (advert & ADVERTISE_100FULL)
18631 + ecmd->advertising |= ADVERTISED_100baseT_Full;
18633 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
18634 + lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
18635 + if (bmcr & BMCR_ANENABLE) {
18636 + ecmd->advertising |= ADVERTISED_Autoneg;
18637 + ecmd->autoneg = AUTONEG_ENABLE;
18639 + nego = mii_nway_result(advert & lpa);
18640 + if (nego == LPA_100FULL || nego == LPA_100HALF)
18641 + ecmd->speed = SPEED_100;
18643 + ecmd->speed = SPEED_10;
18644 + if (nego == LPA_100FULL || nego == LPA_10FULL) {
18645 + ecmd->duplex = DUPLEX_FULL;
18646 + mii->full_duplex = 1;
18648 + ecmd->duplex = DUPLEX_HALF;
18649 + mii->full_duplex = 0;
18652 + ecmd->autoneg = AUTONEG_DISABLE;
18654 + ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
18655 + ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
18658 + /* ignore maxtxpkt, maxrxpkt for now */
18663 +int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
18665 + struct net_device *dev = mii->dev;
18667 + if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
18669 + if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
18671 + if (ecmd->port != PORT_MII)
18673 + if (ecmd->transceiver != XCVR_INTERNAL)
18675 + if (ecmd->phy_address != mii->phy_id)
18677 + if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
18680 + /* ignore supported, maxtxpkt, maxrxpkt */
18682 + if (ecmd->autoneg == AUTONEG_ENABLE) {
18683 + u32 bmcr, advert, tmp;
18685 + if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
18686 + ADVERTISED_10baseT_Full |
18687 + ADVERTISED_100baseT_Half |
18688 + ADVERTISED_100baseT_Full)) == 0)
18691 + /* advertise only what has been requested */
18692 + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
18693 + tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
18694 + if (ADVERTISED_10baseT_Half)
18695 + tmp |= ADVERTISE_10HALF;
18696 + if (ADVERTISED_10baseT_Full)
18697 + tmp |= ADVERTISE_10FULL;
18698 + if (ADVERTISED_100baseT_Half)
18699 + tmp |= ADVERTISE_100HALF;
18700 + if (ADVERTISED_100baseT_Full)
18701 + tmp |= ADVERTISE_100FULL;
18702 + if (advert != tmp) {
18703 + mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp);
18704 + mii->advertising = tmp;
18707 + /* turn on autonegotiation, and force a renegotiate */
18708 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
18709 + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
18710 + mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
18712 + mii->force_media = 0;
18716 + /* turn off auto negotiation, set speed and duplexity */
18717 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
18718 + tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
18719 + if (ecmd->speed == SPEED_100)
18720 + tmp |= BMCR_SPEED100;
18721 + if (ecmd->duplex == DUPLEX_FULL) {
18722 + tmp |= BMCR_FULLDPLX;
18723 + mii->full_duplex = 1;
18725 + mii->full_duplex = 0;
18727 + mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);
18729 + mii->force_media = 1;
18734 +int _kc_mii_link_ok (struct mii_if_info *mii)
18736 + /* first, a dummy read, needed to latch some MII phys */
18737 + mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
18738 + if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
18743 +int _kc_mii_nway_restart (struct mii_if_info *mii)
18748 + /* if autoneg is off, it's an error */
18749 + bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR);
18751 + if (bmcr & BMCR_ANENABLE) {
18752 + bmcr |= BMCR_ANRESTART;
18753 + mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr);
18760 +void _kc_mii_check_link (struct mii_if_info *mii)
18762 + int cur_link = mii_link_ok(mii);
18763 + int prev_link = netif_carrier_ok(mii->dev);
18765 + if (cur_link && !prev_link)
18766 + netif_carrier_on(mii->dev);
18767 + else if (prev_link && !cur_link)
18768 + netif_carrier_off(mii->dev);
18771 +int _kc_generic_mii_ioctl(struct mii_if_info *mii_if,
18772 + struct mii_ioctl_data *mii_data, int cmd,
18773 + unsigned int *duplex_chg_out)
18776 + unsigned int duplex_changed = 0;
18778 + if (duplex_chg_out)
18779 + *duplex_chg_out = 0;
18781 + mii_data->phy_id &= mii_if->phy_id_mask;
18782 + mii_data->reg_num &= mii_if->reg_num_mask;
18785 + case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */
18786 + case SIOCGMIIPHY:
18787 + mii_data->phy_id = mii_if->phy_id;
18788 + /* fall through */
18790 + case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */
18791 + case SIOCGMIIREG:
18792 + mii_data->val_out =
18793 + mii_if->mdio_read(mii_if->dev, mii_data->phy_id,
18794 + mii_data->reg_num);
18797 + case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */
18798 + case SIOCSMIIREG: {
18799 + u16 val = mii_data->val_in;
18801 + if (!capable(CAP_NET_ADMIN))
18804 + if (mii_data->phy_id == mii_if->phy_id) {
18805 + switch(mii_data->reg_num) {
18807 + unsigned int new_duplex = 0;
18808 + if (val & (BMCR_RESET|BMCR_ANENABLE))
18809 + mii_if->force_media = 0;
18811 + mii_if->force_media = 1;
18812 + if (mii_if->force_media &&
18813 + (val & BMCR_FULLDPLX))
18815 + if (mii_if->full_duplex != new_duplex) {
18816 + duplex_changed = 1;
18817 + mii_if->full_duplex = new_duplex;
18821 + case MII_ADVERTISE:
18822 + mii_if->advertising = val;
18830 + mii_if->mdio_write(mii_if->dev, mii_data->phy_id,
18831 + mii_data->reg_num, val);
18836 + rc = -EOPNOTSUPP;
18840 + if ((rc == 0) && (duplex_chg_out) && (duplex_changed))
18841 + *duplex_chg_out = 1;
18846 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat.h linux-2.6.22-10/drivers/net/e1000e/kcompat.h
18847 --- linux-2.6.22-0/drivers/net/e1000e/kcompat.h 1970-01-01 01:00:00.000000000 +0100
18848 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat.h 2008-11-10 17:29:48.000000000 +0100
18850 +/*******************************************************************************
18852 + Intel PRO/1000 Linux driver
18853 + Copyright(c) 1999 - 2008 Intel Corporation.
18855 + This program is free software; you can redistribute it and/or modify it
18856 + under the terms and conditions of the GNU General Public License,
18857 + version 2, as published by the Free Software Foundation.
18859 + This program is distributed in the hope it will be useful, but WITHOUT
18860 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18861 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18864 + You should have received a copy of the GNU General Public License along with
18865 + this program; if not, write to the Free Software Foundation, Inc.,
18866 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18868 + The full GNU General Public License is included in this distribution in
18869 + the file called "COPYING".
18871 + Contact Information:
18872 + Linux NICS <linux.nics@intel.com>
18873 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18874 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18876 +*******************************************************************************/
18878 +#ifndef _KCOMPAT_H_
18879 +#define _KCOMPAT_H_
18881 +#include <linux/version.h>
18882 +#include <linux/init.h>
18883 +#include <linux/types.h>
18884 +#include <linux/errno.h>
18885 +#include <linux/module.h>
18886 +#include <linux/pci.h>
18887 +#include <linux/netdevice.h>
18888 +#include <linux/etherdevice.h>
18889 +#include <linux/skbuff.h>
18890 +#include <linux/ioport.h>
18891 +#include <linux/slab.h>
18892 +#include <linux/list.h>
18893 +#include <linux/delay.h>
18894 +#include <linux/sched.h>
18895 +#include <linux/in.h>
18896 +#include <linux/ip.h>
18897 +#include <linux/udp.h>
18898 +#include <linux/mii.h>
18899 +#include <asm/io.h>
18901 +#define DRIVER_E1000E
18903 +/* NAPI enable/disable flags here */
18905 +#ifdef DRIVER_E1000E
18910 +#ifdef CONFIG_E1000_NAPI
18917 +#ifdef E1000E_NAPI
18921 +#ifdef E1000_NO_NAPI
18924 +#ifdef E1000E_NO_NAPI
18934 +#ifdef DRIVER_E1000E
18935 +#define adapter_struct e1000_adapter
18936 +#define CONFIG_E1000E_MSIX
18942 +/* and finally set defines so that the code sees the changes */
18944 +#ifndef CONFIG_E1000_NAPI
18945 +#define CONFIG_E1000_NAPI
18947 +#ifndef CONFIG_E1000E_NAPI
18948 +#define CONFIG_E1000E_NAPI
18951 +#undef CONFIG_E1000_NAPI
18952 +#undef CONFIG_E1000E_NAPI
18953 +#undef CONFIG_IXGB_NAPI
18956 +/* packet split disable/enable */
18957 +#ifdef DISABLE_PACKET_SPLIT
18958 +#undef CONFIG_E1000_DISABLE_PACKET_SPLIT
18959 +#define CONFIG_E1000_DISABLE_PACKET_SPLIT
18960 +#undef CONFIG_IGB_DISABLE_PACKET_SPLIT
18961 +#define CONFIG_IGB_DISABLE_PACKET_SPLIT
18964 +/* MSI compatibility code for all kernels and drivers */
18965 +#ifdef DISABLE_PCI_MSI
18966 +#undef CONFIG_PCI_MSI
18968 +#ifndef CONFIG_PCI_MSI
18969 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
18970 +struct msix_entry {
18971 + u16 vector; /* kernel uses to write allocated vector */
18972 + u16 entry; /* driver uses to specify entry, OS writes */
18975 +#define pci_enable_msi(a) -ENOTSUPP
18976 +#define pci_disable_msi(a) do {} while (0)
18977 +#define pci_enable_msix(a, b, c) -ENOTSUPP
18978 +#define pci_disable_msix(a) do {} while (0)
18979 +#define msi_remove_pci_irq_vectors(a) do {} while (0)
18980 +#endif /* CONFIG_PCI_MSI */
18985 +#ifdef DISABLE_NET_POLL_CONTROLLER
18986 +#undef CONFIG_NET_POLL_CONTROLLER
18989 +#ifndef PMSG_SUSPEND
18990 +#define PMSG_SUSPEND 3
18993 +/* generic boolean compatibility */
18997 +#define FALSE false
18998 +#ifdef GCC_VERSION
18999 +#if ( GCC_VERSION < 3000 )
19000 +#define _Bool char
19004 +#define bool _Bool
19010 +#ifndef module_param
19011 +#define module_param(v,t,p) MODULE_PARM(v, "i");
19014 +#ifndef DMA_64BIT_MASK
19015 +#define DMA_64BIT_MASK 0xffffffffffffffffULL
19018 +#ifndef DMA_32BIT_MASK
19019 +#define DMA_32BIT_MASK 0x00000000ffffffffULL
19022 +#ifndef PCI_CAP_ID_EXP
19023 +#define PCI_CAP_ID_EXP 0x10
19027 +#ifdef CONFIG_IA64
19028 +#define mmiowb() asm volatile ("mf.a" ::: "memory")
19034 +#ifndef IRQ_HANDLED
19035 +#define irqreturn_t void
19036 +#define IRQ_HANDLED
19040 +#ifndef SET_NETDEV_DEV
19041 +#define SET_NETDEV_DEV(net, pdev)
19044 +#ifndef HAVE_FREE_NETDEV
19045 +#define free_netdev(x) kfree(x)
19048 +#ifdef HAVE_POLL_CONTROLLER
19049 +#define CONFIG_NET_POLL_CONTROLLER
19052 +#ifndef NETDEV_TX_OK
19053 +#define NETDEV_TX_OK 0
19056 +#ifndef NETDEV_TX_BUSY
19057 +#define NETDEV_TX_BUSY 1
19060 +#ifndef NETDEV_TX_LOCKED
19061 +#define NETDEV_TX_LOCKED -1
19064 +#ifndef SKB_DATAREF_SHIFT
19065 +/* if we do not have the infrastructure to detect if skb_header is cloned
19066 + just return false in all cases */
19067 +#define skb_header_cloned(x) 0
19070 +#ifndef NETIF_F_GSO
19071 +#define gso_size tso_size
19072 +#define gso_segs tso_segs
19075 +#ifndef CHECKSUM_PARTIAL
19076 +#define CHECKSUM_PARTIAL CHECKSUM_HW
19077 +#define CHECKSUM_COMPLETE CHECKSUM_HW
19080 +#ifndef __read_mostly
19081 +#define __read_mostly
19084 +#ifndef HAVE_NETIF_MSG
19085 +#define HAVE_NETIF_MSG 1
19087 + NETIF_MSG_DRV = 0x0001,
19088 + NETIF_MSG_PROBE = 0x0002,
19089 + NETIF_MSG_LINK = 0x0004,
19090 + NETIF_MSG_TIMER = 0x0008,
19091 + NETIF_MSG_IFDOWN = 0x0010,
19092 + NETIF_MSG_IFUP = 0x0020,
19093 + NETIF_MSG_RX_ERR = 0x0040,
19094 + NETIF_MSG_TX_ERR = 0x0080,
19095 + NETIF_MSG_TX_QUEUED = 0x0100,
19096 + NETIF_MSG_INTR = 0x0200,
19097 + NETIF_MSG_TX_DONE = 0x0400,
19098 + NETIF_MSG_RX_STATUS = 0x0800,
19099 + NETIF_MSG_PKTDATA = 0x1000,
19100 + NETIF_MSG_HW = 0x2000,
19101 + NETIF_MSG_WOL = 0x4000,
19105 +#define NETIF_MSG_HW 0x2000
19106 +#define NETIF_MSG_WOL 0x4000
19107 +#endif /* HAVE_NETIF_MSG */
19110 +#define MII_RESV1 0x17 /* Reserved... */
19114 +#define unlikely(_x) _x
19115 +#define likely(_x) _x
19119 +#define WARN_ON(x)
19122 +#ifndef PCI_DEVICE
19123 +#define PCI_DEVICE(vend,dev) \
19124 + .vendor = (vend), .device = (dev), \
19125 + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
19128 +#ifndef num_online_cpus
19129 +#define num_online_cpus() smp_num_cpus
19132 +#ifndef _LINUX_RANDOM_H
19133 +#include <linux/random.h>
19136 +#ifndef DECLARE_BITMAP
19137 +#ifndef BITS_TO_LONGS
19138 +#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG)
19140 +#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)]
19144 +#define VLAN_HLEN 4
19147 +#ifndef VLAN_ETH_HLEN
19148 +#define VLAN_ETH_HLEN 18
19151 +#ifndef VLAN_ETH_FRAME_LEN
19152 +#define VLAN_ETH_FRAME_LEN 1518
19155 +#ifndef DCA_GET_TAG_TWO_ARGS
19156 +#define dca3_get_tag(a,b) dca_get_tag(b)
19160 +/*****************************************************************************/
19161 +/* Installations with ethtool version without eeprom, adapter id, or statistics
19164 +#ifndef ETH_GSTRING_LEN
19165 +#define ETH_GSTRING_LEN 32
19168 +#ifndef ETHTOOL_GSTATS
19169 +#define ETHTOOL_GSTATS 0x1d
19170 +#undef ethtool_drvinfo
19171 +#define ethtool_drvinfo k_ethtool_drvinfo
19172 +struct k_ethtool_drvinfo {
19175 + char version[32];
19176 + char fw_version[32];
19177 + char bus_info[32];
19178 + char reserved1[32];
19179 + char reserved2[16];
19181 + u32 testinfo_len;
19186 +struct ethtool_stats {
19191 +#endif /* ETHTOOL_GSTATS */
19193 +#ifndef ETHTOOL_PHYS_ID
19194 +#define ETHTOOL_PHYS_ID 0x1c
19195 +#endif /* ETHTOOL_PHYS_ID */
19197 +#ifndef ETHTOOL_GSTRINGS
19198 +#define ETHTOOL_GSTRINGS 0x1b
19199 +enum ethtool_stringset {
19203 +struct ethtool_gstrings {
19204 + u32 cmd; /* ETHTOOL_GSTRINGS */
19205 + u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
19206 + u32 len; /* number of strings in the string set */
19209 +#endif /* ETHTOOL_GSTRINGS */
19211 +#ifndef ETHTOOL_TEST
19212 +#define ETHTOOL_TEST 0x1a
19213 +enum ethtool_test_flags {
19214 + ETH_TEST_FL_OFFLINE = (1 << 0),
19215 + ETH_TEST_FL_FAILED = (1 << 1),
19217 +struct ethtool_test {
19224 +#endif /* ETHTOOL_TEST */
19226 +#ifndef ETHTOOL_GEEPROM
19227 +#define ETHTOOL_GEEPROM 0xb
19228 +#undef ETHTOOL_GREGS
19229 +struct ethtool_eeprom {
19237 +struct ethtool_value {
19241 +#endif /* ETHTOOL_GEEPROM */
19243 +#ifndef ETHTOOL_GLINK
19244 +#define ETHTOOL_GLINK 0xa
19245 +#endif /* ETHTOOL_GLINK */
19247 +#ifndef ETHTOOL_GREGS
19248 +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */
19249 +#define ethtool_regs _kc_ethtool_regs
19250 +/* for passing big chunks of data */
19251 +struct _kc_ethtool_regs {
19253 + u32 version; /* driver-specific, indicates different chips/revs */
19254 + u32 len; /* bytes */
19257 +#endif /* ETHTOOL_GREGS */
19259 +#ifndef ETHTOOL_GMSGLVL
19260 +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
19262 +#ifndef ETHTOOL_SMSGLVL
19263 +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */
19265 +#ifndef ETHTOOL_NWAY_RST
19266 +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */
19268 +#ifndef ETHTOOL_GLINK
19269 +#define ETHTOOL_GLINK 0x0000000a /* Get link status */
19271 +#ifndef ETHTOOL_GEEPROM
19272 +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
19274 +#ifndef ETHTOOL_SEEPROM
19275 +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */
19277 +#ifndef ETHTOOL_GCOALESCE
19278 +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
19279 +/* for configuring coalescing parameters of chip */
19280 +#define ethtool_coalesce _kc_ethtool_coalesce
19281 +struct _kc_ethtool_coalesce {
19282 + u32 cmd; /* ETHTOOL_{G,S}COALESCE */
19284 + /* How many usecs to delay an RX interrupt after
19285 + * a packet arrives. If 0, only rx_max_coalesced_frames
19288 + u32 rx_coalesce_usecs;
19290 + /* How many packets to delay an RX interrupt after
19291 + * a packet arrives. If 0, only rx_coalesce_usecs is
19292 + * used. It is illegal to set both usecs and max frames
19293 + * to zero as this would cause RX interrupts to never be
19296 + u32 rx_max_coalesced_frames;
19298 + /* Same as above two parameters, except that these values
19299 + * apply while an IRQ is being serviced by the host. Not
19300 + * all cards support this feature and the values are ignored
19303 + u32 rx_coalesce_usecs_irq;
19304 + u32 rx_max_coalesced_frames_irq;
19306 + /* How many usecs to delay a TX interrupt after
19307 + * a packet is sent. If 0, only tx_max_coalesced_frames
19310 + u32 tx_coalesce_usecs;
19312 + /* How many packets to delay a TX interrupt after
19313 + * a packet is sent. If 0, only tx_coalesce_usecs is
19314 + * used. It is illegal to set both usecs and max frames
19315 + * to zero as this would cause TX interrupts to never be
19318 + u32 tx_max_coalesced_frames;
19320 + /* Same as above two parameters, except that these values
19321 + * apply while an IRQ is being serviced by the host. Not
19322 + * all cards support this feature and the values are ignored
19325 + u32 tx_coalesce_usecs_irq;
19326 + u32 tx_max_coalesced_frames_irq;
19328 + /* How many usecs to delay in-memory statistics
19329 + * block updates. Some drivers do not have an in-memory
19330 + * statistic block, and in such cases this value is ignored.
19331 + * This value must not be zero.
19333 + u32 stats_block_coalesce_usecs;
19335 + /* Adaptive RX/TX coalescing is an algorithm implemented by
19336 + * some drivers to improve latency under low packet rates and
19337 + * improve throughput under high packet rates. Some drivers
19338 + * only implement one of RX or TX adaptive coalescing. Anything
19339 + * not implemented by the driver causes these values to be
19340 + * silently ignored.
19342 + u32 use_adaptive_rx_coalesce;
19343 + u32 use_adaptive_tx_coalesce;
19345 + /* When the packet rate (measured in packets per second)
19346 + * is below pkt_rate_low, the {rx,tx}_*_low parameters are
19349 + u32 pkt_rate_low;
19350 + u32 rx_coalesce_usecs_low;
19351 + u32 rx_max_coalesced_frames_low;
19352 + u32 tx_coalesce_usecs_low;
19353 + u32 tx_max_coalesced_frames_low;
19355 + /* When the packet rate is below pkt_rate_high but above
19356 + * pkt_rate_low (both measured in packets per second) the
19357 + * normal {rx,tx}_* coalescing parameters are used.
19360 + /* When the packet rate is (measured in packets per second)
19361 + * is above pkt_rate_high, the {rx,tx}_*_high parameters are
19364 + u32 pkt_rate_high;
19365 + u32 rx_coalesce_usecs_high;
19366 + u32 rx_max_coalesced_frames_high;
19367 + u32 tx_coalesce_usecs_high;
19368 + u32 tx_max_coalesced_frames_high;
19370 + /* How often to do adaptive coalescing packet rate sampling,
19371 + * measured in seconds. Must not be zero.
19373 + u32 rate_sample_interval;
19375 +#endif /* ETHTOOL_GCOALESCE */
19377 +#ifndef ETHTOOL_SCOALESCE
19378 +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
19380 +#ifndef ETHTOOL_GRINGPARAM
19381 +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
19382 +/* for configuring RX/TX ring parameters */
19383 +#define ethtool_ringparam _kc_ethtool_ringparam
19384 +struct _kc_ethtool_ringparam {
19385 + u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */
19387 + /* Read only attributes. These indicate the maximum number
19388 + * of pending RX/TX ring entries the driver will allow the
19391 + u32 rx_max_pending;
19392 + u32 rx_mini_max_pending;
19393 + u32 rx_jumbo_max_pending;
19394 + u32 tx_max_pending;
19396 + /* Values changeable by the user. The valid values are
19397 + * in the range 1 to the "*_max_pending" counterpart above.
19400 + u32 rx_mini_pending;
19401 + u32 rx_jumbo_pending;
19404 +#endif /* ETHTOOL_GRINGPARAM */
19406 +#ifndef ETHTOOL_SRINGPARAM
19407 +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */
19409 +#ifndef ETHTOOL_GPAUSEPARAM
19410 +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
19411 +/* for configuring link flow control parameters */
19412 +#define ethtool_pauseparam _kc_ethtool_pauseparam
19413 +struct _kc_ethtool_pauseparam {
19414 + u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */
19416 + /* If the link is being auto-negotiated (via ethtool_cmd.autoneg
19417 + * being true) the user may set 'autoneg' here non-zero to have the
19418 + * pause parameters be auto-negotiated too. In such a case, the
19419 + * {rx,tx}_pause values below determine what capabilities are
19422 + * If 'autoneg' is zero or the link is not being auto-negotiated,
19423 + * then {rx,tx}_pause force the driver to use/not-use pause
19430 +#endif /* ETHTOOL_GPAUSEPARAM */
19432 +#ifndef ETHTOOL_SPAUSEPARAM
19433 +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
19435 +#ifndef ETHTOOL_GRXCSUM
19436 +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
19438 +#ifndef ETHTOOL_SRXCSUM
19439 +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
19441 +#ifndef ETHTOOL_GTXCSUM
19442 +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
19444 +#ifndef ETHTOOL_STXCSUM
19445 +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
19447 +#ifndef ETHTOOL_GSG
19448 +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable
19449 + * (ethtool_value) */
19451 +#ifndef ETHTOOL_SSG
19452 +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable
19453 + * (ethtool_value). */
19455 +#ifndef ETHTOOL_TEST
19456 +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */
19458 +#ifndef ETHTOOL_GSTRINGS
19459 +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
19461 +#ifndef ETHTOOL_PHYS_ID
19462 +#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */
19464 +#ifndef ETHTOOL_GSTATS
19465 +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
19467 +#ifndef ETHTOOL_GTSO
19468 +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
19470 +#ifndef ETHTOOL_STSO
19471 +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
19474 +#ifndef ETHTOOL_BUSINFO_LEN
19475 +#define ETHTOOL_BUSINFO_LEN 32
19478 +/*****************************************************************************/
19479 +/* 2.4.3 => 2.4.0 */
19480 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )
19482 +/**************************************/
19483 +/* PCI DRIVER API */
19485 +#ifndef pci_set_dma_mask
19486 +#define pci_set_dma_mask _kc_pci_set_dma_mask
19487 +extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask);
19490 +#ifndef pci_request_regions
19491 +#define pci_request_regions _kc_pci_request_regions
19492 +extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name);
19495 +#ifndef pci_release_regions
19496 +#define pci_release_regions _kc_pci_release_regions
19497 +extern void _kc_pci_release_regions(struct pci_dev *pdev);
19500 +/**************************************/
19501 +/* NETWORK DRIVER API */
19503 +#ifndef alloc_etherdev
19504 +#define alloc_etherdev _kc_alloc_etherdev
19505 +extern struct net_device * _kc_alloc_etherdev(int sizeof_priv);
19508 +#ifndef is_valid_ether_addr
19509 +#define is_valid_ether_addr _kc_is_valid_ether_addr
19510 +extern int _kc_is_valid_ether_addr(u8 *addr);
19513 +/**************************************/
19514 +/* MISCELLANEOUS */
19516 +#ifndef INIT_TQUEUE
19517 +#define INIT_TQUEUE(_tq, _routine, _data) \
19519 + INIT_LIST_HEAD(&(_tq)->list); \
19520 + (_tq)->sync = 0; \
19521 + (_tq)->routine = _routine; \
19522 + (_tq)->data = _data; \
19526 +#endif /* 2.4.3 => 2.4.0 */
19528 +/*****************************************************************************/
19529 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) )
19530 +/* Generic MII registers. */
19531 +#define MII_BMCR 0x00 /* Basic mode control register */
19532 +#define MII_BMSR 0x01 /* Basic mode status register */
19533 +#define MII_PHYSID1 0x02 /* PHYS ID 1 */
19534 +#define MII_PHYSID2 0x03 /* PHYS ID 2 */
19535 +#define MII_ADVERTISE 0x04 /* Advertisement control reg */
19536 +#define MII_LPA 0x05 /* Link partner ability reg */
19537 +#define MII_EXPANSION 0x06 /* Expansion register */
19538 +/* Basic mode control register. */
19539 +#define BMCR_FULLDPLX 0x0100 /* Full duplex */
19540 +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
19541 +/* Basic mode status register. */
19542 +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
19543 +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
19544 +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
19545 +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
19546 +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
19547 +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
19548 +/* Advertisement control register. */
19549 +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
19550 +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
19551 +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
19552 +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
19553 +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
19554 +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
19555 + ADVERTISE_100HALF | ADVERTISE_100FULL)
19556 +/* Expansion register for auto-negotiation. */
19557 +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
19560 +/*****************************************************************************/
19561 +/* 2.4.6 => 2.4.3 */
19562 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )
19564 +#ifndef pci_set_power_state
19565 +#define pci_set_power_state _kc_pci_set_power_state
19566 +extern int _kc_pci_set_power_state(struct pci_dev *dev, int state);
19569 +#ifndef pci_save_state
19570 +#define pci_save_state _kc_pci_save_state
19571 +extern int _kc_pci_save_state(struct pci_dev *dev, u32 *buffer);
19574 +#ifndef pci_restore_state
19575 +#define pci_restore_state _kc_pci_restore_state
19576 +extern int _kc_pci_restore_state(struct pci_dev *pdev, u32 *buffer);
19579 +#ifndef pci_enable_wake
19580 +#define pci_enable_wake _kc_pci_enable_wake
19581 +extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable);
19584 +#ifndef pci_disable_device
19585 +#define pci_disable_device _kc_pci_disable_device
19586 +extern void _kc_pci_disable_device(struct pci_dev *pdev);
19589 +/* PCI PM entry point syntax changed, so don't support suspend/resume */
19592 +#endif /* 2.4.6 => 2.4.3 */
19594 +#ifndef HAVE_PCI_SET_MWI
19595 +#define pci_set_mwi(X) pci_write_config_word(X, \
19596 + PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \
19597 + PCI_COMMAND_INVALIDATE);
19598 +#define pci_clear_mwi(X) pci_write_config_word(X, \
19599 + PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \
19600 + ~PCI_COMMAND_INVALIDATE);
19603 +/*****************************************************************************/
19604 +/* 2.4.10 => 2.4.9 */
19605 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) )
19607 +/**************************************/
19610 +#ifndef MODULE_LICENSE
19611 + #define MODULE_LICENSE(X)
19614 +/**************************************/
19618 +#define min(x,y) ({ \
19619 + const typeof(x) _x = (x); \
19620 + const typeof(y) _y = (y); \
19621 + (void) (&_x == &_y); \
19622 + _x < _y ? _x : _y; })
19625 +#define max(x,y) ({ \
19626 + const typeof(x) _x = (x); \
19627 + const typeof(y) _y = (y); \
19628 + (void) (&_x == &_y); \
19629 + _x > _y ? _x : _y; })
19631 +#ifndef list_for_each_safe
19632 +#define list_for_each_safe(pos, n, head) \
19633 + for (pos = (head)->next, n = pos->next; pos != (head); \
19634 + pos = n, n = pos->next)
19637 +#endif /* 2.4.10 -> 2.4.6 */
19640 +/*****************************************************************************/
19641 +/* 2.4.13 => 2.4.10 */
19642 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )
19644 +/**************************************/
19645 +/* PCI DMA MAPPING */
19647 +#ifndef virt_to_page
19648 + #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))
19651 +#ifndef pci_map_page
19652 +#define pci_map_page _kc_pci_map_page
19653 +extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction);
19656 +#ifndef pci_unmap_page
19657 +#define pci_unmap_page _kc_pci_unmap_page
19658 +extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction);
19661 +/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */
19663 +#undef DMA_32BIT_MASK
19664 +#define DMA_32BIT_MASK 0xffffffff
19665 +#undef DMA_64BIT_MASK
19666 +#define DMA_64BIT_MASK 0xffffffff
19668 +/**************************************/
19672 +#define cpu_relax() rep_nop()
19675 +#endif /* 2.4.13 => 2.4.10 */
19677 +/*****************************************************************************/
19678 +/* 2.4.17 => 2.4.12 */
19679 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) )
19681 +#ifndef __devexit_p
19682 + #define __devexit_p(x) &(x)
19685 +#endif /* 2.4.17 => 2.4.13 */
19687 +/*****************************************************************************/
19688 +/* 2.4.20 => 2.4.19 */
19689 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) )
19691 +/* we won't support NAPI on less than 2.4.20 */
19693 +#undef CONFIG_E1000_NAPI
19694 +#undef CONFIG_E1000E_NAPI
19695 +#undef CONFIG_IXGB_NAPI
19698 +#endif /* 2.4.20 => 2.4.19 */
19699 +/*****************************************************************************/
19700 +/* 2.4.22 => 2.4.17 */
19701 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )
19702 +#define pci_name(x) ((x)->slot_name)
19705 +/*****************************************************************************/
19706 +/* 2.4.22 => 2.4.17 */
19708 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )
19711 +/*****************************************************************************/
19712 +/*****************************************************************************/
19713 +/* 2.4.23 => 2.4.22 */
19714 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) )
19715 +/*****************************************************************************/
19717 +#ifndef netif_poll_disable
19718 +#define netif_poll_disable(x) _kc_netif_poll_disable(x)
19719 +static inline void _kc_netif_poll_disable(struct net_device *netdev)
19721 + while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) {
19723 + current->state = TASK_INTERRUPTIBLE;
19724 + schedule_timeout(1);
19729 +#ifndef netif_poll_enable
19730 +#define netif_poll_enable(x) _kc_netif_poll_enable(x)
19731 +static inline void _kc_netif_poll_enable(struct net_device *netdev)
19733 + clear_bit(__LINK_STATE_RX_SCHED, &netdev->state);
19737 +#ifndef netif_tx_disable
19738 +#define netif_tx_disable(x) _kc_netif_tx_disable(x)
19739 +static inline void _kc_netif_tx_disable(struct net_device *dev)
19741 + spin_lock_bh(&dev->xmit_lock);
19742 + netif_stop_queue(dev);
19743 + spin_unlock_bh(&dev->xmit_lock);
19746 +#endif /* 2.4.23 => 2.4.22 */
19748 +/*****************************************************************************/
19749 +/* 2.6.4 => 2.6.0 */
19750 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \
19751 + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
19752 + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )
19753 +#define ETHTOOL_OPS_COMPAT
19754 +#endif /* 2.6.4 => 2.6.0 */
19756 +/*****************************************************************************/
19757 +/* 2.5.71 => 2.4.x */
19758 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) )
19759 +#include <net/sock.h>
19760 +#define sk_protocol protocol
19762 +#define pci_get_device pci_find_device
19763 +#endif /* 2.5.70 => 2.4.x */
19765 +/*****************************************************************************/
19766 +/* < 2.4.27 or 2.6.0 <= 2.6.5 */
19767 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \
19768 + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
19769 + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) )
19771 +#ifndef netif_msg_init
19772 +#define netif_msg_init _kc_netif_msg_init
19773 +static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits)
19775 + /* use default */
19776 + if (debug_value < 0 || debug_value >= (sizeof(u32) * 8))
19777 + return default_msg_enable_bits;
19778 + if (debug_value == 0) /* no output */
19780 + /* set low N bits */
19781 + return (1 << debug_value) -1;
19785 +#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */
19786 +/*****************************************************************************/
19787 +#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \
19788 + (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \
19789 + ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))
19790 +#define netdev_priv(x) x->priv
19793 +/*****************************************************************************/
19795 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) )
19796 +#undef pci_register_driver
19797 +#define pci_register_driver pci_module_init
19799 +#define dev_err(__unused_dev, format, arg...) \
19800 + printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg)
19802 +/* hlist_* code - double linked lists */
19803 +struct hlist_head {
19804 + struct hlist_node *first;
19807 +struct hlist_node {
19808 + struct hlist_node *next, **pprev;
19811 +static inline void __hlist_del(struct hlist_node *n)
19813 + struct hlist_node *next = n->next;
19814 + struct hlist_node **pprev = n->pprev;
19817 + next->pprev = pprev;
19820 +static inline void hlist_del(struct hlist_node *n)
19827 +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
19829 + struct hlist_node *first = h->first;
19832 + first->pprev = &n->next;
19834 + n->pprev = &h->first;
19837 +static inline int hlist_empty(const struct hlist_head *h)
19839 + return !h->first;
19841 +#define HLIST_HEAD_INIT { .first = NULL }
19842 +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }
19843 +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
19844 +static inline void INIT_HLIST_NODE(struct hlist_node *h)
19849 +#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
19851 +#define hlist_for_each_entry(tpos, pos, head, member) \
19852 + for (pos = (head)->first; \
19853 + pos && ({ prefetch(pos->next); 1;}) && \
19854 + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
19857 +#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \
19858 + for (pos = (head)->first; \
19859 + pos && ({ n = pos->next; 1; }) && \
19860 + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
19863 +/* we ignore GFP here */
19864 +#define dma_alloc_coherent(dv, sz, dma, gfp) \
19865 + pci_alloc_consistent(pdev, (sz), (dma))
19866 +#define dma_free_coherent(dv, sz, addr, dma_addr) \
19867 + pci_free_consistent(pdev, (sz), (addr), (dma_addr))
19869 +#ifndef might_sleep
19870 +#define might_sleep()
19873 +#endif /* <= 2.5.0 */
19875 +/*****************************************************************************/
19876 +/* 2.5.28 => 2.4.23 */
19877 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )
19879 +static inline void _kc_synchronize_irq(void)
19881 + synchronize_irq();
19883 +#undef synchronize_irq
19884 +#define synchronize_irq(X) _kc_synchronize_irq()
19886 +#include <linux/tqueue.h>
19887 +#define work_struct tq_struct
19889 +#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a)
19890 +#undef container_of
19891 +#define container_of list_entry
19892 +#define schedule_work schedule_task
19893 +#define flush_scheduled_work flush_scheduled_tasks
19895 +#endif /* 2.5.28 => 2.4.17 */
19897 +/*****************************************************************************/
19898 +/* 2.6.0 => 2.5.28 */
19899 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
19900 +#define MODULE_INFO(version, _version)
19901 +#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
19902 +#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1
19904 +#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
19905 +#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1
19908 +#define pci_set_consistent_dma_mask(dev,mask) 1
19911 +#define dev_put(dev) __dev_put(dev)
19913 +#ifndef skb_fill_page_desc
19914 +#define skb_fill_page_desc _kc_skb_fill_page_desc
19915 +extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);
19919 +#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))
19921 +/* find_first_bit and find_next bit are not defined for most
19922 + * 2.4 kernels (except for the redhat 2.4.21 kernels
19924 +#include <linux/bitops.h>
19925 +#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
19926 +#undef find_next_bit
19927 +#define find_next_bit _kc_find_next_bit
19928 +extern unsigned long _kc_find_next_bit(const unsigned long *addr,
19929 + unsigned long size,
19930 + unsigned long offset);
19931 +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
19933 +#endif /* 2.6.0 => 2.5.28 */
19935 +/*****************************************************************************/
19936 +/* 2.6.4 => 2.6.0 */
19937 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )
19938 +#define MODULE_VERSION(_version) MODULE_INFO(version, _version)
19939 +#endif /* 2.6.4 => 2.6.0 */
19941 +/*****************************************************************************/
19942 +/* 2.6.5 => 2.6.0 */
19943 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )
19944 +#define pci_dma_sync_single_for_cpu pci_dma_sync_single
19945 +#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu
19946 +#endif /* 2.6.5 => 2.6.0 */
19948 +/*****************************************************************************/
19949 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) )
19950 +/* taken from 2.6 include/linux/bitmap.h */
19951 +#undef bitmap_zero
19952 +#define bitmap_zero _kc_bitmap_zero
19953 +static inline void _kc_bitmap_zero(unsigned long *dst, int nbits)
19955 + if (nbits <= BITS_PER_LONG)
19958 + int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
19959 + memset(dst, 0, len);
19962 +#endif /* < 2.6.6 */
19964 +/*****************************************************************************/
19965 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) )
19967 +#define if_mii _kc_if_mii
19968 +static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)
19970 + return (struct mii_ioctl_data *) &rq->ifr_ifru;
19972 +#endif /* < 2.6.7 */
19974 +/*****************************************************************************/
19975 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
19976 +#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \
19977 + schedule_timeout((x * HZ)/1000 + 2); \
19980 +#endif /* < 2.6.8 */
19982 +/*****************************************************************************/
19983 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
19984 +#include <net/dsfield.h>
19988 +#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags)
19989 +extern void *_kc_kzalloc(size_t size, int flags);
19991 +#define MSEC_PER_SEC 1000L
19992 +static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)
19994 +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
19995 + return (MSEC_PER_SEC / HZ) * j;
19996 +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
19997 + return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
19999 + return (j * MSEC_PER_SEC) / HZ;
20002 +static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m)
20004 + if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET))
20005 + return MAX_JIFFY_OFFSET;
20006 +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
20007 + return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
20008 +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
20009 + return m * (HZ / MSEC_PER_SEC);
20011 + return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;
20015 +#define msleep_interruptible _kc_msleep_interruptible
20016 +static inline unsigned long _kc_msleep_interruptible(unsigned int msecs)
20018 + unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1;
20020 + while (timeout && !signal_pending(current)) {
20021 + __set_current_state(TASK_INTERRUPTIBLE);
20022 + timeout = schedule_timeout(timeout);
20024 + return _kc_jiffies_to_msecs(timeout);
20027 +/* Basic mode control register. */
20028 +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
20030 +#ifdef pci_dma_mapping_error
20031 +#undef pci_dma_mapping_error
20033 +#define pci_dma_mapping_error _kc_pci_dma_mapping_error
20034 +static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev,
20035 + dma_addr_t dma_addr)
20037 + return dma_addr == 0;
20040 +#endif /* < 2.6.9 */
20042 +/*****************************************************************************/
20043 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,6) && \
20044 + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )
20045 +#ifdef pci_save_state
20046 +#undef pci_save_state
20048 +#define pci_save_state(X) { \
20050 + if (adapter->pci_state) { \
20051 + for (i = 0; i < 16; i++) { \
20052 + pci_read_config_dword((X), \
20054 + &adapter->pci_state[i]); \
20059 +#ifdef pci_restore_state
20060 +#undef pci_restore_state
20062 +#define pci_restore_state(X) { \
20064 + if (adapter->pci_state) { \
20065 + for (i = 0; i < 16; i++) { \
20066 + pci_write_config_dword((X), \
20068 + adapter->pci_state[i]); \
20071 + for (i = 0; i < 6; i++) { \
20072 + pci_write_config_dword((X), \
20073 + PCI_BASE_ADDRESS_0 + (i * 4), \
20074 + (X)->resource[i].start); \
20078 +#endif /* 2.4.6 <= x < 2.6.10 */
20080 +/*****************************************************************************/
20081 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )
20082 +#ifdef module_param_array_named
20083 +#undef module_param_array_named
20084 +#define module_param_array_named(name, array, type, nump, perm) \
20085 + static struct kparam_array __param_arr_##name \
20086 + = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \
20087 + sizeof(array[0]), array }; \
20088 + module_param_call(name, param_array_set, param_array_get, \
20089 + &__param_arr_##name, perm)
20090 +#endif /* module_param_array_named */
20091 +#endif /* < 2.6.10 */
20093 +/*****************************************************************************/
20094 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) )
20098 +#define PCI_D3hot 3
20099 +#define PCI_D3cold 4
20100 +#define pci_choose_state(pdev,state) state
20101 +#define PMSG_SUSPEND 3
20103 +#undef NETIF_F_LLTX
20105 +#ifndef ARCH_HAS_PREFETCH
20106 +#define prefetch(X)
20109 +#ifndef NET_IP_ALIGN
20110 +#define NET_IP_ALIGN 2
20113 +#define KC_USEC_PER_SEC 1000000L
20114 +#define usecs_to_jiffies _kc_usecs_to_jiffies
20115 +static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j)
20117 +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)
20118 + return (KC_USEC_PER_SEC / HZ) * j;
20119 +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)
20120 + return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC);
20122 + return (j * KC_USEC_PER_SEC) / HZ;
20125 +static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m)
20127 + if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET))
20128 + return MAX_JIFFY_OFFSET;
20129 +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)
20130 + return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ);
20131 +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)
20132 + return m * (HZ / KC_USEC_PER_SEC);
20134 + return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC;
20137 +#endif /* < 2.6.11 */
20139 +/*****************************************************************************/
20140 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) )
20141 +#include <linux/reboot.h>
20142 +#define USE_REBOOT_NOTIFIER
20144 +/* Generic MII registers. */
20145 +#define MII_CTRL1000 0x09 /* 1000BASE-T control */
20146 +#define MII_STAT1000 0x0a /* 1000BASE-T status */
20147 +/* Advertisement control register. */
20148 +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
20149 +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */
20150 +/* 1000BASE-T Control register */
20151 +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
20154 +/*****************************************************************************/
20155 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )
20156 +#define pm_message_t u32
20158 +#define kzalloc _kc_kzalloc
20159 +extern void *_kc_kzalloc(size_t size, int flags);
20162 +/* Generic MII registers. */
20163 +#define MII_ESTATUS 0x0f /* Extended Status */
20164 +/* Basic mode status register. */
20165 +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
20166 +/* Extended status register. */
20167 +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
20168 +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
20171 +/*****************************************************************************/
20172 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) )
20173 +#undef HAVE_PCI_ERS
20174 +#else /* 2.6.16 and above */
20175 +#undef HAVE_PCI_ERS
20176 +#define HAVE_PCI_ERS
20179 +/*****************************************************************************/
20180 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )
20182 +#ifndef IRQF_PROBE_SHARED
20183 +#ifdef SA_PROBEIRQ
20184 +#define IRQF_PROBE_SHARED SA_PROBEIRQ
20186 +#define IRQF_PROBE_SHARED 0
20190 +#ifndef IRQF_SHARED
20191 +#define IRQF_SHARED SA_SHIRQ
20194 +#ifndef ARRAY_SIZE
20195 +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
20198 +#ifndef netdev_alloc_skb
20199 +#define netdev_alloc_skb _kc_netdev_alloc_skb
20200 +extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev,
20201 + unsigned int length);
20204 +#ifndef skb_is_gso
20205 +#ifdef NETIF_F_TSO
20206 +#define skb_is_gso _kc_skb_is_gso
20207 +static inline int _kc_skb_is_gso(const struct sk_buff *skb)
20209 + return skb_shinfo(skb)->gso_size;
20212 +#define skb_is_gso(a) 0
20216 +#endif /* < 2.6.18 */
20218 +/*****************************************************************************/
20219 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )
20221 +#ifndef DIV_ROUND_UP
20222 +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
20225 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) )
20226 +#ifndef RHEL_RELEASE_CODE
20227 +#define RHEL_RELEASE_CODE 0
20229 +#ifndef RHEL_RELEASE_VERSION
20230 +#define RHEL_RELEASE_VERSION(a,b) 0
20232 +#ifndef AX_RELEASE_CODE
20233 +#define AX_RELEASE_CODE 0
20235 +#ifndef AX_RELEASE_VERSION
20236 +#define AX_RELEASE_VERSION(a,b) 0
20238 +#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0))))
20239 +typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *);
20241 +typedef irqreturn_t (*new_handler_t)(int, void*);
20242 +static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
20244 +typedef void (*irq_handler_t)(int, void*, struct pt_regs *);
20245 +typedef void (*new_handler_t)(int, void*);
20246 +static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
20249 + irq_handler_t new_handler = (irq_handler_t) handler;
20250 + return request_irq(irq, new_handler, flags, devname, dev_id);
20253 +#undef request_irq
20254 +#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id))
20256 +#define irq_handler_t new_handler_t
20258 +/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */
20259 +#define PCIE_CONFIG_SPACE_LEN 256
20260 +#define PCI_CONFIG_SPACE_LEN 64
20261 +#define PCIE_LINK_STATUS 0x12
20262 +#ifdef DRIVER_E1000E
20263 +#define pci_config_space_ich8lan() { \
20264 + if (adapter->flags & FLAG_IS_ICH) \
20265 + size = PCIE_CONFIG_SPACE_LEN; \
20268 +#define pci_config_space_ich8lan()
20270 +#undef pci_save_state
20271 +#define pci_save_state(pdev) _kc_pci_save_state(adapter)
20272 +#define _kc_pci_save_state(adapter) 0; { \
20273 + int size = PCI_CONFIG_SPACE_LEN, i; \
20274 + u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); \
20275 + u16 pcie_link_status; \
20277 + if (pcie_cap_offset) { \
20278 + if (!pci_read_config_word(pdev, pcie_cap_offset + PCIE_LINK_STATUS, \
20279 + &pcie_link_status)) \
20280 + size = PCIE_CONFIG_SPACE_LEN; \
20282 + pci_config_space_ich8lan(); \
20283 + WARN_ON(adapter->config_space != NULL); \
20284 + adapter->config_space = kmalloc(size, GFP_KERNEL); \
20285 + if (!adapter->config_space) { \
20286 + printk(KERN_ERR "Out of memory in pci_save_state\n"); \
20287 + return -ENOMEM; \
20289 + for (i = 0; i < (size / 4); i++) \
20290 + pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]); \
20292 +#undef pci_restore_state
20293 +#define pci_restore_state(pdev) _kc_pci_restore_state(adapter)
20294 +#define _kc_pci_restore_state(adapter) { \
20295 + int size = PCI_CONFIG_SPACE_LEN, i; \
20296 + u16 pcie_cap_offset; \
20297 + u16 pcie_link_status; \
20299 + if (adapter->config_space != NULL) { \
20300 + pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP); \
20301 + if (pcie_cap_offset) { \
20302 + if (!pci_read_config_word(pdev, pcie_cap_offset + PCIE_LINK_STATUS, \
20303 + &pcie_link_status)) \
20304 + size = PCIE_CONFIG_SPACE_LEN; \
20306 + pci_config_space_ich8lan(); \
20307 + for (i = 0; i < (size / 4); i++) \
20308 + pci_write_config_dword(pdev, i * 4, adapter->config_space[i]); \
20309 + kfree(adapter->config_space); \
20310 + adapter->config_space = NULL; \
20314 +#endif /* < 2.6.19 */
20315 +/*****************************************************************************/
20316 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )
20317 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) )
20319 +#define INIT_WORK(_work, _func) \
20321 + INIT_LIST_HEAD(&(_work)->entry); \
20322 + (_work)->pending = 0; \
20323 + (_work)->func = (void (*)(void *))_func; \
20324 + (_work)->data = _work; \
20325 + init_timer(&(_work)->timer); \
20329 +#ifndef PCI_VDEVICE
20330 +#define PCI_VDEVICE(ven, dev) \
20331 + PCI_VENDOR_ID_##ven, (dev), \
20332 + PCI_ANY_ID, PCI_ANY_ID, 0, 0
20335 +#ifndef round_jiffies
20336 +#define round_jiffies(x) x
20339 +#define csum_offset csum
20341 +#endif /* < 2.6.20 */
20343 +/*****************************************************************************/
20344 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )
20345 +#define vlan_group_get_device(vg, id) (vg->vlan_devices[id])
20346 +#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev;
20347 +#define pci_channel_offline(pdev) (pdev->error_state && \
20348 + pdev->error_state != pci_channel_io_normal)
20349 +#endif /* < 2.6.21 */
20351 +/*****************************************************************************/
20352 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )
20353 +#define tcp_hdr(skb) (skb->h.th)
20354 +#define tcp_hdrlen(skb) (skb->h.th->doff << 2)
20355 +#define skb_transport_offset(skb) (skb->h.raw - skb->data)
20356 +#define skb_transport_header(skb) (skb->h.raw)
20357 +#define ipv6_hdr(skb) (skb->nh.ipv6h)
20358 +#define ip_hdr(skb) (skb->nh.iph)
20359 +#define skb_network_offset(skb) (skb->nh.raw - skb->data)
20360 +#define skb_network_header(skb) (skb->nh.raw)
20361 +#define skb_tail_pointer(skb) skb->tail
20362 +#define skb_copy_to_linear_data_offset(skb, offset, from, len) \
20363 + memcpy(skb->data + offset, from, len)
20364 +#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)
20365 +#define pci_register_driver pci_module_init
20366 +#define skb_mac_header(skb) skb->mac.raw
20368 +#ifdef NETIF_F_MULTI_QUEUE
20369 +#ifndef alloc_etherdev_mq
20370 +#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a)
20372 +#endif /* NETIF_F_MULTI_QUEUE */
20374 +#ifndef ETH_FCS_LEN
20375 +#define ETH_FCS_LEN 4
20377 +#endif /* < 2.6.22 */
20379 +/*****************************************************************************/
20380 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) )
20381 +#undef ETHTOOL_GPERMADDR
20382 +#undef SET_MODULE_OWNER
20383 +#define SET_MODULE_OWNER(dev) do { } while (0)
20384 +#endif /* > 2.6.22 */
20386 +/*****************************************************************************/
20387 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
20388 +/* NAPI API changes in 2.6.24 break everything */
20389 +struct napi_struct {
20390 + /* used to look up the real NAPI polling routine */
20391 + int (*poll)(struct napi_struct *, int);
20395 +extern int __kc_adapter_clean(struct net_device *, int *);
20396 +#define netif_rx_complete(netdev, napi) netif_rx_complete(netdev)
20397 +#define netif_rx_schedule_prep(netdev, napi) netif_rx_schedule_prep(netdev)
20398 +#define netif_rx_schedule(netdev, napi) netif_rx_schedule(netdev)
20399 +#define __netif_rx_schedule(netdev, napi) __netif_rx_schedule(netdev)
20400 +#define napi_enable(napi) netif_poll_enable(adapter->netdev)
20401 +#define napi_disable(napi) netif_poll_disable(adapter->netdev)
20402 +#define netif_napi_add(_netdev, _napi, _poll, _weight) \
20404 + struct napi_struct *__napi = _napi; \
20405 + _netdev->poll = &(__kc_adapter_clean); \
20406 + _netdev->weight = (_weight); \
20407 + __napi->poll = &(_poll); \
20408 + __napi->weight = (_weight); \
20409 + netif_poll_disable(_netdev); \
20412 +#define netif_napi_add(_netdev, _napi, _poll, _weight) \
20414 + struct napi_struct *__napi = _napi; \
20415 + _netdev->poll = &(_poll); \
20416 + _netdev->weight = (_weight); \
20417 + __napi->poll = &(_poll); \
20418 + __napi->weight = (_weight); \
20422 +#undef dev_get_by_name
20423 +#define dev_get_by_name(_a, _b) dev_get_by_name(_b)
20424 +#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b)
20425 +#endif /* < 2.6.24 */
20427 +/*****************************************************************************/
20428 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) )
20429 +#include <linux/pm_qos_params.h>
20430 +#endif /* > 2.6.24 */
20432 +/*****************************************************************************/
20433 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) )
20434 +#define PM_QOS_CPU_DMA_LATENCY 1
20436 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) )
20437 +#include <linux/latency.h>
20438 +#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY
20439 +#define pm_qos_add_requirement(pm_qos_class, name, value) \
20440 + set_acceptable_latency(name, value)
20441 +#define pm_qos_remove_requirement(pm_qos_class, name) \
20442 + remove_acceptable_latency(name)
20443 +#define pm_qos_update_requirement(pm_qos_class, name, value) \
20444 + modify_acceptable_latency(name, value)
20446 +#define PM_QOS_DEFAULT_VALUE -1
20447 +#define pm_qos_add_requirement(pm_qos_class, name, value)
20448 +#define pm_qos_remove_requirement(pm_qos_class, name)
20449 +#define pm_qos_update_requirement(pm_qos_class, name, value) { \
20450 + if (value != PM_QOS_DEFAULT_VALUE) { \
20451 + printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \
20452 + pci_name(adapter->pdev)); \
20455 +#endif /* > 2.6.18 */
20457 +#endif /* < 2.6.25 */
20459 +/*****************************************************************************/
20460 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )
20461 +#endif /* < 2.6.26 */
20463 +/*****************************************************************************/
20464 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )
20465 +#ifndef pci_dma_mapping_error
20466 +#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr)
20468 +#endif /* < 2.6.27 */
20470 +#ifndef NETIF_F_MULTI_QUEUE
20471 +#define NETIF_F_MULTI_QUEUE 0
20472 +#define netif_is_multiqueue(a) 0
20473 +#define netif_stop_subqueue(a, b)
20474 +#define netif_wake_subqueue(a, b)
20475 +#define netif_start_subqueue(a, b)
20476 +#endif /* NETIF_F_MULTI_QUEUE */
20478 +#endif /* _KCOMPAT_H_ */
20479 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/Makefile linux-2.6.22-10/drivers/net/e1000e/Makefile
20480 --- linux-2.6.22-0/drivers/net/e1000e/Makefile 1970-01-01 01:00:00.000000000 +0100
20481 +++ linux-2.6.22-10/drivers/net/e1000e/Makefile 2008-11-10 00:06:14.000000000 +0100
20483 +################################################################################
20485 +# Intel PRO/1000 Linux driver
20486 +# Copyright(c) 1999 - 2008 Intel Corporation.
20488 +# This program is free software; you can redistribute it and/or modify it
20489 +# under the terms and conditions of the GNU General Public License,
20490 +# version 2, as published by the Free Software Foundation.
20492 +# This program is distributed in the hope it will be useful, but WITHOUT
20493 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20494 +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20497 +# You should have received a copy of the GNU General Public License along with
20498 +# this program; if not, write to the Free Software Foundation, Inc.,
20499 +# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20501 +# The full GNU General Public License is included in this distribution in
20502 +# the file called "COPYING".
20504 +# Contact Information:
20505 +# Linux NICS <linux.nics@intel.com>
20506 +# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20507 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20509 +################################################################################
20511 +obj-$(CONFIG_E1000E) := e1000e.o
20513 +e1000e-objs := e1000_82571.o e1000_ich8lan.o e1000_80003es2lan.o \
20514 + netdev.o ethtool.o param.o e1000_mac.o e1000_nvm.o \
20515 + e1000_phy.o e1000_manage.o kcompat.o
20516 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/netdev.c linux-2.6.22-10/drivers/net/e1000e/netdev.c
20517 --- linux-2.6.22-0/drivers/net/e1000e/netdev.c 1970-01-01 01:00:00.000000000 +0100
20518 +++ linux-2.6.22-10/drivers/net/e1000e/netdev.c 2008-10-14 01:51:32.000000000 +0200
20520 +/*******************************************************************************
20522 + Intel PRO/1000 Linux driver
20523 + Copyright(c) 1999 - 2008 Intel Corporation.
20525 + This program is free software; you can redistribute it and/or modify it
20526 + under the terms and conditions of the GNU General Public License,
20527 + version 2, as published by the Free Software Foundation.
20529 + This program is distributed in the hope it will be useful, but WITHOUT
20530 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20531 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20534 + You should have received a copy of the GNU General Public License along with
20535 + this program; if not, write to the Free Software Foundation, Inc.,
20536 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20538 + The full GNU General Public License is included in this distribution in
20539 + the file called "COPYING".
20541 + Contact Information:
20542 + Linux NICS <linux.nics@intel.com>
20543 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20544 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20546 +*******************************************************************************/
20548 +#include <linux/module.h>
20549 +#include <linux/types.h>
20550 +#include <linux/init.h>
20551 +#include <linux/pci.h>
20552 +#include <linux/vmalloc.h>
20553 +#include <linux/pagemap.h>
20554 +#include <linux/delay.h>
20555 +#include <linux/netdevice.h>
20556 +#include <linux/tcp.h>
20557 +#include <linux/ipv6.h>
20558 +#ifdef NETIF_F_TSO
20559 +#include <net/checksum.h>
20560 +#ifdef NETIF_F_TSO6
20561 +#include <net/ip6_checksum.h>
20564 +#include <linux/mii.h>
20565 +#include <linux/ethtool.h>
20566 +#include <linux/if_vlan.h>
20568 +#include "e1000.h"
20570 +#ifdef CONFIG_E1000E_NAPI
20571 +#define DRV_NAPI "-NAPI"
20578 +#define DRV_VERSION "0.4.1.12" DRV_NAPI DRV_DEBUG
20579 +char e1000e_driver_name[] = "e1000e";
20580 +const char e1000e_driver_version[] = DRV_VERSION;
20582 +static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
20584 + struct e1000_hw *hw = &adapter->hw;
20585 + static int global_quad_port_a; /* global port a indication */
20586 + struct pci_dev *pdev = adapter->pdev;
20587 + u16 eeprom_data = 0;
20588 + int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
20590 + /* tag quad port adapters first, it's used below */
20591 + switch (pdev->device) {
20592 + case E1000_DEV_ID_82571EB_QUAD_COPPER:
20593 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
20594 + case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
20595 + case E1000_DEV_ID_82571PT_QUAD_COPPER:
20596 + adapter->flags |= FLAG_IS_QUAD_PORT;
20597 + /* mark the first port */
20598 + if (global_quad_port_a == 0)
20599 + adapter->flags |= FLAG_IS_QUAD_PORT_A;
20600 + /* Reset for multiple quad port adapters */
20601 + global_quad_port_a++;
20602 + if (global_quad_port_a == 4)
20603 + global_quad_port_a = 0;
20609 + switch (adapter->hw.mac.type) {
20610 + case e1000_82571:
20611 + /* these dual ports don't have WoL on port B at all */
20612 + if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
20613 + (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
20614 + (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
20616 + adapter->flags &= ~FLAG_HAS_WOL;
20617 + /* quad ports only support WoL on port A */
20618 + if (adapter->flags & FLAG_IS_QUAD_PORT &&
20619 + (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
20620 + adapter->flags &= ~FLAG_HAS_WOL;
20621 + /* Does not support WoL on any port */
20622 + if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
20623 + adapter->flags &= ~FLAG_HAS_WOL;
20626 + case e1000_82573:
20627 + if (pdev->device == E1000_DEV_ID_82573L) {
20628 + adapter->hw.nvm.ops.read(&adapter->hw, NVM_INIT_3GIO_3,
20629 + 1, &eeprom_data);
20630 + if (!(eeprom_data & NVM_WORD1A_ASPM_MASK))
20631 + adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
20642 +static struct e1000_info e1000_82571_info = {
20643 + .mac = e1000_82571,
20644 + .flags = FLAG_HAS_HW_VLAN_FILTER
20645 + | FLAG_HAS_JUMBO_FRAMES
20647 + | FLAG_APME_IN_CTRL3
20648 + | FLAG_RX_CSUM_ENABLED
20649 + | FLAG_HAS_CTRLEXT_ON_LOAD
20650 + | FLAG_HAS_SMART_POWER_DOWN
20651 + | FLAG_RESET_OVERWRITES_LAA /* errata */
20652 + | FLAG_TARC_SPEED_MODE_BIT /* errata */
20653 + | FLAG_APME_CHECK_PORT_B,
20655 + .init_ops = e1000_init_function_pointers_82571,
20656 + .get_variants = e1000_get_variants_82571,
20659 +static struct e1000_info e1000_82572_info = {
20660 + .mac = e1000_82572,
20661 + .flags = FLAG_HAS_HW_VLAN_FILTER
20662 + | FLAG_HAS_JUMBO_FRAMES
20664 + | FLAG_APME_IN_CTRL3
20665 + | FLAG_RX_CSUM_ENABLED
20666 + | FLAG_HAS_CTRLEXT_ON_LOAD
20667 + | FLAG_TARC_SPEED_MODE_BIT, /* errata */
20669 + .init_ops = e1000_init_function_pointers_82571,
20670 + .get_variants = e1000_get_variants_82571,
20673 +static struct e1000_info e1000_82573_info = {
20674 + .mac = e1000_82573,
20675 + .flags = FLAG_HAS_HW_VLAN_FILTER
20677 + | FLAG_APME_IN_CTRL3
20678 + | FLAG_RX_CSUM_ENABLED
20679 + | FLAG_HAS_SMART_POWER_DOWN
20683 + | FLAG_HAS_SWSM_ON_LOAD,
20685 + .init_ops = e1000_init_function_pointers_82571,
20686 + .get_variants = e1000_get_variants_82571,
20689 +static struct e1000_info e1000_82574_info = {
20690 + .mac = e1000_82574,
20691 + .flags = FLAG_HAS_HW_VLAN_FILTER
20692 +#ifdef CONFIG_E1000E_MSIX
20695 + | FLAG_HAS_JUMBO_FRAMES
20697 + | FLAG_APME_IN_CTRL3
20698 + | FLAG_RX_CSUM_ENABLED
20699 + | FLAG_HAS_SMART_POWER_DOWN
20702 + | FLAG_HAS_CTRLEXT_ON_LOAD,
20704 + .init_ops = e1000_init_function_pointers_82571,
20705 + .get_variants = e1000_get_variants_82571,
20708 +static struct e1000_info e1000_es2_info = {
20709 + .mac = e1000_80003es2lan,
20710 + .flags = FLAG_HAS_HW_VLAN_FILTER
20711 + | FLAG_HAS_JUMBO_FRAMES
20713 + | FLAG_APME_IN_CTRL3
20714 + | FLAG_RX_CSUM_ENABLED
20715 + | FLAG_HAS_CTRLEXT_ON_LOAD
20716 + | FLAG_RX_NEEDS_RESTART /* errata */
20717 + | FLAG_TARC_SET_BIT_ZERO /* errata */
20718 + | FLAG_APME_CHECK_PORT_B
20719 + | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
20720 + | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
20722 + .init_ops = e1000_init_function_pointers_80003es2lan,
20723 + .get_variants = NULL,
20726 +static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
20728 + if (adapter->hw.phy.type == e1000_phy_ife)
20729 + adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
20731 + if ((adapter->hw.mac.type == e1000_ich8lan) &&
20732 + (adapter->hw.phy.type == e1000_phy_igp_3))
20733 + adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
20738 +static struct e1000_info e1000_ich8_info = {
20739 + .mac = e1000_ich8lan,
20740 + .flags = FLAG_HAS_WOL
20742 + | FLAG_RX_CSUM_ENABLED
20743 + | FLAG_HAS_CTRLEXT_ON_LOAD
20746 + | FLAG_APME_IN_WUC,
20748 + .init_ops = e1000_init_function_pointers_ich8lan,
20749 + .get_variants = e1000_get_variants_ich8lan,
20752 +static struct e1000_info e1000_ich9_info = {
20753 + .mac = e1000_ich9lan,
20754 + .flags = FLAG_HAS_JUMBO_FRAMES
20757 + | FLAG_RX_CSUM_ENABLED
20758 + | FLAG_HAS_CTRLEXT_ON_LOAD
20762 + | FLAG_APME_IN_WUC,
20764 + .init_ops = e1000_init_function_pointers_ich8lan,
20765 + .get_variants = e1000_get_variants_ich8lan,
20768 +static struct e1000_info e1000_ich10_info = {
20769 + .mac = e1000_ich10lan,
20770 + .flags = FLAG_HAS_JUMBO_FRAMES
20773 + | FLAG_RX_CSUM_ENABLED
20774 + | FLAG_HAS_CTRLEXT_ON_LOAD
20778 + | FLAG_APME_IN_WUC,
20780 + .init_ops = e1000_init_function_pointers_ich8lan,
20781 + .get_variants = e1000_get_variants_ich8lan,
20784 +static const struct e1000_info *e1000_info_tbl[] = {
20785 + [board_82571] = &e1000_82571_info,
20786 + [board_82572] = &e1000_82572_info,
20787 + [board_82573] = &e1000_82573_info,
20788 + [board_82574] = &e1000_82574_info,
20789 + [board_80003es2lan] = &e1000_es2_info,
20790 + [board_ich8lan] = &e1000_ich8_info,
20791 + [board_ich9lan] = &e1000_ich9_info,
20792 + [board_ich10lan] = &e1000_ich10_info,
20796 +void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
20798 + struct e1000_adapter *adapter = hw->back;
20800 + pci_read_config_word(adapter->pdev, reg, value);
20803 +s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
20805 + struct e1000_adapter *adapter = hw->back;
20808 + cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
20810 + return -E1000_ERR_CONFIG;
20812 + pci_read_config_word(adapter->pdev, cap_offset + reg, value);
20814 + return E1000_SUCCESS;
20817 +s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size)
20819 + hw->dev_spec = kzalloc(size, GFP_KERNEL);
20821 + if (!hw->dev_spec)
20824 + return E1000_SUCCESS;
20827 +void e1000_free_dev_spec_struct(struct e1000_hw *hw)
20829 + if (!hw->dev_spec)
20832 + kfree(hw->dev_spec);
20836 + * e1000_desc_unused - calculate if we have unused descriptors
20838 +static int e1000_desc_unused(struct e1000_ring *ring)
20840 + if (ring->next_to_clean > ring->next_to_use)
20841 + return ring->next_to_clean - ring->next_to_use - 1;
20843 + return ring->count + ring->next_to_clean - ring->next_to_use - 1;
20847 + * e1000_receive_skb - helper function to handle Rx indications
20848 + * @adapter: board private structure
20849 + * @status: descriptor status field as written by hardware
20850 + * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
20851 + * @skb: pointer to sk_buff to be indicated to stack
20853 +static void e1000_receive_skb(struct e1000_adapter *adapter,
20854 + struct net_device *netdev,
20855 + struct sk_buff *skb,
20856 + u8 status, u16 vlan)
20858 + skb->protocol = eth_type_trans(skb, netdev);
20860 +#ifdef CONFIG_E1000E_NAPI
20861 + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
20862 + vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
20863 + le16_to_cpu(vlan) &
20864 + E1000_RXD_SPC_VLAN_MASK);
20866 + netif_receive_skb(skb);
20868 + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
20869 + vlan_hwaccel_rx(skb, adapter->vlgrp,
20870 + le16_to_cpu(vlan) & E1000_RXD_SPC_VLAN_MASK);
20875 + netdev->last_rx = jiffies;
20879 + * e1000_rx_checksum - Receive Checksum Offload for 82543
20880 + * @adapter: board private structure
20881 + * @status_err: receive descriptor status and error fields
20882 + * @csum: receive descriptor csum field
20883 + * @sk_buff: socket buffer with received data
20885 +static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
20886 + u32 csum, struct sk_buff *skb)
20888 + u16 status = (u16)status_err;
20889 + u8 errors = (u8)(status_err >> 24);
20890 + skb->ip_summed = CHECKSUM_NONE;
20892 + /* Ignore Checksum bit is set */
20893 + if (status & E1000_RXD_STAT_IXSM)
20895 + /* TCP/UDP checksum error bit is set */
20896 + if (errors & E1000_RXD_ERR_TCPE) {
20897 + /* let the stack verify checksum errors */
20898 + adapter->hw_csum_err++;
20902 + /* TCP/UDP Checksum has not been calculated */
20903 + if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
20906 + /* It must be a TCP or UDP packet with a valid checksum */
20907 + if (status & E1000_RXD_STAT_TCPCS) {
20908 + /* TCP checksum is good */
20909 + skb->ip_summed = CHECKSUM_UNNECESSARY;
20912 + * IP fragment with UDP payload
20913 + * Hardware complements the payload checksum, so we undo it
20914 + * and then put the value in host order for further stack use.
20916 + csum = ntohl(csum ^ 0xFFFF);
20917 + skb->csum = csum;
20918 + skb->ip_summed = CHECKSUM_COMPLETE;
20920 + adapter->hw_csum_good++;
20924 + * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
20925 + * @adapter: address of board private structure
20927 +static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
20928 + int cleaned_count)
20930 + struct net_device *netdev = adapter->netdev;
20931 + struct pci_dev *pdev = adapter->pdev;
20932 + struct e1000_ring *rx_ring = adapter->rx_ring;
20933 + struct e1000_rx_desc *rx_desc;
20934 + struct e1000_buffer *buffer_info;
20935 + struct sk_buff *skb;
20937 + unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
20939 + i = rx_ring->next_to_use;
20940 + buffer_info = &rx_ring->buffer_info[i];
20942 + while (cleaned_count--) {
20943 + skb = buffer_info->skb;
20945 + skb_trim(skb, 0);
20949 + skb = netdev_alloc_skb(netdev, bufsz);
20951 + /* Better luck next round */
20952 + adapter->alloc_rx_buff_failed++;
20957 + * Make buffer alignment 2 beyond a 16 byte boundary
20958 + * this will result in a 16 byte aligned IP header after
20959 + * the 14 byte MAC header is removed
20961 + skb_reserve(skb, NET_IP_ALIGN);
20963 + buffer_info->skb = skb;
20965 + buffer_info->dma = pci_map_single(pdev, skb->data,
20966 + adapter->rx_buffer_len,
20967 + PCI_DMA_FROMDEVICE);
20968 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
20969 + dev_err(&pdev->dev, "RX DMA map failed\n");
20970 + adapter->rx_dma_failed++;
20974 + rx_desc = E1000_RX_DESC(*rx_ring, i);
20975 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
20978 + if (i == rx_ring->count)
20980 + buffer_info = &rx_ring->buffer_info[i];
20983 + if (rx_ring->next_to_use != i) {
20984 + rx_ring->next_to_use = i;
20986 + i = (rx_ring->count - 1);
20989 + * Force memory writes to complete before letting h/w
20990 + * know there are new descriptors to fetch. (Only
20991 + * applicable for weak-ordered memory model archs,
20992 + * such as IA-64).
20995 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
21000 + * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
21001 + * @adapter: address of board private structure
21003 +static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
21004 + int cleaned_count)
21006 + struct net_device *netdev = adapter->netdev;
21007 + struct pci_dev *pdev = adapter->pdev;
21008 + union e1000_rx_desc_packet_split *rx_desc;
21009 + struct e1000_ring *rx_ring = adapter->rx_ring;
21010 + struct e1000_buffer *buffer_info;
21011 + struct e1000_ps_page *ps_page;
21012 + struct sk_buff *skb;
21013 + unsigned int i, j;
21015 + i = rx_ring->next_to_use;
21016 + buffer_info = &rx_ring->buffer_info[i];
21018 + while (cleaned_count--) {
21019 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
21021 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
21022 + ps_page = &buffer_info->ps_pages[j];
21023 + if (j >= adapter->rx_ps_pages) {
21024 + /* all unused desc entries get hw null ptr */
21025 + rx_desc->read.buffer_addr[j+1] = ~0;
21028 + if (!ps_page->page) {
21029 + ps_page->page = alloc_page(GFP_ATOMIC);
21030 + if (!ps_page->page) {
21031 + adapter->alloc_rx_buff_failed++;
21034 + ps_page->dma = pci_map_page(pdev,
21037 + PCI_DMA_FROMDEVICE);
21038 + if (pci_dma_mapping_error(pdev, ps_page->dma)) {
21039 + dev_err(&adapter->pdev->dev,
21040 + "RX DMA page map failed\n");
21041 + adapter->rx_dma_failed++;
21046 + * Refresh the desc even if buffer_addrs
21047 + * didn't change because each write-back
21048 + * erases this info.
21050 + rx_desc->read.buffer_addr[j+1] =
21051 + cpu_to_le64(ps_page->dma);
21054 + skb = netdev_alloc_skb(netdev,
21055 + adapter->rx_ps_bsize0 + NET_IP_ALIGN);
21058 + adapter->alloc_rx_buff_failed++;
21063 + * Make buffer alignment 2 beyond a 16 byte boundary
21064 + * this will result in a 16 byte aligned IP header after
21065 + * the 14 byte MAC header is removed
21067 + skb_reserve(skb, NET_IP_ALIGN);
21069 + buffer_info->skb = skb;
21070 + buffer_info->dma = pci_map_single(pdev, skb->data,
21071 + adapter->rx_ps_bsize0,
21072 + PCI_DMA_FROMDEVICE);
21073 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
21074 + dev_err(&pdev->dev, "RX DMA map failed\n");
21075 + adapter->rx_dma_failed++;
21076 + /* cleanup skb */
21077 + dev_kfree_skb_any(skb);
21078 + buffer_info->skb = NULL;
21082 + rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
21085 + if (i == rx_ring->count)
21087 + buffer_info = &rx_ring->buffer_info[i];
21091 + if (rx_ring->next_to_use != i) {
21092 + rx_ring->next_to_use = i;
21095 + i = (rx_ring->count - 1);
21098 + * Force memory writes to complete before letting h/w
21099 + * know there are new descriptors to fetch. (Only
21100 + * applicable for weak-ordered memory model archs,
21101 + * such as IA-64).
21105 + * Hardware increments by 16 bytes, but packet split
21106 + * descriptors are 32 bytes...so we increment tail
21109 + writel(i<<1, adapter->hw.hw_addr + rx_ring->tail);
21113 +#ifdef CONFIG_E1000E_NAPI
21115 + * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
21116 + * @adapter: address of board private structure
21117 + * @rx_ring: pointer to receive ring structure
21118 + * @cleaned_count: number of buffers to allocate this pass
21121 +static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
21122 + int cleaned_count)
21124 + struct net_device *netdev = adapter->netdev;
21125 + struct pci_dev *pdev = adapter->pdev;
21126 + struct e1000_rx_desc *rx_desc;
21127 + struct e1000_ring *rx_ring = adapter->rx_ring;
21128 + struct e1000_buffer *buffer_info;
21129 + struct sk_buff *skb;
21131 + unsigned int bufsz = 256 -
21132 + 16 /* for skb_reserve */ -
21135 + i = rx_ring->next_to_use;
21136 + buffer_info = &rx_ring->buffer_info[i];
21138 + while (cleaned_count--) {
21139 + skb = buffer_info->skb;
21141 + skb_trim(skb, 0);
21145 + skb = netdev_alloc_skb(netdev, bufsz);
21146 + if (unlikely(!skb)) {
21147 + /* Better luck next round */
21148 + adapter->alloc_rx_buff_failed++;
21152 + /* Make buffer alignment 2 beyond a 16 byte boundary
21153 + * this will result in a 16 byte aligned IP header after
21154 + * the 14 byte MAC header is removed
21156 + skb_reserve(skb, NET_IP_ALIGN);
21158 + buffer_info->skb = skb;
21160 + /* allocate a new page if necessary */
21161 + if (!buffer_info->page) {
21162 + buffer_info->page = alloc_page(GFP_ATOMIC);
21163 + if (unlikely(!buffer_info->page)) {
21164 + adapter->alloc_rx_buff_failed++;
21169 + if (!buffer_info->dma)
21170 + buffer_info->dma = pci_map_page(pdev,
21171 + buffer_info->page, 0,
21173 + PCI_DMA_FROMDEVICE);
21175 + rx_desc = E1000_RX_DESC(*rx_ring, i);
21176 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
21178 + if (unlikely(++i == rx_ring->count))
21180 + buffer_info = &rx_ring->buffer_info[i];
21183 + if (likely(rx_ring->next_to_use != i)) {
21184 + rx_ring->next_to_use = i;
21185 + if (unlikely(i-- == 0))
21186 + i = (rx_ring->count - 1);
21188 + /* Force memory writes to complete before letting h/w
21189 + * know there are new descriptors to fetch. (Only
21190 + * applicable for weak-ordered memory model archs,
21191 + * such as IA-64). */
21193 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
21196 +#endif /* CONFIG_E1000E_NAPI */
21199 + * e1000_clean_rx_irq - Send received data up the network stack; legacy
21200 + * @adapter: board private structure
21202 + * the return value indicates whether actual cleaning was done, there
21203 + * is no guarantee that everything was cleaned
21205 +#ifdef CONFIG_E1000E_NAPI
21206 +static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
21207 + int *work_done, int work_to_do)
21209 +static bool e1000_clean_rx_irq(struct e1000_adapter *adapter)
21212 + struct net_device *netdev = adapter->netdev;
21213 + struct pci_dev *pdev = adapter->pdev;
21214 + struct e1000_ring *rx_ring = adapter->rx_ring;
21215 + struct e1000_rx_desc *rx_desc, *next_rxd;
21216 + struct e1000_buffer *buffer_info, *next_buffer;
21219 + int cleaned_count = 0;
21220 + bool cleaned = 0;
21221 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
21223 + i = rx_ring->next_to_clean;
21224 + rx_desc = E1000_RX_DESC(*rx_ring, i);
21225 + buffer_info = &rx_ring->buffer_info[i];
21227 + while (rx_desc->status & E1000_RXD_STAT_DD) {
21228 + struct sk_buff *skb;
21231 +#ifdef CONFIG_E1000E_NAPI
21232 + if (*work_done >= work_to_do)
21237 + status = rx_desc->status;
21238 + skb = buffer_info->skb;
21239 + buffer_info->skb = NULL;
21241 + prefetch(skb->data - NET_IP_ALIGN);
21244 + if (i == rx_ring->count)
21246 + next_rxd = E1000_RX_DESC(*rx_ring, i);
21247 + prefetch(next_rxd);
21249 + next_buffer = &rx_ring->buffer_info[i];
21253 + pci_unmap_single(pdev,
21254 + buffer_info->dma,
21255 + adapter->rx_buffer_len,
21256 + PCI_DMA_FROMDEVICE);
21257 + buffer_info->dma = 0;
21259 + length = le16_to_cpu(rx_desc->length);
21261 + /* !EOP means multiple descriptors were used to store a single
21262 + * packet, also make sure the frame isn't just CRC only */
21263 + if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) {
21264 + /* All receives must fit into a single buffer */
21265 + e_dbg("Receive packet consumed multiple buffers\n");
21267 + buffer_info->skb = skb;
21271 + if (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
21273 + buffer_info->skb = skb;
21277 + total_rx_bytes += length;
21278 + total_rx_packets++;
21281 + * code added for copybreak, this should improve
21282 + * performance for small packets with large amounts
21283 + * of reassembly being done in the stack
21285 + if (length < copybreak) {
21286 + struct sk_buff *new_skb =
21287 + netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
21289 + skb_reserve(new_skb, NET_IP_ALIGN);
21290 + skb_copy_to_linear_data_offset(new_skb,
21296 + /* save the skb in buffer_info as good */
21297 + buffer_info->skb = skb;
21300 + /* else just continue with the old one */
21302 + /* end copybreak code */
21303 + skb_put(skb, length);
21305 + /* Receive Checksum Offload */
21306 + e1000_rx_checksum(adapter,
21308 + ((u32)(rx_desc->errors) << 24),
21309 + le16_to_cpu(rx_desc->csum), skb);
21311 + e1000_receive_skb(adapter, netdev, skb,status,rx_desc->special);
21314 + rx_desc->status = 0;
21316 + /* return some buffers to hardware, one at a time is too slow */
21317 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
21318 + adapter->alloc_rx_buf(adapter, cleaned_count);
21319 + cleaned_count = 0;
21322 + /* use prefetched values */
21323 + rx_desc = next_rxd;
21324 + buffer_info = next_buffer;
21326 + rx_ring->next_to_clean = i;
21328 + cleaned_count = e1000_desc_unused(rx_ring);
21329 + if (cleaned_count)
21330 + adapter->alloc_rx_buf(adapter, cleaned_count);
21332 + adapter->total_rx_packets += total_rx_packets;
21333 + adapter->total_rx_bytes += total_rx_bytes;
21334 + adapter->net_stats.rx_bytes += total_rx_bytes;
21335 + adapter->net_stats.rx_packets += total_rx_packets;
21339 +static void e1000_put_txbuf(struct e1000_adapter *adapter,
21340 + struct e1000_buffer *buffer_info)
21342 + if (buffer_info->dma) {
21343 + pci_unmap_page(adapter->pdev, buffer_info->dma,
21344 + buffer_info->length, PCI_DMA_TODEVICE);
21345 + buffer_info->dma = 0;
21347 + if (buffer_info->skb) {
21348 + dev_kfree_skb_any(buffer_info->skb);
21349 + buffer_info->skb = NULL;
21353 +static void e1000_print_tx_hang(struct e1000_adapter *adapter)
21355 + struct e1000_ring *tx_ring = adapter->tx_ring;
21356 + unsigned int i = tx_ring->next_to_clean;
21357 + unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
21358 + struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
21360 + /* detected Tx unit hang */
21361 + e_err("Detected Tx Unit Hang:\n"
21364 + " next_to_use <%x>\n"
21365 + " next_to_clean <%x>\n"
21366 + "buffer_info[next_to_clean]:\n"
21367 + " time_stamp <%lx>\n"
21368 + " next_to_watch <%x>\n"
21369 + " jiffies <%lx>\n"
21370 + " next_to_watch.status <%x>\n",
21371 + readl(adapter->hw.hw_addr + tx_ring->head),
21372 + readl(adapter->hw.hw_addr + tx_ring->tail),
21373 + tx_ring->next_to_use,
21374 + tx_ring->next_to_clean,
21375 + tx_ring->buffer_info[eop].time_stamp,
21378 + eop_desc->upper.fields.status);
21382 + * @e1000_alloc_ring - allocate memory for a ring structure
21384 +static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
21385 + struct e1000_ring *ring)
21387 + struct pci_dev *pdev = adapter->pdev;
21389 + ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
21398 + * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
21399 + * @adapter: board private structure
21401 + * Return 0 on success, negative on failure
21403 +int e1000_setup_tx_resources(struct e1000_adapter *adapter)
21405 + struct e1000_ring *tx_ring = adapter->tx_ring;
21406 + int err = -ENOMEM, size;
21408 + size = sizeof(struct e1000_buffer) * tx_ring->count;
21409 + tx_ring->buffer_info = vmalloc(size);
21410 + if (!tx_ring->buffer_info)
21412 + memset(tx_ring->buffer_info, 0, size);
21414 + /* round up to nearest 4K */
21415 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
21416 + tx_ring->size = ALIGN(tx_ring->size, 4096);
21418 + err = e1000_alloc_ring_dma(adapter, tx_ring);
21422 + tx_ring->next_to_use = 0;
21423 + tx_ring->next_to_clean = 0;
21424 + spin_lock_init(&adapter->tx_queue_lock);
21428 + vfree(tx_ring->buffer_info);
21429 + e_err("Unable to allocate memory for the transmit descriptor ring\n");
21434 + * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
21435 + * @adapter: board private structure
21437 + * Returns 0 on success, negative on failure
21439 +int e1000_setup_rx_resources(struct e1000_adapter *adapter)
21441 + struct e1000_ring *rx_ring = adapter->rx_ring;
21442 + struct e1000_buffer *buffer_info;
21443 + int i, size, desc_len, err = -ENOMEM;
21445 + size = sizeof(struct e1000_buffer) * rx_ring->count;
21446 + rx_ring->buffer_info = vmalloc(size);
21447 + if (!rx_ring->buffer_info)
21449 + memset(rx_ring->buffer_info, 0, size);
21451 + for (i = 0; i < rx_ring->count; i++) {
21452 + buffer_info = &rx_ring->buffer_info[i];
21453 + buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
21454 + sizeof(struct e1000_ps_page),
21456 + if (!buffer_info->ps_pages)
21460 + desc_len = sizeof(union e1000_rx_desc_packet_split);
21462 + /* Round up to nearest 4K */
21463 + rx_ring->size = rx_ring->count * desc_len;
21464 + rx_ring->size = ALIGN(rx_ring->size, 4096);
21466 + err = e1000_alloc_ring_dma(adapter, rx_ring);
21470 + rx_ring->next_to_clean = 0;
21471 + rx_ring->next_to_use = 0;
21472 + rx_ring->rx_skb_top = NULL;
21477 + for (i = 0; i < rx_ring->count; i++) {
21478 + buffer_info = &rx_ring->buffer_info[i];
21479 + kfree(buffer_info->ps_pages);
21482 + vfree(rx_ring->buffer_info);
21483 + e_err("Unable to allocate memory for the transmit descriptor ring\n");
21488 + * e1000_clean_tx_ring - Free Tx Buffers
21489 + * @adapter: board private structure
21491 +static void e1000_clean_tx_ring(struct e1000_adapter *adapter)
21493 + struct e1000_ring *tx_ring = adapter->tx_ring;
21494 + struct e1000_buffer *buffer_info;
21495 + unsigned long size;
21498 + for (i = 0; i < tx_ring->count; i++) {
21499 + buffer_info = &tx_ring->buffer_info[i];
21500 + e1000_put_txbuf(adapter, buffer_info);
21503 + size = sizeof(struct e1000_buffer) * tx_ring->count;
21504 + memset(tx_ring->buffer_info, 0, size);
21506 + memset(tx_ring->desc, 0, tx_ring->size);
21508 + tx_ring->next_to_use = 0;
21509 + tx_ring->next_to_clean = 0;
21511 + writel(0, adapter->hw.hw_addr + tx_ring->head);
21512 + writel(0, adapter->hw.hw_addr + tx_ring->tail);
21516 + * e1000_free_tx_resources - Free Tx Resources per Queue
21517 + * @adapter: board private structure
21519 + * Free all transmit software resources
21521 +void e1000_free_tx_resources(struct e1000_adapter *adapter)
21523 + struct pci_dev *pdev = adapter->pdev;
21524 + struct e1000_ring *tx_ring = adapter->tx_ring;
21526 + e1000_clean_tx_ring(adapter);
21528 + vfree(tx_ring->buffer_info);
21529 + tx_ring->buffer_info = NULL;
21531 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
21533 + tx_ring->desc = NULL;
21537 + * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
21538 + * @adapter: board private structure
21540 + * the return value indicates whether actual cleaning was done, there
21541 + * is no guarantee that everything was cleaned
21543 +#ifdef CONFIG_E1000E_NAPI
21544 +static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
21545 + int *work_done, int work_to_do)
21547 +static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
21550 + union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
21551 + struct net_device *netdev = adapter->netdev;
21552 + struct pci_dev *pdev = adapter->pdev;
21553 + struct e1000_ring *rx_ring = adapter->rx_ring;
21554 + struct e1000_buffer *buffer_info, *next_buffer;
21555 + struct e1000_ps_page *ps_page;
21556 + struct sk_buff *skb;
21557 + unsigned int i, j;
21558 + u32 length, staterr;
21559 + int cleaned_count = 0;
21560 + bool cleaned = 0;
21561 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
21563 + i = rx_ring->next_to_clean;
21564 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
21565 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
21566 + buffer_info = &rx_ring->buffer_info[i];
21568 + while (staterr & E1000_RXD_STAT_DD) {
21569 +#ifdef CONFIG_E1000E_NAPI
21570 + if (*work_done >= work_to_do)
21574 + skb = buffer_info->skb;
21576 + /* in the packet split case this is header only */
21577 + prefetch(skb->data - NET_IP_ALIGN);
21580 + if (i == rx_ring->count)
21582 + next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
21583 + prefetch(next_rxd);
21585 + next_buffer = &rx_ring->buffer_info[i];
21589 + pci_unmap_single(pdev, buffer_info->dma,
21590 + adapter->rx_ps_bsize0,
21591 + PCI_DMA_FROMDEVICE);
21592 + buffer_info->dma = 0;
21594 + if (!(staterr & E1000_RXD_STAT_EOP)) {
21595 + e_dbg("Packet Split buffers didn't pick up the full"
21597 + dev_kfree_skb_irq(skb);
21601 + if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
21602 + dev_kfree_skb_irq(skb);
21606 + length = le16_to_cpu(rx_desc->wb.middle.length0);
21609 + e_dbg("Last part of the packet spanning multiple"
21610 + " descriptors\n");
21611 + dev_kfree_skb_irq(skb);
21615 + /* Good Receive */
21616 + skb_put(skb, length);
21618 +#ifdef CONFIG_E1000E_NAPI
21621 + * this looks ugly, but it seems compiler issues make it
21622 + * more efficient than reusing j
21624 + int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
21627 + * page alloc/put takes too long and effects small packet
21628 + * throughput, so unsplit small packets and save the alloc/put
21629 + * only valid in softirq (napi) context to call kmap_*
21631 + if (l1 && (l1 <= copybreak) &&
21632 + ((length + l1) <= adapter->rx_ps_bsize0)) {
21635 + ps_page = &buffer_info->ps_pages[0];
21638 + * there is no documentation about how to call
21639 + * kmap_atomic, so we can't hold the mapping
21642 + pci_dma_sync_single_for_cpu(pdev, ps_page->dma,
21643 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
21644 + vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
21645 + memcpy(skb_tail_pointer(skb), vaddr, l1);
21646 + kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
21647 + pci_dma_sync_single_for_device(pdev, ps_page->dma,
21648 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
21650 + skb_put(skb, l1);
21656 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
21657 + length = le16_to_cpu(rx_desc->wb.upper.length[j]);
21661 + ps_page = &buffer_info->ps_pages[j];
21662 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
21663 + PCI_DMA_FROMDEVICE);
21664 + ps_page->dma = 0;
21665 + skb_fill_page_desc(skb, j, ps_page->page, 0, length);
21666 + ps_page->page = NULL;
21667 + skb->len += length;
21668 + skb->data_len += length;
21669 + skb->truesize += length;
21672 +#ifdef CONFIG_E1000E_NAPI
21675 + total_rx_bytes += skb->len;
21676 + total_rx_packets++;
21678 + e1000_rx_checksum(adapter, staterr, le16_to_cpu(
21679 + rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
21681 + if (rx_desc->wb.upper.header_status &
21682 + cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
21683 + adapter->rx_hdr_split++;
21685 + e1000_receive_skb(adapter, netdev, skb,
21686 + staterr, rx_desc->wb.middle.vlan);
21689 + rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
21690 + buffer_info->skb = NULL;
21692 + /* return some buffers to hardware, one at a time is too slow */
21693 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
21694 + adapter->alloc_rx_buf(adapter, cleaned_count);
21695 + cleaned_count = 0;
21698 + /* use prefetched values */
21699 + rx_desc = next_rxd;
21700 + buffer_info = next_buffer;
21702 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
21704 + rx_ring->next_to_clean = i;
21706 + cleaned_count = e1000_desc_unused(rx_ring);
21707 + if (cleaned_count)
21708 + adapter->alloc_rx_buf(adapter, cleaned_count);
21710 + adapter->total_rx_packets += total_rx_packets;
21711 + adapter->total_rx_bytes += total_rx_bytes;
21712 + adapter->net_stats.rx_bytes += total_rx_bytes;
21713 + adapter->net_stats.rx_packets += total_rx_packets;
21717 +#ifdef CONFIG_E1000E_NAPI
21718 +/* NOTE: these new jumbo frame routines rely on NAPI because of the
21719 + * pskb_may_pull call, which eventually must call kmap_atomic which you cannot
21720 + * call from hard irq context */
21723 + * e1000_consume_page - helper function
21725 +static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
21729 + skb->len += length;
21730 + skb->data_len += length;
21731 + skb->truesize += length;
21735 + * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
21736 + * @adapter: board private structure
21738 + * the return value indicates whether actual cleaning was done, there
21739 + * is no guarantee that everything was cleaned
21742 +static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
21743 + int *work_done, int work_to_do)
21745 + struct net_device *netdev = adapter->netdev;
21746 + struct pci_dev *pdev = adapter->pdev;
21747 + struct e1000_ring *rx_ring = adapter->rx_ring;
21748 + struct e1000_rx_desc *rx_desc, *next_rxd;
21749 + struct e1000_buffer *buffer_info, *next_buffer;
21752 + int cleaned_count = 0;
21753 + bool cleaned = FALSE;
21754 + unsigned int total_rx_bytes=0, total_rx_packets=0;
21756 + i = rx_ring->next_to_clean;
21757 + rx_desc = E1000_RX_DESC(*rx_ring, i);
21758 + buffer_info = &rx_ring->buffer_info[i];
21760 + while (rx_desc->status & E1000_RXD_STAT_DD) {
21761 + struct sk_buff *skb;
21764 + if (*work_done >= work_to_do)
21768 + status = rx_desc->status;
21769 + skb = buffer_info->skb;
21770 + buffer_info->skb = NULL;
21773 + if (i == rx_ring->count)
21775 + next_rxd = E1000_RX_DESC(*rx_ring, i);
21776 + prefetch(next_rxd);
21778 + next_buffer = &rx_ring->buffer_info[i];
21782 + pci_unmap_page(pdev, buffer_info->dma, PAGE_SIZE,
21783 + PCI_DMA_FROMDEVICE);
21784 + buffer_info->dma = 0;
21786 + length = le16_to_cpu(rx_desc->length);
21788 + /* errors is only valid for DD + EOP descriptors */
21789 + if (unlikely((status & E1000_RXD_STAT_EOP) &&
21790 + (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK))) {
21791 + /* recycle both page and skb */
21792 + buffer_info->skb = skb;
21793 + /* an error means any chain goes out the window
21795 + if (rx_ring->rx_skb_top)
21796 + dev_kfree_skb(rx_ring->rx_skb_top);
21797 + rx_ring->rx_skb_top = NULL;
21801 +#define rxtop rx_ring->rx_skb_top
21802 + if (!(status & E1000_RXD_STAT_EOP)) {
21803 + /* this descriptor is only the beginning (or middle) */
21805 + /* this is the beginning of a chain */
21807 + skb_fill_page_desc(rxtop, 0, buffer_info->page,
21810 + /* this is the middle of a chain */
21811 + skb_fill_page_desc(rxtop,
21812 + skb_shinfo(rxtop)->nr_frags,
21813 + buffer_info->page, 0, length);
21814 + /* re-use the skb, only consumed the page */
21815 + buffer_info->skb = skb;
21817 + e1000_consume_page(buffer_info, rxtop, length);
21821 + /* end of the chain */
21822 + skb_fill_page_desc(rxtop,
21823 + skb_shinfo(rxtop)->nr_frags,
21824 + buffer_info->page, 0, length);
21825 + /* re-use the current skb, we only consumed the
21827 + buffer_info->skb = skb;
21830 + e1000_consume_page(buffer_info, skb, length);
21832 + /* no chain, got EOP, this buf is the packet
21833 + * copybreak to save the put_page/alloc_page */
21834 + if (length <= copybreak &&
21835 + skb_tailroom(skb) >= length) {
21837 + vaddr = kmap_atomic(buffer_info->page,
21838 + KM_SKB_DATA_SOFTIRQ);
21839 + memcpy(skb_tail_pointer(skb), vaddr,
21841 + kunmap_atomic(vaddr,
21842 + KM_SKB_DATA_SOFTIRQ);
21843 + /* re-use the page, so don't erase
21844 + * buffer_info->page */
21845 + skb_put(skb, length);
21847 + skb_fill_page_desc(skb, 0,
21848 + buffer_info->page, 0,
21850 + e1000_consume_page(buffer_info, skb,
21856 + /* Receive Checksum Offload XXX recompute due to CRC strip? */
21857 + e1000_rx_checksum(adapter,
21859 + ((u32)(rx_desc->errors) << 24),
21860 + le16_to_cpu(rx_desc->csum), skb);
21862 + /* probably a little skewed due to removing CRC */
21863 + total_rx_bytes += skb->len;
21864 + total_rx_packets++;
21866 + /* eth type trans needs skb->data to point to something */
21867 + if (!pskb_may_pull(skb, ETH_HLEN)) {
21868 + e_err("pskb_may_pull failed.\n");
21869 + dev_kfree_skb(skb);
21873 + e1000_receive_skb(adapter, netdev, skb, status,
21874 + rx_desc->special);
21877 + rx_desc->status = 0;
21879 + /* return some buffers to hardware, one at a time is too slow */
21880 + if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
21881 + adapter->alloc_rx_buf(adapter, cleaned_count);
21882 + cleaned_count = 0;
21885 + /* use prefetched values */
21886 + rx_desc = next_rxd;
21887 + buffer_info = next_buffer;
21889 + rx_ring->next_to_clean = i;
21891 + cleaned_count = e1000_desc_unused(rx_ring);
21892 + if (cleaned_count)
21893 + adapter->alloc_rx_buf(adapter, cleaned_count);
21895 + adapter->total_rx_packets += total_rx_packets;
21896 + adapter->total_rx_bytes += total_rx_bytes;
21897 + adapter->net_stats.rx_bytes += total_rx_bytes;
21898 + adapter->net_stats.rx_packets += total_rx_packets;
21901 +#endif /* CONFIG_E1000E_NAPI */
21904 + * e1000_clean_rx_ring - Free Rx Buffers per Queue
21905 + * @adapter: board private structure
21907 +static void e1000_clean_rx_ring(struct e1000_adapter *adapter)
21909 + struct e1000_ring *rx_ring = adapter->rx_ring;
21910 + struct e1000_buffer *buffer_info;
21911 + struct e1000_ps_page *ps_page;
21912 + struct pci_dev *pdev = adapter->pdev;
21913 + unsigned int i, j;
21915 + /* Free all the Rx ring sk_buffs */
21916 + for (i = 0; i < rx_ring->count; i++) {
21917 + buffer_info = &rx_ring->buffer_info[i];
21918 + if (buffer_info->dma) {
21919 + if (adapter->clean_rx == e1000_clean_rx_irq)
21920 + pci_unmap_single(pdev, buffer_info->dma,
21921 + adapter->rx_buffer_len,
21922 + PCI_DMA_FROMDEVICE);
21923 +#ifdef CONFIG_E1000E_NAPI
21924 + else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
21925 + pci_unmap_page(pdev, buffer_info->dma,
21927 + PCI_DMA_FROMDEVICE);
21929 + else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
21930 + pci_unmap_single(pdev, buffer_info->dma,
21931 + adapter->rx_ps_bsize0,
21932 + PCI_DMA_FROMDEVICE);
21933 + buffer_info->dma = 0;
21936 + if (buffer_info->page) {
21937 + put_page(buffer_info->page);
21938 + buffer_info->page = NULL;
21941 + if (buffer_info->skb) {
21942 + dev_kfree_skb(buffer_info->skb);
21943 + buffer_info->skb = NULL;
21946 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
21947 + ps_page = &buffer_info->ps_pages[j];
21948 + if (!ps_page->page)
21950 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
21951 + PCI_DMA_FROMDEVICE);
21952 + ps_page->dma = 0;
21953 + put_page(ps_page->page);
21954 + ps_page->page = NULL;
21958 +#ifdef CONFIG_E1000E_NAPI
21959 + /* there also may be some cached data from a chained receive */
21960 + if (rx_ring->rx_skb_top) {
21961 + dev_kfree_skb(rx_ring->rx_skb_top);
21962 + rx_ring->rx_skb_top = NULL;
21966 + /* Zero out the descriptor ring */
21967 + memset(rx_ring->desc, 0, rx_ring->size);
21969 + rx_ring->next_to_clean = 0;
21970 + rx_ring->next_to_use = 0;
21972 + writel(0, adapter->hw.hw_addr + rx_ring->head);
21973 + writel(0, adapter->hw.hw_addr + rx_ring->tail);
21977 + * e1000_free_rx_resources - Free Rx Resources
21978 + * @adapter: board private structure
21980 + * Free all receive software resources
21983 +void e1000_free_rx_resources(struct e1000_adapter *adapter)
21985 + struct pci_dev *pdev = adapter->pdev;
21986 + struct e1000_ring *rx_ring = adapter->rx_ring;
21989 + e1000_clean_rx_ring(adapter);
21991 + for (i = 0; i < rx_ring->count; i++) {
21992 + kfree(rx_ring->buffer_info[i].ps_pages);
21995 + vfree(rx_ring->buffer_info);
21996 + rx_ring->buffer_info = NULL;
21998 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
22000 + rx_ring->desc = NULL;
22004 + * e1000_update_itr - update the dynamic ITR value based on statistics
22005 + * @adapter: pointer to adapter
22006 + * @itr_setting: current adapter->itr
22007 + * @packets: the number of packets during this measurement interval
22008 + * @bytes: the number of bytes during this measurement interval
22010 + * Stores a new ITR value based on packets and byte
22011 + * counts during the last interrupt. The advantage of per interrupt
22012 + * computation is faster updates and more accurate ITR for the current
22013 + * traffic pattern. Constants in this function were computed
22014 + * based on theoretical maximum wire speed and thresholds were set based
22015 + * on testing data as well as attempting to minimize response time
22016 + * while increasing bulk throughput. This functionality is controlled
22017 + * by the InterruptThrottleRate module parameter.
22019 +static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
22020 + u16 itr_setting, int packets,
22023 + unsigned int retval = itr_setting;
22025 + if (packets == 0)
22026 + goto update_itr_done;
22028 + switch (itr_setting) {
22029 + case lowest_latency:
22030 + /* handle TSO and jumbo frames */
22031 + if (bytes/packets > 8000)
22032 + retval = bulk_latency;
22033 + else if ((packets < 5) && (bytes > 512)) {
22034 + retval = low_latency;
22037 + case low_latency: /* 50 usec aka 20000 ints/s */
22038 + if (bytes > 10000) {
22039 + /* this if handles the TSO accounting */
22040 + if (bytes/packets > 8000) {
22041 + retval = bulk_latency;
22042 + } else if ((packets < 10) || ((bytes/packets) > 1200)) {
22043 + retval = bulk_latency;
22044 + } else if ((packets > 35)) {
22045 + retval = lowest_latency;
22047 + } else if (bytes/packets > 2000) {
22048 + retval = bulk_latency;
22049 + } else if (packets <= 2 && bytes < 512) {
22050 + retval = lowest_latency;
22053 + case bulk_latency: /* 250 usec aka 4000 ints/s */
22054 + if (bytes > 25000) {
22055 + if (packets > 35) {
22056 + retval = low_latency;
22058 + } else if (bytes < 6000) {
22059 + retval = low_latency;
22068 +static void e1000_set_itr(struct e1000_adapter *adapter)
22070 + struct e1000_hw *hw = &adapter->hw;
22072 + u32 new_itr = adapter->itr;
22074 + /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
22075 + if (adapter->link_speed != SPEED_1000) {
22078 + goto set_itr_now;
22081 + adapter->tx_itr = e1000_update_itr(adapter,
22083 + adapter->total_tx_packets,
22084 + adapter->total_tx_bytes);
22085 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
22086 + if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
22087 + adapter->tx_itr = low_latency;
22089 + adapter->rx_itr = e1000_update_itr(adapter,
22091 + adapter->total_rx_packets,
22092 + adapter->total_rx_bytes);
22093 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
22094 + if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
22095 + adapter->rx_itr = low_latency;
22097 + current_itr = max(adapter->rx_itr, adapter->tx_itr);
22099 + switch (current_itr) {
22100 + /* counts and packets in update_itr are dependent on these numbers */
22101 + case lowest_latency:
22104 + case low_latency:
22105 + new_itr = 20000; /* aka hwitr = ~200 */
22107 + case bulk_latency:
22115 + if (new_itr != adapter->itr) {
22117 + * this attempts to bias the interrupt rate towards Bulk
22118 + * by adding intermediate steps when interrupt rate is
22121 + new_itr = new_itr > adapter->itr ?
22122 + min(adapter->itr + (new_itr >> 2), new_itr) :
22124 + adapter->itr = new_itr;
22125 +#ifdef CONFIG_E1000E_MSIX
22126 + adapter->rx_ring->itr_val = new_itr;
22127 + if (adapter->msix_entries)
22128 + adapter->rx_ring->set_itr = 1;
22131 + ew32(ITR, 1000000000 / (new_itr * 256));
22136 + * e1000_clean_tx_irq - Reclaim resources after transmit completes
22137 + * @adapter: board private structure
22139 + * the return value indicates if there is more work to do (later)
22141 +static bool e1000_clean_tx_irq(struct e1000_adapter *adapter)
22143 + struct net_device *netdev = adapter->netdev;
22144 + struct e1000_hw *hw = &adapter->hw;
22145 + struct e1000_ring *tx_ring = adapter->tx_ring;
22146 + struct e1000_tx_desc *tx_desc, *eop_desc;
22147 + struct e1000_buffer *buffer_info;
22148 + unsigned int i, eop;
22149 + bool cleaned = 0, retval = 1;
22150 + unsigned int total_tx_bytes = 0, total_tx_packets = 0;
22152 + i = tx_ring->next_to_clean;
22153 + eop = tx_ring->buffer_info[i].next_to_watch;
22154 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
22156 + while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
22157 + for (cleaned = 0; !cleaned; ) {
22158 + tx_desc = E1000_TX_DESC(*tx_ring, i);
22159 + buffer_info = &tx_ring->buffer_info[i];
22160 + cleaned = (i == eop);
22163 + struct sk_buff *skb = buffer_info->skb;
22164 +#ifdef NETIF_F_TSO
22165 + unsigned int segs, bytecount;
22166 + segs = skb_shinfo(skb)->gso_segs ?: 1;
22167 + /* multiply data chunks by size of headers */
22168 + bytecount = ((segs - 1) * skb_headlen(skb)) +
22170 + total_tx_packets += segs;
22171 + total_tx_bytes += bytecount;
22173 + total_tx_packets++;
22174 + total_tx_bytes += skb->len;
22178 + e1000_put_txbuf(adapter, buffer_info);
22179 + tx_desc->upper.data = 0;
22182 + if (i == tx_ring->count)
22184 +#ifdef CONFIG_E1000E_NAPI
22185 + if (total_tx_packets >= tx_ring->count) {
22187 + goto done_cleaning;
22192 + eop = tx_ring->buffer_info[i].next_to_watch;
22193 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
22196 +#ifdef CONFIG_E1000E_NAPI
22199 + tx_ring->next_to_clean = i;
22201 +#define TX_WAKE_THRESHOLD 32
22202 + if (cleaned && netif_carrier_ok(netdev) &&
22203 + e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
22205 + * Make sure that anybody stopping the queue after this
22206 + * sees the new next_to_clean.
22210 + if (netif_queue_stopped(netdev) &&
22211 + !(test_bit(__E1000_DOWN, &adapter->state))) {
22212 + netif_wake_queue(netdev);
22213 + ++adapter->restart_queue;
22217 + if (adapter->detect_tx_hung) {
22219 + * Detect a transmit hang in hardware, this serializes the
22220 + * check with the clearing of time_stamp and movement of i
22222 + adapter->detect_tx_hung = 0;
22223 + if (tx_ring->buffer_info[eop].dma &&
22224 + time_after(jiffies, tx_ring->buffer_info[eop].time_stamp
22225 + + (adapter->tx_timeout_factor * HZ))
22226 + && !(er32(STATUS) & E1000_STATUS_TXOFF)) {
22227 + e1000_print_tx_hang(adapter);
22228 + netif_stop_queue(netdev);
22231 + adapter->total_tx_bytes += total_tx_bytes;
22232 + adapter->total_tx_packets += total_tx_packets;
22233 + adapter->net_stats.tx_bytes += total_tx_bytes;
22234 + adapter->net_stats.tx_packets += total_tx_packets;
22239 + * e1000_intr_msi - Interrupt Handler
22240 + * @irq: interrupt number
22241 + * @data: pointer to a network interface device structure
22243 +static irqreturn_t e1000_intr_msi(int irq, void *data)
22245 + struct net_device *netdev = data;
22246 + struct e1000_adapter *adapter = netdev_priv(netdev);
22247 + struct e1000_hw *hw = &adapter->hw;
22248 +#ifndef CONFIG_E1000E_NAPI
22251 + /* read ICR disables interrupts using IAM */
22252 + u32 icr = er32(ICR);
22254 + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
22255 + hw->mac.get_link_status = 1;
22257 + * ICH8 workaround-- Call gig speed drop workaround on cable
22258 + * disconnect (LSC) before accessing any PHY registers
22260 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
22261 + (!(er32(STATUS) & E1000_STATUS_LU)))
22262 + e1000_gig_downshift_workaround_ich8lan(hw);
22265 + * 80003ES2LAN workaround-- For packet buffer work-around on
22266 + * link down event; disable receives here in the ISR and reset
22267 + * adapter in watchdog
22269 + if (netif_carrier_ok(netdev) &&
22270 + adapter->flags & FLAG_RX_NEEDS_RESTART) {
22271 + /* disable receives */
22272 + u32 rctl = er32(RCTL);
22273 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
22274 + adapter->flags |= FLAG_RX_RESTART_NOW;
22276 + /* guard against interrupt when we're going down */
22277 + if (!test_bit(__E1000_DOWN, &adapter->state))
22278 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
22281 +#ifdef CONFIG_E1000E_NAPI
22282 + if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
22283 + adapter->total_tx_bytes = 0;
22284 + adapter->total_tx_packets = 0;
22285 + adapter->total_rx_bytes = 0;
22286 + adapter->total_rx_packets = 0;
22287 + __netif_rx_schedule(netdev, &adapter->napi);
22290 + adapter->total_tx_bytes = 0;
22291 + adapter->total_rx_bytes = 0;
22292 + adapter->total_tx_packets = 0;
22293 + adapter->total_rx_packets = 0;
22295 + for (i = 0; i < E1000_MAX_INTR; i++) {
22296 + int rx_cleaned = adapter->clean_rx(adapter);
22297 + int tx_cleaned_complete = e1000_clean_tx_irq(adapter);
22298 + if (!rx_cleaned && tx_cleaned_complete)
22302 + if (likely(adapter->itr_setting & 3))
22303 + e1000_set_itr(adapter);
22304 +#endif /* CONFIG_E1000E_NAPI */
22306 + return IRQ_HANDLED;
22310 + * e1000_intr - Interrupt Handler
22311 + * @irq: interrupt number
22312 + * @data: pointer to a network interface device structure
22314 +static irqreturn_t e1000_intr(int irq, void *data)
22316 + struct net_device *netdev = data;
22317 + struct e1000_adapter *adapter = netdev_priv(netdev);
22318 + struct e1000_hw *hw = &adapter->hw;
22319 +#ifndef CONFIG_E1000E_NAPI
22321 + int rx_cleaned, tx_cleaned_complete;
22323 + u32 rctl, icr = er32(ICR);
22326 + return IRQ_NONE; /* Not our interrupt */
22328 +#ifdef CONFIG_E1000E_NAPI
22330 + * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
22331 + * not set, then the adapter didn't send an interrupt
22333 + if (!(icr & E1000_ICR_INT_ASSERTED))
22336 +#endif /* CONFIG_E1000E_NAPI */
22337 + if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
22338 + hw->mac.get_link_status = 1;
22340 + * ICH8 workaround-- Call gig speed drop workaround on cable
22341 + * disconnect (LSC) before accessing any PHY registers
22343 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
22344 + (!(er32(STATUS) & E1000_STATUS_LU)))
22345 + e1000_gig_downshift_workaround_ich8lan(hw);
22348 + * 80003ES2LAN workaround--
22349 + * For packet buffer work-around on link down event;
22350 + * disable receives here in the ISR and
22351 + * reset adapter in watchdog
22353 + if (netif_carrier_ok(netdev) &&
22354 + (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
22355 + /* disable receives */
22356 + rctl = er32(RCTL);
22357 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
22358 + adapter->flags |= FLAG_RX_RESTART_NOW;
22360 + /* guard against interrupt when we're going down */
22361 + if (!test_bit(__E1000_DOWN, &adapter->state))
22362 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
22365 +#ifdef CONFIG_E1000E_NAPI
22366 + if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
22367 + adapter->total_tx_bytes = 0;
22368 + adapter->total_tx_packets = 0;
22369 + adapter->total_rx_bytes = 0;
22370 + adapter->total_rx_packets = 0;
22371 + __netif_rx_schedule(netdev, &adapter->napi);
22374 + adapter->total_tx_bytes = 0;
22375 + adapter->total_rx_bytes = 0;
22376 + adapter->total_tx_packets = 0;
22377 + adapter->total_rx_packets = 0;
22379 + for (i = 0; i < E1000_MAX_INTR; i++) {
22380 + rx_cleaned = adapter->clean_rx(adapter);
22381 + tx_cleaned_complete = e1000_clean_tx_irq(adapter);
22382 + if (!rx_cleaned && tx_cleaned_complete)
22386 + if (likely(adapter->itr_setting & 3))
22387 + e1000_set_itr(adapter);
22388 +#endif /* CONFIG_E1000E_NAPI */
22390 + return IRQ_HANDLED;
22393 +#ifdef CONFIG_E1000E_MSIX
22394 +static irqreturn_t e1000_msix_other(int irq, void *data)
22396 + struct net_device *netdev = data;
22397 + struct e1000_adapter *adapter = netdev_priv(netdev);
22398 + struct e1000_hw *hw = &adapter->hw;
22399 + u32 icr = er32(ICR);
22401 + if (!(icr & E1000_ICR_INT_ASSERTED))
22403 + ew32(IMS, E1000_IMS_OTHER);
22407 + if (icr & adapter->eiac_mask)
22408 + ew32(ICS, (icr & adapter->eiac_mask));
22410 + if (icr & E1000_ICR_OTHER) {
22411 + if (!(icr & E1000_ICR_LSC))
22412 + goto no_link_interrupt;
22413 + hw->mac.get_link_status = 1;
22414 + /* guard against interrupt when we're going down */
22415 + if (!test_bit(__E1000_DOWN, &adapter->state))
22416 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
22419 +no_link_interrupt:
22420 + ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
22422 + return IRQ_HANDLED;
22426 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22427 +static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
22429 + struct net_device *netdev = data;
22430 + struct e1000_adapter *adapter = netdev_priv(netdev);
22431 + struct e1000_hw *hw = &adapter->hw;
22432 + struct e1000_ring *tx_ring = adapter->tx_ring;
22435 + adapter->total_tx_bytes = 0;
22436 + adapter->total_tx_packets = 0;
22438 + if (!e1000_clean_tx_irq(adapter))
22439 + /* Ring was not completely cleaned, so fire another interrupt */
22440 + ew32(ICS, tx_ring->ims_val);
22442 + return IRQ_HANDLED;
22445 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
22446 +static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
22448 + struct net_device *netdev = data;
22449 + struct e1000_adapter *adapter = netdev_priv(netdev);
22450 +#ifndef CONFIG_E1000E_NAPI
22452 + struct e1000_hw *hw = &adapter->hw;
22455 + /* Write the ITR value calculated at the end of the
22456 + * previous interrupt.
22458 + if (adapter->rx_ring->set_itr) {
22459 + writel(1000000000 / (adapter->rx_ring->itr_val * 256),
22460 + adapter->hw.hw_addr + adapter->rx_ring->itr_register);
22461 + adapter->rx_ring->set_itr = 0;
22464 +#ifdef CONFIG_E1000E_NAPI
22465 + if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
22466 + adapter->total_rx_bytes = 0;
22467 + adapter->total_rx_packets = 0;
22468 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
22469 + adapter->total_tx_bytes = 0;
22470 + adapter->total_tx_packets = 0;
22471 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
22472 + __netif_rx_schedule(netdev, &adapter->napi);
22475 + adapter->total_rx_bytes = 0;
22476 + adapter->total_rx_packets = 0;
22477 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
22478 + adapter->total_tx_bytes = 0;
22479 + adapter->total_tx_packets = 0;
22482 + for (i = 0; i < E1000_MAX_INTR; i++) {
22483 + int rx_cleaned = adapter->clean_rx(adapter);
22484 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
22485 + int tx_cleaned_complete = e1000_clean_tx_irq(adapter);
22486 + if (!rx_cleaned && tx_cleaned_complete)
22492 + /* If we got here, the ring was not completely cleaned,
22493 + * so fire another interrupt.
22495 + ew32(ICS, adapter->rx_ring->ims_val);
22498 +#endif /* CONFIG_E1000E_NAPI */
22499 + return IRQ_HANDLED;
22503 + * e1000_configure_msix - Configure MSI-X hardware
22505 + * e1000_configure_msix sets up the hardware to properly
22506 + * generate MSI-X interrupts.
22508 +static void e1000_configure_msix(struct e1000_adapter *adapter)
22510 + struct e1000_hw *hw = &adapter->hw;
22511 + struct e1000_ring *rx_ring = adapter->rx_ring;
22512 + struct e1000_ring *tx_ring = adapter->tx_ring;
22514 + u32 ctrl_ext, ivar = 0;
22516 + adapter->eiac_mask = 0;
22518 + /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
22519 + if (hw->mac.type == e1000_82574) {
22520 + u32 rfctl = er32(RFCTL);
22521 + rfctl |= E1000_RFCTL_ACK_DIS;
22522 + ew32(RFCTL, rfctl);
22525 +#define E1000_IVAR_INT_ALLOC_VALID 0x8
22526 + /* Configure Rx vector */
22527 + rx_ring->ims_val = E1000_IMS_RXQ0;
22528 + adapter->eiac_mask |= rx_ring->ims_val;
22529 + if (rx_ring->itr_val)
22530 + writel(1000000000 / (rx_ring->itr_val * 256),
22531 + hw->hw_addr + rx_ring->itr_register);
22533 + writel(1, hw->hw_addr + rx_ring->itr_register);
22534 + ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
22536 + /* Configure Tx vector */
22537 + tx_ring->ims_val = E1000_IMS_TXQ0;
22538 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22540 + if (tx_ring->itr_val)
22541 + writel(1000000000 / (tx_ring->itr_val * 256),
22542 + hw->hw_addr + tx_ring->itr_register);
22544 + writel(1, hw->hw_addr + tx_ring->itr_register);
22546 + rx_ring->ims_val |= tx_ring->ims_val;
22548 + adapter->eiac_mask |= tx_ring->ims_val;
22549 + ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
22551 + /* set vector for Other Causes, e.g. link changes */
22553 + ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
22554 + if (rx_ring->itr_val)
22555 + writel(1000000000 / (rx_ring->itr_val * 256),
22556 + hw->hw_addr + E1000_EITR_82574(vector));
22558 + writel(1, hw->hw_addr + E1000_EITR_82574(vector));
22560 + /* Cause Tx interrupts on every write back */
22561 + ivar |= (1 << 31);
22563 + ew32(IVAR, ivar);
22565 + /* enable MSI-X PBA support */
22566 + ctrl_ext = er32(CTRL_EXT);
22567 + ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
22569 + /* Auto-Mask Other interrupts upon ICR read */
22570 + ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
22571 + ctrl_ext |= E1000_CTRL_EXT_EIAME;
22572 + ew32(CTRL_EXT, ctrl_ext);
22576 +void e1000_reset_interrupt_capability(struct e1000_adapter *adapter)
22578 + if (adapter->msix_entries) {
22579 + pci_disable_msix(adapter->pdev);
22580 + kfree(adapter->msix_entries);
22581 + adapter->msix_entries = NULL;
22582 + } else if (adapter->flags & FLAG_MSI_ENABLED) {
22583 + pci_disable_msi(adapter->pdev);
22584 + adapter->flags &= ~FLAG_MSI_ENABLED;
22591 + * e1000_set_interrupt_capability - set MSI or MSI-X if supported
22593 + * Attempt to configure interrupts using the best available
22594 + * capabilities of the hardware and kernel.
22596 +void e1000_set_interrupt_capability(struct e1000_adapter *adapter)
22602 + switch (adapter->int_mode) {
22603 + case E1000E_INT_MODE_MSIX:
22604 + if (adapter->flags & FLAG_HAS_MSIX) {
22605 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22606 + numvecs = 3; /* RxQ0, TxQ0 and other */
22608 + numvecs = 2; /* RxQ0/TxQ0 and other */
22610 + adapter->msix_entries = kcalloc(numvecs,
22611 + sizeof(struct msix_entry),
22613 + if (adapter->msix_entries) {
22614 + for (i=0; i < numvecs; i++)
22615 + adapter->msix_entries[i].entry = i;
22617 + err = pci_enable_msix(adapter->pdev,
22618 + adapter->msix_entries,
22623 + /* MSI-X failed, so fall through and try MSI */
22624 + e_err("Failed to initialize MSI-X interrupts. "
22625 + "Falling back to MSI interrupts.\n");
22626 + e1000_reset_interrupt_capability(adapter);
22628 + adapter->int_mode = E1000E_INT_MODE_MSI;
22629 + /* Fall through */
22630 + case E1000E_INT_MODE_MSI:
22631 + if (!pci_enable_msi(adapter->pdev)) {
22632 + adapter->flags |= FLAG_MSI_ENABLED;
22634 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
22635 + e_err("Failed to initialize MSI interrupts. Falling "
22636 + "back to legacy interrupts.\n");
22638 + /* Fall through */
22639 + case E1000E_INT_MODE_LEGACY:
22640 + /* Don't do anything; this is the system default */
22648 + * e1000_request_msix - Initialize MSI-X interrupts
22650 + * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
22653 +static int e1000_request_msix(struct e1000_adapter *adapter)
22655 + struct net_device *netdev = adapter->netdev;
22656 + int err = 0, vector = 0;
22658 + if (strlen(netdev->name) < (IFNAMSIZ - 5))
22659 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22660 + sprintf(adapter->rx_ring->name, "%s-rx0", netdev->name);
22662 + sprintf(adapter->rx_ring->name, "%s-Q0", netdev->name);
22665 + memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
22666 + err = request_irq(adapter->msix_entries[vector].vector,
22667 + &e1000_intr_msix_rx, 0, adapter->rx_ring->name,
22671 + adapter->rx_ring->itr_register = E1000_EITR_82574(vector);
22672 + adapter->rx_ring->itr_val = adapter->itr;
22675 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22676 + if (strlen(netdev->name) < (IFNAMSIZ - 5))
22677 + sprintf(adapter->tx_ring->name, "%s-tx0", netdev->name);
22679 + memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
22680 + err = request_irq(adapter->msix_entries[vector].vector,
22681 + &e1000_intr_msix_tx, 0, adapter->tx_ring->name,
22685 + adapter->tx_ring->itr_register = E1000_EITR_82574(vector);
22686 + adapter->tx_ring->itr_val = adapter->itr;
22689 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
22690 + err = request_irq(adapter->msix_entries[vector].vector,
22691 + &e1000_msix_other, 0, netdev->name, netdev);
22695 + e1000_configure_msix(adapter);
22701 +#endif /* CONFIG_E1000E_MSIX */
22703 + * e1000_alloc_queues - Allocate memory for all rings
22704 + * @adapter: board private structure to initialize
22706 +static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
22708 + adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
22709 + if (!adapter->tx_ring)
22712 + adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
22713 + if (!adapter->rx_ring)
22718 + e_err("Unable to allocate memory for queues\n");
22719 + kfree(adapter->rx_ring);
22720 + kfree(adapter->tx_ring);
22725 + * e1000_request_irq - initialize interrupts
22727 + * Attempts to configure interrupts using the best available
22728 + * capabilities of the hardware and kernel.
22730 +static int e1000_request_irq(struct e1000_adapter *adapter)
22732 + struct net_device *netdev = adapter->netdev;
22734 +#ifdef CONFIG_E1000E_MSIX
22736 + if (adapter->msix_entries) {
22737 + err = e1000_request_msix(adapter);
22740 + /* fall back to MSI */
22741 + e1000_reset_interrupt_capability(adapter);
22742 + adapter->int_mode = E1000E_INT_MODE_MSI;
22743 + e1000_set_interrupt_capability(adapter);
22745 + if (adapter->flags & FLAG_MSI_ENABLED) {
22746 + err = request_irq(adapter->pdev->irq, &e1000_intr_msi, 0,
22747 + netdev->name, netdev);
22751 + /* fall back to legacy interrupt */
22752 + e1000_reset_interrupt_capability(adapter);
22753 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
22756 + err = request_irq(adapter->pdev->irq, &e1000_intr, IRQF_SHARED,
22757 + netdev->name, netdev);
22759 + e_err("Unable to allocate interrupt, Error: %d\n", err);
22761 + int irq_flags = IRQF_SHARED;
22763 + if (!(adapter->flags & FLAG_MSI_TEST_FAILED)) {
22764 + err = pci_enable_msi(adapter->pdev);
22766 + adapter->flags |= FLAG_MSI_ENABLED;
22771 + err = request_irq(adapter->pdev->irq,
22772 + ((adapter->flags & FLAG_MSI_ENABLED) ?
22773 + &e1000_intr_msi : &e1000_intr),
22774 + irq_flags, netdev->name, netdev);
22776 + if (adapter->flags & FLAG_MSI_ENABLED) {
22777 + pci_disable_msi(adapter->pdev);
22778 + adapter->flags &= ~FLAG_MSI_ENABLED;
22780 + e_err("Unable to allocate interrupt, Error: %d\n", err);
22782 +#endif /* CONFIG_E1000E_MSIX */
22787 +static void e1000_free_irq(struct e1000_adapter *adapter)
22789 + struct net_device *netdev = adapter->netdev;
22791 +#ifdef CONFIG_E1000E_MSIX
22792 + if (adapter->msix_entries) {
22795 + free_irq(adapter->msix_entries[vector].vector, netdev);
22798 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
22799 + free_irq(adapter->msix_entries[vector].vector, netdev);
22803 + /* Other Causes interrupt vector */
22804 + free_irq(adapter->msix_entries[vector].vector, netdev);
22808 +#endif /* CONFIG_E1000E_MSIX */
22809 + free_irq(adapter->pdev->irq, netdev);
22810 +#ifndef CONFIG_E1000E_MSIX
22811 + if (adapter->flags & FLAG_MSI_ENABLED) {
22812 + pci_disable_msi(adapter->pdev);
22813 + adapter->flags &= ~FLAG_MSI_ENABLED;
22819 + * e1000_irq_disable - Mask off interrupt generation on the NIC
22821 +static void e1000_irq_disable(struct e1000_adapter *adapter)
22823 + struct e1000_hw *hw = &adapter->hw;
22826 +#ifdef CONFIG_E1000E_MSIX
22827 + if (adapter->msix_entries) {
22828 + ew32(EIAC_82574, 0);
22830 +#endif /* CONFIG_E1000E_MSIX */
22832 + synchronize_irq(adapter->pdev->irq);
22836 + * e1000_irq_enable - Enable default interrupt generation settings
22838 +static void e1000_irq_enable(struct e1000_adapter *adapter)
22840 + struct e1000_hw *hw = &adapter->hw;
22841 +#ifdef CONFIG_E1000E_MSIX
22843 + if (adapter->msix_entries) {
22844 + ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
22845 + ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
22847 + ew32(IMS, IMS_ENABLE_MASK);
22850 + ew32(IMS, IMS_ENABLE_MASK);
22851 +#endif /* CONFIG_E1000E_MSIX */
22855 + * e1000_get_hw_control - get control of the h/w from f/w
22856 + * @adapter: address of board private structure
22858 + * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
22859 + * For ASF and Pass Through versions of f/w this means that
22860 + * the driver is loaded. For AMT version (only with 82573)
22861 + * of the f/w this means that the network i/f is open.
22863 +static void e1000_get_hw_control(struct e1000_adapter *adapter)
22865 + struct e1000_hw *hw = &adapter->hw;
22869 + /* Let firmware know the driver has taken over */
22870 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
22871 + swsm = er32(SWSM);
22872 + ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
22873 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
22874 + ctrl_ext = er32(CTRL_EXT);
22875 + ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
22880 + * e1000_release_hw_control - release control of the h/w to f/w
22881 + * @adapter: address of board private structure
22883 + * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
22884 + * For ASF and Pass Through versions of f/w this means that the
22885 + * driver is no longer loaded. For AMT version (only with 82573) i
22886 + * of the f/w this means that the network i/f is closed.
22889 +static void e1000_release_hw_control(struct e1000_adapter *adapter)
22891 + struct e1000_hw *hw = &adapter->hw;
22895 + /* Let firmware taken over control of h/w */
22896 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
22897 + swsm = er32(SWSM);
22898 + ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
22899 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
22900 + ctrl_ext = er32(CTRL_EXT);
22901 + ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
22905 +#ifdef CONFIG_E1000E_NAPI
22907 + * e1000_poll - NAPI Rx polling callback
22908 + * @napi: struct associated with this polling callback
22909 + * @budget: amount of packets driver is allowed to process this poll
22911 +static int e1000_poll(struct napi_struct *napi, int budget)
22913 + struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
22915 + struct net_device *netdev = adapter->netdev;
22916 + int tx_clean_complete = 1, work_done = 0;
22917 +#ifdef CONFIG_E1000E_MSIX
22918 + struct e1000_hw *hw = &adapter->hw;
22920 + if (adapter->msix_entries &&
22921 + !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
22926 + * e1000_poll is called per-cpu. This lock protects
22927 + * tx_ring from being cleaned by multiple cpus
22928 + * simultaneously. A failure obtaining the lock means
22929 + * tx_ring is currently being cleaned anyway.
22931 + if (spin_trylock(&adapter->tx_queue_lock)) {
22932 + tx_clean_complete &= e1000_clean_tx_irq(adapter);
22933 + spin_unlock(&adapter->tx_queue_lock);
22936 +#ifdef CONFIG_E1000E_MSIX
22939 + adapter->clean_rx(adapter, &work_done, budget);
22941 + /* If Tx completed and all Rx work done, exit the polling mode */
22942 + if ((tx_clean_complete && (work_done == 0)) || !netif_running(netdev)) {
22943 + netif_rx_complete(netdev, napi);
22944 + if (adapter->itr_setting & 3)
22945 + e1000_set_itr(adapter);
22946 + if (!test_bit(__E1000_DOWN, &adapter->state)) {
22947 +#ifdef CONFIG_E1000E_MSIX
22948 + if (adapter->msix_entries)
22949 + ew32(IMS, adapter->rx_ring->ims_val);
22952 + e1000_irq_enable(adapter);
22957 + if (!tx_clean_complete)
22958 + work_done = budget;
22960 + return work_done;
22963 +#endif /* CONFIG_E1000E_NAPI */
22964 +static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
22966 + struct e1000_adapter *adapter = netdev_priv(netdev);
22967 + struct e1000_hw *hw = &adapter->hw;
22969 + struct net_device *v_netdev;
22971 + /* don't update vlan cookie if already programmed */
22972 + if ((adapter->hw.mng_cookie.status &
22973 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
22974 + (vid == adapter->mng_vlan_id))
22976 + /* add VID to filter table */
22977 + index = (vid >> 5) & 0x7F;
22978 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
22979 + vfta |= (1 << (vid & 0x1F));
22980 + if (hw->mac.ops.write_vfta)
22981 + hw->mac.ops.write_vfta(hw, index, vfta);
22983 + * Copy feature flags from netdev to the vlan netdev for this vid.
22984 + * This allows things like TSO to bubble down to our vlan device.
22986 + v_netdev = vlan_group_get_device(adapter->vlgrp, vid);
22987 + v_netdev->features |= adapter->netdev->features;
22988 + vlan_group_set_device(adapter->vlgrp, vid, v_netdev);
22991 +static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
22993 + struct e1000_adapter *adapter = netdev_priv(netdev);
22994 + struct e1000_hw *hw = &adapter->hw;
22997 + if (!test_bit(__E1000_DOWN, &adapter->state))
22998 + e1000_irq_disable(adapter);
22999 + vlan_group_set_device(adapter->vlgrp, vid, NULL);
23000 + if (!test_bit(__E1000_DOWN, &adapter->state))
23001 + e1000_irq_enable(adapter);
23003 + if ((adapter->hw.mng_cookie.status &
23004 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
23005 + (vid == adapter->mng_vlan_id)) {
23006 + /* release control to f/w */
23007 + e1000_release_hw_control(adapter);
23011 + /* remove VID from filter table */
23012 + index = (vid >> 5) & 0x7F;
23013 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
23014 + vfta &= ~(1 << (vid & 0x1F));
23015 + if (hw->mac.ops.write_vfta)
23016 + hw->mac.ops.write_vfta(hw, index, vfta);
23019 +static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
23021 + struct net_device *netdev = adapter->netdev;
23022 + u16 vid = adapter->hw.mng_cookie.vlan_id;
23023 + u16 old_vid = adapter->mng_vlan_id;
23025 + if (!adapter->vlgrp)
23028 + if (!vlan_group_get_device(adapter->vlgrp, vid)) {
23029 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
23030 + if (adapter->hw.mng_cookie.status &
23031 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
23032 + e1000_vlan_rx_add_vid(netdev, vid);
23033 + adapter->mng_vlan_id = vid;
23036 + if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
23037 + (vid != old_vid) &&
23038 + !vlan_group_get_device(adapter->vlgrp, old_vid))
23039 + e1000_vlan_rx_kill_vid(netdev, old_vid);
23041 + adapter->mng_vlan_id = vid;
23046 +static void e1000_vlan_rx_register(struct net_device *netdev,
23047 + struct vlan_group *grp)
23049 + struct e1000_adapter *adapter = netdev_priv(netdev);
23050 + struct e1000_hw *hw = &adapter->hw;
23053 + if (!test_bit(__E1000_DOWN, &adapter->state))
23054 + e1000_irq_disable(adapter);
23055 + adapter->vlgrp = grp;
23058 + /* enable VLAN tag insert/strip */
23059 + ctrl = er32(CTRL);
23060 + ctrl |= E1000_CTRL_VME;
23061 + ew32(CTRL, ctrl);
23063 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
23064 + /* enable VLAN receive filtering */
23065 + rctl = er32(RCTL);
23066 + rctl |= E1000_RCTL_VFE;
23067 + rctl &= ~E1000_RCTL_CFIEN;
23068 + ew32(RCTL, rctl);
23069 + e1000_update_mng_vlan(adapter);
23072 + /* disable VLAN tag insert/strip */
23073 + ctrl = er32(CTRL);
23074 + ctrl &= ~E1000_CTRL_VME;
23075 + ew32(CTRL, ctrl);
23077 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
23078 + /* disable VLAN filtering */
23079 + rctl = er32(RCTL);
23080 + rctl &= ~E1000_RCTL_VFE;
23081 + ew32(RCTL, rctl);
23082 + if (adapter->mng_vlan_id !=
23083 + (u16)E1000_MNG_VLAN_NONE) {
23084 + e1000_vlan_rx_kill_vid(netdev,
23085 + adapter->mng_vlan_id);
23086 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
23091 + if (!test_bit(__E1000_DOWN, &adapter->state))
23092 + e1000_irq_enable(adapter);
23095 +static void e1000_restore_vlan(struct e1000_adapter *adapter)
23099 + e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
23101 + if (!adapter->vlgrp)
23104 + for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
23105 + if (!vlan_group_get_device(adapter->vlgrp, vid))
23107 + e1000_vlan_rx_add_vid(adapter->netdev, vid);
23111 +static void e1000_init_manageability(struct e1000_adapter *adapter)
23113 + struct e1000_hw *hw = &adapter->hw;
23114 + u32 manc, manc2h;
23116 + if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
23119 + manc = er32(MANC);
23122 + * enable receiving management packets to the host. this will probably
23123 + * generate destination unreachable messages from the host OS, but
23124 + * the packets will be handled on SMBUS
23126 + manc |= E1000_MANC_EN_MNG2HOST;
23127 + manc2h = er32(MANC2H);
23128 +#define E1000_MNG2HOST_PORT_623 (1 << 5)
23129 +#define E1000_MNG2HOST_PORT_664 (1 << 6)
23130 + manc2h |= E1000_MNG2HOST_PORT_623;
23131 + manc2h |= E1000_MNG2HOST_PORT_664;
23132 + ew32(MANC2H, manc2h);
23133 + ew32(MANC, manc);
23137 + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
23138 + * @adapter: board private structure
23140 + * Configure the Tx unit of the MAC after a reset.
23142 +static void e1000_configure_tx(struct e1000_adapter *adapter)
23144 + struct e1000_hw *hw = &adapter->hw;
23145 + struct e1000_ring *tx_ring = adapter->tx_ring;
23147 + u32 tdlen, tctl, tipg, tarc;
23148 + u32 ipgr1, ipgr2;
23150 + /* Setup the HW Tx Head and Tail descriptor pointers */
23151 + tdba = tx_ring->dma;
23152 + tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
23153 + ew32(TDBAL(0), (tdba & DMA_32BIT_MASK));
23154 + ew32(TDBAH(0), (tdba >> 32));
23155 + ew32(TDLEN(0), tdlen);
23158 + tx_ring->head = E1000_TDH(0);
23159 + tx_ring->tail = E1000_TDT(0);
23161 + /* Set the default values for the Tx Inter Packet Gap timer */
23162 + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
23163 + ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
23164 + ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
23166 + if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
23167 + ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
23169 + tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
23170 + tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
23171 + ew32(TIPG, tipg);
23173 + /* Set the Tx Interrupt Delay register */
23174 + ew32(TIDV, adapter->tx_int_delay);
23175 + /* Tx irq moderation */
23176 + ew32(TADV, adapter->tx_abs_int_delay);
23178 + /* Program the Transmit Control Register */
23179 + tctl = er32(TCTL);
23180 + tctl &= ~E1000_TCTL_CT;
23181 + tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
23182 + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
23184 + if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
23185 + tarc = er32(TARC(0));
23187 + * set the speed mode bit, we'll clear it if we're not at
23188 + * gigabit link later
23190 +#define SPEED_MODE_BIT (1 << 21)
23191 + tarc |= SPEED_MODE_BIT;
23192 + ew32(TARC(0), tarc);
23195 + /* errata: program both queues to unweighted RR */
23196 + if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
23197 + tarc = er32(TARC(0));
23199 + ew32(TARC(0), tarc);
23200 + tarc = er32(TARC(1));
23202 + ew32(TARC(1), tarc);
23205 + hw->mac.ops.config_collision_dist(hw);
23207 + /* Setup Transmit Descriptor Settings for eop descriptor */
23208 + adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
23210 + /* only set IDE if we are delaying interrupts using the timers */
23211 + if (adapter->tx_int_delay)
23212 + adapter->txd_cmd |= E1000_TXD_CMD_IDE;
23214 + /* enable Report Status bit */
23215 + adapter->txd_cmd |= E1000_TXD_CMD_RS;
23217 + ew32(TCTL, tctl);
23219 + adapter->tx_queue_len = adapter->netdev->tx_queue_len;
23223 + * e1000_setup_rctl - configure the receive control registers
23224 + * @adapter: Board private structure
23226 +#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
23227 + (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
23228 +static void e1000_setup_rctl(struct e1000_adapter *adapter)
23230 + struct e1000_hw *hw = &adapter->hw;
23235 + /* Program MC offset vector base */
23236 + rctl = er32(RCTL);
23237 + rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
23238 + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
23239 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
23240 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
23242 + /* Do not Store bad packets */
23243 + rctl &= ~E1000_RCTL_SBP;
23245 + /* Enable Long Packet receive */
23246 + if (adapter->netdev->mtu <= ETH_DATA_LEN)
23247 + rctl &= ~E1000_RCTL_LPE;
23249 + rctl |= E1000_RCTL_LPE;
23251 + /* Enable hardware CRC frame stripping */
23252 + rctl |= E1000_RCTL_SECRC;
23254 + /* Setup buffer sizes */
23255 + rctl &= ~E1000_RCTL_SZ_4096;
23256 + rctl |= E1000_RCTL_BSEX;
23257 + switch (adapter->rx_buffer_len) {
23259 + rctl |= E1000_RCTL_SZ_256;
23260 + rctl &= ~E1000_RCTL_BSEX;
23263 + rctl |= E1000_RCTL_SZ_512;
23264 + rctl &= ~E1000_RCTL_BSEX;
23267 + rctl |= E1000_RCTL_SZ_1024;
23268 + rctl &= ~E1000_RCTL_BSEX;
23272 + rctl |= E1000_RCTL_SZ_2048;
23273 + rctl &= ~E1000_RCTL_BSEX;
23276 + rctl |= E1000_RCTL_SZ_4096;
23279 + rctl |= E1000_RCTL_SZ_8192;
23282 + rctl |= E1000_RCTL_SZ_16384;
23287 + * 82571 and greater support packet-split where the protocol
23288 + * header is placed in skb->data and the packet data is
23289 + * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
23290 + * In the case of a non-split, skb->data is linearly filled,
23291 + * followed by the page buffers. Therefore, skb->data is
23292 + * sized to hold the largest protocol header.
23294 + * allocations using alloc_page take too long for regular MTU
23295 + * so only enable packet split for jumbo frames
23297 + * Using pages when the page size is greater than 16k wastes
23298 + * a lot of memory, since we allocate 3 pages at all times
23301 + pages = PAGE_USE_COUNT(adapter->netdev->mtu);
23302 + if (!(adapter->flags & FLAG_IS_ICH) && (pages <= 3) &&
23303 + (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
23304 + adapter->rx_ps_pages = pages;
23306 + adapter->rx_ps_pages = 0;
23308 + if (adapter->rx_ps_pages) {
23309 + /* Configure extra packet-split registers */
23310 + rfctl = er32(RFCTL);
23311 + rfctl |= E1000_RFCTL_EXTEN;
23313 + * disable packet split support for IPv6 extension headers,
23314 + * because some malformed IPv6 headers can hang the Rx
23316 + rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
23317 + E1000_RFCTL_NEW_IPV6_EXT_DIS);
23319 + ew32(RFCTL, rfctl);
23321 + /* Enable Packet split descriptors */
23322 + rctl |= E1000_RCTL_DTYP_PS;
23324 + psrctl |= adapter->rx_ps_bsize0 >>
23325 + E1000_PSRCTL_BSIZE0_SHIFT;
23327 + switch (adapter->rx_ps_pages) {
23329 + psrctl |= PAGE_SIZE <<
23330 + E1000_PSRCTL_BSIZE3_SHIFT;
23332 + psrctl |= PAGE_SIZE <<
23333 + E1000_PSRCTL_BSIZE2_SHIFT;
23335 + psrctl |= PAGE_SIZE >>
23336 + E1000_PSRCTL_BSIZE1_SHIFT;
23340 + ew32(PSRCTL, psrctl);
23343 + ew32(RCTL, rctl);
23344 + /* just started the receive unit, no need to restart */
23345 + adapter->flags &= ~FLAG_RX_RESTART_NOW;
23349 + * e1000_configure_rx - Configure Receive Unit after Reset
23350 + * @adapter: board private structure
23352 + * Configure the Rx unit of the MAC after a reset.
23354 +static void e1000_configure_rx(struct e1000_adapter *adapter)
23356 + struct e1000_hw *hw = &adapter->hw;
23357 + struct e1000_ring *rx_ring = adapter->rx_ring;
23359 + u32 rdlen, rctl, rxcsum, ctrl_ext;
23361 + if (adapter->rx_ps_pages) {
23362 + /* this is a 32 byte descriptor */
23363 + rdlen = rx_ring->count *
23364 + sizeof(union e1000_rx_desc_packet_split);
23365 + adapter->clean_rx = e1000_clean_rx_irq_ps;
23366 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
23367 +#ifdef CONFIG_E1000E_NAPI
23368 + } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
23369 + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc);
23370 + adapter->clean_rx = e1000_clean_jumbo_rx_irq;
23371 + adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
23374 + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc);
23375 + adapter->clean_rx = e1000_clean_rx_irq;
23376 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
23379 + /* disable receives while setting up the descriptors */
23380 + rctl = er32(RCTL);
23381 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
23385 + /* set the Receive Delay Timer Register */
23386 + ew32(RDTR, adapter->rx_int_delay);
23388 + /* irq moderation */
23389 + ew32(RADV, adapter->rx_abs_int_delay);
23390 + if (adapter->itr_setting != 0)
23391 + ew32(ITR, 1000000000 / (adapter->itr * 256));
23393 + ctrl_ext = er32(CTRL_EXT);
23394 + /* Reset delay timers after every interrupt */
23395 + ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
23396 +#ifdef CONFIG_E1000E_NAPI
23397 + /* Auto-Mask interrupts upon ICR access */
23398 + ctrl_ext |= E1000_CTRL_EXT_IAME;
23399 + ew32(IAM, 0xffffffff);
23401 + ew32(CTRL_EXT, ctrl_ext);
23405 + * Setup the HW Rx Head and Tail Descriptor Pointers and
23406 + * the Base and Length of the Rx Descriptor Ring
23408 + rdba = rx_ring->dma;
23409 + ew32(RDBAL(0), (rdba & DMA_32BIT_MASK));
23410 + ew32(RDBAH(0), (rdba >> 32));
23411 + ew32(RDLEN(0), rdlen);
23414 + rx_ring->head = E1000_RDH(0);
23415 + rx_ring->tail = E1000_RDT(0);
23417 + /* Enable Receive Checksum Offload for TCP and UDP */
23418 + rxcsum = er32(RXCSUM);
23419 + if (adapter->flags & FLAG_RX_CSUM_ENABLED) {
23420 + rxcsum |= E1000_RXCSUM_TUOFL;
23423 + * IPv4 payload checksum for UDP fragments must be
23424 + * used in conjunction with packet-split.
23426 + if (adapter->rx_ps_pages)
23427 + rxcsum |= E1000_RXCSUM_IPPCSE;
23429 + rxcsum &= ~E1000_RXCSUM_TUOFL;
23430 + /* no need to clear IPPCSE as it defaults to 0 */
23432 + ew32(RXCSUM, rxcsum);
23435 + * Enable early receives on supported devices, only takes effect when
23436 + * packet size is equal or larger than the specified value (in 8 byte
23437 + * units), e.g. using jumbo frames when setting to E1000_ERT_2048
23439 + if ((adapter->flags & FLAG_HAS_ERT) &&
23440 + (adapter->netdev->mtu > ETH_DATA_LEN)) {
23441 + u32 rxdctl = er32(RXDCTL(0));
23442 + ew32(RXDCTL(0), rxdctl | 0x3);
23443 + ew32(ERT, E1000_ERT_2048 | (1 << 13));
23445 + * With jumbo frames and early-receive enabled, excessive
23446 + * C4->C2 latencies result in dropped transactions.
23448 + pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY,
23449 + e1000e_driver_name, 55);
23451 + pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY,
23452 + e1000e_driver_name,
23453 + PM_QOS_DEFAULT_VALUE);
23456 + /* Enable Receives */
23457 + ew32(RCTL, rctl);
23461 + * e1000_set_multi - Multicast and Promiscuous mode set
23462 + * @netdev: network interface device structure
23464 + * The set_multi entry point is called whenever the multicast address
23465 + * list or the network interface flags are updated. This routine is
23466 + * responsible for configuring the hardware for proper multicast,
23467 + * promiscuous mode, and all-multi behavior.
23469 +static void e1000_set_multi(struct net_device *netdev)
23471 + struct e1000_adapter *adapter = netdev_priv(netdev);
23472 + struct e1000_hw *hw = &adapter->hw;
23473 + struct e1000_mac_info *mac = &hw->mac;
23474 + struct dev_mc_list *mc_ptr;
23479 + /* Check for Promiscuous and All Multicast modes */
23481 + rctl = er32(RCTL);
23483 + if (netdev->flags & IFF_PROMISC) {
23484 + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
23485 + } else if (netdev->flags & IFF_ALLMULTI) {
23486 + rctl |= E1000_RCTL_MPE;
23487 + rctl &= ~E1000_RCTL_UPE;
23489 + rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
23492 + ew32(RCTL, rctl);
23494 + if (netdev->mc_count) {
23495 + mta_list = kmalloc(netdev->mc_count * 6, GFP_ATOMIC);
23499 + /* prepare a packed array of only addresses. */
23500 + mc_ptr = netdev->mc_list;
23502 + for (i = 0; i < netdev->mc_count; i++) {
23505 + memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr,
23507 + mc_ptr = mc_ptr->next;
23510 + hw->mac.ops.update_mc_addr_list(hw, mta_list, i, 1,
23511 + mac->rar_entry_count);
23515 + * if we're called from probe, we might not have
23516 + * anything to do here, so clear out the list
23518 + hw->mac.ops.update_mc_addr_list(hw, NULL, 0, 1,
23519 + mac->rar_entry_count);
23524 + * e1000_configure - configure the hardware for Rx and Tx
23525 + * @adapter: private board structure
23527 +static void e1000_configure(struct e1000_adapter *adapter)
23529 + e1000_set_multi(adapter->netdev);
23531 + e1000_restore_vlan(adapter);
23532 + e1000_init_manageability(adapter);
23534 + e1000_configure_tx(adapter);
23535 + e1000_setup_rctl(adapter);
23536 + e1000_configure_rx(adapter);
23537 + adapter->alloc_rx_buf(adapter, e1000_desc_unused(adapter->rx_ring));
23541 + * e1000e_reset - bring the hardware into a known good state
23543 + * This function boots the hardware and enables some settings that
23544 + * require a configuration cycle of the hardware - those cannot be
23545 + * set/changed during runtime. After reset the device needs to be
23546 + * properly configured for Rx, Tx etc.
23548 +void e1000_reset(struct e1000_adapter *adapter)
23550 + struct e1000_mac_info *mac = &adapter->hw.mac;
23551 + struct e1000_fc_info *fc = &adapter->hw.fc;
23552 + struct e1000_hw *hw = &adapter->hw;
23553 + u32 tx_space, min_tx_space, min_rx_space;
23554 + u32 pba = adapter->pba;
23557 + /* reset Packet Buffer Allocation to default */
23560 + if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN ) {
23562 + * To maintain wire speed transmits, the Tx FIFO should be
23563 + * large enough to accommodate two full transmit packets,
23564 + * rounded up to the next 1KB and expressed in KB. Likewise,
23565 + * the Rx FIFO should be large enough to accommodate at least
23566 + * one full receive packet and is similarly rounded up and
23567 + * expressed in KB.
23570 + /* upper 16 bits has Tx packet buffer allocation size in KB */
23571 + tx_space = pba >> 16;
23572 + /* lower 16 bits has Rx packet buffer allocation size in KB */
23575 + * the Tx fifo also stores 16 bytes of information about the tx
23576 + * but don't include ethernet FCS because hardware appends it
23578 + min_tx_space = (adapter->max_frame_size +
23579 + sizeof(struct e1000_tx_desc) -
23580 + ETH_FCS_LEN) * 2;
23581 + min_tx_space = ALIGN(min_tx_space, 1024);
23582 + min_tx_space >>= 10;
23583 + /* software strips receive CRC, so leave room for it */
23584 + min_rx_space = adapter->max_frame_size;
23585 + min_rx_space = ALIGN(min_rx_space, 1024);
23586 + min_rx_space >>= 10;
23589 + * If current Tx allocation is less than the min Tx FIFO size,
23590 + * and the min Tx FIFO size is less than the current Rx FIFO
23591 + * allocation, take space away from current Rx allocation
23593 + if ((tx_space < min_tx_space) &&
23594 + ((min_tx_space - tx_space) < pba)) {
23595 + pba -= min_tx_space - tx_space;
23598 + * if short on Rx space, Rx wins and must trump tx
23599 + * adjustment or use Early Receive if available
23601 + if ((pba < min_rx_space) &&
23602 + (!(adapter->flags & FLAG_HAS_ERT)))
23603 + /* ERT enabled in e1000_configure_rx */
23604 + pba = min_rx_space;
23612 + * flow control settings
23614 + * The high water mark must be low enough to fit one full frame
23615 + * (or the size used for early receive) above it in the Rx FIFO.
23616 + * Set it to the lower of:
23617 + * - 90% of the Rx FIFO size, and
23618 + * - the full Rx FIFO size minus the early receive size (for parts
23619 + * with ERT support assuming ERT set to E1000_ERT_2048), or
23620 + * - the full Rx FIFO size minus one full frame
23622 + if (adapter->flags & FLAG_HAS_ERT)
23623 + hwm = min(((pba << 10) * 9 / 10),
23624 + ((pba << 10) - (E1000_ERT_2048 << 3)));
23626 + hwm = min(((pba << 10) * 9 / 10),
23627 + ((pba << 10) - adapter->max_frame_size));
23629 + fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
23630 + fc->low_water = fc->high_water - 8;
23632 + if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
23633 + fc->pause_time = 0xFFFF;
23635 + fc->pause_time = E1000_FC_PAUSE_TIME;
23636 + fc->send_xon = 1;
23637 + fc->type = fc->original_type;
23639 + /* Allow time for pending master requests to run */
23640 + mac->ops.reset_hw(hw);
23643 + * For parts with AMT enabled, let the firmware know
23644 + * that the network interface is in control
23646 + if (adapter->flags & FLAG_HAS_AMT)
23647 + e1000_get_hw_control(adapter);
23651 + if (mac->ops.init_hw(hw))
23652 + e_err("Hardware Error\n");
23654 + e1000_update_mng_vlan(adapter);
23656 + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
23657 + ew32(VET, ETH_P_8021Q);
23659 + e1000_reset_adaptive_generic(hw);
23661 + if (!hw->phy.ops.get_info)
23664 + hw->phy.ops.get_info(hw);
23666 + if (!(adapter->flags & FLAG_SMART_POWER_DOWN)) {
23667 + u16 phy_data = 0;
23669 + * speed up time to link by disabling smart power down, ignore
23670 + * the return value of this function because there is nothing
23671 + * different we would do if it failed
23673 + hw->phy.ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
23674 + phy_data &= ~IGP02E1000_PM_SPD;
23675 + hw->phy.ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
23679 +int e1000_up(struct e1000_adapter *adapter)
23681 + struct e1000_hw *hw = &adapter->hw;
23683 + /* hardware has been reset, we need to reload some things */
23684 + e1000_configure(adapter);
23686 + clear_bit(__E1000_DOWN, &adapter->state);
23688 +#ifdef CONFIG_E1000E_NAPI
23689 + napi_enable(&adapter->napi);
23691 +#ifdef CONFIG_E1000E_MSIX
23692 + if (adapter->msix_entries)
23693 + e1000_configure_msix(adapter);
23694 +#endif /* CONFIG_E1000E_MSIX */
23695 + e1000_irq_enable(adapter);
23697 + /* fire a link change interrupt to start the watchdog */
23698 + ew32(ICS, E1000_ICS_LSC);
23702 +void e1000_down(struct e1000_adapter *adapter)
23704 + struct net_device *netdev = adapter->netdev;
23705 + struct e1000_hw *hw = &adapter->hw;
23709 + * signal that we're down so the interrupt handler does not
23710 + * reschedule our watchdog timer
23712 + set_bit(__E1000_DOWN, &adapter->state);
23714 + /* disable receives in the hardware */
23715 + rctl = er32(RCTL);
23716 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
23717 + /* flush and sleep below */
23719 + netif_stop_queue(netdev);
23721 + /* disable transmits in the hardware */
23722 + tctl = er32(TCTL);
23723 + tctl &= ~E1000_TCTL_EN;
23724 + ew32(TCTL, tctl);
23725 + /* flush both disables and wait for them to finish */
23729 +#ifdef CONFIG_E1000E_NAPI
23730 + napi_disable(&adapter->napi);
23733 + e1000_irq_disable(adapter);
23735 + del_timer_sync(&adapter->watchdog_timer);
23736 + del_timer_sync(&adapter->phy_info_timer);
23738 + netdev->tx_queue_len = adapter->tx_queue_len;
23739 + netif_carrier_off(netdev);
23740 + adapter->link_speed = 0;
23741 + adapter->link_duplex = 0;
23743 + e1000_reset(adapter);
23744 + e1000_clean_tx_ring(adapter);
23745 + e1000_clean_rx_ring(adapter);
23748 + * TODO: for power management, we could drop the link and
23749 + * pci_disable_device here.
23753 +void e1000_reinit_locked(struct e1000_adapter *adapter)
23756 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
23758 + e1000_down(adapter);
23759 + e1000_up(adapter);
23760 + clear_bit(__E1000_RESETTING, &adapter->state);
23764 + * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
23765 + * @adapter: board private structure to initialize
23767 + * e1000_sw_init initializes the Adapter private data structure.
23768 + * Fields are initialized based on PCI device information and
23769 + * OS network device settings (MTU size).
23771 +static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
23773 + struct net_device *netdev = adapter->netdev;
23776 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
23777 + adapter->rx_ps_bsize0 = 128;
23778 + adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
23779 + adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
23781 + /* Set various function pointers */
23782 + adapter->ei->init_ops(&adapter->hw);
23784 + rc = adapter->hw.mac.ops.init_params(&adapter->hw);
23788 + rc = adapter->hw.nvm.ops.init_params(&adapter->hw);
23792 + rc = adapter->hw.phy.ops.init_params(&adapter->hw);
23796 +#ifdef CONFIG_E1000E_MSIX
23797 + e1000_set_interrupt_capability(adapter);
23799 +#endif /* CONFIG_E1000E_MSIX */
23800 + if (e1000_alloc_queues(adapter))
23803 + spin_lock_init(&adapter->tx_queue_lock);
23805 + /* Explicitly disable IRQ since the NIC can be in any state. */
23806 + e1000_irq_disable(adapter);
23808 + spin_lock_init(&adapter->stats_lock);
23810 + set_bit(__E1000_DOWN, &adapter->state);
23815 + * e1000_intr_msi_test - Interrupt Handler
23816 + * @irq: interrupt number
23817 + * @data: pointer to a network interface device structure
23819 +static irqreturn_t e1000_intr_msi_test(int irq, void *data)
23821 + struct net_device *netdev = data;
23822 + struct e1000_adapter *adapter = netdev_priv(netdev);
23823 + struct e1000_hw *hw = &adapter->hw;
23824 + u32 icr = er32(ICR);
23826 + e_dbg("icr is %08X\n", icr);
23827 + if (icr & E1000_ICR_RXSEQ) {
23828 + adapter->flags &= ~FLAG_MSI_TEST_FAILED;
23832 + return IRQ_HANDLED;
23836 + * e1000_test_msi_interrupt - Returns 0 for successful test
23837 + * @adapter: board private struct
23839 + * code flow taken from tg3.c
23841 +static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
23843 + struct net_device *netdev = adapter->netdev;
23844 + struct e1000_hw *hw = &adapter->hw;
23847 + /* poll_enable hasn't been called yet, so don't need disable */
23848 + /* clear any pending events */
23851 + /* free the real vector and request a test handler */
23852 + e1000_free_irq(adapter);
23853 +#ifdef CONFIG_E1000E_MSIX
23854 + e1000_reset_interrupt_capability(adapter);
23857 + /* Assume that the test fails, if it succeeds then the test
23858 + * MSI irq handler will unset this flag */
23859 + adapter->flags |= FLAG_MSI_TEST_FAILED;
23861 + err = pci_enable_msi(adapter->pdev);
23863 + goto msi_test_failed;
23865 + err = request_irq(adapter->pdev->irq, &e1000_intr_msi_test, 0,
23866 + netdev->name, netdev);
23868 + pci_disable_msi(adapter->pdev);
23869 + goto msi_test_failed;
23874 + e1000_irq_enable(adapter);
23876 + /* fire an unusual interrupt on the test handler */
23877 + ew32(ICS, E1000_ICS_RXSEQ);
23881 + e1000_irq_disable(adapter);
23885 + if (adapter->flags & FLAG_MSI_TEST_FAILED) {
23886 +#ifdef CONFIG_E1000E_MSIX
23887 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
23890 + e_info("MSI interrupt test failed!\n");
23893 + free_irq(adapter->pdev->irq, netdev);
23894 + pci_disable_msi(adapter->pdev);
23897 + goto msi_test_failed;
23899 + /* okay so the test worked, restore settings */
23900 + e_dbg("MSI interrupt test succeeded!\n");
23902 +#ifdef CONFIG_E1000E_MSIX
23903 + e1000_set_interrupt_capability(adapter);
23905 + /* restore the original vector, even if it failed */
23907 + e1000_request_irq(adapter);
23912 + * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
23913 + * @adapter: board private struct
23915 + * code flow taken from tg3.c, called with e1000 interrupts disabled.
23917 +static int e1000_test_msi(struct e1000_adapter *adapter)
23922 + if (!(adapter->flags & FLAG_MSI_ENABLED))
23925 + /* disable SERR in case the MSI write causes a master abort */
23926 + pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
23927 + pci_write_config_word(adapter->pdev, PCI_COMMAND,
23928 + pci_cmd & ~PCI_COMMAND_SERR);
23930 + err = e1000_test_msi_interrupt(adapter);
23932 + /* restore previous setting of command word */
23933 + pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
23939 + /* EIO means MSI test failed */
23943 + /* back to INTx mode */
23944 + e_warn("MSI interrupt test failed, using legacy interrupt.\n");
23946 + e1000_free_irq(adapter);
23948 + err = e1000_request_irq(adapter);
23954 + * e1000_open - Called when a network interface is made active
23955 + * @netdev: network interface device structure
23957 + * Returns 0 on success, negative value on failure
23959 + * The open entry point is called when a network interface is made
23960 + * active by the system (IFF_UP). At this point all resources needed
23961 + * for transmit and receive operations are allocated, the interrupt
23962 + * handler is registered with the OS, the watchdog timer is started,
23963 + * and the stack is notified that the interface is ready.
23965 +static int e1000_open(struct net_device *netdev)
23967 + struct e1000_adapter *adapter = netdev_priv(netdev);
23968 + struct e1000_hw *hw = &adapter->hw;
23971 + /* disallow open during test */
23972 + if (test_bit(__E1000_TESTING, &adapter->state))
23975 + /* allocate transmit descriptors */
23976 + err = e1000_setup_tx_resources(adapter);
23978 + goto err_setup_tx;
23980 + /* allocate receive descriptors */
23981 + err = e1000_setup_rx_resources(adapter);
23983 + goto err_setup_rx;
23985 + e1000_power_up_phy(hw);
23987 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
23988 + if ((adapter->hw.mng_cookie.status &
23989 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
23990 + e1000_update_mng_vlan(adapter);
23993 + * If AMT is enabled, let the firmware know that the network
23994 + * interface is now open
23996 + if (adapter->flags & FLAG_HAS_AMT)
23997 + e1000_get_hw_control(adapter);
24000 + * before we allocate an interrupt, we must be ready to handle it.
24001 + * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
24002 + * as soon as we call pci_request_irq, so we have to setup our
24003 + * clean_rx handler before we do so.
24005 + e1000_configure(adapter);
24007 + err = e1000_request_irq(adapter);
24009 + goto err_req_irq;
24012 + * Work around PCIe errata with MSI interrupts causing some chipsets to
24013 + * ignore e1000e MSI messages, which means we need to test our MSI
24016 +#ifdef CONFIG_E1000E_MSIX
24017 + if (adapter->int_mode != E1000E_INT_MODE_LEGACY)
24020 + err = e1000_test_msi(adapter);
24022 + e_err("Interrupt allocation failed\n");
24023 + goto err_req_irq;
24027 + /* From here on the code is the same as e1000_up() */
24028 + clear_bit(__E1000_DOWN, &adapter->state);
24030 +#ifdef CONFIG_E1000E_NAPI
24031 + napi_enable(&adapter->napi);
24034 + e1000_irq_enable(adapter);
24036 + /* fire a link status change interrupt to start the watchdog */
24037 + ew32(ICS, E1000_ICS_LSC);
24042 + e1000_release_hw_control(adapter);
24043 + if (!adapter->wol && hw->phy.ops.power_down)
24044 + hw->phy.ops.power_down(hw);
24045 + e1000_free_rx_resources(adapter);
24047 + e1000_free_tx_resources(adapter);
24049 + e1000_reset(adapter);
24055 + * e1000_close - Disables a network interface
24056 + * @netdev: network interface device structure
24058 + * Returns 0, this is not allowed to fail
24060 + * The close entry point is called when an interface is de-activated
24061 + * by the OS. The hardware is still under the drivers control, but
24062 + * needs to be disabled. A global MAC reset is issued to stop the
24063 + * hardware, and all transmit and receive resources are freed.
24065 +static int e1000_close(struct net_device *netdev)
24067 + struct e1000_adapter *adapter = netdev_priv(netdev);
24068 + struct e1000_hw *hw = &adapter->hw;
24070 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
24071 + e1000_down(adapter);
24072 + if (!adapter->wol && hw->phy.ops.power_down)
24073 + hw->phy.ops.power_down(hw);
24074 + e1000_free_irq(adapter);
24076 + e1000_free_tx_resources(adapter);
24077 + e1000_free_rx_resources(adapter);
24080 + * kill manageability vlan ID if supported, but not if a vlan with
24081 + * the same ID is registered on the host OS (let 8021q kill it)
24083 + if ((adapter->hw.mng_cookie.status &
24084 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
24085 + !(adapter->vlgrp &&
24086 + vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
24087 + e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
24090 + * If AMT is enabled, let the firmware know that the network
24091 + * interface is now closed
24093 + if (adapter->flags & FLAG_HAS_AMT)
24094 + e1000_release_hw_control(adapter);
24099 + * e1000_set_mac - Change the Ethernet Address of the NIC
24100 + * @netdev: network interface device structure
24101 + * @p: pointer to an address structure
24103 + * Returns 0 on success, negative on failure
24105 +static int e1000_set_mac(struct net_device *netdev, void *p)
24107 + struct e1000_adapter *adapter = netdev_priv(netdev);
24108 + struct sockaddr *addr = p;
24110 + if (!is_valid_ether_addr(addr->sa_data))
24111 + return -EADDRNOTAVAIL;
24113 + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
24114 + memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
24116 + adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
24118 + if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
24119 + /* activate the work around */
24120 + e1000_set_laa_state_82571(&adapter->hw, 1);
24123 + * Hold a copy of the LAA in RAR[14] This is done so that
24124 + * between the time RAR[0] gets clobbered and the time it
24125 + * gets fixed (in e1000_watchdog), the actual LAA is in one
24126 + * of the RARs and no incoming packets directed to this port
24127 + * are dropped. Eventually the LAA will be in RAR[0] and
24130 + adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
24131 + adapter->hw.mac.rar_entry_count - 1);
24138 + * Need to wait a few seconds after link up to get diagnostic information from
24141 +static void e1000_update_phy_info(unsigned long data)
24143 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
24144 + if (adapter->hw.phy.ops.get_info)
24145 + adapter->hw.phy.ops.get_info(&adapter->hw);
24149 + * e1000_update_stats - Update the board statistics counters
24150 + * @adapter: board private structure
24152 +void e1000_update_stats(struct e1000_adapter *adapter)
24154 + struct e1000_hw *hw = &adapter->hw;
24155 +#ifdef HAVE_PCI_ERS
24156 + struct pci_dev *pdev = adapter->pdev;
24158 + unsigned long irq_flags;
24161 +#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
24164 + * Prevent stats update while adapter is being reset, or if the pci
24165 + * connection is down.
24167 + if (adapter->link_speed == 0)
24169 +#ifdef HAVE_PCI_ERS
24170 + if (pci_channel_offline(pdev))
24174 + spin_lock_irqsave(&adapter->stats_lock, irq_flags);
24177 + * these counters are modified from e1000_adjust_tbi_stats,
24178 + * called from the interrupt context, so they must only
24179 + * be written while holding adapter->stats_lock
24182 + adapter->stats.crcerrs += er32(CRCERRS);
24183 + adapter->stats.gprc += er32(GPRC);
24184 + adapter->stats.gorc += er32(GORCL);
24185 + er32(GORCH); /* Clear gorc */
24186 + adapter->stats.bprc += er32(BPRC);
24187 + adapter->stats.mprc += er32(MPRC);
24188 + adapter->stats.roc += er32(ROC);
24190 + adapter->stats.mpc += er32(MPC);
24191 + adapter->stats.scc += er32(SCC);
24192 + adapter->stats.ecol += er32(ECOL);
24193 + adapter->stats.mcc += er32(MCC);
24194 + adapter->stats.latecol += er32(LATECOL);
24195 + adapter->stats.dc += er32(DC);
24196 + adapter->stats.xonrxc += er32(XONRXC);
24197 + adapter->stats.xontxc += er32(XONTXC);
24198 + adapter->stats.xoffrxc += er32(XOFFRXC);
24199 + adapter->stats.xofftxc += er32(XOFFTXC);
24200 + adapter->stats.gptc += er32(GPTC);
24201 + adapter->stats.gotc += er32(GOTCL);
24202 + er32(GOTCH); /* Clear gotc */
24203 + adapter->stats.rnbc += er32(RNBC);
24204 + adapter->stats.ruc += er32(RUC);
24206 + adapter->stats.mptc += er32(MPTC);
24207 + adapter->stats.bptc += er32(BPTC);
24209 + /* used for adaptive IFS */
24211 + hw->mac.tx_packet_delta = er32(TPT);
24212 + adapter->stats.tpt += hw->mac.tx_packet_delta;
24213 + hw->mac.collision_delta = er32(COLC);
24214 + adapter->stats.colc += hw->mac.collision_delta;
24216 + adapter->stats.algnerrc += er32(ALGNERRC);
24217 + adapter->stats.rxerrc += er32(RXERRC);
24218 + if (hw->mac.type != e1000_82574)
24219 + adapter->stats.tncrs += er32(TNCRS);
24220 + adapter->stats.cexterr += er32(CEXTERR);
24221 + adapter->stats.tsctc += er32(TSCTC);
24222 + adapter->stats.tsctfc += er32(TSCTFC);
24224 + /* Fill out the OS statistics structure */
24225 + adapter->net_stats.multicast = adapter->stats.mprc;
24226 + adapter->net_stats.collisions = adapter->stats.colc;
24231 + * RLEC on some newer hardware can be incorrect so build
24232 + * our own version based on RUC and ROC
24234 + adapter->net_stats.rx_errors = adapter->stats.rxerrc +
24235 + adapter->stats.crcerrs + adapter->stats.algnerrc +
24236 + adapter->stats.ruc + adapter->stats.roc +
24237 + adapter->stats.cexterr;
24238 + adapter->net_stats.rx_length_errors = adapter->stats.ruc +
24239 + adapter->stats.roc;
24240 + adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
24241 + adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
24242 + adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
24245 + adapter->net_stats.tx_errors = adapter->stats.ecol +
24246 + adapter->stats.latecol;
24247 + adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
24248 + adapter->net_stats.tx_window_errors = adapter->stats.latecol;
24249 + adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
24251 + /* Tx Dropped needs to be maintained elsewhere */
24254 + if (hw->phy.media_type == e1000_media_type_copper) {
24255 + if ((adapter->link_speed == SPEED_1000) &&
24256 + (!hw->phy.ops.read_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
24257 + phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
24258 + adapter->phy_stats.idle_errors += phy_tmp;
24262 + /* Management Stats */
24263 + adapter->stats.mgptc += er32(MGTPTC);
24264 + adapter->stats.mgprc += er32(MGTPRC);
24265 + adapter->stats.mgpdc += er32(MGTPDC);
24267 + spin_unlock_irqrestore(&adapter->stats_lock, irq_flags);
24270 +#ifdef SIOCGMIIPHY
24272 + * e1000_phy_read_status - Update the PHY register status snapshot
24273 + * @adapter: board private structure
24275 +static void e1000_phy_read_status(struct e1000_adapter *adapter)
24277 + struct e1000_hw *hw = &adapter->hw;
24278 + struct e1000_phy_regs *phy = &adapter->phy_regs;
24280 + unsigned long irq_flags;
24283 + spin_lock_irqsave(&adapter->stats_lock, irq_flags);
24285 + if ((er32(STATUS) & E1000_STATUS_LU) &&
24286 + (adapter->hw.phy.media_type == e1000_media_type_copper)) {
24287 + ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy->bmcr);
24288 + ret_val |= hw->phy.ops.read_reg(hw, PHY_STATUS, &phy->bmsr);
24289 + ret_val |= hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
24290 + &phy->advertise);
24291 + ret_val |= hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, &phy->lpa);
24292 + ret_val |= hw->phy.ops.read_reg(hw, PHY_AUTONEG_EXP,
24293 + &phy->expansion);
24294 + ret_val |= hw->phy.ops.read_reg(hw, PHY_1000T_CTRL,
24296 + ret_val |= hw->phy.ops.read_reg(hw, PHY_1000T_STATUS,
24298 + ret_val |= hw->phy.ops.read_reg(hw, PHY_EXT_STATUS,
24301 + e_warn("Error reading PHY register\n");
24304 + * Do not read PHY registers if link is not up
24305 + * Set values to typical power-on defaults
24307 + phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
24308 + phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
24309 + BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
24311 + phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
24312 + ADVERTISE_ALL | ADVERTISE_CSMA);
24314 + phy->expansion = EXPANSION_ENABLENPAGE;
24315 + phy->ctrl1000 = ADVERTISE_1000FULL;
24316 + phy->stat1000 = 0;
24317 + phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
24320 + spin_unlock_irqrestore(&adapter->stats_lock, irq_flags);
24323 +#endif /* SIOCGMIIPHY */
24324 +static void e1000_print_link_info(struct e1000_adapter *adapter)
24326 + struct e1000_hw *hw = &adapter->hw;
24327 + u32 ctrl = er32(CTRL);
24329 + e_info("Link is Up %d Mbps %s, Flow Control: %s\n",
24330 + adapter->link_speed,
24331 + (adapter->link_duplex == FULL_DUPLEX) ?
24332 + "Full Duplex" : "Half Duplex",
24333 + ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ?
24335 + ((ctrl & E1000_CTRL_RFCE) ? "RX" :
24336 + ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None" )));
24339 +static bool e1000_has_link(struct e1000_adapter *adapter)
24341 + struct e1000_hw *hw = &adapter->hw;
24342 + bool link_active = 0;
24346 + * get_link_status is set on LSC (link status) interrupt or
24347 + * Rx sequence error interrupt. get_link_status will stay
24348 + * false until the check_for_link establishes link
24349 + * for copper adapters ONLY
24351 + switch (hw->phy.media_type) {
24352 + case e1000_media_type_copper:
24353 + if (hw->mac.get_link_status) {
24354 + ret_val = hw->mac.ops.check_for_link(hw);
24355 + link_active = !hw->mac.get_link_status;
24360 + case e1000_media_type_fiber:
24361 + ret_val = hw->mac.ops.check_for_link(hw);
24362 + link_active = !!(er32(STATUS) & E1000_STATUS_LU);
24364 + case e1000_media_type_internal_serdes:
24365 + ret_val = hw->mac.ops.check_for_link(hw);
24366 + link_active = adapter->hw.mac.serdes_has_link;
24369 + case e1000_media_type_unknown:
24373 + if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
24374 + (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
24375 + /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
24376 + e_info("Gigabit has been disabled, downgrading speed\n");
24379 + return link_active;
24382 +static void e1000e_enable_receives(struct e1000_adapter *adapter)
24384 + /* make sure the receive unit is started */
24385 + if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
24386 + (adapter->flags & FLAG_RX_RESTART_NOW)) {
24387 + struct e1000_hw *hw = &adapter->hw;
24388 + u32 rctl = er32(RCTL);
24389 + ew32(RCTL, rctl | E1000_RCTL_EN);
24390 + adapter->flags &= ~FLAG_RX_RESTART_NOW;
24395 + * e1000_watchdog - Timer Call-back
24396 + * @data: pointer to adapter cast into an unsigned long
24398 +static void e1000_watchdog(unsigned long data)
24400 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
24402 + /* Do the rest outside of interrupt context */
24403 + schedule_work(&adapter->watchdog_task);
24405 + /* TODO: make this use queue_delayed_work() */
24408 +static void e1000_watchdog_task(struct work_struct *work)
24410 + struct e1000_adapter *adapter = container_of(work,
24411 + struct e1000_adapter, watchdog_task);
24412 + struct net_device *netdev = adapter->netdev;
24413 + struct e1000_mac_info *mac = &adapter->hw.mac;
24414 + struct e1000_ring *tx_ring = adapter->tx_ring;
24415 + struct e1000_hw *hw = &adapter->hw;
24417 + int tx_pending = 0;
24418 + unsigned long timer_val;
24420 + link = e1000_has_link(adapter);
24421 + if ((netif_carrier_ok(netdev)) && link) {
24422 + e1000e_enable_receives(adapter);
24426 + if ((e1000_enable_tx_pkt_filtering_generic(hw)) &&
24427 + (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
24428 + e1000_update_mng_vlan(adapter);
24431 + if (!netif_carrier_ok(netdev)) {
24433 +#ifdef SIOCGMIIPHY
24434 + /* update snapshot of PHY registers on LSC */
24435 + e1000_phy_read_status(adapter);
24437 + mac->ops.get_link_up_info(&adapter->hw,
24438 + &adapter->link_speed,
24439 + &adapter->link_duplex);
24440 + e1000_print_link_info(adapter);
24443 + * On supported PHYs, check for duplex mismatch only
24444 + * if link has autonegotiated at 10/100 half
24446 + if ((hw->phy.type == e1000_phy_igp_3 ||
24447 + hw->phy.type == e1000_phy_bm) &&
24448 + (hw->mac.autoneg == TRUE) &&
24449 + (adapter->link_speed == SPEED_10 ||
24450 + adapter->link_speed == SPEED_100) &&
24451 + (adapter->link_duplex == HALF_DUPLEX)) {
24454 + hw->phy.ops.read_reg(hw, PHY_AUTONEG_EXP,
24457 + if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
24458 + e_info("Autonegotiated half duplex but"
24459 + " link partner cannot autoneg. "
24460 + " Try forcing full duplex if "
24461 + "link gets many collisions.");
24465 + * tweak tx_queue_len according to speed/duplex
24466 + * and adjust the timeout factor
24468 + netdev->tx_queue_len = adapter->tx_queue_len;
24469 + adapter->tx_timeout_factor = 1;
24470 + switch (adapter->link_speed) {
24473 + netdev->tx_queue_len = 10;
24474 + adapter->tx_timeout_factor = 16;
24478 + netdev->tx_queue_len = 100;
24479 + /* maybe add some timeout factor ? */
24484 + * workaround: re-program speed mode bit after
24487 + if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
24490 + tarc0 = er32(TARC(0));
24491 + tarc0 &= ~SPEED_MODE_BIT;
24492 + ew32(TARC(0), tarc0);
24495 +#ifdef NETIF_F_TSO
24497 + * disable TSO for pcie and 10/100 speeds, to avoid
24498 + * some hardware issues
24500 + if (!(adapter->flags & FLAG_TSO_FORCE)) {
24501 + switch (adapter->link_speed) {
24504 + e_info("10/100 speed: disabling TSO\n");
24505 + netdev->features &= ~NETIF_F_TSO;
24506 +#ifdef NETIF_F_TSO6
24507 + netdev->features &= ~NETIF_F_TSO6;
24511 + netdev->features |= NETIF_F_TSO;
24512 +#ifdef NETIF_F_TSO6
24513 + netdev->features |= NETIF_F_TSO6;
24524 + * enable transmits in the hardware, need to do this
24525 + * after setting TARC(0)
24527 + tctl = er32(TCTL);
24528 + tctl |= E1000_TCTL_EN;
24529 + ew32(TCTL, tctl);
24531 + netif_carrier_on(netdev);
24532 + netif_wake_queue(netdev);
24535 + if (netif_carrier_ok(netdev)) {
24536 + adapter->link_speed = 0;
24537 + adapter->link_duplex = 0;
24538 + e_info("Link is Down\n");
24539 + netif_carrier_off(netdev);
24540 + netif_stop_queue(netdev);
24542 + if (adapter->flags & FLAG_RX_NEEDS_RESTART)
24543 + schedule_work(&adapter->reset_task);
24548 + e1000_update_stats(adapter);
24550 + mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
24551 + adapter->tpt_old = adapter->stats.tpt;
24552 + mac->collision_delta = adapter->stats.colc - adapter->colc_old;
24553 + adapter->colc_old = adapter->stats.colc;
24555 + adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
24556 + adapter->gorc_old = adapter->stats.gorc;
24557 + adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
24558 + adapter->gotc_old = adapter->stats.gotc;
24560 + e1000_update_adaptive_generic(&adapter->hw);
24562 + if (!netif_carrier_ok(netdev)) {
24563 + tx_pending = (e1000_desc_unused(tx_ring) + 1 <
24565 + if (tx_pending) {
24567 + * We've lost link, so the controller stops DMA,
24568 + * but we've got queued Tx work that's never going
24569 + * to get done, so reset controller to flush Tx.
24570 + * (Do the reset outside of interrupt context).
24572 + adapter->tx_timeout_count++;
24573 + schedule_work(&adapter->reset_task);
24577 + /* Cause software interrupt to ensure Rx ring is cleaned */
24578 +#ifdef CONFIG_E1000E_MSIX
24579 + if (adapter->msix_entries)
24580 + ew32(ICS, adapter->rx_ring->ims_val);
24583 + ew32(ICS, E1000_ICS_RXDMT0);
24585 + /* Force detection of hung controller every watchdog period */
24586 + adapter->detect_tx_hung = 1;
24589 + * With 82571 controllers, LAA may be overwritten due to controller
24590 + * reset from the other port. Set the appropriate LAA in RAR[0]
24592 + if (e1000_get_laa_state_82571(hw))
24593 + hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
24595 + /* Reset the timer */
24596 + if (!test_bit(__E1000_DOWN, &adapter->state)) {
24597 + timer_val = jiffies + usecs_to_jiffies(adapter->stats_freq_us);
24598 + if (adapter->stats_freq_us > 1000000)
24599 + timer_val = round_jiffies(timer_val);
24600 + mod_timer(&adapter->watchdog_timer, timer_val);
24604 +#define E1000_TX_FLAGS_CSUM 0x00000001
24605 +#define E1000_TX_FLAGS_VLAN 0x00000002
24606 +#define E1000_TX_FLAGS_TSO 0x00000004
24607 +#define E1000_TX_FLAGS_IPV4 0x00000008
24608 +#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
24609 +#define E1000_TX_FLAGS_VLAN_SHIFT 16
24611 +static int e1000_tso(struct e1000_adapter *adapter,
24612 + struct sk_buff *skb)
24614 +#ifdef NETIF_F_TSO
24615 + struct e1000_ring *tx_ring = adapter->tx_ring;
24616 + struct e1000_context_desc *context_desc;
24617 + struct e1000_buffer *buffer_info;
24619 + u32 cmd_length = 0;
24620 + u16 ipcse = 0, tucse, mss;
24621 + u8 ipcss, ipcso, tucss, tucso, hdr_len;
24624 + if (!skb_is_gso(skb))
24627 + if (skb_header_cloned(skb)) {
24628 + err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
24633 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
24634 + mss = skb_shinfo(skb)->gso_size;
24635 + if (skb->protocol == htons(ETH_P_IP)) {
24636 + struct iphdr *iph = ip_hdr(skb);
24637 + iph->tot_len = 0;
24639 + tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
24643 + cmd_length = E1000_TXD_CMD_IP;
24644 + ipcse = skb_transport_offset(skb) - 1;
24645 +#ifdef NETIF_F_TSO6
24646 + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
24647 + ipv6_hdr(skb)->payload_len = 0;
24648 + tcp_hdr(skb)->check =
24649 + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
24650 + &ipv6_hdr(skb)->daddr,
24651 + 0, IPPROTO_TCP, 0);
24655 + ipcss = skb_network_offset(skb);
24656 + ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
24657 + tucss = skb_transport_offset(skb);
24658 + tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
24661 + cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
24662 + E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
24664 + i = tx_ring->next_to_use;
24665 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
24666 + buffer_info = &tx_ring->buffer_info[i];
24668 + context_desc->lower_setup.ip_fields.ipcss = ipcss;
24669 + context_desc->lower_setup.ip_fields.ipcso = ipcso;
24670 + context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
24671 + context_desc->upper_setup.tcp_fields.tucss = tucss;
24672 + context_desc->upper_setup.tcp_fields.tucso = tucso;
24673 + context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
24674 + context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
24675 + context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
24676 + context_desc->cmd_and_length = cpu_to_le32(cmd_length);
24678 + buffer_info->time_stamp = jiffies;
24679 + buffer_info->next_to_watch = i;
24682 + if (i == tx_ring->count)
24684 + tx_ring->next_to_use = i;
24692 +static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
24694 + struct e1000_ring *tx_ring = adapter->tx_ring;
24695 + struct e1000_context_desc *context_desc;
24696 + struct e1000_buffer *buffer_info;
24699 + u32 cmd_len = E1000_TXD_CMD_DEXT;
24701 + if (skb->ip_summed != CHECKSUM_PARTIAL)
24704 + switch (skb->protocol) {
24705 + case __constant_htons(ETH_P_IP):
24706 + if (ip_hdr(skb)->protocol == IPPROTO_TCP)
24707 + cmd_len |= E1000_TXD_CMD_TCP;
24709 + case __constant_htons(ETH_P_IPV6):
24710 + /* XXX not handling all IPV6 headers */
24711 + if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
24712 + cmd_len |= E1000_TXD_CMD_TCP;
24715 + if (unlikely(net_ratelimit()))
24716 + e_warn("checksum_partial proto=%x!\n", skb->protocol);
24720 + css = skb_transport_offset(skb);
24722 + i = tx_ring->next_to_use;
24723 + buffer_info = &tx_ring->buffer_info[i];
24724 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
24726 + context_desc->lower_setup.ip_config = 0;
24727 + context_desc->upper_setup.tcp_fields.tucss = css;
24728 + context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
24729 + context_desc->upper_setup.tcp_fields.tucse = 0;
24730 + context_desc->tcp_seg_setup.data = 0;
24731 + context_desc->cmd_and_length = cpu_to_le32(cmd_len);
24733 + buffer_info->time_stamp = jiffies;
24734 + buffer_info->next_to_watch = i;
24737 + if (i == tx_ring->count)
24739 + tx_ring->next_to_use = i;
24744 +#define E1000_MAX_PER_TXD 8192
24745 +#define E1000_MAX_TXD_PWR 12
24747 +static int e1000_tx_map(struct e1000_adapter *adapter,
24748 + struct sk_buff *skb, unsigned int first,
24749 + unsigned int max_per_txd, unsigned int nr_frags,
24750 + unsigned int mss)
24752 + struct e1000_ring *tx_ring = adapter->tx_ring;
24753 + struct pci_dev *pdev = adapter->pdev;
24754 + struct e1000_buffer *buffer_info;
24755 + unsigned int len = skb->len - skb->data_len;
24756 + unsigned int offset = 0, size, count = 0, i;
24759 + i = tx_ring->next_to_use;
24762 + buffer_info = &tx_ring->buffer_info[i];
24763 + size = min(len, max_per_txd);
24765 + buffer_info->length = size;
24766 + /* set time_stamp *before* dma to help avoid a possible race */
24767 + buffer_info->time_stamp = jiffies;
24768 + buffer_info->dma =
24769 + pci_map_single(adapter->pdev,
24770 + skb->data + offset,
24772 + PCI_DMA_TODEVICE);
24773 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
24774 + dev_err(&pdev->dev, "TX DMA map failed\n");
24775 + adapter->tx_dma_failed++;
24778 + buffer_info->next_to_watch = i;
24784 + if (i == tx_ring->count)
24788 + for (f = 0; f < nr_frags; f++) {
24789 + struct skb_frag_struct *frag;
24791 + frag = &skb_shinfo(skb)->frags[f];
24792 + len = frag->size;
24793 + offset = frag->page_offset;
24796 + buffer_info = &tx_ring->buffer_info[i];
24797 + size = min(len, max_per_txd);
24799 + buffer_info->length = size;
24800 + buffer_info->time_stamp = jiffies;
24801 + buffer_info->dma =
24802 + pci_map_page(adapter->pdev,
24806 + PCI_DMA_TODEVICE);
24807 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
24808 + dev_err(&adapter->pdev->dev,
24809 + "TX DMA page map failed\n");
24810 + adapter->tx_dma_failed++;
24814 + buffer_info->next_to_watch = i;
24821 + if (i == tx_ring->count)
24827 + i = tx_ring->count - 1;
24831 + tx_ring->buffer_info[i].skb = skb;
24832 + tx_ring->buffer_info[first].next_to_watch = i;
24837 +static void e1000_tx_queue(struct e1000_adapter *adapter,
24838 + int tx_flags, int count)
24840 + struct e1000_ring *tx_ring = adapter->tx_ring;
24841 + struct e1000_tx_desc *tx_desc = NULL;
24842 + struct e1000_buffer *buffer_info;
24843 + u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
24846 + if (tx_flags & E1000_TX_FLAGS_TSO) {
24847 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
24848 + E1000_TXD_CMD_TSE;
24849 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
24851 + if (tx_flags & E1000_TX_FLAGS_IPV4)
24852 + txd_upper |= E1000_TXD_POPTS_IXSM << 8;
24855 + if (tx_flags & E1000_TX_FLAGS_CSUM) {
24856 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
24857 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
24860 + if (tx_flags & E1000_TX_FLAGS_VLAN) {
24861 + txd_lower |= E1000_TXD_CMD_VLE;
24862 + txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
24865 + i = tx_ring->next_to_use;
24867 + while (count--) {
24868 + buffer_info = &tx_ring->buffer_info[i];
24869 + tx_desc = E1000_TX_DESC(*tx_ring, i);
24870 + tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
24871 + tx_desc->lower.data =
24872 + cpu_to_le32(txd_lower | buffer_info->length);
24873 + tx_desc->upper.data = cpu_to_le32(txd_upper);
24876 + if (i == tx_ring->count)
24880 + tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
24883 + * Force memory writes to complete before letting h/w
24884 + * know there are new descriptors to fetch. (Only
24885 + * applicable for weak-ordered memory model archs,
24886 + * such as IA-64).
24890 + tx_ring->next_to_use = i;
24891 + writel(i, adapter->hw.hw_addr + tx_ring->tail);
24893 + * we need this if more than one processor can write to our tail
24894 + * at a time, it synchronizes IO on IA64/Altix systems
24899 +#define MINIMUM_DHCP_PACKET_SIZE 282
24900 +static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
24901 + struct sk_buff *skb)
24903 + struct e1000_hw *hw = &adapter->hw;
24904 + u16 length, offset;
24906 + if (vlan_tx_tag_present(skb)) {
24907 + if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id)
24908 + && (adapter->hw.mng_cookie.status &
24909 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
24913 + if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
24916 + if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
24920 + const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
24921 + struct udphdr *udp;
24923 + if (ip->protocol != IPPROTO_UDP)
24926 + udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
24927 + if (ntohs(udp->dest) != 67)
24930 + offset = (u8 *)udp + 8 - skb->data;
24931 + length = skb->len - offset;
24932 + return e1000_mng_write_dhcp_info_generic(hw, (u8 *)udp + 8,
24939 +static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
24941 + struct e1000_adapter *adapter = netdev_priv(netdev);
24943 + netif_stop_queue(netdev);
24945 + * Herbert's original patch had:
24946 + * smp_mb__after_netif_stop_queue();
24947 + * but since that doesn't exist yet, just open code it.
24952 + * We need to check again in a case another CPU has just
24953 + * made room available.
24955 + if (e1000_desc_unused(adapter->tx_ring) < size)
24958 + /* A reprieve! */
24959 + netif_start_queue(netdev);
24960 + ++adapter->restart_queue;
24964 +static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
24966 + struct e1000_adapter *adapter = netdev_priv(netdev);
24968 + if (e1000_desc_unused(adapter->tx_ring) >= size)
24970 + return __e1000_maybe_stop_tx(netdev, size);
24973 +#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
24974 +static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
24976 + struct e1000_adapter *adapter = netdev_priv(netdev);
24977 + struct e1000_ring *tx_ring = adapter->tx_ring;
24978 + unsigned int first;
24979 + unsigned int max_per_txd = E1000_MAX_PER_TXD;
24980 + unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
24981 + unsigned int tx_flags = 0;
24982 + unsigned int len = skb->len - skb->data_len;
24983 +#ifdef NETIF_F_LLTX
24984 + unsigned long irq_flags;
24986 + unsigned int nr_frags;
24987 + unsigned int mss = 0;
24992 + if (test_bit(__E1000_DOWN, &adapter->state)) {
24993 + dev_kfree_skb_any(skb);
24994 + return NETDEV_TX_OK;
24997 + if (skb->len <= 0) {
24998 + dev_kfree_skb_any(skb);
24999 + return NETDEV_TX_OK;
25002 +#ifdef NETIF_F_TSO
25003 + mss = skb_shinfo(skb)->gso_size;
25005 + * The controller does a simple calculation to
25006 + * make sure there is enough room in the FIFO before
25007 + * initiating the DMA for each buffer. The calc is:
25008 + * 4 = ceil(buffer len/mss). To make sure we don't
25009 + * overrun the FIFO, adjust the max buffer len if mss
25014 + max_per_txd = min(mss << 2, max_per_txd);
25015 + max_txd_pwr = fls(max_per_txd) - 1;
25018 + * TSO Workaround for 82571/2/3 Controllers -- if skb->data
25019 + * points to just header, pull a few bytes of payload from
25020 + * frags into skb->data
25022 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
25024 + * we do this workaround for ES2LAN, but it is un-necessary,
25025 + * avoiding it could save a lot of cycles
25027 + if (skb->data_len && (hdr_len == len)) {
25028 + unsigned int pull_size;
25030 + pull_size = min((unsigned int)4, skb->data_len);
25031 + if (!__pskb_pull_tail(skb, pull_size)) {
25032 + e_err("__pskb_pull_tail failed.\n");
25033 + dev_kfree_skb_any(skb);
25034 + return NETDEV_TX_OK;
25036 + len = skb->len - skb->data_len;
25040 + /* reserve a descriptor for the offload context */
25041 + if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
25045 + if (skb->ip_summed == CHECKSUM_PARTIAL)
25049 + count += TXD_USE_COUNT(len, max_txd_pwr);
25051 + nr_frags = skb_shinfo(skb)->nr_frags;
25052 + for (f = 0; f < nr_frags; f++)
25053 + count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
25056 + if (adapter->hw.mac.tx_pkt_filtering)
25057 + e1000_transfer_dhcp_info(adapter, skb);
25059 +#ifdef NETIF_F_LLTX
25060 + if (!spin_trylock_irqsave(&adapter->tx_queue_lock, irq_flags))
25061 + /* Collision - tell upper layer to requeue */
25062 + return NETDEV_TX_LOCKED;
25066 + * need: count + 2 desc gap to keep tail from touching
25067 + * head, otherwise try next time
25069 + if (e1000_maybe_stop_tx(netdev, count + 2)) {
25070 +#ifdef NETIF_F_LLTX
25071 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
25073 + return NETDEV_TX_BUSY;
25076 + if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
25077 + tx_flags |= E1000_TX_FLAGS_VLAN;
25078 + tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
25081 + first = tx_ring->next_to_use;
25083 + tso = e1000_tso(adapter, skb);
25084 + if (unlikely(tso < 0)) {
25085 + dev_kfree_skb_any(skb);
25086 +#ifdef NETIF_F_LLTX
25087 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
25089 + return NETDEV_TX_OK;
25093 + tx_flags |= E1000_TX_FLAGS_TSO;
25094 + else if (e1000_tx_csum(adapter, skb))
25095 + tx_flags |= E1000_TX_FLAGS_CSUM;
25098 + * Old method was to assume IPv4 packet by default if TSO was enabled.
25099 + * 82571 hardware supports TSO capabilities for IPv6 as well...
25100 + * no longer assume, we must.
25102 + if (skb->protocol == htons(ETH_P_IP))
25103 + tx_flags |= E1000_TX_FLAGS_IPV4;
25105 + count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
25106 + if (unlikely(count < 0)) {
25107 + /* handle pci_map_single() error in e1000_tx_map */
25108 + dev_kfree_skb_any(skb);
25109 +#ifdef NETIF_F_LLTX
25110 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
25112 + return NETDEV_TX_OK;
25115 + e1000_tx_queue(adapter, tx_flags, count);
25117 + netdev->trans_start = jiffies;
25119 + /* Make sure there is space in the ring for the next send. */
25120 + e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2);
25122 +#ifdef NETIF_F_LLTX
25123 + spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
25125 + return NETDEV_TX_OK;
25129 + * e1000_tx_timeout - Respond to a Tx Hang
25130 + * @netdev: network interface device structure
25132 +static void e1000_tx_timeout(struct net_device *netdev)
25134 + struct e1000_adapter *adapter = netdev_priv(netdev);
25136 + /* Do the reset outside of interrupt context */
25137 + adapter->tx_timeout_count++;
25138 + schedule_work(&adapter->reset_task);
25141 +static void e1000_reset_task(struct work_struct *work)
25143 + struct e1000_adapter *adapter;
25144 + adapter = container_of(work, struct e1000_adapter, reset_task);
25146 + e1000_reinit_locked(adapter);
25150 + * e1000_get_stats - Get System Network Statistics
25151 + * @netdev: network interface device structure
25153 + * Returns the address of the device statistics structure.
25154 + * The statistics are actually updated from the timer callback.
25156 +static struct net_device_stats *e1000_get_stats(struct net_device *netdev)
25158 + struct e1000_adapter *adapter = netdev_priv(netdev);
25160 + /* only return the current stats */
25161 + return &adapter->net_stats;
25165 + * e1000_change_mtu - Change the Maximum Transfer Unit
25166 + * @netdev: network interface device structure
25167 + * @new_mtu: new value for maximum frame size
25169 + * Returns 0 on success, negative on failure
25171 +static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
25173 + struct e1000_adapter *adapter = netdev_priv(netdev);
25174 + int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
25176 + if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
25177 + e_err("Invalid MTU setting\n");
25181 + /* Jumbo frame size limits */
25182 + if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
25183 + if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
25184 + e_err("Jumbo Frames not supported.\n");
25189 +#define MAX_STD_JUMBO_FRAME_SIZE 9234
25190 + if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
25191 + e_err("MTU > 9216 not supported.\n");
25195 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
25197 + /* e1000_down has a dependency on max_frame_size */
25198 + adapter->max_frame_size = max_frame;
25199 + if (netif_running(netdev))
25200 + e1000_down(adapter);
25203 + * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
25204 + * means we reserve 2 more, this pushes us to allocate from the next
25205 + * larger slab size.
25206 + * i.e. RXBUFFER_2048 --> size-4096 slab
25207 + * However with the new *_jumbo_rx* routines, jumbo receives will use
25208 + * fragmented skbs
25211 + if (max_frame <= 256)
25212 + adapter->rx_buffer_len = 256;
25213 + else if (max_frame <= 512)
25214 + adapter->rx_buffer_len = 512;
25215 + else if (max_frame <= 1024)
25216 + adapter->rx_buffer_len = 1024;
25217 + else if (max_frame <= 2048)
25218 + adapter->rx_buffer_len = 2048;
25219 +#ifdef CONFIG_E1000E_NAPI
25221 + adapter->rx_buffer_len = 4096;
25223 + else if (max_frame <= 4096)
25224 + adapter->rx_buffer_len = 4096;
25225 + else if (max_frame <= 8192)
25226 + adapter->rx_buffer_len = 8192;
25227 + else if (max_frame <= 16384)
25228 + adapter->rx_buffer_len = 16384;
25231 + /* adjust allocation if LPE protects us, and we aren't using SBP */
25232 + if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
25233 + (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
25234 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
25237 + e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
25238 + netdev->mtu = new_mtu;
25240 + if (netif_running(netdev))
25241 + e1000_up(adapter);
25243 + e1000_reset(adapter);
25245 + clear_bit(__E1000_RESETTING, &adapter->state);
25250 +static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
25253 + struct e1000_adapter *adapter = netdev_priv(netdev);
25254 + struct mii_ioctl_data *data = if_mii(ifr);
25256 + if (adapter->hw.phy.media_type != e1000_media_type_copper)
25257 + return -EOPNOTSUPP;
25260 + case SIOCGMIIPHY:
25261 + data->phy_id = adapter->hw.phy.addr;
25263 + case SIOCGMIIREG:
25264 + if (!capable(CAP_NET_ADMIN))
25266 + switch (data->reg_num & 0x1F) {
25268 + data->val_out = adapter->phy_regs.bmcr;
25271 + data->val_out = adapter->phy_regs.bmsr;
25273 + case MII_PHYSID1:
25274 + data->val_out = (adapter->hw.phy.id >> 16);
25276 + case MII_PHYSID2:
25277 + data->val_out = (adapter->hw.phy.id & 0xFFFF);
25279 + case MII_ADVERTISE:
25280 + data->val_out = adapter->phy_regs.advertise;
25283 + data->val_out = adapter->phy_regs.lpa;
25285 + case MII_EXPANSION:
25286 + data->val_out = adapter->phy_regs.expansion;
25288 + case MII_CTRL1000:
25289 + data->val_out = adapter->phy_regs.ctrl1000;
25291 + case MII_STAT1000:
25292 + data->val_out = adapter->phy_regs.stat1000;
25294 + case MII_ESTATUS:
25295 + data->val_out = adapter->phy_regs.estatus;
25301 + case SIOCSMIIREG:
25303 + return -EOPNOTSUPP;
25308 +static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
25311 + case SIOCGMIIPHY:
25312 + case SIOCGMIIREG:
25313 + case SIOCSMIIREG:
25314 + return e1000_mii_ioctl(netdev, ifr, cmd);
25315 +#ifdef ETHTOOL_OPS_COMPAT
25316 + case SIOCETHTOOL:
25317 + return ethtool_ioctl(ifr);
25320 + return -EOPNOTSUPP;
25324 +static int e1000_suspend(struct pci_dev *pdev, pm_message_t state)
25326 + struct net_device *netdev = pci_get_drvdata(pdev);
25327 + struct e1000_adapter *adapter = netdev_priv(netdev);
25328 + struct e1000_hw *hw = &adapter->hw;
25329 + u32 ctrl, ctrl_ext, rctl, status;
25330 + u32 wufc = adapter->wol;
25333 + netif_device_detach(netdev);
25335 + if (netif_running(netdev)) {
25336 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
25337 + e1000_down(adapter);
25338 + e1000_free_irq(adapter);
25342 + retval = pci_save_state(pdev);
25347 + status = er32(STATUS);
25348 + if (status & E1000_STATUS_LU)
25349 + wufc &= ~E1000_WUFC_LNKC;
25352 + e1000_setup_rctl(adapter);
25353 + e1000_set_multi(netdev);
25355 + /* turn on all-multi mode if wake on multicast is enabled */
25356 + if (wufc & E1000_WUFC_MC) {
25357 + rctl = er32(RCTL);
25358 + rctl |= E1000_RCTL_MPE;
25359 + ew32(RCTL, rctl);
25362 + ctrl = er32(CTRL);
25363 + /* advertise wake from D3Cold */
25364 + #define E1000_CTRL_ADVD3WUC 0x00100000
25365 + /* phy power management enable */
25366 + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
25367 + ctrl |= E1000_CTRL_ADVD3WUC |
25368 + E1000_CTRL_EN_PHY_PWR_MGMT;
25369 + ew32(CTRL, ctrl);
25371 + if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
25372 + adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
25373 + /* keep the laser running in D3 */
25374 + ctrl_ext = er32(CTRL_EXT);
25375 + ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
25376 + ew32(CTRL_EXT, ctrl_ext);
25379 + if (adapter->flags & FLAG_IS_ICH)
25380 + e1000_disable_gig_wol_ich8lan(&adapter->hw);
25382 + /* Allow time for pending master requests to run */
25383 + e1000_disable_pcie_master_generic(&adapter->hw);
25385 + ew32(WUC, E1000_WUC_PME_EN);
25386 + ew32(WUFC, wufc);
25387 + pci_enable_wake(pdev, PCI_D3hot, 1);
25388 + pci_enable_wake(pdev, PCI_D3cold, 1);
25392 + pci_enable_wake(pdev, PCI_D3hot, 0);
25393 + pci_enable_wake(pdev, PCI_D3cold, 0);
25396 + /* make sure adapter isn't asleep if manageability is enabled */
25397 + if (adapter->flags & FLAG_MNG_PT_ENABLED) {
25398 + pci_enable_wake(pdev, PCI_D3hot, 1);
25399 + pci_enable_wake(pdev, PCI_D3cold, 1);
25402 + if (adapter->hw.phy.type == e1000_phy_igp_3)
25403 + e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
25406 + * Release control of h/w to f/w. If f/w is AMT enabled, this
25407 + * would have already happened in close and is redundant.
25409 + e1000_release_hw_control(adapter);
25411 + pci_disable_device(pdev);
25413 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
25419 +static int e1000_resume(struct pci_dev *pdev)
25421 + struct net_device *netdev = pci_get_drvdata(pdev);
25422 + struct e1000_adapter *adapter = netdev_priv(netdev);
25423 + struct e1000_hw *hw = &adapter->hw;
25426 + pci_set_power_state(pdev, PCI_D0);
25427 + pci_restore_state(pdev);
25428 + err = pci_enable_device(pdev);
25430 + dev_err(&pdev->dev,
25431 + "Cannot enable PCI device from suspend\n");
25435 + pci_set_master(pdev);
25437 + pci_enable_wake(pdev, PCI_D3hot, 0);
25438 + pci_enable_wake(pdev, PCI_D3cold, 0);
25440 + if (netif_running(netdev)) {
25441 + err = e1000_request_irq(adapter);
25446 + e1000_power_up_phy(hw);
25447 + e1000_reset(adapter);
25450 + e1000_init_manageability(adapter);
25452 + if (netif_running(netdev))
25453 + e1000_up(adapter);
25455 + netif_device_attach(netdev);
25458 + * If the controller has AMT, do not set DRV_LOAD until the interface
25459 + * is up. For all other cases, let the f/w know that the h/w is now
25460 + * under the control of the driver.
25462 + if (!(adapter->flags & FLAG_HAS_AMT))
25463 + e1000_get_hw_control(adapter);
25467 +#endif /* CONFIG_PM */
25469 +#ifndef USE_REBOOT_NOTIFIER
25470 +static void e1000_shutdown(struct pci_dev *pdev)
25472 + e1000_suspend(pdev, PMSG_SUSPEND);
25475 +static struct pci_driver e1000_driver;
25476 +static int e1000_notify_reboot(struct notifier_block *nb, unsigned long event,
25479 + struct pci_dev *pdev = NULL;
25484 + case SYS_POWER_OFF:
25485 + while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
25486 + if (pci_dev_driver(pdev) == &e1000_driver)
25487 + e1000_suspend(pdev, PMSG_SUSPEND);
25491 + return NOTIFY_DONE;
25494 +static struct notifier_block e1000_notifier_reboot = {
25495 + .notifier_call = e1000_notify_reboot,
25501 +#ifdef CONFIG_NET_POLL_CONTROLLER
25503 + * Polling 'interrupt' - used by things like netconsole to send skbs
25504 + * without having to re-enable interrupts. It's not called while
25505 + * the interrupt routine is executing.
25507 +static void e1000_netpoll(struct net_device *netdev)
25509 + struct e1000_adapter *adapter = netdev_priv(netdev);
25511 + disable_irq(adapter->pdev->irq);
25512 + e1000_intr(adapter->pdev->irq, netdev);
25514 + e1000_clean_tx_irq(adapter);
25515 +#ifndef CONFIG_E1000E_NAPI
25516 + adapter->clean_rx(adapter);
25519 + enable_irq(adapter->pdev->irq);
25523 +#ifdef HAVE_PCI_ERS
25525 + * e1000_io_error_detected - called when PCI error is detected
25526 + * @pdev: Pointer to PCI device
25527 + * @state: The current pci connection state
25529 + * This function is called after a PCI bus error affecting
25530 + * this device has been detected.
25532 +static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
25533 + pci_channel_state_t state)
25535 + struct net_device *netdev = pci_get_drvdata(pdev);
25536 + struct e1000_adapter *adapter = netdev_priv(netdev);
25538 + netif_device_detach(netdev);
25540 + if (netif_running(netdev))
25541 + e1000_down(adapter);
25542 + pci_disable_device(pdev);
25544 + /* Request a slot slot reset. */
25545 + return PCI_ERS_RESULT_NEED_RESET;
25549 + * e1000_io_slot_reset - called after the pci bus has been reset.
25550 + * @pdev: Pointer to PCI device
25552 + * Restart the card from scratch, as if from a cold-boot. Implementation
25553 + * resembles the first-half of the e1000_resume routine.
25555 +static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
25557 + struct net_device *netdev = pci_get_drvdata(pdev);
25558 + struct e1000_adapter *adapter = netdev_priv(netdev);
25559 + struct e1000_hw *hw = &adapter->hw;
25561 + if (pci_enable_device(pdev)) {
25562 + dev_err(&pdev->dev,
25563 + "Cannot re-enable PCI device after reset.\n");
25564 + return PCI_ERS_RESULT_DISCONNECT;
25566 + pci_set_master(pdev);
25568 + pci_enable_wake(pdev, PCI_D3hot, 0);
25569 + pci_enable_wake(pdev, PCI_D3cold, 0);
25571 + e1000_reset(adapter);
25574 + return PCI_ERS_RESULT_RECOVERED;
25578 + * e1000_io_resume - called when traffic can start flowing again.
25579 + * @pdev: Pointer to PCI device
25581 + * This callback is called when the error recovery driver tells us that
25582 + * its OK to resume normal operation. Implementation resembles the
25583 + * second-half of the e1000_resume routine.
25585 +static void e1000_io_resume(struct pci_dev *pdev)
25587 + struct net_device *netdev = pci_get_drvdata(pdev);
25588 + struct e1000_adapter *adapter = netdev_priv(netdev);
25590 + e1000_init_manageability(adapter);
25592 + if (netif_running(netdev)) {
25593 + if (e1000_up(adapter)) {
25594 + dev_err(&pdev->dev,
25595 + "can't bring device back up after reset\n");
25600 + netif_device_attach(netdev);
25603 + * If the controller has AMT, do not set DRV_LOAD until the interface
25604 + * is up. For all other cases, let the f/w know that the h/w is now
25605 + * under the control of the driver.
25607 + if (!(adapter->flags & FLAG_HAS_AMT))
25608 + e1000_get_hw_control(adapter);
25611 +#endif /* HAVE_PCI_ERS */
25613 +static void e1000_print_device_info(struct e1000_adapter *adapter)
25615 + struct e1000_hw *hw = &adapter->hw;
25616 + struct net_device *netdev = adapter->netdev;
25619 + /* print bus type/speed/width info */
25620 + e_info("(PCI Express:2.5GB/s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
25622 + ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
25624 + /* MAC address */
25625 + netdev->dev_addr[0], netdev->dev_addr[1],
25626 + netdev->dev_addr[2], netdev->dev_addr[3],
25627 + netdev->dev_addr[4], netdev->dev_addr[5]);
25628 + e_info("Intel(R) PRO/%s Network Connection\n",
25629 + (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
25630 + e1000_read_pba_num_generic(hw, &pba_num);
25631 + e_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
25632 + hw->mac.type, hw->phy.type,
25633 + (pba_num >> 8), (pba_num & 0xff));
25637 + * e1000_probe - Device Initialization Routine
25638 + * @pdev: PCI device information struct
25639 + * @ent: entry in e1000e_pci_tbl
25641 + * Returns 0 on success, negative on failure
25643 + * e1000_probe initializes an adapter identified by a pci_dev structure.
25644 + * The OS initialization, configuring of the adapter private structure,
25645 + * and a hardware reset occur.
25647 +static int __devinit e1000_probe(struct pci_dev *pdev,
25648 + const struct pci_device_id *ent)
25650 + struct net_device *netdev;
25651 + struct e1000_adapter *adapter;
25652 + struct e1000_hw *hw;
25653 + const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
25655 + static int cards_found;
25656 + int i, err, pci_using_dac;
25657 + u16 eeprom_data = 0;
25658 + u16 eeprom_apme_mask = E1000_EEPROM_APME;
25660 + err = pci_enable_device(pdev);
25664 + pci_using_dac = 0;
25665 + err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
25667 + err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
25669 + pci_using_dac = 1;
25671 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
25673 + err = pci_set_consistent_dma_mask(pdev,
25676 + printk(KERN_ERR "%s: No usable DMA "
25677 + "configuration, aborting\n",
25684 + err = pci_request_regions(pdev, e1000e_driver_name);
25686 + goto err_pci_reg;
25688 + pci_set_master(pdev);
25691 + netdev = alloc_etherdev(sizeof(struct e1000_adapter));
25693 + goto err_alloc_etherdev;
25695 + SET_MODULE_OWNER(netdev);
25696 + SET_NETDEV_DEV(netdev, &pdev->dev);
25698 + pci_set_drvdata(pdev, netdev);
25699 + adapter = netdev_priv(netdev);
25700 + hw = &adapter->hw;
25701 + adapter->netdev = netdev;
25702 + adapter->pdev = pdev;
25703 + adapter->ei = ei;
25704 + adapter->pba = ei->pba;
25705 + adapter->flags = ei->flags;
25706 + adapter->flags2 = ei->flags2;
25707 + adapter->hw.back = adapter;
25708 + adapter->hw.mac.type = ei->mac;
25709 + adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
25710 + adapter->stats_freq_us = 2 * 1000000; /* default watchdog timer 2sec */
25712 + /* PCI config space info */
25714 + hw->vendor_id = pdev->vendor;
25715 + hw->device_id = pdev->device;
25716 + hw->subsystem_vendor_id = pdev->subsystem_vendor;
25717 + hw->subsystem_device_id = pdev->subsystem_device;
25719 + pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
25720 + pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
25723 + adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0),
25724 + pci_resource_len(pdev, 0));
25725 + if (!adapter->hw.hw_addr)
25726 + goto err_ioremap;
25728 + if ((adapter->flags & FLAG_HAS_FLASH) &&
25729 + (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
25730 + adapter->hw.flash_address = ioremap(pci_resource_start(pdev, 1),
25731 + pci_resource_len(pdev, 1));
25732 + if (!adapter->hw.flash_address)
25733 + goto err_flashmap;
25736 + adapter->bd_number = cards_found++;
25738 + e1000_check_options(adapter);
25740 + /* setup adapter struct */
25741 + err = e1000_sw_init(adapter);
25743 + goto err_sw_init;
25745 + if (ei->get_variants) {
25746 + err = ei->get_variants(adapter);
25748 + goto err_hw_init;
25751 + /* construct the net_device struct */
25752 + netdev->open = &e1000_open;
25753 + netdev->stop = &e1000_close;
25754 + netdev->hard_start_xmit = &e1000_xmit_frame;
25755 + netdev->get_stats = &e1000_get_stats;
25756 + netdev->set_multicast_list = &e1000_set_multi;
25757 + netdev->set_mac_address = &e1000_set_mac;
25758 + netdev->change_mtu = &e1000_change_mtu;
25759 + netdev->do_ioctl = &e1000_ioctl;
25760 + e1000_set_ethtool_ops(netdev);
25761 + netdev->tx_timeout = &e1000_tx_timeout;
25762 + netdev->watchdog_timeo = 5 * HZ;
25763 +#ifdef CONFIG_E1000E_NAPI
25764 + netif_napi_add(netdev, &adapter->napi, e1000_poll, 64);
25766 + netdev->vlan_rx_register = e1000_vlan_rx_register;
25767 + netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
25768 + netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
25769 +#ifdef CONFIG_NET_POLL_CONTROLLER
25770 + netdev->poll_controller = e1000_netpoll;
25772 + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
25774 + if ((adapter->flags & FLAG_IS_ICH) &&
25775 + (adapter->flags2 & FLAG2_READ_ONLY_NVM))
25776 + e1000e_write_protect_nvm_ich8lan(&adapter->hw);
25778 + hw->mac.ops.get_bus_info(&adapter->hw);
25780 + adapter->hw.phy.autoneg_wait_to_complete = 0;
25782 + /* Copper options */
25783 + if (adapter->hw.phy.media_type == e1000_media_type_copper) {
25784 + adapter->hw.phy.mdix = AUTO_ALL_MODES;
25785 + adapter->hw.phy.disable_polarity_correction = 0;
25786 + adapter->hw.phy.ms_type = e1000_ms_hw_default;
25789 + if (hw->phy.ops.check_reset_block &&
25790 + hw->phy.ops.check_reset_block(hw))
25791 + e_info("PHY reset is blocked due to SOL/IDER session.\n");
25793 + netdev->features = NETIF_F_SG |
25794 + NETIF_F_HW_CSUM |
25795 + NETIF_F_HW_VLAN_TX |
25796 + NETIF_F_HW_VLAN_RX;
25798 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
25799 + netdev->features |= NETIF_F_HW_VLAN_FILTER;
25801 +#ifdef NETIF_F_TSO
25802 + netdev->features |= NETIF_F_TSO;
25803 +#ifdef NETIF_F_TSO6
25804 + netdev->features |= NETIF_F_TSO6;
25808 + if (pci_using_dac)
25809 + netdev->features |= NETIF_F_HIGHDMA;
25811 +#ifdef NETIF_F_LLTX
25813 + * We should not be using LLTX anymore, but we are still Tx faster with
25816 + netdev->features |= NETIF_F_LLTX;
25819 + if (e1000_enable_mng_pass_thru(&adapter->hw))
25820 + adapter->flags |= FLAG_MNG_PT_ENABLED;
25823 + * before reading the NVM, reset the controller to
25824 + * put the device in a known good starting state
25826 + adapter->hw.mac.ops.reset_hw(&adapter->hw);
25829 + * systems with ASPM and others may see the checksum fail on the first
25830 + * attempt. Let's give it a few tries
25832 + for (i = 0;; i++) {
25833 + if (hw->nvm.ops.validate(hw) >= 0)
25836 + e_err("The NVM Checksum Is Not Valid\n");
25842 + /* copy the MAC address out of the NVM */
25843 + if (e1000_read_mac_addr(&adapter->hw))
25844 + e_err("NVM Read Error while reading MAC address\n");
25846 + memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
25847 +#ifdef ETHTOOL_GPERMADDR
25848 + memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
25850 + if (!is_valid_ether_addr(netdev->perm_addr)) {
25852 + if (!is_valid_ether_addr(netdev->dev_addr)) {
25854 + e_err("Invalid MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
25855 + netdev->dev_addr[0], netdev->dev_addr[1],
25856 + netdev->dev_addr[2], netdev->dev_addr[3],
25857 + netdev->dev_addr[4], netdev->dev_addr[5]);
25862 + init_timer(&adapter->watchdog_timer);
25863 + adapter->watchdog_timer.function = &e1000_watchdog;
25864 + adapter->watchdog_timer.data = (unsigned long) adapter;
25866 + init_timer(&adapter->phy_info_timer);
25867 + adapter->phy_info_timer.function = &e1000_update_phy_info;
25868 + adapter->phy_info_timer.data = (unsigned long) adapter;
25870 + INIT_WORK(&adapter->reset_task, e1000_reset_task);
25871 + INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
25873 + /* Initialize link parameters. User can change them with ethtool */
25874 + adapter->hw.mac.autoneg = 1;
25875 + adapter->fc_autoneg = 1;
25876 + adapter->hw.fc.original_type = e1000_fc_default;
25877 + adapter->hw.fc.type = e1000_fc_default;
25878 + adapter->hw.phy.autoneg_advertised = 0x2f;
25880 + /* ring size defaults */
25881 + adapter->rx_ring->count = 256;
25882 + adapter->tx_ring->count = 256;
25885 + * Initial Wake on LAN setting - If APM wake is enabled in
25886 + * the EEPROM, enable the ACPI Magic Packet filter
25888 + if (adapter->flags & FLAG_APME_IN_WUC) {
25889 + /* APME bit in EEPROM is mapped to WUC.APME */
25890 + eeprom_data = er32(WUC);
25891 + eeprom_apme_mask = E1000_WUC_APME;
25892 + } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
25893 + if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
25894 + (adapter->hw.bus.func == 1))
25895 + hw->nvm.ops.read(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
25896 + 1, &eeprom_data);
25898 + hw->nvm.ops.read(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
25899 + 1, &eeprom_data);
25902 + /* fetch WoL from EEPROM */
25903 + if (eeprom_data & eeprom_apme_mask)
25904 + adapter->eeprom_wol |= E1000_WUFC_MAG;
25907 + * now that we have the eeprom settings, apply the special cases
25908 + * where the eeprom may be wrong or the board simply won't support
25909 + * wake on lan on a particular port
25911 + if (!(adapter->flags & FLAG_HAS_WOL))
25912 + adapter->eeprom_wol = 0;
25914 + /* initialize the wol settings based on the eeprom settings */
25915 + adapter->wol = adapter->eeprom_wol;
25917 + /* reset the hardware with the new settings */
25918 + e1000_reset(adapter);
25921 + * If the controller has AMT, do not set DRV_LOAD until the interface
25922 + * is up. For all other cases, let the f/w know that the h/w is now
25923 + * under the control of the driver.
25925 + if (!(adapter->flags & FLAG_HAS_AMT))
25926 + e1000_get_hw_control(adapter);
25928 + /* tell the stack to leave us alone until e1000_open() is called */
25929 + netif_carrier_off(netdev);
25930 + netif_stop_queue(netdev);
25932 + strcpy(netdev->name, "eth%d");
25933 + err = register_netdev(netdev);
25935 + goto err_register;
25937 + e1000_print_device_info(adapter);
25942 + if (!(adapter->flags & FLAG_HAS_AMT))
25943 + e1000_release_hw_control(adapter);
25945 + if (hw->phy.ops.check_reset_block &&
25946 + !hw->phy.ops.check_reset_block(hw))
25947 + hw->phy.ops.reset(hw);
25949 + hw->mac.ops.remove_device(&adapter->hw);
25950 + kfree(adapter->tx_ring);
25951 + kfree(adapter->rx_ring);
25953 + if (adapter->hw.flash_address)
25954 + iounmap(adapter->hw.flash_address);
25956 + iounmap(adapter->hw.hw_addr);
25958 + free_netdev(netdev);
25959 +err_alloc_etherdev:
25960 + pci_release_regions(pdev);
25963 + pci_disable_device(pdev);
25968 + * e1000_remove - Device Removal Routine
25969 + * @pdev: PCI device information struct
25971 + * e1000_remove is called by the PCI subsystem to alert the driver
25972 + * that it should release a PCI device. The could be caused by a
25973 + * Hot-Plug event, or because the driver is going to be removed from
25976 +static void __devexit e1000_remove(struct pci_dev *pdev)
25978 + struct net_device *netdev = pci_get_drvdata(pdev);
25979 + struct e1000_adapter *adapter = netdev_priv(netdev);
25980 + struct e1000_hw *hw = &adapter->hw;
25983 + * flush_scheduled work may reschedule our watchdog task, so
25984 + * explicitly disable watchdog tasks from being rescheduled
25986 + set_bit(__E1000_DOWN, &adapter->state);
25987 + del_timer_sync(&adapter->watchdog_timer);
25988 + del_timer_sync(&adapter->phy_info_timer);
25990 + flush_scheduled_work();
25993 + * Release control of h/w to f/w. If f/w is AMT enabled, this
25994 + * would have already happened in close and is redundant.
25996 + e1000_release_hw_control(adapter);
25998 + unregister_netdev(netdev);
26000 + if (hw->phy.ops.check_reset_block &&
26001 + !hw->phy.ops.check_reset_block(hw))
26002 + hw->phy.ops.reset(hw);
26004 +#ifdef CONFIG_E1000E_MSIX
26005 + e1000_reset_interrupt_capability(adapter);
26006 +#endif /* CONFIG_E1000E_MSIX */
26007 + hw->mac.ops.remove_device(&adapter->hw);
26008 + kfree(adapter->tx_ring);
26009 + kfree(adapter->rx_ring);
26011 + iounmap(adapter->hw.hw_addr);
26012 + if (adapter->hw.flash_address)
26013 + iounmap(adapter->hw.flash_address);
26014 + pci_release_regions(pdev);
26016 + free_netdev(netdev);
26018 + pci_disable_device(pdev);
26021 +#ifdef HAVE_PCI_ERS
26022 +/* PCI Error Recovery (ERS) */
26023 +static struct pci_error_handlers e1000_err_handler = {
26024 + .error_detected = e1000_io_error_detected,
26025 + .slot_reset = e1000_io_slot_reset,
26026 + .resume = e1000_io_resume,
26030 +static struct pci_device_id e1000e_pci_tbl[] = {
26031 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
26032 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
26033 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
26034 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
26035 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
26036 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
26037 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
26038 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
26039 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
26041 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
26042 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
26043 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
26044 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
26046 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
26047 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
26048 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
26050 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
26052 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
26053 + board_80003es2lan },
26054 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
26055 + board_80003es2lan },
26056 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
26057 + board_80003es2lan },
26058 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
26059 + board_80003es2lan },
26061 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
26062 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
26063 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
26064 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
26065 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
26066 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
26067 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
26069 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
26070 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
26071 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
26072 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
26073 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
26074 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
26075 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
26076 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
26077 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
26079 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
26080 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
26081 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
26083 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
26084 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
26086 + { } /* terminate list */
26088 +MODULE_DEVICE_TABLE(pci, e1000e_pci_tbl);
26090 +/* PCI Device API Driver */
26091 +static struct pci_driver e1000_driver = {
26092 + .name = e1000e_driver_name,
26093 + .id_table = e1000e_pci_tbl,
26094 + .probe = e1000_probe,
26095 + .remove = __devexit_p(e1000_remove),
26097 + /* Power Management Hooks */
26098 + .suspend = e1000_suspend,
26099 + .resume = e1000_resume,
26101 +#ifndef USE_REBOOT_NOTIFIER
26102 + .shutdown = e1000_shutdown,
26104 +#ifdef HAVE_PCI_ERS
26105 + .err_handler = &e1000_err_handler
26110 + * e1000_init_module - Driver Registration Routine
26112 + * e1000_init_module is the first routine called when the driver is
26113 + * loaded. All it does is register with the PCI subsystem.
26115 +static int __init e1000_init_module(void)
26118 + printk(KERN_INFO "%s: Intel(R) PRO/1000 Network Driver - %s\n",
26119 + e1000e_driver_name, e1000e_driver_version);
26120 + printk(KERN_INFO "%s: Copyright (c) 1999-2008 Intel Corporation.\n",
26121 + e1000e_driver_name);
26122 + ret = pci_register_driver(&e1000_driver);
26123 + pm_qos_add_requirement(PM_QOS_CPU_DMA_LATENCY, e1000e_driver_name,
26124 + PM_QOS_DEFAULT_VALUE);
26125 +#ifdef USE_REBOOT_NOTIFIER
26127 + register_reboot_notifier(&e1000_notifier_reboot);
26132 +module_init(e1000_init_module);
26135 + * e1000_exit_module - Driver Exit Cleanup Routine
26137 + * e1000_exit_module is called just before the driver is removed
26140 +static void __exit e1000_exit_module(void)
26142 +#ifdef USE_REBOOT_NOTIFIER
26143 + unregister_reboot_notifier(&e1000_notifier_reboot);
26145 + pci_unregister_driver(&e1000_driver);
26146 + pm_qos_remove_requirement(PM_QOS_CPU_DMA_LATENCY, e1000e_driver_name);
26148 +module_exit(e1000_exit_module);
26151 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
26152 +MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
26153 +MODULE_LICENSE("GPL");
26154 +MODULE_VERSION(DRV_VERSION);
26157 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/param.c linux-2.6.22-10/drivers/net/e1000e/param.c
26158 --- linux-2.6.22-0/drivers/net/e1000e/param.c 1970-01-01 01:00:00.000000000 +0100
26159 +++ linux-2.6.22-10/drivers/net/e1000e/param.c 2008-10-14 01:51:32.000000000 +0200
26161 +/*******************************************************************************
26163 + Intel PRO/1000 Linux driver
26164 + Copyright(c) 1999 - 2008 Intel Corporation.
26166 + This program is free software; you can redistribute it and/or modify it
26167 + under the terms and conditions of the GNU General Public License,
26168 + version 2, as published by the Free Software Foundation.
26170 + This program is distributed in the hope it will be useful, but WITHOUT
26171 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26172 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
26175 + You should have received a copy of the GNU General Public License along with
26176 + this program; if not, write to the Free Software Foundation, Inc.,
26177 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26179 + The full GNU General Public License is included in this distribution in
26180 + the file called "COPYING".
26182 + Contact Information:
26183 + Linux NICS <linux.nics@intel.com>
26184 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26185 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26187 +*******************************************************************************/
26189 +#include <linux/netdevice.h>
26191 +#include "e1000.h"
26194 + * This is the only thing that needs to be changed to adjust the
26195 + * maximum number of ports that the driver can manage.
26198 +#define E1000_MAX_NIC 32
26200 +#define OPTION_UNSET -1
26201 +#define OPTION_DISABLED 0
26202 +#define OPTION_ENABLED 1
26204 +#define COPYBREAK_DEFAULT 256
26205 +unsigned int copybreak = COPYBREAK_DEFAULT;
26206 +module_param(copybreak, uint, 0644);
26207 +MODULE_PARM_DESC(copybreak,
26208 + "Maximum size of packet that is copied to a new buffer on receive");
26211 + * All parameters are treated the same, as an integer array of values.
26212 + * This macro just reduces the need to repeat the same declaration code
26213 + * over and over (plus this helps to avoid typo bugs).
26216 +#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
26217 +#ifndef module_param_array
26218 +/* Module Parameters are always initialized to -1, so that the driver
26219 + * can tell the difference between no user specified value or the
26220 + * user asking for the default value.
26221 + * The true default values are loaded in when e1000_check_options is called.
26223 + * This is a GCC extension to ANSI C.
26224 + * See the item "Labeled Elements in Initializers" in the section
26225 + * "Extensions to the C Language Family" of the GCC documentation.
26227 +#define E1000_PARAM(X, desc) \
26228 + static const int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
26229 + static unsigned int num_##X; \
26230 + MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \
26231 + MODULE_PARM_DESC(X, desc);
26233 +#define E1000_PARAM(X, desc) \
26234 + static int __devinitdata X[E1000_MAX_NIC+1] \
26235 + = E1000_PARAM_INIT; \
26236 + static unsigned int num_##X; \
26237 + module_param_array_named(X, X, int, &num_##X, 0); \
26238 + MODULE_PARM_DESC(X, desc);
26242 + * Transmit Interrupt Delay in units of 1.024 microseconds
26243 + * Tx interrupt delay needs to typically be set to something non zero
26245 + * Valid Range: 0-65535
26247 +E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
26248 +#define DEFAULT_TIDV 8
26249 +#define MAX_TXDELAY 0xFFFF
26250 +#define MIN_TXDELAY 0
26253 + * Transmit Absolute Interrupt Delay in units of 1.024 microseconds
26255 + * Valid Range: 0-65535
26257 +E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
26258 +#define DEFAULT_TADV 32
26259 +#define MAX_TXABSDELAY 0xFFFF
26260 +#define MIN_TXABSDELAY 0
26263 + * Receive Interrupt Delay in units of 1.024 microseconds
26264 + * hardware will likely hang if you set this to anything but zero.
26266 + * Valid Range: 0-65535
26268 +E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
26269 +#define DEFAULT_RDTR 0
26270 +#define MAX_RXDELAY 0xFFFF
26271 +#define MIN_RXDELAY 0
26274 + * Receive Absolute Interrupt Delay in units of 1.024 microseconds
26276 + * Valid Range: 0-65535
26278 +E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
26279 +#define DEFAULT_RADV 8
26280 +#define MAX_RXABSDELAY 0xFFFF
26281 +#define MIN_RXABSDELAY 0
26284 + * Interrupt Throttle Rate (interrupts/sec)
26286 + * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
26288 +E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
26289 +#define DEFAULT_ITR 3
26290 +#define MAX_ITR 100000
26291 +#define MIN_ITR 100
26293 +#ifdef CONFIG_E1000E_MSIX
26294 +/* IntMode (Interrupt Mode)
26296 + * Valid Range: 0 - 2
26298 + * Default Value: 2 (MSI-X)
26300 +E1000_PARAM(IntMode, "Interrupt Mode");
26301 +#define MAX_INTMODE 2
26302 +#define MIN_INTMODE 0
26304 +#endif /* CONFIG_E1000E_MSIX */
26306 + * Enable Smart Power Down of the PHY
26308 + * Valid Range: 0, 1
26310 + * Default Value: 0 (disabled)
26312 +E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
26315 + * Enable Kumeran Lock Loss workaround
26317 + * Valid Range: 0, 1
26319 + * Default Value: 1 (enabled)
26321 +E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
26324 + * Write Protect NVM
26326 + * Valid Range: 0, 1
26328 + * Default Value: 1 (enabled)
26330 +E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can "
26331 + "lead to corrupted NVM]");
26334 +struct e1000_option {
26335 + enum { enable_option, range_option, list_option } type;
26336 + const char *name;
26340 + struct { /* range_option info */
26344 + struct { /* list_option info */
26346 + struct e1000_opt_list { int i; char *str; } *p;
26351 +static int __devinit e1000_validate_option(unsigned int *value,
26352 + const struct e1000_option *opt,
26353 + struct e1000_adapter *adapter)
26355 + if (*value == OPTION_UNSET) {
26356 + *value = opt->def;
26360 + switch (opt->type) {
26361 + case enable_option:
26362 + switch (*value) {
26363 + case OPTION_ENABLED:
26364 + e_info("%s Enabled\n", opt->name);
26366 + case OPTION_DISABLED:
26367 + e_info("%s Disabled\n", opt->name);
26371 + case range_option:
26372 + if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
26373 + e_info("%s set to %i\n", opt->name, *value);
26377 + case list_option: {
26379 + struct e1000_opt_list *ent;
26381 + for (i = 0; i < opt->arg.l.nr; i++) {
26382 + ent = &opt->arg.l.p[i];
26383 + if (*value == ent->i) {
26384 + if (ent->str[0] != '\0')
26385 + e_info("%s\n", ent->str);
26395 + e_info("Invalid %s value specified (%i) %s\n", opt->name, *value,
26397 + *value = opt->def;
26402 + * e1000_check_options - Range Checking for Command Line Parameters
26403 + * @adapter: board private structure
26405 + * This routine checks all command line parameters for valid user
26406 + * input. If an invalid value is given, or if no user specified
26407 + * value exists, a default value is used. The final value is stored
26408 + * in a variable in the adapter structure.
26410 +void __devinit e1000_check_options(struct e1000_adapter *adapter)
26412 + struct e1000_hw *hw = &adapter->hw;
26413 + int bd = adapter->bd_number;
26415 + if (bd >= E1000_MAX_NIC) {
26416 + e_notice("Warning: no configuration for board #%i\n", bd);
26417 + e_notice("Using defaults for all values\n");
26420 + { /* Transmit Interrupt Delay */
26421 + const struct e1000_option opt = {
26422 + .type = range_option,
26423 + .name = "Transmit Interrupt Delay",
26424 + .err = "using default of "
26425 + __MODULE_STRING(DEFAULT_TIDV),
26426 + .def = DEFAULT_TIDV,
26427 + .arg = { .r = { .min = MIN_TXDELAY,
26428 + .max = MAX_TXDELAY } }
26431 + if (num_TxIntDelay > bd) {
26432 + adapter->tx_int_delay = TxIntDelay[bd];
26433 + e1000_validate_option(&adapter->tx_int_delay, &opt,
26436 + adapter->tx_int_delay = opt.def;
26439 + { /* Transmit Absolute Interrupt Delay */
26440 + const struct e1000_option opt = {
26441 + .type = range_option,
26442 + .name = "Transmit Absolute Interrupt Delay",
26443 + .err = "using default of "
26444 + __MODULE_STRING(DEFAULT_TADV),
26445 + .def = DEFAULT_TADV,
26446 + .arg = { .r = { .min = MIN_TXABSDELAY,
26447 + .max = MAX_TXABSDELAY } }
26450 + if (num_TxAbsIntDelay > bd) {
26451 + adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
26452 + e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
26455 + adapter->tx_abs_int_delay = opt.def;
26458 + { /* Receive Interrupt Delay */
26459 + struct e1000_option opt = {
26460 + .type = range_option,
26461 + .name = "Receive Interrupt Delay",
26462 + .err = "using default of "
26463 + __MODULE_STRING(DEFAULT_RDTR),
26464 + .def = DEFAULT_RDTR,
26465 + .arg = { .r = { .min = MIN_RXDELAY,
26466 + .max = MAX_RXDELAY } }
26470 + * modify min and default if 82573 for slow ping w/a,
26471 + * a value greater than 8 needs to be set for RDTR
26473 + if (adapter->flags & FLAG_HAS_ASPM) {
26475 + opt.arg.r.min = 8;
26478 + if (num_RxIntDelay > bd) {
26479 + adapter->rx_int_delay = RxIntDelay[bd];
26480 + e1000_validate_option(&adapter->rx_int_delay, &opt,
26483 + adapter->rx_int_delay = opt.def;
26486 + { /* Receive Absolute Interrupt Delay */
26487 + const struct e1000_option opt = {
26488 + .type = range_option,
26489 + .name = "Receive Absolute Interrupt Delay",
26490 + .err = "using default of "
26491 + __MODULE_STRING(DEFAULT_RADV),
26492 + .def = DEFAULT_RADV,
26493 + .arg = { .r = { .min = MIN_RXABSDELAY,
26494 + .max = MAX_RXABSDELAY } }
26497 + if (num_RxAbsIntDelay > bd) {
26498 + adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
26499 + e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
26502 + adapter->rx_abs_int_delay = opt.def;
26505 + { /* Interrupt Throttling Rate */
26506 + const struct e1000_option opt = {
26507 + .type = range_option,
26508 + .name = "Interrupt Throttling Rate (ints/sec)",
26509 + .err = "using default of "
26510 + __MODULE_STRING(DEFAULT_ITR),
26511 + .def = DEFAULT_ITR,
26512 + .arg = { .r = { .min = MIN_ITR,
26513 + .max = MAX_ITR } }
26516 + if (num_InterruptThrottleRate > bd) {
26517 + adapter->itr = InterruptThrottleRate[bd];
26518 + switch (adapter->itr) {
26520 + e_info("%s turned off\n", opt.name);
26523 + e_info("%s set to dynamic mode\n", opt.name);
26524 + adapter->itr_setting = adapter->itr;
26525 + adapter->itr = 20000;
26528 + e_info("%s set to dynamic conservative mode\n",
26530 + adapter->itr_setting = adapter->itr;
26531 + adapter->itr = 20000;
26535 + * Save the setting, because the dynamic bits
26538 + if (e1000_validate_option(&adapter->itr, &opt,
26540 + (adapter->itr == 3)) {
26542 + * In case of invalid user value,
26543 + * default to conservative mode.
26545 + adapter->itr_setting = adapter->itr;
26546 + adapter->itr = 20000;
26549 + * Clear the lower two bits because
26550 + * they are used as control.
26552 + adapter->itr_setting =
26553 + adapter->itr & ~3;
26558 + adapter->itr_setting = opt.def;
26559 + adapter->itr = 20000;
26562 +#ifdef CONFIG_E1000E_MSIX
26563 + { /* Interrupt Mode */
26564 + struct e1000_option opt = {
26565 + .type = range_option,
26566 + .name = "Interrupt Mode",
26567 + .err = "defaulting to 2 (MSI-X)",
26568 + .def = E1000E_INT_MODE_MSIX,
26569 + .arg = { .r = { .min = MIN_INTMODE,
26570 + .max = MAX_INTMODE }}
26573 + if (num_IntMode > bd) {
26574 + unsigned int int_mode = IntMode[bd];
26575 + e1000_validate_option(&int_mode, &opt, adapter);
26576 + adapter->int_mode = int_mode;
26578 + adapter->int_mode = opt.def;
26581 +#endif /* CONFIG_E1000E_MSIX */
26582 + { /* Smart Power Down */
26583 + const struct e1000_option opt = {
26584 + .type = enable_option,
26585 + .name = "PHY Smart Power Down",
26586 + .err = "defaulting to Disabled",
26587 + .def = OPTION_DISABLED
26590 + if (num_SmartPowerDownEnable > bd) {
26591 + unsigned int spd = SmartPowerDownEnable[bd];
26592 + e1000_validate_option(&spd, &opt, adapter);
26593 + if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN)
26595 + adapter->flags |= FLAG_SMART_POWER_DOWN;
26598 + { /* Kumeran Lock Loss Workaround */
26599 + const struct e1000_option opt = {
26600 + .type = enable_option,
26601 + .name = "Kumeran Lock Loss Workaround",
26602 + .err = "defaulting to Enabled",
26603 + .def = OPTION_ENABLED
26606 + if (num_KumeranLockLoss > bd) {
26607 + unsigned int kmrn_lock_loss = KumeranLockLoss[bd];
26608 + e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
26609 + if (hw->mac.type == e1000_ich8lan)
26610 + e1000_set_kmrn_lock_loss_workaround_ich8lan(hw,
26613 + if (hw->mac.type == e1000_ich8lan)
26614 + e1000_set_kmrn_lock_loss_workaround_ich8lan(hw,
26618 + { /* Write-protect NVM */
26619 + const struct e1000_option opt = {
26620 + .type = enable_option,
26621 + .name = "Write-protect NVM",
26622 + .err = "defaulting to Enabled",
26623 + .def = OPTION_ENABLED
26626 + if (adapter->flags & FLAG_IS_ICH) {
26627 + if (num_WriteProtectNVM > bd) {
26628 + unsigned int write_protect_nvm = WriteProtectNVM[bd];
26629 + e1000_validate_option(&write_protect_nvm, &opt,
26631 + if (write_protect_nvm)
26632 + adapter->flags2 |= FLAG2_READ_ONLY_NVM;
26635 + adapter->flags2 |= FLAG2_READ_ONLY_NVM;
26640 diff -Nurp linux-2.6.22-0/drivers/net/Kconfig linux-2.6.22-10/drivers/net/Kconfig
26641 --- linux-2.6.22-0/drivers/net/Kconfig 2007-07-09 01:32:17.000000000 +0200
26642 +++ linux-2.6.22-10/drivers/net/Kconfig 2008-11-10 00:06:46.000000000 +0100
26643 @@ -1993,6 +1993,29 @@ config E1000_DISABLE_PACKET_SPLIT
26645 If in doubt, say N.
26648 + tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
26651 + This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
26652 + ethernet family of adapters. For PCI or PCI-X e1000 adapters,
26653 + use the regular e1000 driver For more information on how to
26654 + identify your adapter, go to the Adapter & Driver ID Guide at:
26656 + <http://support.intel.com/support/network/adapter/pro100/21397.htm>
26658 + For general information and support, go to the Intel support
26661 + <http://support.intel.com>
26663 + More specific information on configuring the driver is in
26664 + <file:Documentation/networking/e1000e.txt>.
26666 + To compile this driver as a module, choose M here and read
26667 + <file:Documentation/networking/net-modules.txt>. The module
26668 + will be called e1000e.
26670 source "drivers/net/ixp2000/Kconfig"
26673 diff -Nurp linux-2.6.22-0/drivers/net/Makefile linux-2.6.22-10/drivers/net/Makefile
26674 --- linux-2.6.22-0/drivers/net/Makefile 2007-07-09 01:32:17.000000000 +0200
26675 +++ linux-2.6.22-10/drivers/net/Makefile 2008-11-10 00:02:57.000000000 +0100
26679 obj-$(CONFIG_E1000) += e1000/
26680 +obj-$(CONFIG_E1000E) += e1000e/
26681 obj-$(CONFIG_IBM_EMAC) += ibm_emac/
26682 obj-$(CONFIG_IXGB) += ixgb/
26683 obj-$(CONFIG_CHELSIO_T1) += chelsio/