2 * cmpci.c -- C-Media PCI audio driver.
4 * Copyright (C) 1999 C-media support (support@cmedia.com.tw)
6 * Based on the PCI drivers by Thomas Sailer (sailer@ife.ee.ethz.ch)
9 * http://www.cmedia.com.tw
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Special thanks to David C. Niemi, Jan Pfeifer
28 * Module command line parameters:
33 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
34 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
35 * /dev/midi simple MIDI UART interface, no ioctl
37 * The card has both an FM and a Wavetable synth, but I have to figure
38 * out first how to drive them...
41 * 06.05.98 0.1 Initial release
42 * 10.05.98 0.2 Fixed many bugs, esp. ADC rate calculation
43 * First stab at a simple midi interface (no bells&whistles)
44 * 13.05.98 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
45 * set_dac_rate in the FMODE_WRITE case in cm_open
46 * Fix hwptr out of bounds (now mpg123 works)
47 * 14.05.98 0.4 Don't allow excessive interrupt rates
48 * 08.06.98 0.5 First release using Alan Cox' soundcore instead of miscdevice
49 * 03.08.98 0.6 Do not include modversions.h
50 * Now mixer behaviour can basically be selected between
51 * "OSS documented" and "OSS actual" behaviour
52 * 31.08.98 0.7 Fix realplayer problems - dac.count issues
53 * 10.12.98 0.8 Fix drain_dac trying to wait on not yet initialized DMA
54 * 16.12.98 0.9 Fix a few f_file & FMODE_ bugs
55 * 06.01.99 0.10 remove the silly SA_INTERRUPT flag.
56 * hopefully killed the egcs section type conflict
57 * 12.03.99 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
58 * reported by Johan Maes <joma@telindus.be>
59 * 22.03.99 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
60 * read/write cannot be executed
61 * 18.08.99 1.5 Only deallocate DMA buffer when unloading.
62 * 02.09.99 1.6 Enable SPDIF LOOP
63 * Change the mixer read back
64 * 21.09.99 2.33 Use RCS version as driver version.
65 * Add support for modem, S/PDIF loop and 4 channels.
67 * Fix bug cause x11amp cannot play.
70 * Arnaldo Carvalho de Melo <acme@conectiva.com.br>
71 * 18/05/2001 - .bss nitpicks, fix a bug in set_dac_channels where it
72 * was calling prog_dmabuf with s->lock held, call missing
73 * unlock_kernel in cm_midi_release
74 * 08/10/2001 - use set_current_state in some more places
76 * Carlos Eduardo Gorges <carlos@techlinux.com.br>
78 * - SMP support ( spin[un]lock* revision )
79 * - speaker mixer support
81 * - optimizations and cleanups
83 * 03/01/2003 - open_mode fixes from Georg Acher <acher@in.tum.de>
84 * Simon Braunschmidt <brasimon@web.de>
86 * - provide support for opl3 FM by releasing IO range after initialization
88 * ChenLi Tien <cltien@cmedia.com.tw>
90 * - Fix S/PDIF out if spdif_loop enabled
91 * - Load opl3 driver if enabled (fmio in proper range)
92 * - Load mpu401 if enabled (mpuio in proper range)
94 * - Fix DUAL_DAC dma synchronization bug
95 * - Check exist FM/MPU401 I/O before activate.
96 * - Add AFTM_S16_BE format support, so MPlayer/Xine can play AC3/mutlichannel
98 * - Change to support kernel 2.6 so only small patch needed
99 * - All parameters default to 0
100 * - Add spdif_out to send PCM through S/PDIF out jack
101 * - Add hw_copy to get 4-spaker output for general PCM/analog output
103 * Stefan Thater <stefan.thaeter@gmx.de>
105 * - Fix mute single channel for CD/Line-in/AUX-in
107 /*****************************************************************************/
109 #include <linux/config.h>
110 #include <linux/module.h>
111 #include <linux/string.h>
112 #include <linux/interrupt.h>
113 #include <linux/ioport.h>
114 #include <linux/sched.h>
115 #include <linux/delay.h>
116 #include <linux/sound.h>
117 #include <linux/slab.h>
118 #include <linux/soundcard.h>
119 #include <linux/pci.h>
120 #include <linux/init.h>
121 #include <linux/poll.h>
122 #include <linux/spinlock.h>
123 #include <linux/smp_lock.h>
124 #include <linux/bitops.h>
125 #include <linux/wait.h>
128 #include <asm/page.h>
129 #include <asm/uaccess.h>
131 #ifdef CONFIG_SOUND_CMPCI_MIDI
132 #include "sound_config.h"
135 #ifdef CONFIG_SOUND_CMPCI_FM
138 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
139 #include <linux/gameport.h>
142 /* --------------------------------------------------------------------- */
143 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
146 /* --------------------------------------------------------------------- */
148 #define CM_MAGIC ((PCI_VENDOR_ID_CMEDIA<<16)|PCI_DEVICE_ID_CMEDIA_CM8338A)
150 /* CM8338 registers definition ****************/
152 #define CODEC_CMI_FUNCTRL0 (0x00)
153 #define CODEC_CMI_FUNCTRL1 (0x04)
154 #define CODEC_CMI_CHFORMAT (0x08)
155 #define CODEC_CMI_INT_HLDCLR (0x0C)
156 #define CODEC_CMI_INT_STATUS (0x10)
157 #define CODEC_CMI_LEGACY_CTRL (0x14)
158 #define CODEC_CMI_MISC_CTRL (0x18)
159 #define CODEC_CMI_TDMA_POS (0x1C)
160 #define CODEC_CMI_MIXER (0x20)
161 #define CODEC_SB16_DATA (0x22)
162 #define CODEC_SB16_ADDR (0x23)
163 #define CODEC_CMI_MIXER1 (0x24)
164 #define CODEC_CMI_MIXER2 (0x25)
165 #define CODEC_CMI_AUX_VOL (0x26)
166 #define CODEC_CMI_MISC (0x27)
167 #define CODEC_CMI_AC97 (0x28)
169 #define CODEC_CMI_CH0_FRAME1 (0x80)
170 #define CODEC_CMI_CH0_FRAME2 (0x84)
171 #define CODEC_CMI_CH1_FRAME1 (0x88)
172 #define CODEC_CMI_CH1_FRAME2 (0x8C)
174 #define CODEC_CMI_SPDIF_CTRL (0x90)
175 #define CODEC_CMI_MISC_CTRL2 (0x92)
177 #define CODEC_CMI_EXT_REG (0xF0)
179 /* Mixer registers for SB16 ******************/
181 #define DSP_MIX_DATARESETIDX ((unsigned char)(0x00))
183 #define DSP_MIX_MASTERVOLIDX_L ((unsigned char)(0x30))
184 #define DSP_MIX_MASTERVOLIDX_R ((unsigned char)(0x31))
185 #define DSP_MIX_VOICEVOLIDX_L ((unsigned char)(0x32))
186 #define DSP_MIX_VOICEVOLIDX_R ((unsigned char)(0x33))
187 #define DSP_MIX_FMVOLIDX_L ((unsigned char)(0x34))
188 #define DSP_MIX_FMVOLIDX_R ((unsigned char)(0x35))
189 #define DSP_MIX_CDVOLIDX_L ((unsigned char)(0x36))
190 #define DSP_MIX_CDVOLIDX_R ((unsigned char)(0x37))
191 #define DSP_MIX_LINEVOLIDX_L ((unsigned char)(0x38))
192 #define DSP_MIX_LINEVOLIDX_R ((unsigned char)(0x39))
194 #define DSP_MIX_MICVOLIDX ((unsigned char)(0x3A))
195 #define DSP_MIX_SPKRVOLIDX ((unsigned char)(0x3B))
197 #define DSP_MIX_OUTMIXIDX ((unsigned char)(0x3C))
199 #define DSP_MIX_ADCMIXIDX_L ((unsigned char)(0x3D))
200 #define DSP_MIX_ADCMIXIDX_R ((unsigned char)(0x3E))
202 #define DSP_MIX_INGAINIDX_L ((unsigned char)(0x3F))
203 #define DSP_MIX_INGAINIDX_R ((unsigned char)(0x40))
204 #define DSP_MIX_OUTGAINIDX_L ((unsigned char)(0x41))
205 #define DSP_MIX_OUTGAINIDX_R ((unsigned char)(0x42))
207 #define DSP_MIX_AGCIDX ((unsigned char)(0x43))
209 #define DSP_MIX_TREBLEIDX_L ((unsigned char)(0x44))
210 #define DSP_MIX_TREBLEIDX_R ((unsigned char)(0x45))
211 #define DSP_MIX_BASSIDX_L ((unsigned char)(0x46))
212 #define DSP_MIX_BASSIDX_R ((unsigned char)(0x47))
213 #define DSP_MIX_EXTENSION ((unsigned char)(0xf0))
214 // pseudo register for AUX
215 #define DSP_MIX_AUXVOL_L ((unsigned char)(0x50))
216 #define DSP_MIX_AUXVOL_R ((unsigned char)(0x51))
219 #define CM_EXTENT_CODEC 0x100
220 #define CM_EXTENT_MIDI 0x2
221 #define CM_EXTENT_SYNTH 0x4
222 #define CM_EXTENT_GAME 0x8
224 // Function Control Register 0 (00h)
230 // Function Control Register 0+2 (02h)
236 // Function Control Register 1 (04h)
237 #define JYSTK_EN 0x02
239 #define SPDO2DAC 0x40
240 #define SPDFLOOP 0x80
242 // Function Control Register 1+1 (05h)
247 #define SPDIF2DAC (SPDF_1 << 8 | SPDO2DAC)
249 // Channel Format Register (08h)
250 #define CM_CFMT_STEREO 0x01
251 #define CM_CFMT_16BIT 0x02
252 #define CM_CFMT_MASK 0x03
253 #define POLVALID 0x20
254 #define INVSPDIFI 0x80
256 // Channel Format Register+2 (0ah)
257 #define SPD24SEL 0x20
259 // Channel Format Register+3 (0bh)
263 // Interrupt Hold/Clear Register+2 (0eh)
264 #define CH0_INT_EN 0x01
265 #define CH1_INT_EN 0x02
267 // Interrupt Register (10h)
273 // Legacy Control/Status Register+1 (15h)
275 #define BASE2LIN 0x20
276 #define CENTR2LIN 0x40
277 #define CB2LIN (BASE2LIN | CENTR2LIN)
280 // Legacy Control/Status Register+2 (16h)
281 #define DAC2SPDO 0x20
282 #define SPDCOPYRHT 0x40
283 #define ENSPDOUT 0x80
285 // Legacy Control/Status Register+3 (17h)
291 // Miscellaneous Control Register (18h)
292 #define REAR2LIN 0x20
294 #define ENCENTER 0x80
296 // Miscellaneous Control Register+1 (19h)
297 #define SELSPDIFI2 0x01
298 #define SPDF_AC97 0x80
300 // Miscellaneous Control Register+2 (1ah)
303 #define SPD32SEL 0x20
307 // Miscellaneous Control Register+3 (1bh)
308 #define SPDIFI48K 0x01
313 #define SPDIF48K (SPDIFI48K << 24 | SPDF_AC97 << 8)
318 #define REAR2FRONT 0x10
323 // Miscellaneous Register (27h)
324 #define SPDVALID 0x02
325 #define CENTR2MIC 0x04
327 // Miscellaneous Register2 (92h)
328 #define SPD32KFMT 0x10
330 #define CM_CFMT_DACSHIFT 2
331 #define CM_CFMT_ADCSHIFT 0
332 #define CM_FREQ_DACSHIFT 5
333 #define CM_FREQ_ADCSHIFT 2
334 #define RSTDAC RST_CH1
335 #define RSTADC RST_CH0
338 #define PAUSEDAC PAUSE1
339 #define PAUSEADC PAUSE0
340 #define CODEC_CMI_ADC_FRAME1 CODEC_CMI_CH0_FRAME1
341 #define CODEC_CMI_ADC_FRAME2 CODEC_CMI_CH0_FRAME2
342 #define CODEC_CMI_DAC_FRAME1 CODEC_CMI_CH1_FRAME1
343 #define CODEC_CMI_DAC_FRAME2 CODEC_CMI_CH1_FRAME2
344 #define DACINT CHINT1
345 #define ADCINT CHINT0
346 #define DACBUSY CH1BUSY
347 #define ADCBUSY CH0BUSY
348 #define ENDACINT CH1_INT_EN
349 #define ENADCINT CH0_INT_EN
351 static const unsigned sample_size[] = { 1, 2, 2, 4 };
352 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
354 #define SND_DEV_DSP16 5
356 #define NR_DEVICE 3 /* maximum number of devices */
358 #define set_dac1_rate set_adc_rate
359 #define set_dac1_rate_unlocked set_adc_rate_unlocked
360 #define stop_dac1 stop_adc
361 #define stop_dac1_unlocked stop_adc_unlocked
362 #define get_dmadac1 get_dmaadc
364 static unsigned int devindex = 0;
366 //*********************************************/
372 /* list of cmedia devices */
373 struct list_head devs;
375 /* the corresponding pci_dev structure */
378 int dev_audio; /* soundcore stuff */
381 unsigned int iosb, iobase, iosynth,
382 iomidi, iogame, irq; /* hardware resources */
383 unsigned short deviceid; /* pci_id */
385 struct { /* mixer stuff */
387 unsigned short vol[13];
390 unsigned int rateadc, ratedac; /* wave stuff */
391 unsigned char fmt, enable;
394 struct semaphore open_sem;
396 wait_queue_head_t open_wait;
404 unsigned hwptr, swptr;
405 unsigned total_bytes;
407 unsigned error; /* over/underrun */
408 wait_queue_head_t wait;
410 unsigned fragsize; /* redundant, but makes calculations easier */
412 unsigned fragsamples;
415 unsigned mapped:1; /* OSS stuff */
417 unsigned endcleared:1;
419 unsigned ossfragshift;
421 unsigned subdivision;
424 #ifdef CONFIG_SOUND_CMPCI_MIDI
426 struct address_info mpu_data;
428 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
429 struct gameport gameport;
435 int capability; /* HW capability, various for chip versions */
437 int status; /* HW or SW state */
439 int spdif_counter; /* spdif frame counter */
442 /* flags used for capability */
443 #define CAN_AC3_HW 0x00000001 /* 037 or later */
444 #define CAN_AC3_SW 0x00000002 /* 033 or later */
445 #define CAN_AC3 (CAN_AC3_HW | CAN_AC3_SW)
446 #define CAN_DUAL_DAC 0x00000004 /* 033 or later */
447 #define CAN_MULTI_CH_HW 0x00000008 /* 039 or later */
448 #define CAN_MULTI_CH (CAN_MULTI_CH_HW | CAN_DUAL_DAC)
449 #define CAN_LINE_AS_REAR 0x00000010 /* 033 or later */
450 #define CAN_LINE_AS_BASS 0x00000020 /* 039 or later */
451 #define CAN_MIC_AS_BASS 0x00000040 /* 039 or later */
453 /* flags used for status */
454 #define DO_AC3_HW 0x00000001
455 #define DO_AC3_SW 0x00000002
456 #define DO_AC3 (DO_AC3_HW | DO_AC3_SW)
457 #define DO_DUAL_DAC 0x00000004
458 #define DO_MULTI_CH_HW 0x00000008
459 #define DO_MULTI_CH (DO_MULTI_CH_HW | DO_DUAL_DAC)
460 #define DO_LINE_AS_REAR 0x00000010 /* 033 or later */
461 #define DO_LINE_AS_BASS 0x00000020 /* 039 or later */
462 #define DO_MIC_AS_BASS 0x00000040 /* 039 or later */
463 #define DO_SPDIF_OUT 0x00000100
464 #define DO_SPDIF_IN 0x00000200
465 #define DO_SPDIF_LOOP 0x00000400
466 #define DO_BIGENDIAN_W 0x00001000 /* used in PowerPC */
467 #define DO_BIGENDIAN_R 0x00002000 /* used in PowerPC */
469 static LIST_HEAD(devs);
471 static int mpuio = 0;
473 static int joystick = 0;
474 static int spdif_inverse = 0;
475 static int spdif_loop = 0;
476 static int spdif_out = 0;
477 static int use_line_as_rear = 0;
478 static int use_line_as_bass = 0;
479 static int use_mic_as_bass = 0;
480 static int mic_boost = 0;
481 static int hw_copy = 0;
482 MODULE_PARM(mpuio, "i");
483 MODULE_PARM(fmio, "i");
484 MODULE_PARM(joystick, "i");
485 MODULE_PARM(spdif_inverse, "i");
486 MODULE_PARM(spdif_loop, "i");
487 MODULE_PARM(spdif_out, "i");
488 MODULE_PARM(use_line_as_rear, "i");
489 MODULE_PARM(use_line_as_bass, "i");
490 MODULE_PARM(use_mic_as_bass, "i");
491 MODULE_PARM(mic_boost, "i");
492 MODULE_PARM(hw_copy, "i");
493 MODULE_PARM_DESC(mpuio, "(0x330, 0x320, 0x310, 0x300) Base of MPU-401, 0 to disable");
494 MODULE_PARM_DESC(fmio, "(0x388, 0x3C8, 0x3E0) Base of OPL3, 0 to disable");
495 MODULE_PARM_DESC(joystick, "(1/0) Enable joystick interface, still need joystick driver");
496 MODULE_PARM_DESC(spdif_inverse, "(1/0) Invert S/PDIF-in signal");
497 MODULE_PARM_DESC(spdif_loop, "(1/0) Route S/PDIF-in to S/PDIF-out directly");
498 MODULE_PARM_DESC(spdif_out, "(1/0) Send PCM to S/PDIF-out (PCM volume will not function)");
499 MODULE_PARM_DESC(use_line_as_rear, "(1/0) Use line-in jack as rear-out");
500 MODULE_PARM_DESC(use_line_as_bass, "(1/0) Use line-in jack as bass/center");
501 MODULE_PARM_DESC(use_mic_as_bass, "(1/0) Use mic-in jack as bass/center");
502 MODULE_PARM_DESC(mic_boost, "(1/0) Enable microphone boost");
503 MODULE_PARM_DESC(hw_copy, "Copy front channel to surround channel");
505 /* --------------------------------------------------------------------- */
507 static inline unsigned ld2(unsigned int x)
509 unsigned exp=16,l=5,r=0;
510 static const unsigned num[]={0x2,0x4,0x10,0x100,0x10000};
512 /* num: 2, 4, 16, 256, 65536 */
513 /* exp: 1, 2, 4, 8, 16 */
517 if(num[l]>2) x >>= exp;
526 /* --------------------------------------------------------------------- */
528 static void maskb(unsigned int addr, unsigned int mask, unsigned int value)
530 outb((inb(addr) & mask) | value, addr);
533 static void maskw(unsigned int addr, unsigned int mask, unsigned int value)
535 outw((inw(addr) & mask) | value, addr);
538 static void maskl(unsigned int addr, unsigned int mask, unsigned int value)
540 outl((inl(addr) & mask) | value, addr);
543 static void set_dmadac1(struct cm_state *s, unsigned int addr, unsigned int count)
546 outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
547 outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
548 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC0, 0);
551 static void set_dmaadc(struct cm_state *s, unsigned int addr, unsigned int count)
553 outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
554 outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
555 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, CHADC0);
558 static void set_dmadac(struct cm_state *s, unsigned int addr, unsigned int count)
560 outl(addr, s->iobase + CODEC_CMI_DAC_FRAME1);
561 outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2);
562 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, 0);
563 if (s->status & DO_DUAL_DAC)
564 set_dmadac1(s, 0, count);
567 static void set_countadc(struct cm_state *s, unsigned count)
569 outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2 + 2);
572 static void set_countdac(struct cm_state *s, unsigned count)
574 outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2 + 2);
575 if (s->status & DO_DUAL_DAC)
576 set_countadc(s, count);
579 static unsigned get_dmadac(struct cm_state *s)
581 unsigned int curr_addr;
583 curr_addr = inw(s->iobase + CODEC_CMI_DAC_FRAME2) + 1;
584 curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
585 curr_addr = s->dma_dac.dmasize - curr_addr;
590 static unsigned get_dmaadc(struct cm_state *s)
592 unsigned int curr_addr;
594 curr_addr = inw(s->iobase + CODEC_CMI_ADC_FRAME2) + 1;
595 curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_ADCSHIFT) & CM_CFMT_MASK];
596 curr_addr = s->dma_adc.dmasize - curr_addr;
601 static void wrmixer(struct cm_state *s, unsigned char idx, unsigned char data)
603 unsigned char regval, pseudo;
606 if (idx == DSP_MIX_AUXVOL_L) {
609 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0x0f;
610 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
613 if (idx == DSP_MIX_AUXVOL_R) {
615 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0xf0;
616 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
619 outb(idx, s->iobase + CODEC_SB16_ADDR);
622 if (idx == DSP_MIX_OUTMIXIDX) {
623 pseudo = data & ~0x1f;
625 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x30;
626 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
628 if (idx == DSP_MIX_ADCMIXIDX_L) {
629 pseudo = data & 0x80;
631 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x40;
632 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
634 if (idx == DSP_MIX_ADCMIXIDX_R) {
635 pseudo = data & 0x80;
636 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x80;
637 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
639 outb(data, s->iobase + CODEC_SB16_DATA);
643 static unsigned char rdmixer(struct cm_state *s, unsigned char idx)
645 unsigned char v, pseudo;
648 if (idx == DSP_MIX_AUXVOL_L) {
649 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0x0f;
653 if (idx == DSP_MIX_AUXVOL_L) {
654 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0xf0;
657 outb(idx, s->iobase + CODEC_SB16_ADDR);
659 v = inb(s->iobase + CODEC_SB16_DATA);
662 if (idx == DSP_MIX_OUTMIXIDX) {
663 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x30;
667 if (idx == DSP_MIX_ADCMIXIDX_L) {
668 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x40;
672 if (idx == DSP_MIX_ADCMIXIDX_R) {
673 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x80;
679 static void set_fmt_unlocked(struct cm_state *s, unsigned char mask, unsigned char data)
681 if (mask && s->chip_version > 0) { /* 8338 cannot keep this */
682 s->fmt = inb(s->iobase + CODEC_CMI_CHFORMAT);
685 s->fmt = (s->fmt & mask) | data;
686 outb(s->fmt, s->iobase + CODEC_CMI_CHFORMAT);
690 static void set_fmt(struct cm_state *s, unsigned char mask, unsigned char data)
694 spin_lock_irqsave(&s->lock, flags);
695 set_fmt_unlocked(s,mask,data);
696 spin_unlock_irqrestore(&s->lock, flags);
699 static void frobindir(struct cm_state *s, unsigned char idx, unsigned char mask, unsigned char data)
701 outb(idx, s->iobase + CODEC_SB16_ADDR);
703 outb((inb(s->iobase + CODEC_SB16_DATA) & mask) | data, s->iobase + CODEC_SB16_DATA);
714 { 5512, (0 + 5512) / 2, (5512 + 8000) / 2, 0 },
715 { 8000, (5512 + 8000) / 2, (8000 + 11025) / 2, 4 },
716 { 11025, (8000 + 11025) / 2, (11025 + 16000) / 2, 1 },
717 { 16000, (11025 + 16000) / 2, (16000 + 22050) / 2, 5 },
718 { 22050, (16000 + 22050) / 2, (22050 + 32000) / 2, 2 },
719 { 32000, (22050 + 32000) / 2, (32000 + 44100) / 2, 6 },
720 { 44100, (32000 + 44100) / 2, (44100 + 48000) / 2, 3 },
721 { 48000, (44100 + 48000) / 2, 48000, 7 }
724 static void set_spdif_copyright(struct cm_state *s, int spdif_copyright)
726 /* enable SPDIF-in Copyright */
727 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~SPDCOPYRHT, spdif_copyright ? SPDCOPYRHT : 0);
730 static void set_spdif_loop(struct cm_state *s, int spdif_loop)
732 /* enable SPDIF loop */
734 s->status |= DO_SPDIF_LOOP;
735 /* turn on spdif-in to spdif-out */
736 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, SPDFLOOP);
738 s->status &= ~DO_SPDIF_LOOP;
739 /* turn off spdif-in to spdif-out */
740 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDFLOOP, 0);
744 static void set_spdif_monitor(struct cm_state *s, int channel)
747 maskw(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDO2DAC, channel == 2 ? SPDO2DAC : 0);
749 if (s->chip_version >= 39)
750 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, channel ? CDPLAY : 0);
753 static void set_spdifout_level(struct cm_state *s, int level5v)
756 if (s->chip_version > 0)
757 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~SPDO5V, level5v ? SPDO5V : 0);
760 static void set_spdifin_inverse(struct cm_state *s, int spdif_inverse)
762 if (s->chip_version == 0) /* 8338 has not this feature */
765 /* turn on spdif-in inverse */
766 if (s->chip_version >= 39)
767 maskb(s->iobase + CODEC_CMI_CHFORMAT, ~0, INVSPDIFI);
769 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 1);
771 /* turn off spdif-ininverse */
772 if (s->chip_version >= 39)
773 maskb(s->iobase + CODEC_CMI_CHFORMAT, ~INVSPDIFI, 0);
775 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~1, 0);
779 static void set_spdifin_channel2(struct cm_state *s, int channel2)
782 if (s->chip_version >= 39)
783 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 1, ~SELSPDIFI2, channel2 ? SELSPDIFI2 : 0);
786 static void set_spdifin_valid(struct cm_state *s, int valid)
789 maskb(s->iobase + CODEC_CMI_MISC, ~SPDVALID, valid ? SPDVALID : 0);
792 static void set_spdifout_unlocked(struct cm_state *s, unsigned rate)
794 if (rate != 48000 && rate != 44100)
796 if (rate == 48000 || rate == 44100) {
797 set_spdif_loop(s, 0);
799 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
800 // SPDIFI48K SPDF_AC97
801 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
802 if (s->chip_version >= 55)
804 maskb(s->iobase + CODEC_CMI_MISC_CTRL2, ~SPD32KFMT, rate == 48000 ? SPD32KFMT : 0);
805 if (s->chip_version > 0)
807 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~0, ENSPDOUT);
809 set_spdif_monitor(s, 2);
810 s->status |= DO_SPDIF_OUT;
812 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
813 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~ENSPDOUT, 0);
815 set_spdif_monitor(s, 0);
816 s->status &= ~DO_SPDIF_OUT;
820 static void set_spdifout(struct cm_state *s, unsigned rate)
824 spin_lock_irqsave(&s->lock, flags);
825 set_spdifout_unlocked(s,rate);
826 spin_unlock_irqrestore(&s->lock, flags);
829 static void set_spdifin_unlocked(struct cm_state *s, unsigned rate)
831 if (rate == 48000 || rate == 44100) {
833 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
834 // SPDIFI48K SPDF_AC97
835 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
836 s->status |= DO_SPDIF_IN;
838 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
839 s->status &= ~DO_SPDIF_IN;
843 static void set_spdifin(struct cm_state *s, unsigned rate)
847 spin_lock_irqsave(&s->lock, flags);
848 set_spdifin_unlocked(s,rate);
849 spin_unlock_irqrestore(&s->lock, flags);
852 /* find parity for bit 4~30 */
853 static unsigned parity(unsigned data)
858 data >>= 4; // start from bit 4
859 while (counter <= 30) {
868 static void set_ac3_unlocked(struct cm_state *s, unsigned rate)
870 if (!(s->capability & CAN_AC3))
873 if (rate && rate != 44100)
875 if (rate == 48000 || rate == 44100) {
877 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, WSMUTE);
878 if (s->chip_version >= 39)
879 maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~0, MUTECH1);
880 // AC3EN for 039, 0x04
881 if (s->chip_version >= 39) {
882 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, AC3_EN);
883 if (s->chip_version == 55)
884 maskb(s->iobase + CODEC_CMI_SPDIF_CTRL, ~2, 0);
885 // AC3EN for 037, 0x10
886 } else if (s->chip_version == 37)
887 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x10);
888 if (s->capability & CAN_AC3_HW) {
889 // SPD24SEL for 039, 0x20, but cannot be set
890 if (s->chip_version == 39)
891 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, SPD24SEL);
892 // SPD24SEL for 037, 0x02
893 else if (s->chip_version == 37)
894 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x02);
895 if (s->chip_version >= 39)
896 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, 0);
898 s->status |= DO_AC3_HW;
900 // SPD32SEL for 037 & 039
901 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, SPD32SEL);
902 // set 176K sample rate to fix 033 HW bug
903 if (s->chip_version == 33) {
905 maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0, 0x08);
907 maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
909 s->status |= DO_AC3_SW;
912 maskb(s->iobase + CODEC_CMI_MIXER1, ~WSMUTE, 0);
913 if (s->chip_version >= 39)
914 maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~MUTECH1, 0);
915 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~(SPD24SEL|0x12), 0);
916 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~(SPD32SEL|AC3_EN), 0);
917 if (s->chip_version == 33)
918 maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
919 if (s->chip_version >= 39)
920 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, CDPLAY);
921 s->status &= ~DO_AC3;
923 s->spdif_counter = 0;
926 static void set_line_as_rear(struct cm_state *s, int use_line_as_rear)
928 if (!(s->capability & CAN_LINE_AS_REAR))
930 if (use_line_as_rear) {
931 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, SPK4);
932 s->status |= DO_LINE_AS_REAR;
934 maskb(s->iobase + CODEC_CMI_MIXER1, ~SPK4, 0);
935 s->status &= ~DO_LINE_AS_REAR;
939 static void set_line_as_bass(struct cm_state *s, int use_line_as_bass)
941 if (!(s->capability & CAN_LINE_AS_BASS))
943 if (use_line_as_bass) {
944 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~0, CB2LIN);
945 s->status |= DO_LINE_AS_BASS;
947 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CB2LIN, 0);
948 s->status &= ~DO_LINE_AS_BASS;
952 static void set_mic_as_bass(struct cm_state *s, int use_mic_as_bass)
954 if (!(s->capability & CAN_MIC_AS_BASS))
956 if (use_mic_as_bass) {
957 maskb(s->iobase + CODEC_CMI_MISC, ~0, 0x04);
958 s->status |= DO_MIC_AS_BASS;
960 maskb(s->iobase + CODEC_CMI_MISC, ~0x04, 0);
961 s->status &= ~DO_MIC_AS_BASS;
965 static void set_hw_copy(struct cm_state *s, int hw_copy)
967 if (s->max_channels > 2 && hw_copy)
968 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~0, N4SPK3D);
970 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~N4SPK3D, 0);
973 static void set_ac3(struct cm_state *s, unsigned rate)
977 spin_lock_irqsave(&s->lock, flags);
978 set_spdifout_unlocked(s, rate);
979 set_ac3_unlocked(s, rate);
980 spin_unlock_irqrestore(&s->lock, flags);
983 static int trans_ac3(struct cm_state *s, void *dest, const char *source, int size)
987 unsigned short data16;
988 unsigned long *dst = (unsigned long *) dest;
989 unsigned short *src = (unsigned short *)source;
993 if ((err = __get_user(data16, src++)))
995 data = (unsigned long)le16_to_cpu(data16);
996 data <<= 12; // ok for 16-bit data
997 if (s->spdif_counter == 2 || s->spdif_counter == 3)
998 data |= 0x40000000; // indicate AC-3 raw data
1000 data |= 0x80000000; // parity
1001 if (s->spdif_counter == 0)
1002 data |= 3; // preamble 'M'
1003 else if (s->spdif_counter & 1)
1004 data |= 5; // odd, 'W'
1006 data |= 9; // even, 'M'
1007 *dst++ = cpu_to_le32(data);
1009 if (s->spdif_counter == 384)
1010 s->spdif_counter = 0;
1016 static void set_adc_rate_unlocked(struct cm_state *s, unsigned rate)
1018 unsigned char freq = 4;
1025 for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1026 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1027 rate = rate_lookup[i].rate;
1028 freq = rate_lookup[i].freq;
1033 freq <<= CM_FREQ_ADCSHIFT;
1035 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1038 static void set_adc_rate(struct cm_state *s, unsigned rate)
1040 unsigned long flags;
1041 unsigned char freq = 4;
1048 for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1049 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1050 rate = rate_lookup[i].rate;
1051 freq = rate_lookup[i].freq;
1056 freq <<= CM_FREQ_ADCSHIFT;
1058 spin_lock_irqsave(&s->lock, flags);
1059 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1060 spin_unlock_irqrestore(&s->lock, flags);
1063 static void set_dac_rate(struct cm_state *s, unsigned rate)
1065 unsigned long flags;
1066 unsigned char freq = 4;
1073 for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1074 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1075 rate = rate_lookup[i].rate;
1076 freq = rate_lookup[i].freq;
1081 freq <<= CM_FREQ_DACSHIFT;
1083 spin_lock_irqsave(&s->lock, flags);
1084 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~DSFC, freq);
1085 spin_unlock_irqrestore(&s->lock, flags);
1087 if (s->curr_channels <= 2 && spdif_out)
1088 set_spdifout(s, rate);
1089 if (s->status & DO_DUAL_DAC)
1090 set_dac1_rate(s, rate);
1093 /* --------------------------------------------------------------------- */
1094 static inline void reset_adc(struct cm_state *s)
1096 /* reset bus master */
1097 outb(s->enable | RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1099 outb(s->enable & ~RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1102 static inline void reset_dac(struct cm_state *s)
1104 /* reset bus master */
1105 outb(s->enable | RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1107 outb(s->enable & ~RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1108 if (s->status & DO_DUAL_DAC)
1112 static inline void pause_adc(struct cm_state *s)
1114 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEADC);
1117 static inline void pause_dac(struct cm_state *s)
1119 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEDAC);
1120 if (s->status & DO_DUAL_DAC)
1124 static inline void disable_adc(struct cm_state *s)
1126 /* disable channel */
1127 s->enable &= ~ENADC;
1128 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1132 static inline void disable_dac(struct cm_state *s)
1134 /* disable channel */
1135 s->enable &= ~ENDAC;
1136 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1138 if (s->status & DO_DUAL_DAC)
1142 static inline void enable_adc(struct cm_state *s)
1144 if (!(s->enable & ENADC)) {
1145 /* enable channel */
1147 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1149 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEADC, 0);
1152 static inline void enable_dac_unlocked(struct cm_state *s)
1154 if (!(s->enable & ENDAC)) {
1155 /* enable channel */
1157 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1159 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEDAC, 0);
1161 if (s->status & DO_DUAL_DAC)
1165 static inline void enable_dac(struct cm_state *s)
1167 unsigned long flags;
1169 spin_lock_irqsave(&s->lock, flags);
1170 enable_dac_unlocked(s);
1171 spin_unlock_irqrestore(&s->lock, flags);
1174 static inline void stop_adc_unlocked(struct cm_state *s)
1176 if (s->enable & ENADC) {
1177 /* disable interrupt */
1178 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENADCINT, 0);
1183 static inline void stop_adc(struct cm_state *s)
1185 unsigned long flags;
1187 spin_lock_irqsave(&s->lock, flags);
1188 stop_adc_unlocked(s);
1189 spin_unlock_irqrestore(&s->lock, flags);
1193 static inline void stop_dac_unlocked(struct cm_state *s)
1195 if (s->enable & ENDAC) {
1196 /* disable interrupt */
1197 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENDACINT, 0);
1200 if (s->status & DO_DUAL_DAC)
1201 stop_dac1_unlocked(s);
1204 static inline void stop_dac(struct cm_state *s)
1206 unsigned long flags;
1208 spin_lock_irqsave(&s->lock, flags);
1209 stop_dac_unlocked(s);
1210 spin_unlock_irqrestore(&s->lock, flags);
1213 static inline void start_adc_unlocked(struct cm_state *s)
1215 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1216 && s->dma_adc.ready) {
1217 /* enable interrupt */
1218 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1223 static void start_adc(struct cm_state *s)
1225 unsigned long flags;
1227 spin_lock_irqsave(&s->lock, flags);
1228 start_adc_unlocked(s);
1229 spin_unlock_irqrestore(&s->lock, flags);
1232 static void start_dac1_unlocked(struct cm_state *s)
1234 if ((s->dma_adc.mapped || s->dma_adc.count > 0) && s->dma_adc.ready) {
1235 /* enable interrupt */
1236 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1237 enable_dac_unlocked(s);
1241 static void start_dac_unlocked(struct cm_state *s)
1243 if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
1244 /* enable interrupt */
1245 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENDACINT);
1246 enable_dac_unlocked(s);
1248 if (s->status & DO_DUAL_DAC)
1249 start_dac1_unlocked(s);
1252 static void start_dac(struct cm_state *s)
1254 unsigned long flags;
1256 spin_lock_irqsave(&s->lock, flags);
1257 start_dac_unlocked(s);
1258 spin_unlock_irqrestore(&s->lock, flags);
1261 static int prog_dmabuf(struct cm_state *s, unsigned rec);
1263 static int set_dac_channels(struct cm_state *s, int channels)
1265 unsigned long flags;
1266 static unsigned int fmmute = 0;
1268 spin_lock_irqsave(&s->lock, flags);
1270 if ((channels > 2) && (channels <= s->max_channels)
1271 && (((s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK) == (CM_CFMT_STEREO | CM_CFMT_16BIT))) {
1272 set_spdifout_unlocked(s, 0);
1273 if (s->capability & CAN_MULTI_CH_HW) {
1275 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0, NXCHG);
1277 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), channels > 4 ? CHB3D5C : CHB3D);
1279 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, channels == 6 ? CHB3D6C : 0);
1281 maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~ENCENTER, channels == 6 ? ENCENTER : 0);
1282 s->status |= DO_MULTI_CH_HW;
1283 } else if (s->capability & CAN_DUAL_DAC) {
1284 unsigned char fmtm = ~0, fmts = 0;
1287 // ENDBDAC, turn on double DAC mode
1288 // XCHGDAC, CH0 -> back, CH1->front
1289 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, ENDBDAC|XCHGDAC);
1291 fmmute = inb(s->iobase + CODEC_CMI_MIXER1) & FMMUTE;
1292 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, FMMUTE);
1293 s->status |= DO_DUAL_DAC;
1294 // prepare secondary buffer
1295 spin_unlock_irqrestore(&s->lock, flags);
1296 ret = prog_dmabuf(s, 1);
1297 if (ret) return ret;
1298 spin_lock_irqsave(&s->lock, flags);
1300 // copy the hw state
1301 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
1302 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
1303 // the HW only support 16-bit stereo
1304 fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
1305 fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
1306 fmts |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
1307 fmts |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
1309 set_fmt_unlocked(s, fmtm, fmts);
1310 set_adc_rate_unlocked(s, s->ratedac);
1312 // disable 4 speaker mode (analog duplicate)
1314 s->curr_channels = channels;
1316 // enable jack redirect
1317 set_line_as_rear(s, use_line_as_rear);
1319 set_line_as_bass(s, use_line_as_bass);
1320 set_mic_as_bass(s, use_mic_as_bass);
1323 if (s->status & DO_MULTI_CH_HW) {
1324 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~NXCHG, 0);
1325 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), 0);
1326 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, 0);
1327 } else if (s->status & DO_DUAL_DAC) {
1328 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~ENDBDAC, 0);
1329 maskb(s->iobase + CODEC_CMI_MIXER1, ~FMMUTE, fmmute);
1331 // enable 4 speaker mode (analog duplicate)
1332 set_hw_copy(s, hw_copy);
1333 s->status &= ~DO_MULTI_CH;
1334 s->curr_channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
1335 // disable jack redirect
1336 set_line_as_rear(s, hw_copy ? use_line_as_rear : 0);
1337 set_line_as_bass(s, 0);
1338 set_mic_as_bass(s, 0);
1340 spin_unlock_irqrestore(&s->lock, flags);
1341 return s->curr_channels;
1344 /* --------------------------------------------------------------------- */
1346 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
1347 #define DMABUF_MINORDER 1
1349 static void dealloc_dmabuf(struct cm_state *s, struct dmabuf *db)
1351 struct page *pstart, *pend;
1354 /* undo marking the pages as reserved */
1355 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1356 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1357 ClearPageReserved(pstart);
1358 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
1361 db->mapped = db->ready = 0;
1364 /* Ch1 is used for playback, Ch0 is used for recording */
1366 static int prog_dmabuf(struct cm_state *s, unsigned rec)
1368 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1369 unsigned rate = rec ? s->rateadc : s->ratedac;
1371 unsigned bytepersec;
1373 struct page *pstart, *pend;
1375 unsigned long flags;
1380 fmt >>= CM_CFMT_ADCSHIFT;
1383 fmt >>= CM_CFMT_DACSHIFT;
1386 fmt &= CM_CFMT_MASK;
1387 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1389 db->ready = db->mapped = 0;
1390 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
1391 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
1393 if (!db->rawbuf || !db->dmaaddr)
1395 db->buforder = order;
1396 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
1397 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1398 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1399 SetPageReserved(pstart);
1401 bytepersec = rate << sample_shift[fmt];
1402 bufs = PAGE_SIZE << db->buforder;
1403 if (db->ossfragshift) {
1404 if ((1000 << db->ossfragshift) < bytepersec)
1405 db->fragshift = ld2(bytepersec/1000);
1407 db->fragshift = db->ossfragshift;
1409 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1410 if (db->fragshift < 3)
1413 db->numfrag = bufs >> db->fragshift;
1414 while (db->numfrag < 4 && db->fragshift > 3) {
1416 db->numfrag = bufs >> db->fragshift;
1418 db->fragsize = 1 << db->fragshift;
1419 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1420 db->numfrag = db->ossmaxfrags;
1421 /* to make fragsize >= 4096 */
1422 db->fragsamples = db->fragsize >> sample_shift[fmt];
1423 db->dmasize = db->numfrag << db->fragshift;
1424 db->dmasamples = db->dmasize >> sample_shift[fmt];
1425 memset(db->rawbuf, (fmt & CM_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
1426 spin_lock_irqsave(&s->lock, flags);
1428 if (s->status & DO_DUAL_DAC)
1429 set_dmadac1(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1431 set_dmaadc(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1432 /* program sample counts */
1433 set_countdac(s, db->fragsamples);
1435 set_dmadac(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1436 /* program sample counts */
1437 set_countdac(s, db->fragsamples);
1439 spin_unlock_irqrestore(&s->lock, flags);
1445 static inline void clear_advance(struct cm_state *s)
1447 unsigned char c = (s->fmt & (CM_CFMT_16BIT << CM_CFMT_DACSHIFT)) ? 0 : 0x80;
1448 unsigned char *buf = s->dma_dac.rawbuf;
1449 unsigned char *buf1 = s->dma_adc.rawbuf;
1450 unsigned bsize = s->dma_dac.dmasize;
1451 unsigned bptr = s->dma_dac.swptr;
1452 unsigned len = s->dma_dac.fragsize;
1454 if (bptr + len > bsize) {
1455 unsigned x = bsize - bptr;
1456 memset(buf + bptr, c, x);
1457 if (s->status & DO_DUAL_DAC)
1458 memset(buf1 + bptr, c, x);
1462 memset(buf + bptr, c, len);
1463 if (s->status & DO_DUAL_DAC)
1464 memset(buf1 + bptr, c, len);
1467 /* call with spinlock held! */
1468 static void cm_update_ptr(struct cm_state *s)
1473 /* update ADC pointer */
1474 if (s->dma_adc.ready) {
1475 if (s->status & DO_DUAL_DAC) {
1476 /* the dac part will finish for this */
1478 hwptr = get_dmaadc(s) % s->dma_adc.dmasize;
1479 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1480 s->dma_adc.hwptr = hwptr;
1481 s->dma_adc.total_bytes += diff;
1482 s->dma_adc.count += diff;
1483 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1484 wake_up(&s->dma_adc.wait);
1485 if (!s->dma_adc.mapped) {
1486 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1493 /* update DAC pointer */
1494 if (s->dma_dac.ready) {
1495 hwptr = get_dmadac(s) % s->dma_dac.dmasize;
1496 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1497 s->dma_dac.hwptr = hwptr;
1498 s->dma_dac.total_bytes += diff;
1499 if (s->status & DO_DUAL_DAC) {
1500 s->dma_adc.hwptr = hwptr;
1501 s->dma_adc.total_bytes += diff;
1503 if (s->dma_dac.mapped) {
1504 s->dma_dac.count += diff;
1505 if (s->status & DO_DUAL_DAC)
1506 s->dma_adc.count += diff;
1507 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1508 wake_up(&s->dma_dac.wait);
1510 s->dma_dac.count -= diff;
1511 if (s->status & DO_DUAL_DAC)
1512 s->dma_adc.count -= diff;
1513 if (s->dma_dac.count <= 0) {
1516 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1518 s->dma_dac.endcleared = 1;
1519 if (s->status & DO_DUAL_DAC)
1520 s->dma_adc.endcleared = 1;
1522 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
1523 wake_up(&s->dma_dac.wait);
1528 static irqreturn_t cm_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1530 struct cm_state *s = (struct cm_state *)dev_id;
1531 unsigned int intsrc, intstat;
1532 unsigned char mask = 0;
1534 /* fastpath out, to ease interrupt sharing */
1535 intsrc = inl(s->iobase + CODEC_CMI_INT_STATUS);
1536 if (!(intsrc & 0x80000000))
1538 spin_lock(&s->lock);
1539 intstat = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1540 /* acknowledge interrupt */
1541 if (intsrc & ADCINT)
1543 if (intsrc & DACINT)
1545 outb(intstat & ~mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1546 outb(intstat | mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1548 spin_unlock(&s->lock);
1549 #ifdef CONFIG_SOUND_CMPCI_MIDI
1550 if (intsrc & 0x00010000) { // UART interrupt
1551 if (s->midi_devc && intchk_mpu401((void *)s->midi_devc))
1552 mpuintr(irq, (void *)s->midi_devc, regs);
1554 inb(s->iomidi);// dummy read
1560 /* --------------------------------------------------------------------- */
1562 static const char invalid_magic[] = KERN_CRIT "cmpci: invalid magic value\n";
1564 #define VALIDATE_STATE(s) \
1566 if (!(s) || (s)->magic != CM_MAGIC) { \
1567 printk(invalid_magic); \
1572 /* --------------------------------------------------------------------- */
1576 #define MT_4MUTEMONO 3
1578 #define MT_5MUTEMONO 5
1580 static const struct {
1586 } mixtable[SOUND_MIXER_NRDEVICES] = {
1587 [SOUND_MIXER_CD] = { DSP_MIX_CDVOLIDX_L, DSP_MIX_CDVOLIDX_R, MT_5MUTE, 0x04, 0x06 },
1588 [SOUND_MIXER_LINE] = { DSP_MIX_LINEVOLIDX_L, DSP_MIX_LINEVOLIDX_R, MT_5MUTE, 0x10, 0x18 },
1589 [SOUND_MIXER_MIC] = { DSP_MIX_MICVOLIDX, DSP_MIX_MICVOLIDX, MT_5MUTEMONO, 0x01, 0x01 },
1590 [SOUND_MIXER_SYNTH] = { DSP_MIX_FMVOLIDX_L, DSP_MIX_FMVOLIDX_R, MT_5MUTE, 0x40, 0x00 },
1591 [SOUND_MIXER_VOLUME] = { DSP_MIX_MASTERVOLIDX_L, DSP_MIX_MASTERVOLIDX_R, MT_5MUTE, 0x00, 0x00 },
1592 [SOUND_MIXER_PCM] = { DSP_MIX_VOICEVOLIDX_L, DSP_MIX_VOICEVOLIDX_R, MT_5MUTE, 0x00, 0x00 },
1593 [SOUND_MIXER_LINE1] = { DSP_MIX_AUXVOL_L, DSP_MIX_AUXVOL_R, MT_5MUTE, 0x80, 0x60 },
1594 [SOUND_MIXER_SPEAKER]= { DSP_MIX_SPKRVOLIDX, DSP_MIX_SPKRVOLIDX, MT_5MUTEMONO, 0x00, 0x01 }
1597 static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1599 [SOUND_MIXER_CD] = 1,
1600 [SOUND_MIXER_LINE] = 2,
1601 [SOUND_MIXER_MIC] = 3,
1602 [SOUND_MIXER_SYNTH] = 4,
1603 [SOUND_MIXER_VOLUME] = 5,
1604 [SOUND_MIXER_PCM] = 6,
1605 [SOUND_MIXER_LINE1] = 7,
1606 [SOUND_MIXER_SPEAKER]= 8
1609 static unsigned mixer_outmask(struct cm_state *s)
1611 unsigned long flags;
1614 spin_lock_irqsave(&s->lock, flags);
1615 j = rdmixer(s, DSP_MIX_OUTMIXIDX);
1616 spin_unlock_irqrestore(&s->lock, flags);
1617 for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1618 if (j & mixtable[i].play)
1623 static unsigned mixer_recmask(struct cm_state *s)
1625 unsigned long flags;
1628 spin_lock_irqsave(&s->lock, flags);
1629 j = rdmixer(s, DSP_MIX_ADCMIXIDX_L);
1630 spin_unlock_irqrestore(&s->lock, flags);
1631 for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1632 if (j & mixtable[i].rec)
1637 static int mixer_ioctl(struct cm_state *s, unsigned int cmd, unsigned long arg)
1639 unsigned long flags;
1641 unsigned char l, r, rl, rr;
1644 if (cmd == SOUND_MIXER_INFO) {
1646 memset(&info, 0, sizeof(info));
1647 strlcpy(info.id, "cmpci", sizeof(info.id));
1648 strlcpy(info.name, "C-Media PCI", sizeof(info.name));
1649 info.modify_counter = s->mix.modcnt;
1650 if (copy_to_user((void *)arg, &info, sizeof(info)))
1654 if (cmd == SOUND_OLD_MIXER_INFO) {
1655 _old_mixer_info info;
1656 memset(&info, 0, sizeof(info));
1657 strlcpy(info.id, "cmpci", sizeof(info.id));
1658 strlcpy(info.name, "C-Media cmpci", sizeof(info.name));
1659 if (copy_to_user((void *)arg, &info, sizeof(info)))
1663 if (cmd == OSS_GETVERSION)
1664 return put_user(SOUND_VERSION, (int *)arg);
1665 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1667 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1668 switch (_IOC_NR(cmd)) {
1669 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1670 val = mixer_recmask(s);
1671 return put_user(val, (int *)arg);
1673 case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1674 val = mixer_outmask(s);
1675 return put_user(val, (int *)arg);
1677 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
1678 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1679 if (mixtable[i].type)
1681 return put_user(val, (int *)arg);
1683 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1684 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1685 if (mixtable[i].rec)
1687 return put_user(val, (int *)arg);
1689 case SOUND_MIXER_OUTMASK: /* Arg contains a bit for each supported recording source */
1690 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1691 if (mixtable[i].play)
1693 return put_user(val, (int *)arg);
1695 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1696 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1697 if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1699 return put_user(val, (int *)arg);
1701 case SOUND_MIXER_CAPS:
1702 return put_user(0, (int *)arg);
1706 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1710 return put_user(s->mix.vol[volidx[i]-1], (int *)arg);
1713 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1716 switch (_IOC_NR(cmd)) {
1717 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1718 if (get_user(val, (int *)arg))
1720 i = generic_hweight32(val);
1721 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1722 if (!(val & (1 << i)))
1724 if (!mixtable[i].rec) {
1728 j |= mixtable[i].rec;
1730 spin_lock_irqsave(&s->lock, flags);
1731 wrmixer(s, DSP_MIX_ADCMIXIDX_L, j);
1732 wrmixer(s, DSP_MIX_ADCMIXIDX_R, (j & 1) | (j>>1) | (j & 0x80));
1733 spin_unlock_irqrestore(&s->lock, flags);
1736 case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1737 if (get_user(val, (int *)arg))
1739 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1740 if (!(val & (1 << i)))
1742 if (!mixtable[i].play) {
1746 j |= mixtable[i].play;
1748 spin_lock_irqsave(&s->lock, flags);
1749 wrmixer(s, DSP_MIX_OUTMIXIDX, j);
1750 spin_unlock_irqrestore(&s->lock, flags);
1755 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1757 if (get_user(val, (int *)arg))
1760 r = (val >> 8) & 0xff;
1765 spin_lock_irqsave(&s->lock, flags);
1766 switch (mixtable[i].type) {
1772 frobindir(s, mixtable[i].left, 0xf0, l / 6);
1773 frobindir(s, mixtable[i].right, 0xf0, l / 6);
1777 rl = (l < 4 ? 0 : (l - 5) / 3) & 31;
1779 wrmixer(s, mixtable[i].left, rl<<3);
1780 if (i == SOUND_MIXER_MIC)
1781 maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1785 rl = l < 4 ? 0 : (l - 5) / 3;
1786 wrmixer(s, mixtable[i].left, rl<<3);
1787 l = rdmixer(s, DSP_MIX_OUTMIXIDX) & ~mixtable[i].play;
1788 r = rl ? mixtable[i].play : 0;
1789 wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1791 if (i == SOUND_MIXER_MIC) {
1792 if (s->chip_version >= 37) {
1794 maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, (rr&0x07)<<1);
1795 frobindir(s, DSP_MIX_EXTENSION, ~0x01, rr>>3);
1798 maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1804 rl = l < 4 ? 0 : (l - 5) / 3;
1805 rr = r < 4 ? 0 : (r - 5) / 3;
1806 wrmixer(s, mixtable[i].left, rl<<3);
1807 wrmixer(s, mixtable[i].right, rr<<3);
1808 l = rdmixer(s, DSP_MIX_OUTMIXIDX);
1809 l &= ~mixtable[i].play;
1810 r = (rl|rr) ? mixtable[i].play : 0;
1811 wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1823 wrmixer(s, mixtable[i].left, rl);
1824 wrmixer(s, mixtable[i].right, rr);
1827 spin_unlock_irqrestore(&s->lock, flags);
1831 s->mix.vol[volidx[i]-1] = val;
1832 return put_user(s->mix.vol[volidx[i]-1], (int *)arg);
1836 /* --------------------------------------------------------------------- */
1838 static int cm_open_mixdev(struct inode *inode, struct file *file)
1840 int minor = iminor(inode);
1841 struct list_head *list;
1844 for (list = devs.next; ; list = list->next) {
1847 s = list_entry(list, struct cm_state, devs);
1848 if (s->dev_mixer == minor)
1852 file->private_data = s;
1856 static int cm_release_mixdev(struct inode *inode, struct file *file)
1858 struct cm_state *s = (struct cm_state *)file->private_data;
1864 static int cm_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1866 return mixer_ioctl((struct cm_state *)file->private_data, cmd, arg);
1869 static /*const*/ struct file_operations cm_mixer_fops = {
1870 .owner = THIS_MODULE,
1871 .llseek = no_llseek,
1872 .ioctl = cm_ioctl_mixdev,
1873 .open = cm_open_mixdev,
1874 .release = cm_release_mixdev,
1878 /* --------------------------------------------------------------------- */
1880 static int drain_dac(struct cm_state *s, int nonblock)
1882 DECLARE_WAITQUEUE(wait, current);
1883 unsigned long flags;
1886 if (s->dma_dac.mapped || !s->dma_dac.ready)
1888 add_wait_queue(&s->dma_dac.wait, &wait);
1890 __set_current_state(TASK_INTERRUPTIBLE);
1891 spin_lock_irqsave(&s->lock, flags);
1892 count = s->dma_dac.count;
1893 spin_unlock_irqrestore(&s->lock, flags);
1896 if (signal_pending(current))
1899 remove_wait_queue(&s->dma_dac.wait, &wait);
1900 set_current_state(TASK_RUNNING);
1903 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
1904 tmo >>= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
1905 if (!schedule_timeout(tmo + 1))
1906 DBG(printk(KERN_DEBUG "cmpci: dma timed out??\n");)
1908 remove_wait_queue(&s->dma_dac.wait, &wait);
1909 set_current_state(TASK_RUNNING);
1910 if (signal_pending(current))
1911 return -ERESTARTSYS;
1915 /* --------------------------------------------------------------------- */
1917 static ssize_t cm_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1919 struct cm_state *s = (struct cm_state *)file->private_data;
1920 DECLARE_WAITQUEUE(wait, current);
1922 unsigned long flags;
1927 if (ppos != &file->f_pos)
1929 if (s->dma_adc.mapped)
1931 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1933 if (!access_ok(VERIFY_WRITE, buffer, count))
1937 add_wait_queue(&s->dma_adc.wait, &wait);
1939 spin_lock_irqsave(&s->lock, flags);
1940 swptr = s->dma_adc.swptr;
1941 cnt = s->dma_adc.dmasize-swptr;
1942 if (s->dma_adc.count < cnt)
1943 cnt = s->dma_adc.count;
1945 __set_current_state(TASK_INTERRUPTIBLE);
1946 spin_unlock_irqrestore(&s->lock, flags);
1950 if (s->dma_adc.enabled)
1952 if (file->f_flags & O_NONBLOCK) {
1957 if (!schedule_timeout(HZ)) {
1958 printk(KERN_DEBUG "cmpci: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1959 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1960 s->dma_adc.hwptr, s->dma_adc.swptr);
1961 spin_lock_irqsave(&s->lock, flags);
1962 stop_adc_unlocked(s);
1963 set_dmaadc(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
1964 /* program sample counts */
1965 set_countadc(s, s->dma_adc.fragsamples);
1966 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1967 spin_unlock_irqrestore(&s->lock, flags);
1969 if (signal_pending(current)) {
1976 if (s->status & DO_BIGENDIAN_R) {
1978 unsigned char *src, *dst;
1979 unsigned char data[2];
1981 src = (unsigned char *) (s->dma_adc.rawbuf + swptr);
1982 dst = (unsigned char *) buffer;
1983 // copy left/right sample at one time
1984 for (i = 0; i < cnt / 2; i++) {
1987 if ((err = __put_user(data[0], dst++))) {
1991 if ((err = __put_user(data[1], dst++))) {
1997 } else if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
2002 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2003 spin_lock_irqsave(&s->lock, flags);
2004 s->dma_adc.swptr = swptr;
2005 s->dma_adc.count -= cnt;
2009 if (s->dma_adc.enabled)
2010 start_adc_unlocked(s);
2011 spin_unlock_irqrestore(&s->lock, flags);
2014 remove_wait_queue(&s->dma_adc.wait, &wait);
2015 set_current_state(TASK_RUNNING);
2019 static ssize_t cm_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2021 struct cm_state *s = (struct cm_state *)file->private_data;
2022 DECLARE_WAITQUEUE(wait, current);
2024 unsigned long flags;
2029 if (ppos != &file->f_pos)
2031 if (s->dma_dac.mapped)
2033 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2035 if (!access_ok(VERIFY_READ, buffer, count))
2037 if (s->status & DO_DUAL_DAC) {
2038 if (s->dma_adc.mapped)
2040 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2043 if (!access_ok(VERIFY_READ, buffer, count))
2047 add_wait_queue(&s->dma_dac.wait, &wait);
2049 spin_lock_irqsave(&s->lock, flags);
2050 if (s->dma_dac.count < 0) {
2051 s->dma_dac.count = 0;
2052 s->dma_dac.swptr = s->dma_dac.hwptr;
2054 if (s->status & DO_DUAL_DAC) {
2055 s->dma_adc.swptr = s->dma_dac.swptr;
2056 s->dma_adc.count = s->dma_dac.count;
2057 s->dma_adc.endcleared = s->dma_dac.endcleared;
2059 swptr = s->dma_dac.swptr;
2060 cnt = s->dma_dac.dmasize-swptr;
2061 if (s->status & DO_AC3_SW) {
2062 if (s->dma_dac.count + 2 * cnt > s->dma_dac.dmasize)
2063 cnt = (s->dma_dac.dmasize - s->dma_dac.count) / 2;
2065 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
2066 cnt = s->dma_dac.dmasize - s->dma_dac.count;
2069 __set_current_state(TASK_INTERRUPTIBLE);
2070 spin_unlock_irqrestore(&s->lock, flags);
2073 if ((s->status & DO_DUAL_DAC) && (cnt > count / 2))
2076 if (s->dma_dac.enabled)
2078 if (file->f_flags & O_NONBLOCK) {
2083 if (!schedule_timeout(HZ)) {
2084 printk(KERN_DEBUG "cmpci: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
2085 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
2086 s->dma_dac.hwptr, s->dma_dac.swptr);
2087 spin_lock_irqsave(&s->lock, flags);
2088 stop_dac_unlocked(s);
2089 set_dmadac(s, s->dma_dac.dmaaddr, s->dma_dac.dmasamples);
2090 /* program sample counts */
2091 set_countdac(s, s->dma_dac.fragsamples);
2092 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
2093 if (s->status & DO_DUAL_DAC) {
2094 set_dmadac1(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
2095 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
2097 spin_unlock_irqrestore(&s->lock, flags);
2099 if (signal_pending(current)) {
2106 if (s->status & DO_AC3_SW) {
2109 // clip exceeded data, caught by 033 and 037
2110 if (swptr + 2 * cnt > s->dma_dac.dmasize)
2111 cnt = (s->dma_dac.dmasize - swptr) / 2;
2112 if ((err = trans_ac3(s, s->dma_dac.rawbuf + swptr, buffer, cnt))) {
2116 swptr = (swptr + 2 * cnt) % s->dma_dac.dmasize;
2117 } else if ((s->status & DO_DUAL_DAC) && (s->status & DO_BIGENDIAN_W)) {
2119 unsigned char *src, *dst0, *dst1;
2120 unsigned char data[8];
2122 src = (unsigned char *) buffer;
2123 dst0 = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2124 dst1 = (unsigned char *) (s->dma_adc.rawbuf + swptr);
2125 // copy left/right sample at one time
2126 for (i = 0; i < cnt / 4; i++) {
2127 if ((err = __get_user(data[0], src++))) {
2131 if ((err = __get_user(data[1], src++))) {
2135 if ((err = __get_user(data[2], src++))) {
2139 if ((err = __get_user(data[3], src++))) {
2143 if ((err = __get_user(data[4], src++))) {
2147 if ((err = __get_user(data[5], src++))) {
2151 if ((err = __get_user(data[6], src++))) {
2155 if ((err = __get_user(data[7], src++))) {
2170 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2171 } else if (s->status & DO_DUAL_DAC) {
2173 unsigned long *src, *dst0, *dst1;
2175 src = (unsigned long *) buffer;
2176 dst0 = (unsigned long *) (s->dma_dac.rawbuf + swptr);
2177 dst1 = (unsigned long *) (s->dma_adc.rawbuf + swptr);
2178 // copy left/right sample at one time
2179 for (i = 0; i < cnt / 4; i++) {
2180 if ((err = __get_user(*dst0++, src++))) {
2184 if ((err = __get_user(*dst1++, src++))) {
2189 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2190 } else if (s->status & DO_BIGENDIAN_W) {
2192 unsigned char *src, *dst;
2193 unsigned char data[2];
2195 src = (unsigned char *) buffer;
2196 dst = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2197 // swap hi/lo bytes for each sample
2198 for (i = 0; i < cnt / 2; i++) {
2199 if ((err = __get_user(data[0], src++))) {
2203 if ((err = __get_user(data[1], src++))) {
2211 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2213 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
2218 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2220 spin_lock_irqsave(&s->lock, flags);
2221 s->dma_dac.swptr = swptr;
2222 s->dma_dac.count += cnt;
2223 if (s->status & DO_AC3_SW)
2224 s->dma_dac.count += cnt;
2225 s->dma_dac.endcleared = 0;
2226 spin_unlock_irqrestore(&s->lock, flags);
2230 if (s->status & DO_DUAL_DAC) {
2235 if (s->dma_dac.enabled)
2239 remove_wait_queue(&s->dma_dac.wait, &wait);
2240 set_current_state(TASK_RUNNING);
2244 static unsigned int cm_poll(struct file *file, struct poll_table_struct *wait)
2246 struct cm_state *s = (struct cm_state *)file->private_data;
2247 unsigned long flags;
2248 unsigned int mask = 0;
2251 if (file->f_mode & FMODE_WRITE) {
2252 if (!s->dma_dac.ready && prog_dmabuf(s, 0))
2254 poll_wait(file, &s->dma_dac.wait, wait);
2256 if (file->f_mode & FMODE_READ) {
2257 if (!s->dma_adc.ready && prog_dmabuf(s, 1))
2259 poll_wait(file, &s->dma_adc.wait, wait);
2261 spin_lock_irqsave(&s->lock, flags);
2263 if (file->f_mode & FMODE_READ) {
2264 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
2265 mask |= POLLIN | POLLRDNORM;
2267 if (file->f_mode & FMODE_WRITE) {
2268 if (s->dma_dac.mapped) {
2269 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
2270 mask |= POLLOUT | POLLWRNORM;
2272 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
2273 mask |= POLLOUT | POLLWRNORM;
2276 spin_unlock_irqrestore(&s->lock, flags);
2280 static int cm_mmap(struct file *file, struct vm_area_struct *vma)
2282 struct cm_state *s = (struct cm_state *)file->private_data;
2289 if (vma->vm_flags & VM_WRITE) {
2290 if ((ret = prog_dmabuf(s, 0)) != 0)
2293 } else if (vma->vm_flags & VM_READ) {
2294 if ((ret = prog_dmabuf(s, 1)) != 0)
2300 if (vma->vm_pgoff != 0)
2302 size = vma->vm_end - vma->vm_start;
2303 if (size > (PAGE_SIZE << db->buforder))
2306 if (remap_page_range(vma, vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
2315 #define SNDCTL_SPDIF_COPYRIGHT _SIOW('S', 0, int) // set/reset S/PDIF copy protection
2316 #define SNDCTL_SPDIF_LOOP _SIOW('S', 1, int) // set/reset S/PDIF loop
2317 #define SNDCTL_SPDIF_MONITOR _SIOW('S', 2, int) // set S/PDIF monitor
2318 #define SNDCTL_SPDIF_LEVEL _SIOW('S', 3, int) // set/reset S/PDIF out level
2319 #define SNDCTL_SPDIF_INV _SIOW('S', 4, int) // set/reset S/PDIF in inverse
2320 #define SNDCTL_SPDIF_SEL2 _SIOW('S', 5, int) // set S/PDIF in #2
2321 #define SNDCTL_SPDIF_VALID _SIOW('S', 6, int) // set S/PDIF valid
2322 #define SNDCTL_SPDIFOUT _SIOW('S', 7, int) // set S/PDIF out
2323 #define SNDCTL_SPDIFIN _SIOW('S', 8, int) // set S/PDIF out
2325 static int cm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2327 struct cm_state *s = (struct cm_state *)file->private_data;
2328 unsigned long flags;
2329 audio_buf_info abinfo;
2331 int val, mapped, ret;
2332 unsigned char fmtm, fmtd;
2335 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2336 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2338 case OSS_GETVERSION:
2339 return put_user(SOUND_VERSION, (int *)arg);
2341 case SNDCTL_DSP_SYNC:
2342 if (file->f_mode & FMODE_WRITE)
2343 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
2346 case SNDCTL_DSP_SETDUPLEX:
2349 case SNDCTL_DSP_GETCAPS:
2350 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP | DSP_CAP_BIND, (int *)arg);
2352 case SNDCTL_DSP_RESET:
2353 if (file->f_mode & FMODE_WRITE) {
2355 synchronize_irq(s->irq);
2356 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
2357 if (s->status & DO_DUAL_DAC)
2358 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2360 if (file->f_mode & FMODE_READ) {
2362 synchronize_irq(s->irq);
2363 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2367 case SNDCTL_DSP_SPEED:
2368 if (get_user(val, (int *)arg))
2371 if (file->f_mode & FMODE_READ) {
2372 spin_lock_irqsave(&s->lock, flags);
2373 stop_adc_unlocked(s);
2374 s->dma_adc.ready = 0;
2375 set_adc_rate_unlocked(s, val);
2376 spin_unlock_irqrestore(&s->lock, flags);
2378 if (file->f_mode & FMODE_WRITE) {
2380 s->dma_dac.ready = 0;
2381 if (s->status & DO_DUAL_DAC)
2382 s->dma_adc.ready = 0;
2383 set_dac_rate(s, val);
2386 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2388 case SNDCTL_DSP_STEREO:
2389 if (get_user(val, (int *)arg))
2393 if (file->f_mode & FMODE_READ) {
2395 s->dma_adc.ready = 0;
2397 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2399 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2401 if (file->f_mode & FMODE_WRITE) {
2403 s->dma_dac.ready = 0;
2405 fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2407 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2408 if (s->status & DO_DUAL_DAC) {
2409 s->dma_adc.ready = 0;
2411 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2413 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2416 set_fmt(s, fmtm, fmtd);
2419 case SNDCTL_DSP_CHANNELS:
2420 if (get_user(val, (int *)arg))
2425 if (file->f_mode & FMODE_READ) {
2427 s->dma_adc.ready = 0;
2429 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2431 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2433 if (file->f_mode & FMODE_WRITE) {
2435 s->dma_dac.ready = 0;
2437 fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2439 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2440 if (s->status & DO_DUAL_DAC) {
2441 s->dma_adc.ready = 0;
2443 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2445 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2448 set_fmt(s, fmtm, fmtd);
2449 if ((s->capability & CAN_MULTI_CH)
2450 && (file->f_mode & FMODE_WRITE)) {
2451 val = set_dac_channels(s, val);
2452 return put_user(val, (int *)arg);
2455 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT)
2456 : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, (int *)arg);
2458 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2459 return put_user(AFMT_S16_BE|AFMT_S16_LE|AFMT_U8|
2460 ((s->capability & CAN_AC3) ? AFMT_AC3 : 0), (int *)arg);
2462 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2463 if (get_user(val, (int *)arg))
2465 if (val != AFMT_QUERY) {
2468 if (file->f_mode & FMODE_READ) {
2470 s->dma_adc.ready = 0;
2471 if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2472 fmtd |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2474 fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_ADCSHIFT);
2475 if (val == AFMT_S16_BE)
2476 s->status |= DO_BIGENDIAN_R;
2478 s->status &= ~DO_BIGENDIAN_R;
2480 if (file->f_mode & FMODE_WRITE) {
2482 s->dma_dac.ready = 0;
2483 if (val == AFMT_S16_BE || val == AFMT_S16_LE || val == AFMT_AC3)
2484 fmtd |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2486 fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_DACSHIFT);
2487 if (val == AFMT_AC3) {
2488 fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2492 if (s->status & DO_DUAL_DAC) {
2493 s->dma_adc.ready = 0;
2494 if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2495 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2497 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2499 if (val == AFMT_S16_BE)
2500 s->status |= DO_BIGENDIAN_W;
2502 s->status &= ~DO_BIGENDIAN_W;
2504 set_fmt(s, fmtm, fmtd);
2506 if (s->status & DO_AC3) return put_user(AFMT_AC3, (int *)arg);
2507 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT)
2508 : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? val : AFMT_U8, (int *)arg);
2510 case SNDCTL_DSP_POST:
2513 case SNDCTL_DSP_GETTRIGGER:
2515 if (s->status & DO_DUAL_DAC) {
2516 if (file->f_mode & FMODE_WRITE &&
2517 (s->enable & ENDAC) &&
2518 (s->enable & ENADC))
2519 val |= PCM_ENABLE_OUTPUT;
2520 return put_user(val, (int *)arg);
2522 if (file->f_mode & FMODE_READ && s->enable & ENADC)
2523 val |= PCM_ENABLE_INPUT;
2524 if (file->f_mode & FMODE_WRITE && s->enable & ENDAC)
2525 val |= PCM_ENABLE_OUTPUT;
2526 return put_user(val, (int *)arg);
2528 case SNDCTL_DSP_SETTRIGGER:
2529 if (get_user(val, (int *)arg))
2531 if (file->f_mode & FMODE_READ) {
2532 if (val & PCM_ENABLE_INPUT) {
2533 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2535 s->dma_adc.enabled = 1;
2538 s->dma_adc.enabled = 0;
2542 if (file->f_mode & FMODE_WRITE) {
2543 if (val & PCM_ENABLE_OUTPUT) {
2544 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2546 if (s->status & DO_DUAL_DAC) {
2547 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2550 s->dma_dac.enabled = 1;
2553 s->dma_dac.enabled = 0;
2559 case SNDCTL_DSP_GETOSPACE:
2560 if (!(file->f_mode & FMODE_WRITE))
2562 if (!(s->enable & ENDAC) && (val = prog_dmabuf(s, 0)) != 0)
2564 spin_lock_irqsave(&s->lock, flags);
2566 abinfo.fragsize = s->dma_dac.fragsize;
2567 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2568 abinfo.fragstotal = s->dma_dac.numfrag;
2569 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2570 spin_unlock_irqrestore(&s->lock, flags);
2571 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2573 case SNDCTL_DSP_GETISPACE:
2574 if (!(file->f_mode & FMODE_READ))
2576 if (!(s->enable & ENADC) && (val = prog_dmabuf(s, 1)) != 0)
2578 spin_lock_irqsave(&s->lock, flags);
2580 abinfo.fragsize = s->dma_adc.fragsize;
2581 abinfo.bytes = s->dma_adc.count;
2582 abinfo.fragstotal = s->dma_adc.numfrag;
2583 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2584 spin_unlock_irqrestore(&s->lock, flags);
2585 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2587 case SNDCTL_DSP_NONBLOCK:
2588 file->f_flags |= O_NONBLOCK;
2591 case SNDCTL_DSP_GETODELAY:
2592 if (!(file->f_mode & FMODE_WRITE))
2594 spin_lock_irqsave(&s->lock, flags);
2596 val = s->dma_dac.count;
2597 spin_unlock_irqrestore(&s->lock, flags);
2598 return put_user(val, (int *)arg);
2600 case SNDCTL_DSP_GETIPTR:
2601 if (!(file->f_mode & FMODE_READ))
2603 spin_lock_irqsave(&s->lock, flags);
2605 cinfo.bytes = s->dma_adc.total_bytes;
2606 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2607 cinfo.ptr = s->dma_adc.hwptr;
2608 if (s->dma_adc.mapped)
2609 s->dma_adc.count &= s->dma_adc.fragsize-1;
2610 spin_unlock_irqrestore(&s->lock, flags);
2611 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2613 case SNDCTL_DSP_GETOPTR:
2614 if (!(file->f_mode & FMODE_WRITE))
2616 spin_lock_irqsave(&s->lock, flags);
2618 cinfo.bytes = s->dma_dac.total_bytes;
2619 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2620 cinfo.ptr = s->dma_dac.hwptr;
2621 if (s->dma_dac.mapped)
2622 s->dma_dac.count &= s->dma_dac.fragsize-1;
2623 if (s->status & DO_DUAL_DAC) {
2624 if (s->dma_adc.mapped)
2625 s->dma_adc.count &= s->dma_adc.fragsize-1;
2627 spin_unlock_irqrestore(&s->lock, flags);
2628 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2630 case SNDCTL_DSP_GETBLKSIZE:
2631 if (file->f_mode & FMODE_WRITE) {
2632 if ((val = prog_dmabuf(s, 0)))
2634 if (s->status & DO_DUAL_DAC) {
2635 if ((val = prog_dmabuf(s, 1)))
2637 return put_user(2 * s->dma_dac.fragsize, (int *)arg);
2639 return put_user(s->dma_dac.fragsize, (int *)arg);
2641 if ((val = prog_dmabuf(s, 1)))
2643 return put_user(s->dma_adc.fragsize, (int *)arg);
2645 case SNDCTL_DSP_SETFRAGMENT:
2646 if (get_user(val, (int *)arg))
2648 if (file->f_mode & FMODE_READ) {
2649 s->dma_adc.ossfragshift = val & 0xffff;
2650 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2651 if (s->dma_adc.ossfragshift < 4)
2652 s->dma_adc.ossfragshift = 4;
2653 if (s->dma_adc.ossfragshift > 15)
2654 s->dma_adc.ossfragshift = 15;
2655 if (s->dma_adc.ossmaxfrags < 4)
2656 s->dma_adc.ossmaxfrags = 4;
2658 if (file->f_mode & FMODE_WRITE) {
2659 s->dma_dac.ossfragshift = val & 0xffff;
2660 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2661 if (s->dma_dac.ossfragshift < 4)
2662 s->dma_dac.ossfragshift = 4;
2663 if (s->dma_dac.ossfragshift > 15)
2664 s->dma_dac.ossfragshift = 15;
2665 if (s->dma_dac.ossmaxfrags < 4)
2666 s->dma_dac.ossmaxfrags = 4;
2667 if (s->status & DO_DUAL_DAC) {
2668 s->dma_adc.ossfragshift = s->dma_dac.ossfragshift;
2669 s->dma_adc.ossmaxfrags = s->dma_dac.ossmaxfrags;
2674 case SNDCTL_DSP_SUBDIVIDE:
2675 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2676 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2678 if (get_user(val, (int *)arg))
2680 if (val != 1 && val != 2 && val != 4)
2682 if (file->f_mode & FMODE_READ)
2683 s->dma_adc.subdivision = val;
2684 if (file->f_mode & FMODE_WRITE) {
2685 s->dma_dac.subdivision = val;
2686 if (s->status & DO_DUAL_DAC)
2687 s->dma_adc.subdivision = val;
2691 case SOUND_PCM_READ_RATE:
2692 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2694 case SOUND_PCM_READ_CHANNELS:
2695 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT) : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, (int *)arg);
2697 case SOUND_PCM_READ_BITS:
2698 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT) : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? 16 : 8, (int *)arg);
2700 case SOUND_PCM_READ_FILTER:
2701 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2703 case SNDCTL_DSP_GETCHANNELMASK:
2704 return put_user(DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE|DSP_BIND_SPDIF, (int *)arg);
2706 case SNDCTL_DSP_BIND_CHANNEL:
2707 if (get_user(val, (int *)arg))
2709 if (val == DSP_BIND_QUERY) {
2710 val = DSP_BIND_FRONT;
2711 if (s->status & DO_SPDIF_OUT)
2712 val |= DSP_BIND_SPDIF;
2714 if (s->curr_channels == 4)
2715 val |= DSP_BIND_SURR;
2716 if (s->curr_channels > 4)
2717 val |= DSP_BIND_CENTER_LFE;
2720 if (file->f_mode & FMODE_READ) {
2722 s->dma_adc.ready = 0;
2723 if (val & DSP_BIND_SPDIF) {
2724 set_spdifin(s, s->rateadc);
2725 if (!(s->status & DO_SPDIF_OUT))
2726 val &= ~DSP_BIND_SPDIF;
2729 if (file->f_mode & FMODE_WRITE) {
2731 s->dma_dac.ready = 0;
2732 if (val & DSP_BIND_SPDIF) {
2733 set_spdifout(s, s->ratedac);
2734 set_dac_channels(s, s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1);
2735 if (!(s->status & DO_SPDIF_OUT))
2736 val &= ~DSP_BIND_SPDIF;
2741 mask = val & (DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE);
2743 case DSP_BIND_FRONT:
2746 case DSP_BIND_FRONT|DSP_BIND_SURR:
2749 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2753 channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
2756 set_dac_channels(s, channels);
2760 return put_user(val, (int *)arg);
2762 case SOUND_PCM_WRITE_FILTER:
2763 case SNDCTL_DSP_MAPINBUF:
2764 case SNDCTL_DSP_MAPOUTBUF:
2765 case SNDCTL_DSP_SETSYNCRO:
2767 case SNDCTL_SPDIF_COPYRIGHT:
2768 if (get_user(val, (int *)arg))
2770 set_spdif_copyright(s, val);
2772 case SNDCTL_SPDIF_LOOP:
2773 if (get_user(val, (int *)arg))
2775 set_spdif_loop(s, val);
2777 case SNDCTL_SPDIF_MONITOR:
2778 if (get_user(val, (int *)arg))
2780 set_spdif_monitor(s, val);
2782 case SNDCTL_SPDIF_LEVEL:
2783 if (get_user(val, (int *)arg))
2785 set_spdifout_level(s, val);
2787 case SNDCTL_SPDIF_INV:
2788 if (get_user(val, (int *)arg))
2790 set_spdifin_inverse(s, val);
2792 case SNDCTL_SPDIF_SEL2:
2793 if (get_user(val, (int *)arg))
2795 set_spdifin_channel2(s, val);
2797 case SNDCTL_SPDIF_VALID:
2798 if (get_user(val, (int *)arg))
2800 set_spdifin_valid(s, val);
2802 case SNDCTL_SPDIFOUT:
2803 if (get_user(val, (int *)arg))
2805 set_spdifout(s, val ? s->ratedac : 0);
2807 case SNDCTL_SPDIFIN:
2808 if (get_user(val, (int *)arg))
2810 set_spdifin(s, val ? s->rateadc : 0);
2813 return mixer_ioctl(s, cmd, arg);
2816 static int cm_open(struct inode *inode, struct file *file)
2818 int minor = iminor(inode);
2819 DECLARE_WAITQUEUE(wait, current);
2820 unsigned char fmtm = ~0, fmts = 0;
2821 struct list_head *list;
2824 for (list = devs.next; ; list = list->next) {
2827 s = list_entry(list, struct cm_state, devs);
2828 if (!((s->dev_audio ^ minor) & ~0xf))
2832 file->private_data = s;
2833 /* wait for device to become free */
2835 while (s->open_mode & file->f_mode) {
2836 if (file->f_flags & O_NONBLOCK) {
2840 add_wait_queue(&s->open_wait, &wait);
2841 __set_current_state(TASK_INTERRUPTIBLE);
2844 remove_wait_queue(&s->open_wait, &wait);
2845 set_current_state(TASK_RUNNING);
2846 if (signal_pending(current))
2847 return -ERESTARTSYS;
2850 if (file->f_mode & FMODE_READ) {
2851 s->status &= ~DO_BIGENDIAN_R;
2852 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
2853 if ((minor & 0xf) == SND_DEV_DSP16)
2854 fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2855 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2856 s->dma_adc.enabled = 1;
2857 set_adc_rate(s, 8000);
2858 // spdif-in is turnned off by default
2861 if (file->f_mode & FMODE_WRITE) {
2862 s->status &= ~DO_BIGENDIAN_W;
2863 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
2864 if ((minor & 0xf) == SND_DEV_DSP16)
2865 fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2866 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2867 s->dma_dac.enabled = 1;
2868 set_dac_rate(s, 8000);
2869 // clear previous multichannel, spdif, ac3 state
2872 set_dac_channels(s, 1);
2874 set_fmt(s, fmtm, fmts);
2875 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2880 static int cm_release(struct inode *inode, struct file *file)
2882 struct cm_state *s = (struct cm_state *)file->private_data;
2886 if (file->f_mode & FMODE_WRITE)
2887 drain_dac(s, file->f_flags & O_NONBLOCK);
2889 if (file->f_mode & FMODE_WRITE) {
2892 dealloc_dmabuf(s, &s->dma_dac);
2893 if (s->status & DO_DUAL_DAC)
2894 dealloc_dmabuf(s, &s->dma_adc);
2896 if (s->status & DO_MULTI_CH)
2897 set_dac_channels(s, 1);
2898 if (s->status & DO_AC3)
2900 if (s->status & DO_SPDIF_OUT)
2902 /* enable SPDIF loop */
2903 set_spdif_loop(s, spdif_loop);
2904 s->status &= ~DO_BIGENDIAN_W;
2906 if (file->f_mode & FMODE_READ) {
2908 dealloc_dmabuf(s, &s->dma_adc);
2909 s->status &= ~DO_BIGENDIAN_R;
2911 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2913 wake_up(&s->open_wait);
2918 static /*const*/ struct file_operations cm_audio_fops = {
2919 .owner = THIS_MODULE,
2920 .llseek = no_llseek,
2927 .release = cm_release,
2930 /* --------------------------------------------------------------------- */
2932 static struct initvol {
2935 } initvol[] __initdata = {
2936 { SOUND_MIXER_WRITE_CD, 0x4f4f },
2937 { SOUND_MIXER_WRITE_LINE, 0x4f4f },
2938 { SOUND_MIXER_WRITE_MIC, 0x4f4f },
2939 { SOUND_MIXER_WRITE_SYNTH, 0x4f4f },
2940 { SOUND_MIXER_WRITE_VOLUME, 0x4f4f },
2941 { SOUND_MIXER_WRITE_PCM, 0x4f4f }
2944 /* check chip version and capability */
2945 static int query_chip(struct cm_state *s)
2947 int ChipVersion = -1;
2948 unsigned char RegValue;
2950 // check reg 0Ch, bit 24-31
2951 RegValue = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 3);
2952 if (RegValue == 0) {
2953 // check reg 08h, bit 24-28
2954 RegValue = inb(s->iobase + CODEC_CMI_CHFORMAT + 3);
2956 if (RegValue == 0) {
2958 s->max_channels = 4;
2959 s->capability |= CAN_AC3_SW;
2960 s->capability |= CAN_DUAL_DAC;
2963 s->max_channels = 4;
2964 s->capability |= CAN_AC3_HW;
2965 s->capability |= CAN_DUAL_DAC;
2968 // check reg 0Ch, bit 26
2969 if (RegValue & (1 << (26-24))) {
2971 if (RegValue & (1 << (24-24)))
2972 s->max_channels = 6;
2974 s->max_channels = 4;
2975 s->capability |= CAN_AC3_HW;
2976 s->capability |= CAN_DUAL_DAC;
2977 s->capability |= CAN_MULTI_CH_HW;
2978 s->capability |= CAN_LINE_AS_BASS;
2979 s->capability |= CAN_MIC_AS_BASS;
2981 ChipVersion = 55; // 4 or 6 channels
2982 s->max_channels = 6;
2983 s->capability |= CAN_AC3_HW;
2984 s->capability |= CAN_DUAL_DAC;
2985 s->capability |= CAN_MULTI_CH_HW;
2986 s->capability |= CAN_LINE_AS_BASS;
2987 s->capability |= CAN_MIC_AS_BASS;
2990 s->capability |= CAN_LINE_AS_REAR;
2994 #define echo_option(x)\
2995 if (x) strcat(options, "" #x " ")
2997 static int __devinit cm_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
3002 unsigned char reg_mask;
3004 unsigned short deviceid;
3007 { PCI_DEVICE_ID_CMEDIA_CM8338A, "CM8338A" },
3008 { PCI_DEVICE_ID_CMEDIA_CM8338B, "CM8338B" },
3009 { PCI_DEVICE_ID_CMEDIA_CM8738, "CM8738" },
3010 { PCI_DEVICE_ID_CMEDIA_CM8738B, "CM8738B" },
3012 char *devicename = "unknown";
3015 if ((ret = pci_enable_device(pcidev)))
3017 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
3019 if (pcidev->irq == 0)
3021 i = pci_set_dma_mask(pcidev, 0xffffffff);
3023 printk(KERN_WARNING "cmpci: architecture does not support 32bit PCI busmaster DMA\n");
3026 s = kmalloc(sizeof(*s), GFP_KERNEL);
3028 printk(KERN_WARNING "cmpci: out of memory\n");
3031 /* search device name */
3032 for (i = 0; i < sizeof(devicetable) / sizeof(devicetable[0]); i++) {
3033 if (devicetable[i].deviceid == pcidev->device) {
3034 devicename = devicetable[i].devicename;
3038 memset(s, 0, sizeof(struct cm_state));
3039 init_waitqueue_head(&s->dma_adc.wait);
3040 init_waitqueue_head(&s->dma_dac.wait);
3041 init_waitqueue_head(&s->open_wait);
3042 init_MUTEX(&s->open_sem);
3043 spin_lock_init(&s->lock);
3044 s->magic = CM_MAGIC;
3046 s->iobase = pci_resource_start(pcidev, 0);
3049 #ifdef CONFIG_SOUND_CMPCI_MIDI
3055 s->irq = pcidev->irq;
3057 if (!request_region(s->iobase, CM_EXTENT_CODEC, "cmpci")) {
3058 printk(KERN_ERR "cmpci: io ports %#x-%#x in use\n", s->iobase, s->iobase+CM_EXTENT_CODEC-1);
3062 /* dump parameters */
3063 strcpy(options, "cmpci: ");
3064 echo_option(joystick);
3065 echo_option(spdif_inverse);
3066 echo_option(spdif_loop);
3067 echo_option(spdif_out);
3068 echo_option(use_line_as_rear);
3069 echo_option(use_line_as_bass);
3070 echo_option(use_mic_as_bass);
3071 echo_option(mic_boost);
3072 echo_option(hw_copy);
3073 printk(KERN_INFO "%s\n", options);
3075 /* initialize codec registers */
3076 outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2); /* disable ints */
3077 outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3079 wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3082 if ((ret = request_irq(s->irq, cm_interrupt, SA_SHIRQ, "cmpci", s))) {
3083 printk(KERN_ERR "cmpci: irq %u in use\n", s->irq);
3086 printk(KERN_INFO "cmpci: found %s adapter at io %#x irq %u\n",
3087 devicename, s->iobase, s->irq);
3088 /* register devices */
3089 if ((s->dev_audio = register_sound_dsp(&cm_audio_fops, -1)) < 0) {
3093 if ((s->dev_mixer = register_sound_mixer(&cm_mixer_fops, -1)) < 0) {
3097 pci_set_master(pcidev); /* enable bus mastering */
3098 /* initialize the chips */
3101 /* set mixer output */
3102 frobindir(s, DSP_MIX_OUTMIXIDX, 0x1f, 0x1f);
3103 /* set mixer input */
3104 val = SOUND_MASK_LINE|SOUND_MASK_SYNTH|SOUND_MASK_CD|SOUND_MASK_MIC;
3105 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
3106 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3107 val = initvol[i].vol;
3108 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
3111 /* use channel 1 for playback, channel 0 for record */
3112 maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, CHADC0);
3113 /* turn off VMIC3 - mic boost */
3115 maskb(s->iobase + CODEC_CMI_MIXER2, ~1, 0);
3117 maskb(s->iobase + CODEC_CMI_MIXER2, ~0, 1);
3118 s->deviceid = pcidev->device;
3120 if (pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738
3121 || pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
3123 /* chip version and hw capability check */
3124 s->chip_version = query_chip(s);
3125 printk(KERN_INFO "cmpci: chip version = 0%d\n", s->chip_version);
3127 /* set SPDIF-in inverse before enable SPDIF loop */
3128 set_spdifin_inverse(s, spdif_inverse);
3130 /* use SPDIF in #1 */
3131 set_spdifin_channel2(s, 0);
3133 s->chip_version = 0;
3134 /* 8338 will fall here */
3135 s->max_channels = 4;
3136 s->capability |= CAN_DUAL_DAC;
3137 s->capability |= CAN_LINE_AS_REAR;
3139 /* enable SPDIF loop */
3140 set_spdif_loop(s, spdif_loop);
3142 // enable 4 speaker mode (analog duplicate)
3143 set_hw_copy(s, hw_copy);
3146 #ifdef CONFIG_SOUND_CMPCI_FM
3148 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3150 /* don't enable OPL3 if there is one */
3151 if (opl3_detect(s->iosynth, NULL)) {
3154 /* set IO based at 0x388 */
3155 switch (s->iosynth) {
3172 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x03, reg_mask);
3175 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, 8);
3176 if (opl3_detect(s->iosynth, NULL))
3177 ret = opl3_init(s->iosynth, NULL, THIS_MODULE);
3179 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3186 #ifdef CONFIG_SOUND_CMPCI_MIDI
3187 /* disable MPU-401 */
3188 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3189 s->mpu_data.name = "cmpci mpu";
3190 s->mpu_data.io_base = s->iomidi;
3191 s->mpu_data.irq = -s->irq; // tell mpu401 to share irq
3192 if (probe_mpu401(&s->mpu_data))
3195 /* set IO based at 0x330 */
3196 switch (s->iomidi) {
3213 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x60, reg_mask);
3214 /* enable MPU-401 */
3218 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3219 /* clear all previously received interrupt */
3220 for (timeout = 900000; timeout > 0; timeout--) {
3221 if ((inb(s->iomidi + 1) && 0x80) == 0)
3226 if (!probe_mpu401(&s->mpu_data)) {
3228 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3230 attach_mpu401(&s->mpu_data, THIS_MODULE);
3231 s->midi_devc = s->mpu_data.slots[1];
3236 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
3237 /* enable joystick */
3239 s->gameport.io = 0x200;
3240 if (!request_region(s->gameport.io, CM_EXTENT_GAME, "cmpci GAME")) {
3241 printk(KERN_ERR "cmpci: gameport io ports in use\n");
3244 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x02);
3245 gameport_register_port(&s->gameport);
3248 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3252 /* store it in the driver field */
3253 pci_set_drvdata(pcidev, s);
3254 /* put it into driver list */
3255 list_add_tail(&s->devs, &devs);
3256 /* increment devindex */
3257 if (devindex < NR_DEVICE-1)
3262 unregister_sound_dsp(s->dev_audio);
3264 printk(KERN_ERR "cmpci: cannot register misc device\n");
3265 free_irq(s->irq, s);
3267 release_region(s->iobase, CM_EXTENT_CODEC);
3273 /* --------------------------------------------------------------------- */
3275 MODULE_AUTHOR("ChenLi Tien, cltien@cmedia.com.tw");
3276 MODULE_DESCRIPTION("CM8x38 Audio Driver");
3277 MODULE_LICENSE("GPL");
3279 static void __devinit cm_remove(struct pci_dev *dev)
3281 struct cm_state *s = pci_get_drvdata(dev);
3285 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
3286 if (s->gameport.io) {
3287 gameport_unregister_port(&s->gameport);
3288 release_region(s->gameport.io, CM_EXTENT_GAME);
3289 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3292 #ifdef CONFIG_SOUND_CMPCI_FM
3295 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3298 #ifdef CONFIG_SOUND_CMPCI_MIDI
3300 unload_mpu401(&s->mpu_data);
3301 /* disable MPU-401 */
3302 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3305 set_spdif_loop(s, 0);
3307 outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2); /* disable ints */
3308 synchronize_irq(s->irq);
3309 outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3310 free_irq(s->irq, s);
3313 wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3315 release_region(s->iobase, CM_EXTENT_CODEC);
3316 unregister_sound_dsp(s->dev_audio);
3317 unregister_sound_mixer(s->dev_mixer);
3319 pci_set_drvdata(dev, NULL);
3322 static struct pci_device_id id_table[] __devinitdata = {
3323 { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3324 { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3325 { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3326 { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3330 MODULE_DEVICE_TABLE(pci, id_table);
3332 static struct pci_driver cm_driver = {
3334 .id_table = id_table,
3339 static int __init init_cmpci(void)
3341 printk(KERN_INFO "cmpci: version $Revision: 6.82 $ time " __TIME__ " " __DATE__ "\n");
3342 return pci_module_init(&cm_driver);
3345 static void __exit cleanup_cmpci(void)
3347 printk(KERN_INFO "cmpci: unloading\n");
3348 pci_unregister_driver(&cm_driver);
3351 module_init(init_cmpci);
3352 module_exit(cleanup_cmpci);