1 /*******************************************************************************
3 * "cs4281.c" -- Cirrus Logic-Crystal CS4281 linux audio driver.
5 * Copyright (C) 2000,2001 Cirrus Logic Corp.
6 * -- adapted from drivers by Thomas Sailer,
7 * -- but don't bug him; Problems should go to:
8 * -- tom woller (twoller@crystal.cirrus.com) or
9 * (audio@crystal.cirrus.com).
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Module command line parameters:
29 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
30 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
31 * /dev/midi simple MIDI UART interface, no ioctl
33 * Modification History
34 * 08/20/00 trw - silence and no stopping DAC until release
35 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
36 * 09/18/00 trw - added 16bit only record with conversion
37 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
38 * capture/playback rates)
39 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
41 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
42 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
43 * 11/10/00 bkz - added __devinit to cs4281_hw_init()
44 * 11/10/00 trw - fixed SMP and capture spinlock hang.
45 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
46 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
47 * 12/08/00 trw - added PM support.
48 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
49 * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
50 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
51 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
52 * defaultorder-100 as power of 2 for the buffer size. example:
53 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
55 *******************************************************************************/
57 /* uncomment the following line to disable building PM support into the driver */
58 //#define NOT_CS4281_PM 1
60 #include <linux/list.h>
61 #include <linux/module.h>
62 #include <linux/string.h>
63 #include <linux/ioport.h>
64 #include <linux/sched.h>
65 #include <linux/delay.h>
66 #include <linux/sound.h>
67 #include <linux/slab.h>
68 #include <linux/soundcard.h>
69 #include <linux/pci.h>
70 #include <linux/bitops.h>
71 #include <linux/init.h>
72 #include <linux/interrupt.h>
73 #include <linux/poll.h>
75 #include <linux/wait.h>
77 #include <asm/current.h>
81 #include <asm/uaccess.h>
84 #include "cs4281_hwdefs.h"
89 static void stop_dac(struct cs4281_state *s);
90 static void stop_adc(struct cs4281_state *s);
91 static void start_dac(struct cs4281_state *s);
92 static void start_adc(struct cs4281_state *s);
93 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
95 // ---------------------------------------------------------------------
97 #ifndef PCI_VENDOR_ID_CIRRUS
98 #define PCI_VENDOR_ID_CIRRUS 0x1013
100 #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
101 #define PCI_DEVICE_ID_CRYSTAL_CS4281 0x6005
104 #define CS4281_MAGIC ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
105 #define CS4281_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
107 // buffer order determines the size of the dma buffer for the driver.
108 // under Linux, a smaller buffer allows more responsiveness from many of the
109 // applications (e.g. games). A larger buffer allows some of the apps (esound)
110 // to not underrun the dma buffer as easily. As default, use 32k (order=3)
111 // rather than 64k as some of the games work more responsively.
112 // log base 2( buff sz = 32k).
113 static unsigned long defaultorder = 3;
114 MODULE_PARM(defaultorder, "i");
117 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
121 #define CSDEBUG_INTERFACE 1
123 #undef CSDEBUG_INTERFACE
126 // cs_debugmask areas
128 #define CS_INIT 0x00000001 // initialization and probe functions
129 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
130 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
131 #define CS_FUNCTION 0x00000008 // enter/leave functions
132 #define CS_WAVE_WRITE 0x00000010 // write information for wave
133 #define CS_WAVE_READ 0x00000020 // read information for wave
134 #define CS_MIDI_WRITE 0x00000040 // write information for midi
135 #define CS_MIDI_READ 0x00000080 // read information for midi
136 #define CS_MPU401_WRITE 0x00000100 // write information for mpu401
137 #define CS_MPU401_READ 0x00000200 // read information for mpu401
138 #define CS_OPEN 0x00000400 // all open functions in the driver
139 #define CS_RELEASE 0x00000800 // all release functions in the driver
140 #define CS_PARMS 0x00001000 // functional and operational parameters
141 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
142 #define CS_PM 0x00004000 // power management
143 #define CS_TMP 0x10000000 // tmp debug mask bit
145 #define CS_IOCTL_CMD_SUSPEND 0x1 // suspend
146 #define CS_IOCTL_CMD_RESUME 0x2 // resume
148 // CSDEBUG is usual mode is set to 1, then use the
149 // cs_debuglevel and cs_debugmask to turn on or off debugging.
150 // Debug level of 1 has been defined to be kernel errors and info
151 // that should be printed on any released driver.
154 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
156 #define CS_DBGOUT(mask,level,x)
160 static unsigned long cs_debuglevel = 1; // levels range from 1-9
161 static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
162 MODULE_PARM(cs_debuglevel, "i");
163 MODULE_PARM(cs_debugmask, "i");
169 #define MIDIINBUF 500
170 #define MIDIOUTBUF 500
172 #define FMODE_MIDI_SHIFT 3
173 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
174 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
176 #define CS4281_MAJOR_VERSION 1
177 #define CS4281_MINOR_VERSION 13
179 #define CS4281_ARCH 64 //architecture key
181 #define CS4281_ARCH 32 //architecture key
184 #define CS_TYPE_ADC 0
185 #define CS_TYPE_DAC 1
188 static const char invalid_magic[] =
189 KERN_CRIT "cs4281: invalid magic value\n";
191 #define VALIDATE_STATE(s) \
193 if (!(s) || (s)->magic != CS4281_MAGIC) { \
194 printk(invalid_magic); \
199 //LIST_HEAD(cs4281_devs);
200 struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
204 #include "cs4281_wrapper-24.c"
206 struct cs4281_state {
210 // we keep the cards in a linked list
211 struct cs4281_state *next;
213 // pcidev is needed to turn off the DDMA controller at driver shutdown
214 struct pci_dev *pcidev;
215 struct list_head list;
222 // hardware resources
223 unsigned int pBA0phys, pBA1phys;
229 unsigned short vol[10];
232 unsigned short micpreamp;
238 unsigned fmt_original; // original requested format
241 unsigned char clkdiv;
242 } prop_dac, prop_adc;
243 unsigned conversion:1; // conversion from 16 to 8 bit in progress
244 void *tmpbuff; // tmp buffer for sample conversions
247 struct semaphore open_sem;
248 struct semaphore open_sem_adc;
249 struct semaphore open_sem_dac;
251 wait_queue_head_t open_wait;
252 wait_queue_head_t open_wait_adc;
253 wait_queue_head_t open_wait_dac;
255 dma_addr_t dmaaddr_tmpbuff;
256 unsigned buforder_tmpbuff; // Log base 2 of 'rawbuf' size in bytes..
258 void *rawbuf; // Physical address of
260 unsigned buforder; // Log base 2 of 'rawbuf' size in bytes..
261 unsigned numfrag; // # of 'fragments' in the buffer.
262 unsigned fragshift; // Log base 2 of fragment size.
263 unsigned hwptr, swptr;
264 unsigned total_bytes; // # bytes process since open.
265 unsigned blocks; // last returned blocks value GETOPTR
266 unsigned wakeup; // interrupt occurred on block
268 unsigned underrun; // underrun flag
269 unsigned error; // over/underrun
270 wait_queue_head_t wait;
271 // redundant, but makes calculations easier
272 unsigned fragsize; // 2**fragshift..
273 unsigned dmasize; // 2**buforder.
274 unsigned fragsamples;
276 unsigned mapped:1; // Buffer mapped in cs4281_mmap()?
277 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
278 unsigned endcleared:1;
279 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
280 unsigned ossfragshift;
282 unsigned subdivision;
287 unsigned ird, iwr, icnt;
288 unsigned ord, owr, ocnt;
289 wait_queue_head_t iwait;
290 wait_queue_head_t owait;
291 struct timer_list timer;
292 unsigned char ibuf[MIDIINBUF];
293 unsigned char obuf[MIDIOUTBUF];
297 struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
300 #include "cs4281pm-24.c"
306 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
307 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
308 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
309 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
311 #define SOUND_MIXER_CS_APM _SIOWR('M',124, int)
314 static void cs_printioctl(unsigned int x)
318 // Index of mixtable1[] member is Device ID
319 // and must be <= SOUND_MIXER_NRDEVICES.
320 // Value of array member is index into s->mix.vol[]
321 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
322 [SOUND_MIXER_PCM] = 1, // voice
323 [SOUND_MIXER_LINE1] = 2, // AUX
324 [SOUND_MIXER_CD] = 3, // CD
325 [SOUND_MIXER_LINE] = 4, // Line
326 [SOUND_MIXER_SYNTH] = 5, // FM
327 [SOUND_MIXER_MIC] = 6, // Mic
328 [SOUND_MIXER_SPEAKER] = 7, // Speaker
329 [SOUND_MIXER_RECLEV] = 8, // Recording level
330 [SOUND_MIXER_VOLUME] = 9 // Master Volume
334 case SOUND_MIXER_CS_GETDBGMASK:
335 CS_DBGOUT(CS_IOCTL, 4,
336 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
338 case SOUND_MIXER_CS_GETDBGLEVEL:
339 CS_DBGOUT(CS_IOCTL, 4,
340 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
342 case SOUND_MIXER_CS_SETDBGMASK:
343 CS_DBGOUT(CS_IOCTL, 4,
344 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
346 case SOUND_MIXER_CS_SETDBGLEVEL:
347 CS_DBGOUT(CS_IOCTL, 4,
348 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
351 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
353 case SNDCTL_DSP_SYNC:
354 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
356 case SNDCTL_DSP_SETDUPLEX:
357 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
359 case SNDCTL_DSP_GETCAPS:
360 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
362 case SNDCTL_DSP_RESET:
363 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
365 case SNDCTL_DSP_SPEED:
366 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
368 case SNDCTL_DSP_STEREO:
369 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
371 case SNDCTL_DSP_CHANNELS:
372 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
374 case SNDCTL_DSP_GETFMTS:
375 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
377 case SNDCTL_DSP_SETFMT:
378 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
380 case SNDCTL_DSP_POST:
381 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
383 case SNDCTL_DSP_GETTRIGGER:
384 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
386 case SNDCTL_DSP_SETTRIGGER:
387 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
389 case SNDCTL_DSP_GETOSPACE:
390 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
392 case SNDCTL_DSP_GETISPACE:
393 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
395 case SNDCTL_DSP_NONBLOCK:
396 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
398 case SNDCTL_DSP_GETODELAY:
399 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
401 case SNDCTL_DSP_GETIPTR:
402 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
404 case SNDCTL_DSP_GETOPTR:
405 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
407 case SNDCTL_DSP_GETBLKSIZE:
408 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
410 case SNDCTL_DSP_SETFRAGMENT:
411 CS_DBGOUT(CS_IOCTL, 4,
412 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
414 case SNDCTL_DSP_SUBDIVIDE:
415 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
417 case SOUND_PCM_READ_RATE:
418 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
420 case SOUND_PCM_READ_CHANNELS:
421 CS_DBGOUT(CS_IOCTL, 4,
422 printk("SOUND_PCM_READ_CHANNELS:\n"));
424 case SOUND_PCM_READ_BITS:
425 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
427 case SOUND_PCM_WRITE_FILTER:
428 CS_DBGOUT(CS_IOCTL, 4,
429 printk("SOUND_PCM_WRITE_FILTER:\n"));
431 case SNDCTL_DSP_SETSYNCRO:
432 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
434 case SOUND_PCM_READ_FILTER:
435 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
437 case SOUND_MIXER_PRIVATE1:
438 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
440 case SOUND_MIXER_PRIVATE2:
441 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
443 case SOUND_MIXER_PRIVATE3:
444 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
446 case SOUND_MIXER_PRIVATE4:
447 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
449 case SOUND_MIXER_PRIVATE5:
450 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
452 case SOUND_MIXER_INFO:
453 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
455 case SOUND_OLD_MIXER_INFO:
456 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
460 switch (_IOC_NR(x)) {
461 case SOUND_MIXER_VOLUME:
462 CS_DBGOUT(CS_IOCTL, 4,
463 printk("SOUND_MIXER_VOLUME:\n"));
465 case SOUND_MIXER_SPEAKER:
466 CS_DBGOUT(CS_IOCTL, 4,
467 printk("SOUND_MIXER_SPEAKER:\n"));
469 case SOUND_MIXER_RECLEV:
470 CS_DBGOUT(CS_IOCTL, 4,
471 printk("SOUND_MIXER_RECLEV:\n"));
473 case SOUND_MIXER_MIC:
474 CS_DBGOUT(CS_IOCTL, 4,
475 printk("SOUND_MIXER_MIC:\n"));
477 case SOUND_MIXER_SYNTH:
478 CS_DBGOUT(CS_IOCTL, 4,
479 printk("SOUND_MIXER_SYNTH:\n"));
481 case SOUND_MIXER_RECSRC:
482 CS_DBGOUT(CS_IOCTL, 4,
483 printk("SOUND_MIXER_RECSRC:\n"));
485 case SOUND_MIXER_DEVMASK:
486 CS_DBGOUT(CS_IOCTL, 4,
487 printk("SOUND_MIXER_DEVMASK:\n"));
489 case SOUND_MIXER_RECMASK:
490 CS_DBGOUT(CS_IOCTL, 4,
491 printk("SOUND_MIXER_RECMASK:\n"));
493 case SOUND_MIXER_STEREODEVS:
494 CS_DBGOUT(CS_IOCTL, 4,
495 printk("SOUND_MIXER_STEREODEVS:\n"));
497 case SOUND_MIXER_CAPS:
498 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
502 if (i >= SOUND_MIXER_NRDEVICES
503 || !(vidx = mixtable1[i])) {
504 CS_DBGOUT(CS_IOCTL, 4, printk
505 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
508 CS_DBGOUT(CS_IOCTL, 4, printk
509 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
517 static int prog_dmabuf_adc(struct cs4281_state *s);
518 static void prog_codec(struct cs4281_state *s, unsigned type);
520 // ---------------------------------------------------------------------
522 // Hardware Interfaces For the CS4281
526 //******************************************************************************
527 // "delayus()-- Delay for the specified # of microseconds.
528 //******************************************************************************
529 static void delayus(struct cs4281_state *s, u32 delay)
532 if ((delay > 9999) && (s->pm.flags & CS4281_PM_IDLE)) {
533 j = (delay * HZ) / 1000000; /* calculate delay in jiffies */
535 j = 1; /* minimum one jiffy. */
536 current->state = TASK_UNINTERRUPTIBLE;
544 //******************************************************************************
545 // "cs4281_read_ac97" -- Reads a word from the specified location in the
546 // CS4281's address space(based on the BA0 register).
548 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
549 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
551 // 3. Write ACCTL = Control Register = 460h for initiating the write
552 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
553 // 5. if DCV not cleared, break and return error
554 // 6. Read ACSTS = Status Register = 464h, check VSTS bit
555 //****************************************************************************
556 static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
561 // Make sure that there is not data sitting
562 // around from a previous uncompleted access.
563 // ACSDA = Status Data Register = 47Ch
564 status = readl(card->pBA0 + BA0_ACSDA);
566 // Setup the AC97 control registers on the CS4281 to send the
567 // appropriate command to the AC97 to perform the read.
568 // ACCAD = Command Address Register = 46Ch
569 // ACCDA = Command Data Register = 470h
570 // ACCTL = Control Register = 460h
571 // bit DCV - will clear when process completed
572 // bit CRW - Read command
573 // bit VFRM - valid frame enabled
574 // bit ESYN - ASYNC generation enabled
576 // Get the actual AC97 register from the offset
577 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
578 writel(0, card->pBA0 + BA0_ACCDA);
579 writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
580 card->pBA0 + BA0_ACCTL);
582 // Wait for the read to occur.
583 for (count = 0; count < 10; count++) {
584 // First, we want to wait for a short time.
587 // Now, check to see if the read has completed.
588 // ACCTL = 460h, DCV should be reset by now and 460h = 17h
589 if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
593 // Make sure the read completed.
594 if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
597 // Wait for the valid status bit to go active.
598 for (count = 0; count < 10; count++) {
599 // Read the AC97 status register.
600 // ACSTS = Status Register = 464h
601 status = readl(card->pBA0 + BA0_ACSTS);
603 // See if we have valid status.
604 // VSTS - Valid Status
605 if (status & ACSTS_VSTS)
607 // Wait for a short while.
611 // Make sure we got valid status.
612 if (!(status & ACSTS_VSTS))
615 // Read the data returned from the AC97 register.
616 // ACSDA = Status Data Register = 474h
617 *value = readl(card->pBA0 + BA0_ACSDA);
624 //****************************************************************************
626 // "cs4281_write_ac97()"-- writes a word to the specified location in the
627 // CS461x's address space (based on the part's base address zero register).
629 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
630 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
631 // 3. Write ACCTL = Control Register = 460h for initiating the write
632 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
633 // 5. if DCV not cleared, break and return error
635 //****************************************************************************
636 static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
641 CS_DBGOUT(CS_FUNCTION, 2,
642 printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
644 // Setup the AC97 control registers on the CS4281 to send the
645 // appropriate command to the AC97 to perform the read.
646 // ACCAD = Command Address Register = 46Ch
647 // ACCDA = Command Data Register = 470h
648 // ACCTL = Control Register = 460h
649 // set DCV - will clear when process completed
650 // reset CRW - Write command
651 // set VFRM - valid frame enabled
652 // set ESYN - ASYNC generation enabled
653 // set RSTN - ARST# inactive, AC97 codec not reset
655 // Get the actual AC97 register from the offset
657 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
658 writel(value, card->pBA0 + BA0_ACCDA);
659 writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
660 card->pBA0 + BA0_ACCTL);
662 // Wait for the write to occur.
663 for (count = 0; count < 100; count++) {
664 // First, we want to wait for a short time.
666 // Now, check to see if the write has completed.
667 // ACCTL = 460h, DCV should be reset by now and 460h = 07h
668 status = readl(card->pBA0 + BA0_ACCTL);
669 if (!(status & ACCTL_DCV))
673 // Make sure the write completed.
674 if (status & ACCTL_DCV) {
675 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
676 "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
679 CS_DBGOUT(CS_FUNCTION, 2,
680 printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
686 //******************************************************************************
687 // "Init4281()" -- Bring up the part.
688 //******************************************************************************
689 static __devinit int cs4281_hw_init(struct cs4281_state *card)
694 CS_DBGOUT(CS_FUNCTION, 2,
695 printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
696 #ifndef NOT_CS4281_PM
700 temp2 = readl(card->pBA0 + BA0_CFLR);
701 CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO
702 "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2));
703 if(temp2 != CS4281_CFLR_DEFAULT)
705 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
706 "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n",
707 temp2,CS4281_CFLR_DEFAULT));
708 writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
709 temp2 = readl(card->pBA0 + BA0_CFLR);
710 if(temp2 != CS4281_CFLR_DEFAULT)
712 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
713 "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR\n"));
718 //***************************************7
719 // Set up the Sound System Configuration
720 //***************************************
722 // Set the 'Configuration Write Protect' register
723 // to 4281h. Allows vendor-defined configuration
724 // space between 0e4h and 0ffh to be written.
726 writel(0x4281, card->pBA0 + BA0_CWPR); // (3e0h)
728 // (0), Blast the clock control register to zero so that the
729 // PLL starts out in a known state, and blast the master serial
730 // port control register to zero so that the serial ports also
731 // start out in a known state.
733 writel(0, card->pBA0 + BA0_CLKCR1); // (400h)
734 writel(0, card->pBA0 + BA0_SERMC); // (420h)
737 // (1), Make ESYN go to zero to turn off
738 // the Sync pulse on the AC97 link.
740 writel(0, card->pBA0 + BA0_ACCTL);
744 // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
745 // the AC97 spec) and then drive it high. This is done for non
746 // AC97 modes since there might be logic external to the CS461x
747 // that uses the ARST# line for a reset.
749 writel(0, card->pBA0 + BA0_SPMC); // (3ech)
751 writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
752 delayus(card,50000); // Wait 50 ms for ABITCLK to become stable.
754 // (3) Turn on the Sound System Clocks.
755 writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1); // (400h)
756 delayus(card,50000); // Wait for the PLL to stabilize.
757 // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
758 writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
760 // (4) Power on everything for now..
761 writel(0x7E, card->pBA0 + BA0_SSPM); // (740h)
763 // (5) Wait for clock stabilization.
764 for (temp1 = 0; temp1 < 1000; temp1++) {
766 if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
769 if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
770 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
771 "cs4281: DLLRDY failed!\n"));
774 // (6) Enable ASYNC generation.
775 writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
777 // Now wait 'for a short while' to allow the AC97
778 // part to start generating bit clock. (so we don't
779 // Try to start the PLL without an input clock.)
782 // Set the serial port timing configuration, so that the
783 // clock control circuit gets its clock from the right place.
784 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
786 // (7) Wait for the codec ready signal from the AC97 codec.
788 for (temp1 = 0; temp1 < 1000; temp1++) {
789 // Delay a mil to let things settle out and
790 // to prevent retrying the read too quickly.
792 if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready, (464h)
793 break; // exit the 'for' loop.
795 if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY)) // If never came ready,
797 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
798 "cs4281: ACSTS never came ready!\n"));
799 return -EIO; // exit initialization.
801 // (8) Assert the 'valid frame' signal so we can
802 // begin sending commands to the AC97 codec.
803 writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
805 // (9), Wait until CODEC calibration is finished.
806 // Print an error message if it doesn't.
807 for (temp1 = 0; temp1 < 1000; temp1++) {
809 // Read the AC97 Powerdown Control/Status Register.
810 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
811 if ((temp2 & 0x0000000F) == 0x0000000F)
814 if ((temp2 & 0x0000000F) != 0x0000000F) {
815 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
816 "cs4281: Codec failed to calibrate. Status = %.8x.\n",
820 // (10), Set the serial port timing configuration, so that the
821 // clock control circuit gets its clock from the right place.
822 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
825 // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
826 // that the codec is pumping ADC data across the AC link.
827 for (temp1 = 0; temp1 < 1000; temp1++) {
828 // Delay a mil to let things settle out and
829 // to prevent retrying the read too quickly.
830 delayus(card,1000); //(test)
832 // Read the input slot valid register; See
833 // if input slots 3 and 4 are valid yet.
835 (readl(card->pBA0 + BA0_ACISV) &
836 (ACISV_ISV3 | ACISV_ISV4)) ==
837 (ACISV_ISV3 | ACISV_ISV4)) break; // Exit the 'for' if slots are valid.
839 // If we never got valid data, exit initialization.
840 if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
841 != (ACISV_ISV3 | ACISV_ISV4)) {
842 CS_DBGOUT(CS_FUNCTION, 2,
844 "cs4281: Never got valid data!\n"));
845 return -EIO; // If no valid data, exit initialization.
847 // (12), Start digital data transfer of audio data to the codec.
848 writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV); // (468h)
851 //**************************************
852 // Unmute the Master and Alternate
853 // (headphone) volumes. Set to max.
854 //**************************************
855 cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
856 cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
858 //******************************************
859 // Power on the DAC(AddDACUser()from main())
860 //******************************************
861 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
862 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
864 // Wait until we sample a DAC ready state.
865 for (temp2 = 0; temp2 < 32; temp2++) {
866 // Let's wait a mil to let things settle.
868 // Read the current state of the power control reg.
869 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
870 // If the DAC ready state bit is set, stop waiting.
875 //******************************************
876 // Power on the ADC(AddADCUser()from main())
877 //******************************************
878 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
879 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
881 // Wait until we sample ADC ready state.
882 for (temp2 = 0; temp2 < 32; temp2++) {
883 // Let's wait a mil to let things settle.
885 // Read the current state of the power control reg.
886 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
887 // If the ADC ready state bit is set, stop waiting.
891 // Set up 4281 Register contents that
892 // don't change for boot duration.
894 // For playback, we map AC97 slot 3 and 4(Left
895 // & Right PCM playback) to DMA Channel 0.
896 // Set the fifo to be 15 bytes at offset zero.
898 ac97_slotid = 0x01000f00; // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
899 // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
900 // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
901 writel(ac97_slotid, card->pBA0 + BA0_FCR0); // (180h)
902 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0); // Turn on FIFO Enable.
904 // For capture, we map AC97 slot 10 and 11(Left
905 // and Right PCM Record) to DMA Channel 1.
906 // Set the fifo to be 15 bytes at offset sixteen.
907 ac97_slotid = 0x0B0A0f10; // FCR1.RS[4:0]=11(=>slot11, right PCM record).
908 // FCR1.LS[4:0]=10(=>slot10, left PCM record).
909 // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
910 writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1); // (184h)
911 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1); // Turn on FIFO Enable.
913 // Map the Playback SRC to the same AC97 slots(3 & 4--
914 // --Playback left & right)as DMA channel 0.
915 // Map the record SRC to the same AC97 slots(10 & 11--
916 // -- Record left & right) as DMA channel 1.
918 ac97_slotid = 0x0b0a0100; // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
919 // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
920 // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
921 // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
922 writel(ac97_slotid, card->pBA0 + BA0_SRCSA); // (75ch)
924 // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
925 // Count Interrupt Enable' in DMA Control Registers 0 & 1.
926 // Set 'MSK' flag to 1 to keep the DMA engines paused.
927 temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK); // (00030001h)
928 writel(temp1, card->pBA0 + BA0_DCR0); // (154h
929 writel(temp1, card->pBA0 + BA0_DCR1); // (15ch)
931 // Set 'Auto-Initialize Control' to 'enabled'; For playback,
932 // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
933 // for record, set Transfer Type Control to 'write transfer'.
934 // All other bits set to zero; Some will be changed @ transfer start.
935 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); // (20000018h)
936 writel(temp1, card->pBA0 + BA0_DMR0); // (150h)
937 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
938 writel(temp1, card->pBA0 + BA0_DMR1); // (158h)
940 // Enable DMA interrupts generally, and
941 // DMA0 & DMA1 interrupts specifically.
942 temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
943 writel(temp1, card->pBA0 + BA0_HIMR);
945 CS_DBGOUT(CS_FUNCTION, 2,
946 printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
950 #ifndef NOT_CS4281_PM
951 static void printpm(struct cs4281_state *s)
953 CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
954 CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n",
955 (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
956 CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n",
957 s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
958 CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n",
959 s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
960 CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n",
961 s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
962 CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n",
963 s->pm.u32SSCR,s->pm.u32SRCSA));
964 CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n",
965 s->pm.u32DacASR,s->pm.u32AdcASR));
966 CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n",
967 s->pm.u32DacSR,s->pm.u32AdcSR));
968 CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n",
969 s->pm.u32MIDCR_Save));
972 static void printpipe(struct cs4281_pipeline *pl)
975 CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
976 CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n",
977 (unsigned)pl->flags,pl->number));
978 CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n",
979 pl->u32DBAnValue,pl->u32DBCnValue));
980 CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n",
981 pl->u32DMRnValue,pl->u32DCRnValue));
982 CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n",
983 pl->u32DBAnAddress,pl->u32DBCnAddress));
984 CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n",
985 pl->u32DCCnAddress,pl->u32DCCnAddress));
986 CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n",
987 pl->u32DMRnAddress,pl->u32DCRnAddress));
988 CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n",
989 pl->u32HDSRnAddress,pl->u32DBAn_Save));
990 CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n",
991 pl->u32DBCn_Save,pl->u32DMRn_Save));
992 CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n",
993 pl->u32DCRn_Save,pl->u32DCCn_Save));
994 CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n",
996 CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n",
997 pl->u32FCRn_Save,pl->u32FSICn_Save));
998 CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n",
999 pl->u32FCRnValue,pl->u32FSICnValue));
1000 CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n",
1001 pl->u32FCRnAddress,pl->u32FSICnAddress));
1002 CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n",
1003 pl->u32FPDRnValue,pl->u32FPDRnAddress));
1005 static void printpipelines(struct cs4281_state *s)
1008 for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
1010 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1012 printpipe(&s->pl[i]);
1016 /****************************************************************************
1018 * Suspend - save the ac97 regs, mute the outputs and power down the part.
1020 ****************************************************************************/
1021 void cs4281_ac97_suspend(struct cs4281_state *s)
1025 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n"));
1027 * change the state, save the current hwptr, then stop the dac/adc
1029 s->pm.flags &= ~CS4281_PM_IDLE;
1030 s->pm.flags |= CS4281_PM_SUSPENDING;
1031 s->pm.u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
1032 s->pm.u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
1036 for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1037 && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1040 cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
1043 * Save the ac97 volume registers as well as the current powerdown state.
1044 * Now, mute the all the outputs (master, headphone, and mono), as well
1045 * as the PCM volume, in preparation for powering down the entire part.
1047 cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
1048 cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
1049 cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
1050 cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
1052 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
1053 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
1054 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
1055 cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
1057 cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
1058 cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
1061 * And power down everything on the AC97 codec.
1063 cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
1064 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n"));
1067 /****************************************************************************
1069 * Resume - power up the part and restore its registers..
1071 ****************************************************************************/
1072 void cs4281_ac97_resume(struct cs4281_state *s)
1076 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n"));
1078 /* do not save the power state registers at this time
1080 // If we saved away the power control registers, write them into the
1081 // shadows so those saved values get restored instead of the current
1084 if( bPowerStateSaved )
1086 PokeShadow( 0x26, ulSaveReg0x26 );
1087 bPowerStateSaved = FALSE;
1092 // First, we restore the state of the general purpose register. This
1093 // contains the mic select (mic1 or mic2) and if we restore this after
1094 // we restore the mic volume/boost state and mic2 was selected at
1095 // suspend time, we will end up with a brief period of time where mic1
1096 // is selected with the volume/boost settings for mic2, causing
1097 // acoustic feedback. So we restore the general purpose register
1098 // first, thereby getting the correct mic selected before we restore
1099 // the mic volume/boost.
1101 cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
1104 // Now, while the outputs are still muted, restore the state of power
1105 // on the AC97 part.
1107 cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
1110 * Restore just the first set of registers, from register number
1111 * 0x02 to the register number that ulHighestRegToRestore specifies.
1113 for( Count = 0x2, i=0;
1114 (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1115 && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1118 cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
1120 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n"));
1123 /* do not save the power state registers at this time
1124 ****************************************************************************
1126 * SavePowerState - Save the power registers away.
1128 ****************************************************************************
1130 HWAC97codec::SavePowerState(void)
1132 ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n");
1134 ulSaveReg0x26 = PeekShadow(0x26);
1137 // Note that we have saved registers that need to be restored during a
1138 // resume instead of ulAC97Regs[].
1140 bPowerStateSaved = TRUE;
1145 void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1148 * We need to save the contents of the BASIC FIFO Registers.
1150 pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
1151 pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
1153 void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1156 * We need to restore the contents of the BASIC FIFO Registers.
1158 writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
1159 writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
1161 void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1164 // We need to save the contents of the BASIC DMA Registers.
1166 pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
1167 pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
1168 pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
1169 pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
1170 pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
1171 pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
1173 void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1176 // We need to save the contents of the BASIC DMA Registers.
1178 writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
1179 writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
1180 writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
1181 writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
1182 writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
1183 writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
1186 int cs4281_suspend(struct cs4281_state *s)
1190 struct cs4281_pm *pm = &s->pm;
1191 CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1192 printk("cs4281: cs4281_suspend()+ flags=%d\n",
1193 (unsigned)s->pm.flags));
1195 * check the current state, only suspend if IDLE
1197 if(!(s->pm.flags & CS4281_PM_IDLE))
1199 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1200 printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n"));
1203 s->pm.flags &= ~CS4281_PM_IDLE;
1204 s->pm.flags |= CS4281_PM_SUSPENDING;
1207 // Gershwin CLKRUN - Set CKRA
1209 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1211 pm->u32CLKCR1_SAVE = u32CLKCR1;
1212 if(!(u32CLKCR1 & 0x00010000 ) )
1213 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1216 // First, turn on the clocks (yikes) to the devices, so that they will
1217 // respond when we try to save their state.
1219 if(!(u32CLKCR1 & CLKCR1_SWCE))
1221 writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
1225 // Save the power state
1227 pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
1230 // Disable interrupts.
1232 writel(HICR_CHGM, s->pBA0 + BA0_HICR);
1235 // Save the PCM Playback Left and Right Volume Control.
1237 pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
1238 pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
1241 // Save the FM Synthesis Left and Right Volume Control.
1243 pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
1244 pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
1247 // Save the GPIOR value.
1249 pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
1252 // Save the JSCTL value.
1254 pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
1257 // Save Sound System Control Register
1259 pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
1262 // Save SRC Slot Assinment register
1264 pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
1269 pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
1270 pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
1271 pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
1272 pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
1275 // Loop through all of the PipeLines
1277 for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1279 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1282 // Ask the DMAengines and FIFOs to Suspend.
1284 cs4281_SuspendDMAengine(s,&s->pl[i]);
1285 cs4281_SuspendFIFO(s,&s->pl[i]);
1289 // We need to save the contents of the Midi Control Register.
1291 pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
1293 * save off the AC97 part information
1295 cs4281_ac97_suspend(s);
1298 // Turn off the serial ports.
1300 writel(0, s->pBA0 + BA0_SERMC);
1303 // Power off FM, Joystick, AC link,
1305 writel(0, s->pBA0 + BA0_SSPM);
1310 writel(0, s->pBA0 + BA0_CLKCR1);
1315 writel(0, s->pBA0 + BA0_SPMC);
1318 // Put the chip into D3(hot) state.
1320 // PokeBA0(BA0_PMCS, 0x00000003);
1323 // Gershwin CLKRUN - Clear CKRA
1325 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1326 writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
1333 s->pm.flags &= ~CS4281_PM_SUSPENDING;
1334 s->pm.flags |= CS4281_PM_SUSPENDED;
1336 CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1337 printk("cs4281: cs4281_suspend()- flags=%d\n",
1338 (unsigned)s->pm.flags));
1342 int cs4281_resume(struct cs4281_state *s)
1347 struct cs4281_pm *pm = &s->pm;
1348 CS_DBGOUT(CS_PM | CS_FUNCTION, 4,
1349 printk( "cs4281: cs4281_resume()+ flags=%d\n",
1350 (unsigned)s->pm.flags));
1351 if(!(s->pm.flags & CS4281_PM_SUSPENDED))
1353 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1354 printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n"));
1357 s->pm.flags &= ~CS4281_PM_SUSPENDED;
1358 s->pm.flags |= CS4281_PM_RESUMING;
1361 // Gershwin CLKRUN - Set CKRA
1363 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1364 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1367 // set the power state.
1369 //old PokeBA0(BA0_PMCS, 0);
1372 // Program the clock circuit and serial ports.
1374 temp1 = cs4281_hw_init(s);
1376 CS_DBGOUT(CS_ERROR | CS_INIT, 1,
1378 "cs4281: resume cs4281_hw_init() error.\n"));
1383 // restore the Power state
1385 writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
1388 // Set post SRC mix setting (FM or ALT48K)
1390 writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
1393 // Loop through all of the PipeLines
1395 for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1397 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1400 // Ask the DMAengines and FIFOs to Resume.
1402 cs4281_ResumeDMAengine(s,&s->pl[i]);
1403 cs4281_ResumeFIFO(s,&s->pl[i]);
1407 // We need to restore the contents of the Midi Control Register.
1409 writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
1411 cs4281_ac97_resume(s);
1413 // Restore the PCM Playback Left and Right Volume Control.
1415 writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
1416 writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
1419 // Restore the FM Synthesis Left and Right Volume Control.
1421 writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
1422 writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
1425 // Restore the JSCTL value.
1427 writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
1430 // Restore the GPIOR register value.
1432 writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
1435 // Restore Sound System Control Register
1437 writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
1440 // Restore SRC Slot Assignment register
1442 writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
1445 // Restore sample rate
1447 writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
1448 writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
1449 writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
1450 writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
1453 // Restore CFL1/2 registers we saved to compensate for OEM bugs.
1455 // PokeBA0(BA0_CFLR, ulConfig);
1458 // Gershwin CLKRUN - Clear CKRA
1460 writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
1463 // Enable interrupts on the part.
1465 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
1472 * change the state, restore the current hwptrs, then stop the dac/adc
1474 s->pm.flags |= CS4281_PM_IDLE;
1475 s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED
1476 | CS4281_PM_RESUMING | CS4281_PM_RESUMED);
1478 writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
1479 writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
1483 CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n",
1484 (unsigned)s->pm.flags));
1490 //******************************************************************************
1491 // "cs4281_play_rate()" --
1492 //******************************************************************************
1493 static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
1497 // Based on the sample rate, program the DACSR register.
1498 if (playrate == 8000)
1500 if (playrate == 11025)
1502 else if (playrate == 22050)
1504 else if (playrate == 44100)
1506 else if ((playrate <= 48000) && (playrate >= 6023))
1507 DACSRvalue = 24576000 / (playrate * 16);
1508 else if (playrate < 6023)
1509 // Not allowed by open.
1511 else if (playrate > 48000)
1512 // Not allowed by open.
1514 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
1515 "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
1516 DACSRvalue, playrate));
1517 // Write the 'sample rate select code'
1518 // to the 'DAC Sample Rate' register.
1519 writel(DACSRvalue, card->pBA0 + BA0_DACSR); // (744h)
1522 //******************************************************************************
1523 // "cs4281_record_rate()" -- Initialize the record sample rate converter.
1524 //******************************************************************************
1525 static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
1530 // Based on the sample rate, program the ADCSR register
1532 if (outrate == 8000)
1534 if (outrate == 11025)
1536 else if (outrate == 22050)
1538 else if (outrate == 44100)
1540 else if ((outrate <= 48000) && (outrate >= 6023))
1541 ADCSRvalue = 24576000 / (outrate * 16);
1542 else if (outrate < 6023) {
1543 // Not allowed by open.
1545 } else if (outrate > 48000) {
1546 // Not allowed by open.
1549 CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
1550 "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
1551 ADCSRvalue, outrate));
1552 // Write the 'sample rate select code
1553 // to the 'ADC Sample Rate' register.
1554 writel(ADCSRvalue, card->pBA0 + BA0_ADCSR); // (748h)
1559 static void stop_dac(struct cs4281_state *s)
1561 unsigned long flags;
1564 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n"));
1565 spin_lock_irqsave(&s->lock, flags);
1566 s->ena &= ~FMODE_WRITE;
1567 temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
1568 writel(temp1, s->pBA0 + BA0_DCR0);
1570 spin_unlock_irqrestore(&s->lock, flags);
1574 static void start_dac(struct cs4281_state *s)
1576 unsigned long flags;
1579 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n"));
1580 spin_lock_irqsave(&s->lock, flags);
1581 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
1582 (s->dma_dac.count > 0
1583 && s->dma_dac.ready))
1584 #ifndef NOT_CS4281_PM
1585 && (s->pm.flags & CS4281_PM_IDLE))
1590 s->ena |= FMODE_WRITE;
1591 temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK; // Clear DMA0 channel mask.
1592 writel(temp1, s->pBA0 + BA0_DCR0); // Start DMA'ing.
1593 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
1595 writel(7, s->pBA0 + BA0_PPRVC);
1596 writel(7, s->pBA0 + BA0_PPLVC);
1597 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1598 "cs4281: start_dac(): writel 0x%x start dma\n", temp1));
1601 spin_unlock_irqrestore(&s->lock, flags);
1602 CS_DBGOUT(CS_FUNCTION, 3,
1603 printk(KERN_INFO "cs4281: start_dac()-\n"));
1607 static void stop_adc(struct cs4281_state *s)
1609 unsigned long flags;
1612 CS_DBGOUT(CS_FUNCTION, 3,
1613 printk(KERN_INFO "cs4281: stop_adc()+\n"));
1615 spin_lock_irqsave(&s->lock, flags);
1616 s->ena &= ~FMODE_READ;
1618 if (s->conversion == 1) {
1620 s->prop_adc.fmt = s->prop_adc.fmt_original;
1622 temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1623 writel(temp1, s->pBA0 + BA0_DCR1);
1624 spin_unlock_irqrestore(&s->lock, flags);
1625 CS_DBGOUT(CS_FUNCTION, 3,
1626 printk(KERN_INFO "cs4281: stop_adc()-\n"));
1630 static void start_adc(struct cs4281_state *s)
1632 unsigned long flags;
1635 CS_DBGOUT(CS_FUNCTION, 2,
1636 printk(KERN_INFO "cs4281: start_adc()+\n"));
1638 if (!(s->ena & FMODE_READ) &&
1639 (s->dma_adc.mapped || s->dma_adc.count <=
1640 (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1642 #ifndef NOT_CS4281_PM
1643 && (s->pm.flags & CS4281_PM_IDLE))
1648 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1650 // now only use 16 bit capture, due to truncation issue
1651 // in the chip, noticable distortion occurs.
1652 // allocate buffer and then convert from 16 bit to
1653 // 8 bit for the user buffer.
1655 s->prop_adc.fmt_original = s->prop_adc.fmt;
1656 if (s->prop_adc.fmt & AFMT_S8) {
1657 s->prop_adc.fmt &= ~AFMT_S8;
1658 s->prop_adc.fmt |= AFMT_S16_LE;
1660 if (s->prop_adc.fmt & AFMT_U8) {
1661 s->prop_adc.fmt &= ~AFMT_U8;
1662 s->prop_adc.fmt |= AFMT_U16_LE;
1665 // prog_dmabuf_adc performs a stop_adc() but that is
1666 // ok since we really haven't started the DMA yet.
1668 prog_codec(s, CS_TYPE_ADC);
1670 if (prog_dmabuf_adc(s) != 0) {
1671 CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
1672 "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1676 spin_lock_irqsave(&s->lock, flags);
1677 s->ena |= FMODE_READ;
1678 temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK; // Clear DMA1 channel mask bit.
1679 writel(temp1, s->pBA0 + BA0_DCR1); // Start recording
1680 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
1681 spin_unlock_irqrestore(&s->lock, flags);
1683 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
1684 "cs4281: start_adc(): writel 0x%x \n", temp1));
1686 CS_DBGOUT(CS_FUNCTION, 2,
1687 printk(KERN_INFO "cs4281: start_adc()-\n"));
1692 // ---------------------------------------------------------------------
1694 #define DMABUF_MINORDER 1 // ==> min buffer size = 8K.
1697 extern void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1699 struct page *map, *mapend;
1702 // Undo prog_dmabuf()'s marking the pages as reserved
1704 virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1706 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1707 ClearPageReserved(map);
1710 if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1711 // Undo prog_dmabuf()'s marking the pages as reserved
1713 virt_to_page(s->tmpbuff +
1714 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1715 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1716 ClearPageReserved(map);
1717 free_dmabuf2(s, db);
1721 db->mapped = db->ready = 0;
1724 static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1727 unsigned bytespersec, temp1;
1728 unsigned bufs, sample_shift = 0;
1729 struct page *map, *mapend;
1732 CS_DBGOUT(CS_FUNCTION, 2,
1733 printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1734 db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1735 db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
1737 * check for order within limits, but do not overwrite value, check
1738 * later for a fractional defaultorder (i.e. 100+).
1740 if((defaultorder > 0) && (defaultorder < 12))
1746 db->ready = db->mapped = 0;
1747 for (order = df; order >= DMABUF_MINORDER; order--)
1748 if ( (db->rawbuf = (void *) pci_alloc_consistent(
1749 s->pcidev, PAGE_SIZE << order, &db-> dmaaddr)))
1752 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1753 "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1756 db->buforder = order;
1757 // Now mark the pages as reserved; otherwise the
1758 // remap_page_range() in cs4281_mmap doesn't work.
1759 // 1. get index to last page in mem_map array for rawbuf.
1760 mapend = virt_to_page(db->rawbuf +
1761 (PAGE_SIZE << db->buforder) - 1);
1763 // 2. mark each physical page in range as 'reserved'.
1764 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1765 SetPageReserved(map);
1767 if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1768 for (order = df; order >= DMABUF_MINORDER;
1770 if ( (s->tmpbuff = (void *) pci_alloc_consistent(
1771 s->pcidev, PAGE_SIZE << order,
1772 &s->dmaaddr_tmpbuff)))
1775 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1776 "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1779 s->buforder_tmpbuff = order;
1780 // Now mark the pages as reserved; otherwise the
1781 // remap_page_range() in cs4281_mmap doesn't work.
1782 // 1. get index to last page in mem_map array for rawbuf.
1783 mapend = virt_to_page(s->tmpbuff +
1784 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1786 // 2. mark each physical page in range as 'reserved'.
1787 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1788 SetPageReserved(map);
1790 if (db->type == CS_TYPE_DAC) {
1791 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1793 if (s->prop_dac.channels > 1)
1795 bytespersec = s->prop_dac.rate << sample_shift;
1796 } else // CS_TYPE_ADC
1798 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1800 if (s->prop_adc.channels > 1)
1802 bytespersec = s->prop_adc.rate << sample_shift;
1804 bufs = PAGE_SIZE << db->buforder;
1807 * added fractional "defaultorder" inputs. if >100 then use
1808 * defaultorder-100 as power of 2 for the buffer size. example:
1809 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
1811 if(defaultorder >= 100)
1813 bufs = 1 << (defaultorder-100);
1816 #define INTERRUPT_RATE_MS 100 // Interrupt rate in milliseconds.
1819 * Nominal frag size(bytes/interrupt)
1821 temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
1822 db->fragshift = 8; // Min 256 bytes.
1823 while (1 << db->fragshift < temp1) // Calc power of 2 frag size.
1825 db->fragsize = 1 << db->fragshift;
1826 db->dmasize = db->fragsize * 2;
1827 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1829 // If the calculated size is larger than the allocated
1830 // buffer, divide the allocated buffer into 2 fragments.
1831 if (db->dmasize > bufs) {
1833 db->numfrag = 2; // Two fragments.
1834 db->fragsize = bufs >> 1; // Each 1/2 the alloc'ed buffer.
1835 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1836 db->dmasize = bufs; // Use all the alloc'ed buffer.
1838 db->fragshift = 0; // Calculate 'fragshift'.
1839 temp1 = db->fragsize; // update_ptr() uses it
1840 while ((temp1 >>= 1) > 1) // to calc 'total-bytes'
1841 db->fragshift += 1; // returned in DSP_GETI/OPTR.
1843 CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
1844 "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1845 db->numfrag, db->fragsize, db->fragsamples,
1846 db->fragshift, bufs,
1847 (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt :
1849 (db->type == CS_TYPE_DAC) ? s->prop_dac.channels :
1850 s->prop_adc.channels));
1851 CS_DBGOUT(CS_FUNCTION, 2,
1852 printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1857 static int prog_dmabuf_adc(struct cs4281_state *s)
1863 s->dma_adc.type = CS_TYPE_ADC;
1864 if ((c = prog_dmabuf(s, &s->dma_adc)))
1867 if (s->dma_adc.rawbuf) {
1868 memset(s->dma_adc.rawbuf,
1870 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1871 s->dma_adc.dmasize);
1876 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1877 PAGE_SIZE << s->buforder_tmpbuff);
1880 va = virt_to_bus(s->dma_adc.rawbuf);
1882 count = s->dma_adc.dmasize;
1885 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1886 count /= 2; // 16-bit.
1888 if (s->prop_adc.channels > 1)
1889 count /= 2; // Assume stereo.
1891 CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1892 "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1893 count, (unsigned) va));
1895 writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1896 writel(count - 1, s->pBA0 + BA0_DBC1); // Set count.
1897 s->dma_adc.ready = 1;
1902 static int prog_dmabuf_dac(struct cs4281_state *s)
1908 s->dma_dac.type = CS_TYPE_DAC;
1909 if ((c = prog_dmabuf(s, &s->dma_dac)))
1911 memset(s->dma_dac.rawbuf,
1912 (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1913 s->dma_dac.dmasize);
1915 va = virt_to_bus(s->dma_dac.rawbuf);
1917 count = s->dma_dac.dmasize;
1919 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1920 count /= 2; // 16-bit.
1922 if (s->prop_dac.channels > 1)
1923 count /= 2; // Assume stereo.
1925 writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1926 writel(count - 1, s->pBA0 + BA0_DBC0); // Set count.
1928 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1929 "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1930 count, (unsigned) va));
1932 s->dma_dac.ready = 1;
1937 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1938 unsigned len, unsigned char c)
1940 if (bptr + len > bsize) {
1941 unsigned x = bsize - bptr;
1942 memset(((char *) buf) + bptr, c, x);
1946 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1947 "cs4281: clear_advance(): memset %d at %p for %d size \n",
1948 (unsigned)c, ((char *) buf) + bptr, len));
1949 memset(((char *) buf) + bptr, c, len);
1954 // call with spinlock held!
1955 static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
1960 // update ADC pointer
1961 if (s->ena & FMODE_READ) {
1962 hwptr = readl(s->pBA0 + BA0_DCA1); // Read capture DMA address.
1963 va = virt_to_bus(s->dma_adc.rawbuf);
1964 hwptr -= (unsigned) va;
1966 (s->dma_adc.dmasize + hwptr -
1967 s->dma_adc.hwptr) % s->dma_adc.dmasize;
1968 s->dma_adc.hwptr = hwptr;
1969 s->dma_adc.total_bytes += diff;
1970 s->dma_adc.count += diff;
1971 if (s->dma_adc.count > s->dma_adc.dmasize)
1972 s->dma_adc.count = s->dma_adc.dmasize;
1973 if (s->dma_adc.mapped) {
1974 if (s->dma_adc.count >=
1975 (signed) s->dma_adc.fragsize) wake_up(&s->
1979 if (s->dma_adc.count > 0)
1980 wake_up(&s->dma_adc.wait);
1982 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1983 "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
1984 s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count));
1986 // update DAC pointer
1988 // check for end of buffer, means that we are going to wait for another interrupt
1989 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1991 if (s->ena & FMODE_WRITE) {
1992 hwptr = readl(s->pBA0 + BA0_DCA0); // Read play DMA address.
1993 va = virt_to_bus(s->dma_dac.rawbuf);
1994 hwptr -= (unsigned) va;
1995 diff = (s->dma_dac.dmasize + hwptr -
1996 s->dma_dac.hwptr) % s->dma_dac.dmasize;
1997 s->dma_dac.hwptr = hwptr;
1998 s->dma_dac.total_bytes += diff;
1999 if (s->dma_dac.mapped) {
2000 s->dma_dac.count += diff;
2001 if (s->dma_dac.count >= s->dma_dac.fragsize) {
2002 s->dma_dac.wakeup = 1;
2003 wake_up(&s->dma_dac.wait);
2004 if (s->dma_dac.count > s->dma_dac.dmasize)
2006 s->dma_dac.dmasize - 1;
2009 s->dma_dac.count -= diff;
2010 if (s->dma_dac.count <= 0) {
2012 // fill with silence, and do not shut down the DAC.
2013 // Continue to play silence until the _release.
2015 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
2016 "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n",
2017 (unsigned)(s->prop_dac.fmt &
2018 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
2019 s->dma_dac.rawbuf, s->dma_dac.dmasize));
2020 memset(s->dma_dac.rawbuf,
2022 fmt & (AFMT_U8 | AFMT_U16_LE)) ?
2023 0x80 : 0, s->dma_dac.dmasize);
2024 if (s->dma_dac.count < 0) {
2025 s->dma_dac.underrun = 1;
2026 s->dma_dac.count = 0;
2027 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
2028 "cs4281: cs4281_update_ptr(): underrun\n"));
2030 } else if (s->dma_dac.count <=
2031 (signed) s->dma_dac.fragsize
2032 && !s->dma_dac.endcleared) {
2033 clear_advance(s->dma_dac.rawbuf,
2036 s->dma_dac.fragsize,
2039 AFMT_U16_LE)) ? 0x80
2041 s->dma_dac.endcleared = 1;
2043 if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
2046 wake_up(&s->dma_dac.wait);
2049 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2050 "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
2051 s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count));
2056 // ---------------------------------------------------------------------
2058 static void prog_codec(struct cs4281_state *s, unsigned type)
2060 unsigned long flags;
2061 unsigned temp1, format;
2063 CS_DBGOUT(CS_FUNCTION, 2,
2064 printk(KERN_INFO "cs4281: prog_codec()+ \n"));
2066 spin_lock_irqsave(&s->lock, flags);
2067 if (type == CS_TYPE_ADC) {
2068 temp1 = readl(s->pBA0 + BA0_DCR1);
2069 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1); // Stop capture DMA, if active.
2071 // program sampling rates
2072 // Note, for CS4281, capture & play rates can be set independently.
2073 cs4281_record_rate(s, s->prop_adc.rate);
2075 // program ADC parameters
2076 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
2078 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
2079 if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE)) // Big-endian?
2080 format |= DMRn_BEND;
2081 if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2082 format |= DMRn_USIGN; // Unsigned.
2084 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
2085 if (s->prop_adc.channels < 2)
2086 format |= DMRn_MONO;
2088 writel(format, s->pBA0 + BA0_DMR1);
2090 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2091 "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
2092 (format & DMRn_SIZE8) ? "8" : "16",
2093 (format & DMRn_USIGN) ? "Unsigned" : "Signed",
2094 (format & DMRn_MONO) ? "Mono" : "Stereo",
2095 s->prop_adc.rate, format));
2097 s->ena &= ~FMODE_READ; // not capturing data yet
2101 if (type == CS_TYPE_DAC) {
2102 temp1 = readl(s->pBA0 + BA0_DCR0);
2103 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0); // Stop play DMA, if active.
2105 // program sampling rates
2106 // Note, for CS4281, capture & play rates can be set independently.
2107 cs4281_play_rate(s, s->prop_dac.rate);
2109 // program DAC parameters
2110 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
2112 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
2113 if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
2114 format |= DMRn_BEND; // Big Endian.
2115 if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2116 format |= DMRn_USIGN; // Unsigned.
2118 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
2120 if (s->prop_dac.channels < 2)
2121 format |= DMRn_MONO;
2123 writel(format, s->pBA0 + BA0_DMR0);
2126 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2127 "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
2128 (format & DMRn_SIZE8) ? "8" : "16",
2129 (format & DMRn_USIGN) ? "Unsigned" : "Signed",
2130 (format & DMRn_MONO) ? "Mono" : "Stereo",
2131 s->prop_dac.rate, format));
2133 s->ena &= ~FMODE_WRITE; // not capturing data yet
2136 spin_unlock_irqrestore(&s->lock, flags);
2137 CS_DBGOUT(CS_FUNCTION, 2,
2138 printk(KERN_INFO "cs4281: prog_codec()- \n"));
2142 static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
2145 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
2146 // Value of array member is recording source Device ID Mask.
2147 static const unsigned int mixer_src[8] = {
2148 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
2149 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
2152 // Index of mixtable1[] member is Device ID
2153 // and must be <= SOUND_MIXER_NRDEVICES.
2154 // Value of array member is index into s->mix.vol[]
2155 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
2156 [SOUND_MIXER_PCM] = 1, // voice
2157 [SOUND_MIXER_LINE1] = 2, // AUX
2158 [SOUND_MIXER_CD] = 3, // CD
2159 [SOUND_MIXER_LINE] = 4, // Line
2160 [SOUND_MIXER_SYNTH] = 5, // FM
2161 [SOUND_MIXER_MIC] = 6, // Mic
2162 [SOUND_MIXER_SPEAKER] = 7, // Speaker
2163 [SOUND_MIXER_RECLEV] = 8, // Recording level
2164 [SOUND_MIXER_VOLUME] = 9 // Master Volume
2168 static const unsigned mixreg[] = {
2169 BA0_AC97_PCM_OUT_VOLUME,
2170 BA0_AC97_AUX_VOLUME,
2172 BA0_AC97_LINE_IN_VOLUME
2174 unsigned char l, r, rl, rr, vidx;
2175 unsigned char attentbl[11] =
2176 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
2181 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
2182 "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd));
2186 #if CSDEBUG_INTERFACE
2188 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
2189 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
2190 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
2191 (cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
2192 (cmd == SOUND_MIXER_CS_APM))
2196 case SOUND_MIXER_CS_GETDBGMASK:
2197 return put_user(cs_debugmask,
2198 (unsigned long *) arg);
2200 case SOUND_MIXER_CS_GETDBGLEVEL:
2201 return put_user(cs_debuglevel,
2202 (unsigned long *) arg);
2204 case SOUND_MIXER_CS_SETDBGMASK:
2205 if (get_user(val, (unsigned long *) arg))
2210 case SOUND_MIXER_CS_SETDBGLEVEL:
2211 if (get_user(val, (unsigned long *) arg))
2213 cs_debuglevel = val;
2215 #ifndef NOT_CS4281_PM
2216 case SOUND_MIXER_CS_APM:
2217 if (get_user(val, (unsigned long *) arg))
2219 if(val == CS_IOCTL_CMD_SUSPEND)
2221 else if(val == CS_IOCTL_CMD_RESUME)
2225 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2226 "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n",
2232 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2233 "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
2239 if (cmd == SOUND_MIXER_PRIVATE1) {
2240 // enable/disable/query mixer preamp
2241 if (get_user(val, (int *) arg))
2244 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2245 temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
2246 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2248 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2249 val = (temp1 & 0x40) ? 1 : 0;
2250 return put_user(val, (int *) arg);
2252 if (cmd == SOUND_MIXER_PRIVATE2) {
2253 // enable/disable/query spatializer
2254 if (get_user(val, (int *) arg))
2257 temp1 = (val & 0x3f) >> 2;
2258 cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
2259 cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2261 cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2264 cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
2265 return put_user((temp1 << 2) | 3, (int *) arg);
2267 if (cmd == SOUND_MIXER_INFO) {
2269 strlcpy(info.id, "CS4281", sizeof(info.id));
2270 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2271 info.modify_counter = s->mix.modcnt;
2272 if (copy_to_user((void *) arg, &info, sizeof(info)))
2276 if (cmd == SOUND_OLD_MIXER_INFO) {
2277 _old_mixer_info info;
2278 strlcpy(info.id, "CS4281", sizeof(info.id));
2279 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2280 if (copy_to_user((void *) arg, &info, sizeof(info)))
2284 if (cmd == OSS_GETVERSION)
2285 return put_user(SOUND_VERSION, (int *) arg);
2287 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
2290 // If ioctl has only the SIOC_READ bit(bit 31)
2291 // on, process the only-read commands.
2292 if (_SIOC_DIR(cmd) == _SIOC_READ) {
2293 switch (_IOC_NR(cmd)) {
2294 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
2295 cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT,
2297 return put_user(mixer_src[temp1 & 7], (int *) arg);
2299 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
2300 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2301 SOUND_MASK_CD | SOUND_MASK_LINE |
2302 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2305 SOUND_MASK_SPEAKER, (int *) arg);
2307 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
2308 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC |
2309 SOUND_MASK_CD | SOUND_MASK_VOLUME |
2310 SOUND_MASK_LINE1, (int *) arg);
2312 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
2313 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2314 SOUND_MASK_CD | SOUND_MASK_LINE |
2315 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2317 SOUND_MASK_RECLEV, (int *) arg);
2319 case SOUND_MIXER_CAPS:
2320 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
2324 if (i >= SOUND_MIXER_NRDEVICES
2325 || !(vidx = mixtable1[i]))
2327 return put_user(s->mix.vol[vidx - 1], (int *) arg);
2330 // If ioctl doesn't have both the SIOC_READ and
2331 // the SIOC_WRITE bit set, return invalid.
2332 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
2335 // Increment the count of volume writes.
2338 // Isolate the command; it must be a write.
2339 switch (_IOC_NR(cmd)) {
2341 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
2342 if (get_user(val, (int *) arg))
2344 i = hweight32(val); // i = # bits on in val.
2345 if (i != 1) // One & only 1 bit must be on.
2347 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
2348 if (val == mixer_src[i]) {
2349 temp1 = (i << 8) | i;
2350 cs4281_write_ac97(s,
2351 BA0_AC97_RECORD_SELECT,
2358 case SOUND_MIXER_VOLUME:
2359 if (get_user(val, (int *) arg))
2363 l = 100; // Max soundcard.h vol is 100.
2368 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
2370 r = (val >> 8) & 0xff;
2372 r = 100; // Max right volume is 100, too
2377 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
2379 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
2380 temp1 = 0x8000; // turn on the mute bit.
2384 temp1 |= (rl << 8) | rr;
2386 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
2387 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
2389 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2390 s->mix.vol[8] = ((unsigned int) r << 8) | l;
2392 s->mix.vol[8] = val;
2394 return put_user(s->mix.vol[8], (int *) arg);
2396 case SOUND_MIXER_SPEAKER:
2397 if (get_user(val, (int *) arg))
2406 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
2407 l = (rl * 13 + 5) / 2;
2415 rl = 15 - rl; // Convert volume to attenuation.
2417 cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
2419 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2420 s->mix.vol[6] = l << 8;
2422 s->mix.vol[6] = val;
2424 return put_user(s->mix.vol[6], (int *) arg);
2426 case SOUND_MIXER_RECLEV:
2427 if (get_user(val, (int *) arg))
2432 r = (val >> 8) & 0xff;
2435 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
2436 rr = (r * 2 - 5) / 13;
2437 if (rl < 3 && rr < 3)
2442 temp1 = temp1 | (rl << 8) | rr;
2443 cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
2445 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2446 s->mix.vol[7] = ((unsigned int) r << 8) | l;
2448 s->mix.vol[7] = val;
2450 return put_user(s->mix.vol[7], (int *) arg);
2452 case SOUND_MIXER_MIC:
2453 if (get_user(val, (int *) arg))
2462 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
2463 l = (rl * 16 + 4) / 5;
2465 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2466 temp1 &= 0x40; // Isolate 20db gain bit.
2471 rl = 31 - rl; // Convert volume to attenuation.
2473 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2475 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2476 s->mix.vol[5] = val << 8;
2478 s->mix.vol[5] = val;
2480 return put_user(s->mix.vol[5], (int *) arg);
2483 case SOUND_MIXER_SYNTH:
2484 if (get_user(val, (int *) arg))
2489 if (get_user(val, (int *) arg))
2491 r = (val >> 8) & 0xff;
2494 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
2495 rr = (r * 2 - 11) / 3;
2496 if (rl < 3) // If l is low, turn on
2497 temp1 = 0x0080; // the mute bit.
2501 rl = 63 - rl; // Convert vol to attenuation.
2502 writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
2503 if (rr < 3) // If rr is low, turn on
2504 temp1 = 0x0080; // the mute bit.
2507 rr = 63 - rr; // Convert vol to attenuation.
2508 writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
2510 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2511 s->mix.vol[4] = (r << 8) | l;
2513 s->mix.vol[4] = val;
2515 return put_user(s->mix.vol[4], (int *) arg);
2519 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2520 "cs4281: mixer_ioctl(): default\n"));
2523 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
2525 if (get_user(val, (int *) arg))
2534 rl = (attentbl[(l * 10) / 100]) >> 1;
2536 r = (val >> 8) & 0xff;
2543 rr = (attentbl[(r * 10) / 100]) >> 1;
2544 if ((rl > 30) && (rr > 30))
2548 temp1 = temp1 | (rl << 8) | rr;
2549 cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
2551 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2552 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
2554 s->mix.vol[vidx - 1] = val;
2556 #ifndef NOT_CS4281_PM
2557 CS_DBGOUT(CS_PM, 9, printk(KERN_INFO
2558 "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n",
2559 vidx-1,temp1,s->mix.vol[vidx-1]));
2561 return put_user(s->mix.vol[vidx - 1], (int *) arg);
2566 // ---------------------------------------------------------------------
2568 static int cs4281_open_mixdev(struct inode *inode, struct file *file)
2570 unsigned int minor = iminor(inode);
2571 struct cs4281_state *s=NULL;
2572 struct list_head *entry;
2574 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2575 printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n"));
2577 list_for_each(entry, &cs4281_devs)
2579 s = list_entry(entry, struct cs4281_state, list);
2580 if(s->dev_mixer == minor)
2585 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
2586 printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n"));
2590 file->private_data = s;
2592 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2593 printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n"));
2599 static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2601 struct cs4281_state *s =
2602 (struct cs4281_state *) file->private_data;
2609 static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2610 unsigned int cmd, unsigned long arg)
2612 return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2617 // ******************************************************************************************
2618 // Mixer file operations struct.
2619 // ******************************************************************************************
2620 static /*const */ struct file_operations cs4281_mixer_fops = {
2621 .owner = THIS_MODULE,
2622 .llseek = no_llseek,
2623 .ioctl = cs4281_ioctl_mixdev,
2624 .open = cs4281_open_mixdev,
2625 .release = cs4281_release_mixdev,
2628 // ---------------------------------------------------------------------
2631 static int drain_adc(struct cs4281_state *s, int nonblock)
2633 DECLARE_WAITQUEUE(wait, current);
2634 unsigned long flags;
2638 if (s->dma_adc.mapped)
2640 add_wait_queue(&s->dma_adc.wait, &wait);
2642 set_current_state(TASK_INTERRUPTIBLE);
2643 spin_lock_irqsave(&s->lock, flags);
2644 count = s->dma_adc.count;
2645 CS_DBGOUT(CS_FUNCTION, 2,
2646 printk(KERN_INFO "cs4281: drain_adc() %d\n", count));
2647 spin_unlock_irqrestore(&s->lock, flags);
2649 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2650 "cs4281: drain_adc() count<0\n"));
2653 if (signal_pending(current))
2656 remove_wait_queue(&s->dma_adc.wait, &wait);
2657 current->state = TASK_RUNNING;
2662 s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2663 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2665 if (s->prop_adc.channels > 1)
2667 if (!schedule_timeout(tmo + 1))
2668 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2670 remove_wait_queue(&s->dma_adc.wait, &wait);
2671 current->state = TASK_RUNNING;
2672 if (signal_pending(current))
2673 return -ERESTARTSYS;
2677 static int drain_dac(struct cs4281_state *s, int nonblock)
2679 DECLARE_WAITQUEUE(wait, current);
2680 unsigned long flags;
2684 if (s->dma_dac.mapped)
2686 add_wait_queue(&s->dma_dac.wait, &wait);
2688 set_current_state(TASK_INTERRUPTIBLE);
2689 spin_lock_irqsave(&s->lock, flags);
2690 count = s->dma_dac.count;
2691 spin_unlock_irqrestore(&s->lock, flags);
2694 if (signal_pending(current))
2697 remove_wait_queue(&s->dma_dac.wait, &wait);
2698 current->state = TASK_RUNNING;
2703 s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2704 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2706 if (s->prop_dac.channels > 1)
2708 if (!schedule_timeout(tmo + 1))
2709 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2711 remove_wait_queue(&s->dma_dac.wait, &wait);
2712 current->state = TASK_RUNNING;
2713 if (signal_pending(current))
2714 return -ERESTARTSYS;
2718 //****************************************************************************
2720 // CopySamples copies 16-bit stereo samples from the source to the
2721 // destination, possibly converting down to either 8-bit or mono or both.
2722 // count specifies the number of output bytes to write.
2726 // dst - Pointer to a destination buffer.
2727 // src - Pointer to a source buffer
2728 // count - The number of bytes to copy into the destination buffer.
2729 // iChannels - Stereo - 2
2731 // fmt - AFMT_xxx (soundcard.h formats)
2733 // NOTES: only call this routine for conversion to 8bit from 16bit
2735 //****************************************************************************
2736 static void CopySamples(char *dst, char *src, int count, int iChannels,
2740 unsigned short *psSrc;
2743 CS_DBGOUT(CS_FUNCTION, 2,
2744 printk(KERN_INFO "cs4281: CopySamples()+ "));
2745 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2746 " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n",
2747 dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt));
2749 // Gershwin does format conversion in hardware so normally
2750 // we don't do any host based coversion. The data formatter
2751 // truncates 16 bit data to 8 bit and that causes some hiss.
2752 // We have already forced the HW to do 16 bit sampling and
2753 // 2 channel so that we can use software to round instead
2757 // See if the data should be output as 8-bit unsigned stereo.
2758 // or if the data should be output at 8-bit unsigned mono.
2760 if ( ((iChannels == 2) && (fmt & AFMT_U8)) ||
2761 ((iChannels == 1) && (fmt & AFMT_U8)) ) {
2763 // Convert each 16-bit unsigned stereo sample to 8-bit unsigned
2764 // stereo using rounding.
2766 psSrc = (unsigned short *) src;
2769 lAudioSample = (long) psSrc[count] + (long) 0x80;
2770 if (lAudioSample > 0xffff) {
2771 lAudioSample = 0xffff;
2773 dst[count] = (char) (lAudioSample >> 8);
2777 // check for 8-bit signed stereo.
2779 else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2781 // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2783 psSrc = (short *) src;
2786 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2788 *dst++ = (char) ((short) lAudioSample >> 8);
2792 // Otherwise, the data should be output as 8-bit signed mono.
2794 else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2796 // Convert each 16-bit signed mono sample to 8-bit signed mono
2799 psSrc = (short *) src;
2803 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2804 if (lAudioSample > 0x7fff) {
2805 lAudioSample = 0x7fff;
2808 *dst++ = (char) ((short) lAudioSample >> 8);
2814 // cs_copy_to_user()
2815 // replacement for the standard copy_to_user, to allow for a conversion from
2816 // 16 bit to 8 bit if the record conversion is active. the cs4281 has some
2817 // issues with 8 bit capture, so the driver always captures data in 16 bit
2818 // and then if the user requested 8 bit, converts from 16 to 8 bit.
2820 static unsigned cs_copy_to_user(struct cs4281_state *s, void *dest,
2821 unsigned *hwsrc, unsigned cnt,
2824 void *src = hwsrc; //default to the standard destination buffer addr
2826 CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2827 "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n",
2828 s->prop_adc.fmt, s->prop_adc.fmt_original,
2829 (unsigned) cnt, dest));
2831 if (cnt > s->dma_adc.dmasize) {
2832 cnt = s->dma_adc.dmasize;
2838 if (s->conversion) {
2843 CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2844 (unsigned) s->prop_adc.channels,
2845 s->prop_adc.fmt_original);
2850 if (copy_to_user(dest, src, cnt)) {
2855 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2856 "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt));
2860 // ---------------------------------------------------------------------
2862 static ssize_t cs4281_read(struct file *file, char *buffer, size_t count,
2865 struct cs4281_state *s =
2866 (struct cs4281_state *) file->private_data;
2868 unsigned long flags;
2871 unsigned copied = 0;
2873 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2874 printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count));
2877 if (ppos != &file->f_pos)
2879 if (s->dma_adc.mapped)
2881 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2883 if (!access_ok(VERIFY_WRITE, buffer, count))
2887 // "count" is the amount of bytes to read (from app), is decremented each loop
2888 // by the amount of bytes that have been returned to the user buffer.
2889 // "cnt" is the running total of each read from the buffer (changes each loop)
2890 // "buffer" points to the app's buffer
2891 // "ret" keeps a running total of the amount of bytes that have been copied
2892 // to the user buffer.
2893 // "copied" is the total bytes copied into the user buffer for each loop.
2896 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2897 "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n",
2898 count, s->dma_adc.count,
2899 s->dma_adc.swptr, s->dma_adc.hwptr));
2900 spin_lock_irqsave(&s->lock, flags);
2902 // get the current copy point of the sw buffer
2903 swptr = s->dma_adc.swptr;
2905 // cnt is the amount of unread bytes from the end of the
2906 // hw buffer to the current sw pointer
2907 cnt = s->dma_adc.dmasize - swptr;
2909 // dma_adc.count is the current total bytes that have not been read.
2910 // if the amount of unread bytes from the current sw pointer to the
2911 // end of the buffer is greater than the current total bytes that
2912 // have not been read, then set the "cnt" (unread bytes) to the
2913 // amount of unread bytes.
2915 if (s->dma_adc.count < cnt)
2916 cnt = s->dma_adc.count;
2917 spin_unlock_irqrestore(&s->lock, flags);
2919 // if we are converting from 8/16 then we need to copy
2920 // twice the number of 16 bit bytes then 8 bit bytes.
2922 if (s->conversion) {
2923 if (cnt > (count * 2))
2930 // "cnt" NOW is the smaller of the amount that will be read,
2931 // and the amount that is requested in this read (or partial).
2932 // if there are no bytes in the buffer to read, then start the
2933 // ADC and wait for the interrupt handler to wake us up.
2937 // start up the dma engine and then continue back to the top of
2938 // the loop when wake up occurs.
2940 if (file->f_flags & O_NONBLOCK)
2941 return ret ? ret : -EAGAIN;
2942 interruptible_sleep_on(&s->dma_adc.wait);
2943 if (signal_pending(current))
2944 return ret ? ret : -ERESTARTSYS;
2947 // there are bytes in the buffer to read.
2948 // copy from the hw buffer over to the user buffer.
2949 // user buffer is designated by "buffer"
2950 // virtual address to copy from is rawbuf+swptr
2951 // the "cnt" is the number of bytes to read.
2953 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
2954 "_read() copy_to cnt=%d count=%Zu ", cnt, count));
2955 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2956 " .dmasize=%d .count=%d buffer=%p ret=%Zd\n",
2957 s->dma_adc.dmasize, s->dma_adc.count, buffer, ret));
2960 (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
2961 return ret ? ret : -EFAULT;
2962 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2963 spin_lock_irqsave(&s->lock, flags);
2964 s->dma_adc.swptr = swptr;
2965 s->dma_adc.count -= cnt;
2966 spin_unlock_irqrestore(&s->lock, flags);
2972 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2973 printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret));
2978 static ssize_t cs4281_write(struct file *file, const char *buffer,
2979 size_t count, loff_t * ppos)
2981 struct cs4281_state *s =
2982 (struct cs4281_state *) file->private_data;
2984 unsigned long flags;
2985 unsigned swptr, hwptr, busaddr;
2988 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2989 printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n",
2993 if (ppos != &file->f_pos)
2995 if (s->dma_dac.mapped)
2997 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
2999 if (!access_ok(VERIFY_READ, buffer, count))
3003 spin_lock_irqsave(&s->lock, flags);
3004 if (s->dma_dac.count < 0) {
3005 s->dma_dac.count = 0;
3006 s->dma_dac.swptr = s->dma_dac.hwptr;
3008 if (s->dma_dac.underrun) {
3009 s->dma_dac.underrun = 0;
3010 hwptr = readl(s->pBA0 + BA0_DCA0);
3011 busaddr = virt_to_bus(s->dma_dac.rawbuf);
3012 hwptr -= (unsigned) busaddr;
3013 s->dma_dac.swptr = s->dma_dac.hwptr = hwptr;
3015 swptr = s->dma_dac.swptr;
3016 cnt = s->dma_dac.dmasize - swptr;
3017 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
3018 cnt = s->dma_dac.dmasize - s->dma_dac.count;
3019 spin_unlock_irqrestore(&s->lock, flags);
3024 if (file->f_flags & O_NONBLOCK)
3025 return ret ? ret : -EAGAIN;
3026 interruptible_sleep_on(&s->dma_dac.wait);
3027 if (signal_pending(current))
3028 return ret ? ret : -ERESTARTSYS;
3031 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
3032 return ret ? ret : -EFAULT;
3033 swptr = (swptr + cnt) % s->dma_dac.dmasize;
3034 spin_lock_irqsave(&s->lock, flags);
3035 s->dma_dac.swptr = swptr;
3036 s->dma_dac.count += cnt;
3037 s->dma_dac.endcleared = 0;
3038 spin_unlock_irqrestore(&s->lock, flags);
3044 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3045 printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret));
3050 static unsigned int cs4281_poll(struct file *file,
3051 struct poll_table_struct *wait)
3053 struct cs4281_state *s =
3054 (struct cs4281_state *) file->private_data;
3055 unsigned long flags;
3056 unsigned int mask = 0;
3058 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3059 printk(KERN_INFO "cs4281: cs4281_poll()+\n"));
3061 if (file->f_mode & FMODE_WRITE) {
3062 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3064 "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
3065 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3067 poll_wait(file, &s->dma_dac.wait, wait);
3069 if (file->f_mode & FMODE_READ) {
3070 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3072 "cs4281: cs4281_poll() wait on FMODE_READ\n"));
3073 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
3075 poll_wait(file, &s->dma_adc.wait, wait);
3077 spin_lock_irqsave(&s->lock, flags);
3078 cs4281_update_ptr(s,CS_FALSE);
3079 if (file->f_mode & FMODE_WRITE) {
3080 if (s->dma_dac.mapped) {
3081 if (s->dma_dac.count >=
3082 (signed) s->dma_dac.fragsize) {
3083 if (s->dma_dac.wakeup)
3084 mask |= POLLOUT | POLLWRNORM;
3087 s->dma_dac.wakeup = 0;
3090 if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count)
3091 mask |= POLLOUT | POLLWRNORM;
3093 } else if (file->f_mode & FMODE_READ) {
3094 if (s->dma_adc.mapped) {
3095 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
3096 mask |= POLLIN | POLLRDNORM;
3098 if (s->dma_adc.count > 0)
3099 mask |= POLLIN | POLLRDNORM;
3102 spin_unlock_irqrestore(&s->lock, flags);
3103 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3104 printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
3110 static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
3112 struct cs4281_state *s =
3113 (struct cs4281_state *) file->private_data;
3118 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3119 printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
3122 if (vma->vm_flags & VM_WRITE) {
3123 if ((ret = prog_dmabuf_dac(s)) != 0)
3126 } else if (vma->vm_flags & VM_READ) {
3127 if ((ret = prog_dmabuf_adc(s)) != 0)
3133 // only support PLAYBACK for now
3137 if (cs4x_pgoff(vma) != 0)
3139 size = vma->vm_end - vma->vm_start;
3140 if (size > (PAGE_SIZE << db->buforder))
3142 if (remap_page_range
3143 (vma, vma->vm_start, virt_to_phys(db->rawbuf), size,
3144 vma->vm_page_prot)) return -EAGAIN;
3147 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3148 printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
3155 static int cs4281_ioctl(struct inode *inode, struct file *file,
3156 unsigned int cmd, unsigned long arg)
3158 struct cs4281_state *s =
3159 (struct cs4281_state *) file->private_data;
3160 unsigned long flags;
3161 audio_buf_info abinfo;
3163 int val, mapped, ret;
3165 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
3166 "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd));
3171 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
3172 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
3174 case OSS_GETVERSION:
3175 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3176 "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
3178 return put_user(SOUND_VERSION, (int *) arg);
3180 case SNDCTL_DSP_SYNC:
3181 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3182 "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
3183 if (file->f_mode & FMODE_WRITE)
3185 0 /*file->f_flags & O_NONBLOCK */
3189 case SNDCTL_DSP_SETDUPLEX:
3192 case SNDCTL_DSP_GETCAPS:
3193 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
3194 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
3197 case SNDCTL_DSP_RESET:
3198 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3199 "cs4281: cs4281_ioctl(): DSP_RESET\n"));
3200 if (file->f_mode & FMODE_WRITE) {
3202 synchronize_irq(s->irq);
3203 s->dma_dac.swptr = s->dma_dac.hwptr =
3204 s->dma_dac.count = s->dma_dac.total_bytes =
3205 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
3206 prog_codec(s, CS_TYPE_DAC);
3208 if (file->f_mode & FMODE_READ) {
3210 synchronize_irq(s->irq);
3211 s->dma_adc.swptr = s->dma_adc.hwptr =
3212 s->dma_adc.count = s->dma_adc.total_bytes =
3213 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
3214 prog_codec(s, CS_TYPE_ADC);
3218 case SNDCTL_DSP_SPEED:
3219 if (get_user(val, (int *) arg))
3221 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3222 "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val));
3224 // support independent capture and playback channels
3225 // assume that the file mode bit determines the
3226 // direction of the data flow.
3228 if (file->f_mode & FMODE_READ) {
3231 s->dma_adc.ready = 0;
3232 // program sampling rates
3237 s->prop_adc.rate = val;
3238 prog_codec(s, CS_TYPE_ADC);
3241 if (file->f_mode & FMODE_WRITE) {
3244 s->dma_dac.ready = 0;
3245 // program sampling rates
3250 s->prop_dac.rate = val;
3251 prog_codec(s, CS_TYPE_DAC);
3255 if (file->f_mode & FMODE_WRITE)
3256 val = s->prop_dac.rate;
3257 else if (file->f_mode & FMODE_READ)
3258 val = s->prop_adc.rate;
3260 return put_user(val, (int *) arg);
3262 case SNDCTL_DSP_STEREO:
3263 if (get_user(val, (int *) arg))
3265 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3266 "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val));
3267 if (file->f_mode & FMODE_READ) {
3269 s->dma_adc.ready = 0;
3270 s->prop_adc.channels = val ? 2 : 1;
3271 prog_codec(s, CS_TYPE_ADC);
3273 if (file->f_mode & FMODE_WRITE) {
3275 s->dma_dac.ready = 0;
3276 s->prop_dac.channels = val ? 2 : 1;
3277 prog_codec(s, CS_TYPE_DAC);
3281 case SNDCTL_DSP_CHANNELS:
3282 if (get_user(val, (int *) arg))
3284 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3285 "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
3288 if (file->f_mode & FMODE_READ) {
3290 s->dma_adc.ready = 0;
3292 s->prop_adc.channels = 2;
3294 s->prop_adc.channels = 1;
3295 prog_codec(s, CS_TYPE_ADC);
3297 if (file->f_mode & FMODE_WRITE) {
3299 s->dma_dac.ready = 0;
3301 s->prop_dac.channels = 2;
3303 s->prop_dac.channels = 1;
3304 prog_codec(s, CS_TYPE_DAC);
3308 if (file->f_mode & FMODE_WRITE)
3309 val = s->prop_dac.channels;
3310 else if (file->f_mode & FMODE_READ)
3311 val = s->prop_adc.channels;
3313 return put_user(val, (int *) arg);
3315 case SNDCTL_DSP_GETFMTS: // Returns a mask
3316 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3317 "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
3318 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3320 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3321 AFMT_U8, (int *) arg);
3323 case SNDCTL_DSP_SETFMT:
3324 if (get_user(val, (int *) arg))
3326 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3327 "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
3329 if (val != AFMT_QUERY) {
3330 if (file->f_mode & FMODE_READ) {
3332 s->dma_adc.ready = 0;
3333 if (val != AFMT_S16_LE
3334 && val != AFMT_U16_LE && val != AFMT_S8
3337 s->prop_adc.fmt = val;
3338 s->prop_adc.fmt_original = s->prop_adc.fmt;
3339 prog_codec(s, CS_TYPE_ADC);
3341 if (file->f_mode & FMODE_WRITE) {
3343 s->dma_dac.ready = 0;
3344 if (val != AFMT_S16_LE
3345 && val != AFMT_U16_LE && val != AFMT_S8
3348 s->prop_dac.fmt = val;
3349 s->prop_dac.fmt_original = s->prop_dac.fmt;
3350 prog_codec(s, CS_TYPE_DAC);
3353 if (file->f_mode & FMODE_WRITE)
3354 val = s->prop_dac.fmt_original;
3355 else if (file->f_mode & FMODE_READ)
3356 val = s->prop_adc.fmt_original;
3358 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3359 "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n",
3361 return put_user(val, (int *) arg);
3363 case SNDCTL_DSP_POST:
3364 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3365 "cs4281: cs4281_ioctl(): DSP_POST\n"));
3368 case SNDCTL_DSP_GETTRIGGER:
3370 if (file->f_mode & s->ena & FMODE_READ)
3371 val |= PCM_ENABLE_INPUT;
3372 if (file->f_mode & s->ena & FMODE_WRITE)
3373 val |= PCM_ENABLE_OUTPUT;
3374 return put_user(val, (int *) arg);
3376 case SNDCTL_DSP_SETTRIGGER:
3377 if (get_user(val, (int *) arg))
3379 if (file->f_mode & FMODE_READ) {
3380 if (val & PCM_ENABLE_INPUT) {
3381 if (!s->dma_adc.ready
3382 && (ret = prog_dmabuf_adc(s)))
3388 if (file->f_mode & FMODE_WRITE) {
3389 if (val & PCM_ENABLE_OUTPUT) {
3390 if (!s->dma_dac.ready
3391 && (ret = prog_dmabuf_dac(s)))
3399 case SNDCTL_DSP_GETOSPACE:
3400 if (!(file->f_mode & FMODE_WRITE))
3402 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
3404 spin_lock_irqsave(&s->lock, flags);
3405 cs4281_update_ptr(s,CS_FALSE);
3406 abinfo.fragsize = s->dma_dac.fragsize;
3407 if (s->dma_dac.mapped)
3408 abinfo.bytes = s->dma_dac.dmasize;
3411 s->dma_dac.dmasize - s->dma_dac.count;
3412 abinfo.fragstotal = s->dma_dac.numfrag;
3413 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
3414 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
3415 "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
3416 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
3418 spin_unlock_irqrestore(&s->lock, flags);
3419 return copy_to_user((void *) arg, &abinfo,
3420 sizeof(abinfo)) ? -EFAULT : 0;
3422 case SNDCTL_DSP_GETISPACE:
3423 if (!(file->f_mode & FMODE_READ))
3425 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
3427 spin_lock_irqsave(&s->lock, flags);
3428 cs4281_update_ptr(s,CS_FALSE);
3429 if (s->conversion) {
3430 abinfo.fragsize = s->dma_adc.fragsize / 2;
3431 abinfo.bytes = s->dma_adc.count / 2;
3432 abinfo.fragstotal = s->dma_adc.numfrag;
3434 abinfo.bytes >> (s->dma_adc.fragshift - 1);
3436 abinfo.fragsize = s->dma_adc.fragsize;
3437 abinfo.bytes = s->dma_adc.count;
3438 abinfo.fragstotal = s->dma_adc.numfrag;
3440 abinfo.bytes >> s->dma_adc.fragshift;
3442 spin_unlock_irqrestore(&s->lock, flags);
3443 return copy_to_user((void *) arg, &abinfo,
3444 sizeof(abinfo)) ? -EFAULT : 0;
3446 case SNDCTL_DSP_NONBLOCK:
3447 file->f_flags |= O_NONBLOCK;
3450 case SNDCTL_DSP_GETODELAY:
3451 if (!(file->f_mode & FMODE_WRITE))
3453 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3455 spin_lock_irqsave(&s->lock, flags);
3456 cs4281_update_ptr(s,CS_FALSE);
3457 val = s->dma_dac.count;
3458 spin_unlock_irqrestore(&s->lock, flags);
3459 return put_user(val, (int *) arg);
3461 case SNDCTL_DSP_GETIPTR:
3462 if (!(file->f_mode & FMODE_READ))
3464 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3466 spin_lock_irqsave(&s->lock, flags);
3467 cs4281_update_ptr(s,CS_FALSE);
3468 cinfo.bytes = s->dma_adc.total_bytes;
3469 if (s->dma_adc.mapped) {
3471 (cinfo.bytes >> s->dma_adc.fragshift) -
3474 cinfo.bytes >> s->dma_adc.fragshift;
3476 if (s->conversion) {
3479 2 >> (s->dma_adc.fragshift - 1);
3482 s->dma_adc.count >> s->dma_adc.
3486 cinfo.ptr = s->dma_adc.hwptr / 2;
3488 cinfo.ptr = s->dma_adc.hwptr;
3489 if (s->dma_adc.mapped)
3490 s->dma_adc.count &= s->dma_adc.fragsize - 1;
3491 spin_unlock_irqrestore(&s->lock, flags);
3492 if (copy_to_user((void *) arg, &cinfo, sizeof(cinfo)))
3496 case SNDCTL_DSP_GETOPTR:
3497 if (!(file->f_mode & FMODE_WRITE))
3499 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3501 spin_lock_irqsave(&s->lock, flags);
3502 cs4281_update_ptr(s,CS_FALSE);
3503 cinfo.bytes = s->dma_dac.total_bytes;
3504 if (s->dma_dac.mapped) {
3506 (cinfo.bytes >> s->dma_dac.fragshift) -
3509 cinfo.bytes >> s->dma_dac.fragshift;
3512 s->dma_dac.count >> s->dma_dac.fragshift;
3514 cinfo.ptr = s->dma_dac.hwptr;
3515 if (s->dma_dac.mapped)
3516 s->dma_dac.count &= s->dma_dac.fragsize - 1;
3517 spin_unlock_irqrestore(&s->lock, flags);
3518 if (copy_to_user((void *) arg, &cinfo, sizeof(cinfo)))
3522 case SNDCTL_DSP_GETBLKSIZE:
3523 if (file->f_mode & FMODE_WRITE) {
3524 if ((val = prog_dmabuf_dac(s)))
3526 return put_user(s->dma_dac.fragsize, (int *) arg);
3528 if ((val = prog_dmabuf_adc(s)))
3531 return put_user(s->dma_adc.fragsize / 2,
3534 return put_user(s->dma_adc.fragsize, (int *) arg);
3536 case SNDCTL_DSP_SETFRAGMENT:
3537 if (get_user(val, (int *) arg))
3539 return 0; // Say OK, but do nothing.
3541 case SNDCTL_DSP_SUBDIVIDE:
3542 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
3543 || (file->f_mode & FMODE_WRITE
3544 && s->dma_dac.subdivision)) return -EINVAL;
3545 if (get_user(val, (int *) arg))
3547 if (val != 1 && val != 2 && val != 4)
3549 if (file->f_mode & FMODE_READ)
3550 s->dma_adc.subdivision = val;
3551 else if (file->f_mode & FMODE_WRITE)
3552 s->dma_dac.subdivision = val;
3555 case SOUND_PCM_READ_RATE:
3556 if (file->f_mode & FMODE_READ)
3557 return put_user(s->prop_adc.rate, (int *) arg);
3558 else if (file->f_mode & FMODE_WRITE)
3559 return put_user(s->prop_dac.rate, (int *) arg);
3561 case SOUND_PCM_READ_CHANNELS:
3562 if (file->f_mode & FMODE_READ)
3563 return put_user(s->prop_adc.channels, (int *) arg);
3564 else if (file->f_mode & FMODE_WRITE)
3565 return put_user(s->prop_dac.channels, (int *) arg);
3567 case SOUND_PCM_READ_BITS:
3568 if (file->f_mode & FMODE_READ)
3572 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3574 else if (file->f_mode & FMODE_WRITE)
3578 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3581 case SOUND_PCM_WRITE_FILTER:
3582 case SNDCTL_DSP_SETSYNCRO:
3583 case SOUND_PCM_READ_FILTER:
3586 return mixer_ioctl(s, cmd, arg);
3590 static int cs4281_release(struct inode *inode, struct file *file)
3592 struct cs4281_state *s =
3593 (struct cs4281_state *) file->private_data;
3595 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
3596 "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n",
3597 inode, file, file->f_mode));
3601 if (file->f_mode & FMODE_WRITE) {
3602 drain_dac(s, file->f_flags & O_NONBLOCK);
3603 down(&s->open_sem_dac);
3605 dealloc_dmabuf(s, &s->dma_dac);
3606 s->open_mode &= ~FMODE_WRITE;
3607 up(&s->open_sem_dac);
3608 wake_up(&s->open_wait_dac);
3610 if (file->f_mode & FMODE_READ) {
3611 drain_adc(s, file->f_flags & O_NONBLOCK);
3612 down(&s->open_sem_adc);
3614 dealloc_dmabuf(s, &s->dma_adc);
3615 s->open_mode &= ~FMODE_READ;
3616 up(&s->open_sem_adc);
3617 wake_up(&s->open_wait_adc);
3622 static int cs4281_open(struct inode *inode, struct file *file)
3624 unsigned int minor = iminor(inode);
3625 struct cs4281_state *s=NULL;
3626 struct list_head *entry;
3628 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3629 "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n",
3630 inode, file, file->f_mode));
3632 list_for_each(entry, &cs4281_devs)
3634 s = list_entry(entry, struct cs4281_state, list);
3636 if (!((s->dev_audio ^ minor) & ~0xf))
3639 if (entry == &cs4281_devs)
3642 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3643 "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3647 file->private_data = s;
3649 // wait for device to become free
3650 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3651 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
3652 "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3655 if (file->f_mode & FMODE_WRITE) {
3656 down(&s->open_sem_dac);
3657 while (s->open_mode & FMODE_WRITE) {
3658 if (file->f_flags & O_NONBLOCK) {
3659 up(&s->open_sem_dac);
3662 up(&s->open_sem_dac);
3663 interruptible_sleep_on(&s->open_wait_dac);
3665 if (signal_pending(current))
3666 return -ERESTARTSYS;
3667 down(&s->open_sem_dac);
3670 if (file->f_mode & FMODE_READ) {
3671 down(&s->open_sem_adc);
3672 while (s->open_mode & FMODE_READ) {
3673 if (file->f_flags & O_NONBLOCK) {
3674 up(&s->open_sem_adc);
3677 up(&s->open_sem_adc);
3678 interruptible_sleep_on(&s->open_wait_adc);
3680 if (signal_pending(current))
3681 return -ERESTARTSYS;
3682 down(&s->open_sem_adc);
3685 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3686 if (file->f_mode & FMODE_READ) {
3687 s->prop_adc.fmt = AFMT_U8;
3688 s->prop_adc.fmt_original = s->prop_adc.fmt;
3689 s->prop_adc.channels = 1;
3690 s->prop_adc.rate = 8000;
3691 s->prop_adc.clkdiv = 96 | 0x80;
3693 s->ena &= ~FMODE_READ;
3694 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3695 s->dma_adc.subdivision = 0;
3696 up(&s->open_sem_adc);
3698 if (prog_dmabuf_adc(s)) {
3699 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3700 "cs4281: adc Program dmabufs failed.\n"));
3701 cs4281_release(inode, file);
3704 prog_codec(s, CS_TYPE_ADC);
3706 if (file->f_mode & FMODE_WRITE) {
3707 s->prop_dac.fmt = AFMT_U8;
3708 s->prop_dac.fmt_original = s->prop_dac.fmt;
3709 s->prop_dac.channels = 1;
3710 s->prop_dac.rate = 8000;
3711 s->prop_dac.clkdiv = 96 | 0x80;
3713 s->ena &= ~FMODE_WRITE;
3714 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3715 s->dma_dac.subdivision = 0;
3716 up(&s->open_sem_dac);
3718 if (prog_dmabuf_dac(s)) {
3719 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3720 "cs4281: dac Program dmabufs failed.\n"));
3721 cs4281_release(inode, file);
3724 prog_codec(s, CS_TYPE_DAC);
3726 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3727 printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3732 // ******************************************************************************************
3733 // Wave (audio) file operations struct.
3734 // ******************************************************************************************
3735 static /*const */ struct file_operations cs4281_audio_fops = {
3736 .owner = THIS_MODULE,
3737 .llseek = no_llseek,
3738 .read = cs4281_read,
3739 .write = cs4281_write,
3740 .poll = cs4281_poll,
3741 .ioctl = cs4281_ioctl,
3742 .mmap = cs4281_mmap,
3743 .open = cs4281_open,
3744 .release = cs4281_release,
3747 // ---------------------------------------------------------------------
3749 // hold spinlock for the following!
3750 static void cs4281_handle_midi(struct cs4281_state *s)
3757 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3758 ch = readl(s->pBA0 + BA0_MIDRP);
3759 if (s->midi.icnt < MIDIINBUF) {
3760 s->midi.ibuf[s->midi.iwr] = ch;
3761 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3767 wake_up(&s->midi.iwait);
3769 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3770 temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3771 writel(temp1, s->pBA0 + BA0_MIDWP);
3772 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3774 if (s->midi.ocnt < MIDIOUTBUF - 16)
3778 wake_up(&s->midi.owait);
3783 static irqreturn_t cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3785 struct cs4281_state *s = (struct cs4281_state *) dev_id;
3788 // fastpath out, to ease interrupt sharing
3789 temp1 = readl(s->pBA0 + BA0_HISR); // Get Int Status reg.
3791 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3792 "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1));
3794 * If not DMA or MIDI interrupt, then just return.
3796 if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {
3797 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
3798 CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO
3799 "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3803 if (temp1 & HISR_DMA0) // If play interrupt,
3804 readl(s->pBA0 + BA0_HDSR0); // clear the source.
3806 if (temp1 & HISR_DMA1) // Same for play.
3807 readl(s->pBA0 + BA0_HDSR1);
3808 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Local EOI
3810 spin_lock(&s->lock);
3811 cs4281_update_ptr(s,CS_TRUE);
3812 cs4281_handle_midi(s);
3813 spin_unlock(&s->lock);
3817 // **************************************************************************
3819 static void cs4281_midi_timer(unsigned long data)
3821 struct cs4281_state *s = (struct cs4281_state *) data;
3822 unsigned long flags;
3824 spin_lock_irqsave(&s->lock, flags);
3825 cs4281_handle_midi(s);
3826 spin_unlock_irqrestore(&s->lock, flags);
3827 s->midi.timer.expires = jiffies + 1;
3828 add_timer(&s->midi.timer);
3832 // ---------------------------------------------------------------------
3834 static ssize_t cs4281_midi_read(struct file *file, char *buffer,
3835 size_t count, loff_t * ppos)
3837 struct cs4281_state *s =
3838 (struct cs4281_state *) file->private_data;
3840 unsigned long flags;
3845 if (ppos != &file->f_pos)
3847 if (!access_ok(VERIFY_WRITE, buffer, count))
3851 spin_lock_irqsave(&s->lock, flags);
3853 cnt = MIDIINBUF - ptr;
3854 if (s->midi.icnt < cnt)
3856 spin_unlock_irqrestore(&s->lock, flags);
3860 if (file->f_flags & O_NONBLOCK)
3861 return ret ? ret : -EAGAIN;
3862 interruptible_sleep_on(&s->midi.iwait);
3863 if (signal_pending(current))
3864 return ret ? ret : -ERESTARTSYS;
3867 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3868 return ret ? ret : -EFAULT;
3869 ptr = (ptr + cnt) % MIDIINBUF;
3870 spin_lock_irqsave(&s->lock, flags);
3872 s->midi.icnt -= cnt;
3873 spin_unlock_irqrestore(&s->lock, flags);
3882 static ssize_t cs4281_midi_write(struct file *file, const char *buffer,
3883 size_t count, loff_t * ppos)
3885 struct cs4281_state *s =
3886 (struct cs4281_state *) file->private_data;
3888 unsigned long flags;
3893 if (ppos != &file->f_pos)
3895 if (!access_ok(VERIFY_READ, buffer, count))
3899 spin_lock_irqsave(&s->lock, flags);
3901 cnt = MIDIOUTBUF - ptr;
3902 if (s->midi.ocnt + cnt > MIDIOUTBUF)
3903 cnt = MIDIOUTBUF - s->midi.ocnt;
3905 cs4281_handle_midi(s);
3906 spin_unlock_irqrestore(&s->lock, flags);
3910 if (file->f_flags & O_NONBLOCK)
3911 return ret ? ret : -EAGAIN;
3912 interruptible_sleep_on(&s->midi.owait);
3913 if (signal_pending(current))
3914 return ret ? ret : -ERESTARTSYS;
3917 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
3918 return ret ? ret : -EFAULT;
3919 ptr = (ptr + cnt) % MIDIOUTBUF;
3920 spin_lock_irqsave(&s->lock, flags);
3922 s->midi.ocnt += cnt;
3923 spin_unlock_irqrestore(&s->lock, flags);
3927 spin_lock_irqsave(&s->lock, flags);
3928 cs4281_handle_midi(s);
3929 spin_unlock_irqrestore(&s->lock, flags);
3935 static unsigned int cs4281_midi_poll(struct file *file,
3936 struct poll_table_struct *wait)
3938 struct cs4281_state *s =
3939 (struct cs4281_state *) file->private_data;
3940 unsigned long flags;
3941 unsigned int mask = 0;
3944 if (file->f_flags & FMODE_WRITE)
3945 poll_wait(file, &s->midi.owait, wait);
3946 if (file->f_flags & FMODE_READ)
3947 poll_wait(file, &s->midi.iwait, wait);
3948 spin_lock_irqsave(&s->lock, flags);
3949 if (file->f_flags & FMODE_READ) {
3950 if (s->midi.icnt > 0)
3951 mask |= POLLIN | POLLRDNORM;
3953 if (file->f_flags & FMODE_WRITE) {
3954 if (s->midi.ocnt < MIDIOUTBUF)
3955 mask |= POLLOUT | POLLWRNORM;
3957 spin_unlock_irqrestore(&s->lock, flags);
3962 static int cs4281_midi_open(struct inode *inode, struct file *file)
3964 unsigned long flags, temp1;
3965 unsigned int minor = iminor(inode);
3966 struct cs4281_state *s=NULL;
3967 struct list_head *entry;
3968 list_for_each(entry, &cs4281_devs)
3970 s = list_entry(entry, struct cs4281_state, list);
3972 if (s->dev_midi == minor)
3976 if (entry == &cs4281_devs)
3980 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3981 "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3985 file->private_data = s;
3986 // wait for device to become free
3988 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
3989 if (file->f_flags & O_NONBLOCK) {
3994 interruptible_sleep_on(&s->open_wait);
3995 if (signal_pending(current))
3996 return -ERESTARTSYS;
3999 spin_lock_irqsave(&s->lock, flags);
4000 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4001 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4002 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4003 writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
4004 writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
4005 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4006 writel(0x0000000f, s->pBA0 + BA0_MIDCR); // Enable transmit, record, ints.
4007 temp1 = readl(s->pBA0 + BA0_HIMR);
4008 writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
4009 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts
4010 init_timer(&s->midi.timer);
4011 s->midi.timer.expires = jiffies + 1;
4012 s->midi.timer.data = (unsigned long) s;
4013 s->midi.timer.function = cs4281_midi_timer;
4014 add_timer(&s->midi.timer);
4016 if (file->f_mode & FMODE_READ) {
4017 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4019 if (file->f_mode & FMODE_WRITE) {
4020 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4022 spin_unlock_irqrestore(&s->lock, flags);
4025 f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
4032 static int cs4281_midi_release(struct inode *inode, struct file *file)
4034 struct cs4281_state *s =
4035 (struct cs4281_state *) file->private_data;
4036 DECLARE_WAITQUEUE(wait, current);
4037 unsigned long flags;
4038 unsigned count, tmo;
4042 if (file->f_mode & FMODE_WRITE) {
4043 add_wait_queue(&s->midi.owait, &wait);
4045 set_current_state(TASK_INTERRUPTIBLE);
4046 spin_lock_irqsave(&s->lock, flags);
4047 count = s->midi.ocnt;
4048 spin_unlock_irqrestore(&s->lock, flags);
4051 if (signal_pending(current))
4053 if (file->f_flags & O_NONBLOCK) {
4054 remove_wait_queue(&s->midi.owait, &wait);
4055 current->state = TASK_RUNNING;
4058 tmo = (count * HZ) / 3100;
4059 if (!schedule_timeout(tmo ? : 1) && tmo)
4061 "cs4281: midi timed out??\n");
4063 remove_wait_queue(&s->midi.owait, &wait);
4064 current->state = TASK_RUNNING;
4068 (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
4070 spin_lock_irqsave(&s->lock, flags);
4071 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4072 writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.
4073 del_timer(&s->midi.timer);
4075 spin_unlock_irqrestore(&s->lock, flags);
4077 wake_up(&s->open_wait);
4081 // ******************************************************************************************
4082 // Midi file operations struct.
4083 // ******************************************************************************************
4084 static /*const */ struct file_operations cs4281_midi_fops = {
4085 .owner = THIS_MODULE,
4086 .llseek = no_llseek,
4087 .read = cs4281_midi_read,
4088 .write = cs4281_midi_write,
4089 .poll = cs4281_midi_poll,
4090 .open = cs4281_midi_open,
4091 .release = cs4281_midi_release,
4095 // ---------------------------------------------------------------------
4097 // maximum number of devices
4098 #define NR_DEVICE 8 // Only eight devices supported currently.
4100 // ---------------------------------------------------------------------
4102 static struct initvol {
4105 } initvol[] __initdata = {
4108 SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
4109 SOUND_MIXER_WRITE_PCM, 0x4040}, {
4110 SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
4111 SOUND_MIXER_WRITE_CD, 0x4040}, {
4112 SOUND_MIXER_WRITE_LINE, 0x4040}, {
4113 SOUND_MIXER_WRITE_LINE1, 0x4040}, {
4114 SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
4115 SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
4116 SOUND_MIXER_WRITE_MIC, 0x0000}
4120 #ifndef NOT_CS4281_PM
4121 void __devinit cs4281_BuildFIFO(
4122 struct cs4281_pipeline *p,
4123 struct cs4281_state *s)
4127 case 0: /* playback */
4129 p->u32FCRnAddress = BA0_FCR0;
4130 p->u32FSICnAddress = BA0_FSIC0;
4131 p->u32FPDRnAddress = BA0_FPDR0;
4134 case 1: /* capture */
4136 p->u32FCRnAddress = BA0_FCR1;
4137 p->u32FSICnAddress = BA0_FSIC1;
4138 p->u32FPDRnAddress = BA0_FPDR1;
4144 p->u32FCRnAddress = BA0_FCR2;
4145 p->u32FSICnAddress = BA0_FSIC2;
4146 p->u32FPDRnAddress = BA0_FPDR2;
4151 p->u32FCRnAddress = BA0_FCR3;
4152 p->u32FSICnAddress = BA0_FSIC3;
4153 p->u32FPDRnAddress = BA0_FPDR3;
4160 // first read the hardware to initialize the member variables
4162 p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress);
4163 p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress);
4164 p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress);
4168 void __devinit cs4281_BuildDMAengine(
4169 struct cs4281_pipeline *p,
4170 struct cs4281_state *s)
4173 * initialize all the addresses of this pipeline dma info.
4177 case 0: /* playback */
4179 p->u32DBAnAddress = BA0_DBA0;
4180 p->u32DCAnAddress = BA0_DCA0;
4181 p->u32DBCnAddress = BA0_DBC0;
4182 p->u32DCCnAddress = BA0_DCC0;
4183 p->u32DMRnAddress = BA0_DMR0;
4184 p->u32DCRnAddress = BA0_DCR0;
4185 p->u32HDSRnAddress = BA0_HDSR0;
4189 case 1: /* capture */
4191 p->u32DBAnAddress = BA0_DBA1;
4192 p->u32DCAnAddress = BA0_DCA1;
4193 p->u32DBCnAddress = BA0_DBC1;
4194 p->u32DCCnAddress = BA0_DCC1;
4195 p->u32DMRnAddress = BA0_DMR1;
4196 p->u32DCRnAddress = BA0_DCR1;
4197 p->u32HDSRnAddress = BA0_HDSR1;
4203 p->u32DBAnAddress = BA0_DBA2;
4204 p->u32DCAnAddress = BA0_DCA2;
4205 p->u32DBCnAddress = BA0_DBC2;
4206 p->u32DCCnAddress = BA0_DCC2;
4207 p->u32DMRnAddress = BA0_DMR2;
4208 p->u32DCRnAddress = BA0_DCR2;
4209 p->u32HDSRnAddress = BA0_HDSR2;
4215 p->u32DBAnAddress = BA0_DBA3;
4216 p->u32DCAnAddress = BA0_DCA3;
4217 p->u32DBCnAddress = BA0_DBC3;
4218 p->u32DCCnAddress = BA0_DCC3;
4219 p->u32DMRnAddress = BA0_DMR3;
4220 p->u32DCRnAddress = BA0_DCR3;
4221 p->u32HDSRnAddress = BA0_HDSR3;
4229 // Initialize the dma values for this pipeline
4231 p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress);
4232 p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress);
4233 p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress);
4234 p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress);
4238 void __devinit cs4281_InitPM(struct cs4281_state *s)
4241 struct cs4281_pipeline *p;
4243 for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
4247 cs4281_BuildDMAengine(p,s);
4248 cs4281_BuildFIFO(p,s);
4250 * currently only 2 pipelines are used
4251 * so, only set the valid bit on the playback and capture.
4253 if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) ||
4254 (i == CS4281_CAPTURE_PIPELINE_NUMBER))
4255 p->flags |= CS4281_PIPELINE_VALID;
4257 s->pm.u32SSPM_BITS = 0x7e; /* rev c, use 0x7c for rev a or b */
4261 static int __devinit cs4281_probe(struct pci_dev *pcidev,
4262 const struct pci_device_id *pciid)
4264 #ifndef NOT_CS4281_PM
4265 struct pm_dev *pmdev;
4267 struct cs4281_state *s;
4268 dma_addr_t dma_mask;
4271 unsigned int temp1, temp2;
4273 CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
4274 printk(KERN_INFO "cs4281: probe()+\n"));
4276 if (pci_enable_device(pcidev)) {
4277 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4278 "cs4281: pci_enable_device() failed\n"));
4281 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) ||
4282 !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) {
4283 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4284 "cs4281: probe()- Memory region not assigned\n"));
4287 if (pcidev->irq == 0) {
4288 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4289 "cs4281: probe() IRQ not assigned\n"));
4292 dma_mask = 0xffffffff; /* this enables playback and recording */
4293 i = pci_set_dma_mask(pcidev, dma_mask);
4295 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4296 "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
4299 if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
4300 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4301 "cs4281: probe() no memory for state struct.\n"));
4304 memset(s, 0, sizeof(struct cs4281_state));
4305 init_waitqueue_head(&s->dma_adc.wait);
4306 init_waitqueue_head(&s->dma_dac.wait);
4307 init_waitqueue_head(&s->open_wait);
4308 init_waitqueue_head(&s->open_wait_adc);
4309 init_waitqueue_head(&s->open_wait_dac);
4310 init_waitqueue_head(&s->midi.iwait);
4311 init_waitqueue_head(&s->midi.owait);
4312 init_MUTEX(&s->open_sem);
4313 init_MUTEX(&s->open_sem_adc);
4314 init_MUTEX(&s->open_sem_dac);
4315 spin_lock_init(&s->lock);
4316 s->pBA0phys = pci_resource_start(pcidev, 0);
4317 s->pBA1phys = pci_resource_start(pcidev, 1);
4319 /* Convert phys to linear. */
4320 s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);
4322 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4323 "cs4281: BA0 I/O mapping failed. Skipping part.\n"));
4326 s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);
4328 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4329 "cs4281: BA1 I/O mapping failed. Skipping part.\n"));
4333 temp1 = readl(s->pBA0 + BA0_PCICFG00);
4334 temp2 = readl(s->pBA0 + BA0_PCICFG04);
4336 CS_DBGOUT(CS_INIT, 2,
4338 "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n",
4339 (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1));
4340 CS_DBGOUT(CS_INIT, 2,
4342 "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
4343 (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
4345 #ifndef NOT_CS4281_PM
4346 s->pm.flags = CS4281_PM_IDLE;
4348 temp1 = cs4281_hw_init(s);
4350 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4351 "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
4354 s->magic = CS4281_MAGIC;
4356 s->irq = pcidev->irq;
4358 (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
4359 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
4360 printk(KERN_ERR "cs4281: irq %u in use\n", s->irq));
4363 if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
4365 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4366 "cs4281: probe() register_sound_dsp() failed.\n"));
4369 if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
4371 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4372 "cs4281: probe() register_sound_mixer() failed.\n"));
4375 if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
4376 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4377 "cs4281: probe() register_sound_midi() failed.\n"));
4380 #ifndef NOT_CS4281_PM
4382 pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback);
4385 CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO
4386 "cs4281: probe() pm_register() succeeded (%p).\n", pmdev));
4391 CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO
4392 "cs4281: probe() pm_register() failed (%p).\n", pmdev));
4393 s->pm.flags |= CS4281_PM_NOT_REGISTERED;
4397 pci_set_master(pcidev); // enable bus mastering
4401 val = SOUND_MASK_LINE;
4402 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
4403 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
4404 val = initvol[i].vol;
4405 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
4407 val = 1; // enable mic preamp
4408 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
4411 pci_set_drvdata(pcidev, s);
4412 list_add(&s->list, &cs4281_devs);
4413 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4414 "cs4281: probe()- device allocated successfully\n"));
4418 unregister_sound_mixer(s->dev_mixer);
4420 unregister_sound_dsp(s->dev_audio);
4422 free_irq(s->irq, s);
4430 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
4431 "cs4281: probe()- no device allocated\n"));
4436 // ---------------------------------------------------------------------
4438 static void __devexit cs4281_remove(struct pci_dev *pci_dev)
4440 struct cs4281_state *s = pci_get_drvdata(pci_dev);
4441 // stop DMA controller
4442 synchronize_irq(s->irq);
4443 free_irq(s->irq, s);
4444 unregister_sound_dsp(s->dev_audio);
4445 unregister_sound_mixer(s->dev_mixer);
4446 unregister_sound_midi(s->dev_midi);
4449 pci_set_drvdata(pci_dev,NULL);
4452 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4453 "cs4281: cs4281_remove()-: remove successful\n"));
4456 static struct pci_device_id cs4281_pci_tbl[] = {
4458 .vendor = PCI_VENDOR_ID_CIRRUS,
4459 .device = PCI_DEVICE_ID_CRYSTAL_CS4281,
4460 .subvendor = PCI_ANY_ID,
4461 .subdevice = PCI_ANY_ID,
4466 MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl);
4468 struct pci_driver cs4281_pci_driver = {
4470 .id_table = cs4281_pci_tbl,
4471 .probe = cs4281_probe,
4472 .remove = __devexit_p(cs4281_remove),
4473 .suspend = CS4281_SUSPEND_TBL,
4474 .resume = CS4281_RESUME_TBL,
4477 int __init cs4281_init_module(void)
4480 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4481 "cs4281: cs4281_init_module()+ \n"));
4482 printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
4483 __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
4485 rtn = pci_module_init(&cs4281_pci_driver);
4487 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4488 printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn));
4492 void __exit cs4281_cleanup_module(void)
4494 pci_unregister_driver(&cs4281_pci_driver);
4495 #ifndef NOT_CS4281_PM
4496 cs_pm_unregister_all(cs4281_pm_callback);
4498 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4499 printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
4501 // ---------------------------------------------------------------------
4503 MODULE_AUTHOR("gw boynton, audio@crystal.cirrus.com");
4504 MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
4505 MODULE_LICENSE("GPL");
4507 // ---------------------------------------------------------------------
4509 module_init(cs4281_init_module);
4510 module_exit(cs4281_cleanup_module);
4513 int __init init_cs4281(void)
4515 return cs4281_init_module();