2 * Driver for HAL2 sound processors
3 * Copyright (c) 2001, 2002 Ladislav Michl <ladis@psi.cz>
5 * Based on Ulf Carlsson's code.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * /dev/dsp standard dsp device, (mostly) OSS compatible
22 * /dev/mixer standard mixer device, (mostly) OSS compatible
25 * + Driver currently supports indigo mode only.
26 * + Recording doesn't work. I guess that it is caused by PBUS channel
27 * misconfiguration, but until I get relevant info I'm unable to fix it.
30 #include <linux/module.h>
31 #include <linux/sched.h>
32 #include <linux/init.h>
33 #include <linux/slab.h>
34 #include <linux/poll.h>
35 #include <linux/sound.h>
36 #include <linux/soundcard.h>
38 #include <asm/uaccess.h>
39 #include <asm/sgi/sgint23.h>
44 #define DEBUG(args...) printk(args)
46 #define DEBUG(args...)
50 #define DEBUG_MIX(args...) printk(args)
52 #define DEBUG_MIX(args...)
55 #define H2_INDIRECT_WAIT(regs) while (regs->isr & H2_ISR_TSTATUS);
57 #define H2_READ_ADDR(addr) (addr | (1<<7))
58 #define H2_WRITE_ADDR(addr) (addr)
60 static char *hal2str = "HAL2 audio";
61 static int ibuffers = 32;
62 static int obuffers = 32;
64 /* I doubt anyone has a machine with two HAL2 cards. It's possible to
65 * have two HPC's, so it is probably possible to have two HAL2 cards.
66 * Try to deal with it, but note that it is not tested.
69 static hal2_card_t* hal2_card[MAXCARDS];
72 unsigned char idx:4, avail:1;
73 } mixtable[SOUND_MIXER_NRDEVICES] = {
74 [SOUND_MIXER_PCM] = { H2_MIX_OUTPUT_ATT, 1 }, /* voice */
75 [SOUND_MIXER_MIC] = { H2_MIX_INPUT_GAIN, 1 }, /* mic */
78 #define H2_SUPPORTED_FORMATS (AFMT_S16_LE | AFMT_S16_BE)
80 static inline void hal2_isr_write(hal2_card_t *hal2, u32 val)
82 hal2->ctl_regs->isr = val;
85 static inline u32 hal2_isr_look(hal2_card_t *hal2)
87 return hal2->ctl_regs->isr;
90 static inline u32 hal2_rev_look(hal2_card_t *hal2)
92 return hal2->ctl_regs->rev;
96 static u16 hal2_i_look16(hal2_card_t *hal2, u32 addr)
98 hal2_ctl_regs_t *regs = hal2->ctl_regs;
100 regs->iar = H2_READ_ADDR(addr);
101 H2_INDIRECT_WAIT(regs);
102 return (regs->idr0 & 0xffff);
106 static u32 hal2_i_look32(hal2_card_t *hal2, u32 addr)
109 hal2_ctl_regs_t *regs = hal2->ctl_regs;
111 regs->iar = H2_READ_ADDR(addr);
112 H2_INDIRECT_WAIT(regs);
113 ret = regs->idr0 & 0xffff;
114 regs->iar = H2_READ_ADDR(addr | 0x1);
115 H2_INDIRECT_WAIT(regs);
116 ret |= (regs->idr0 & 0xffff) << 16;
120 static void hal2_i_write16(hal2_card_t *hal2, u32 addr, u16 val)
122 hal2_ctl_regs_t *regs = hal2->ctl_regs;
128 regs->iar = H2_WRITE_ADDR(addr);
129 H2_INDIRECT_WAIT(regs);
132 static void hal2_i_write32(hal2_card_t *hal2, u32 addr, u32 val)
134 hal2_ctl_regs_t *regs = hal2->ctl_regs;
136 regs->idr0 = val & 0xffff;
137 regs->idr1 = val >> 16;
140 regs->iar = H2_WRITE_ADDR(addr);
141 H2_INDIRECT_WAIT(regs);
144 static void hal2_i_setbit16(hal2_card_t *hal2, u32 addr, u16 bit)
146 hal2_ctl_regs_t *regs = hal2->ctl_regs;
148 regs->iar = H2_READ_ADDR(addr);
149 H2_INDIRECT_WAIT(regs);
150 regs->idr0 = regs->idr0 | bit;
154 regs->iar = H2_WRITE_ADDR(addr);
155 H2_INDIRECT_WAIT(regs);
158 static void hal2_i_setbit32(hal2_card_t *hal2, u32 addr, u32 bit)
161 hal2_ctl_regs_t *regs = hal2->ctl_regs;
163 regs->iar = H2_READ_ADDR(addr);
164 H2_INDIRECT_WAIT(regs);
165 tmp = regs->idr0 | (regs->idr1 << 16) | bit;
166 regs->idr0 = tmp & 0xffff;
167 regs->idr1 = tmp >> 16;
170 regs->iar = H2_WRITE_ADDR(addr);
171 H2_INDIRECT_WAIT(regs);
174 static void hal2_i_clearbit16(hal2_card_t *hal2, u32 addr, u16 bit)
176 hal2_ctl_regs_t *regs = hal2->ctl_regs;
178 regs->iar = H2_READ_ADDR(addr);
179 H2_INDIRECT_WAIT(regs);
180 regs->idr0 = regs->idr0 & ~bit;
184 regs->iar = H2_WRITE_ADDR(addr);
185 H2_INDIRECT_WAIT(regs);
189 static void hal2_i_clearbit32(hal2_card_t *hal2, u32 addr, u32 bit)
192 hal2_ctl_regs_t *regs = hal2->ctl_regs;
194 regs->iar = H2_READ_ADDR(addr);
195 H2_INDIRECT_WAIT(regs);
196 tmp = (regs->idr0 | (regs->idr1 << 16)) & ~bit;
197 regs->idr0 = tmp & 0xffff;
198 regs->idr1 = tmp >> 16;
201 regs->iar = H2_WRITE_ADDR(addr);
202 H2_INDIRECT_WAIT(regs);
207 static void hal2_dump_regs(hal2_card_t *hal2)
209 printk("isr: %08hx ", hal2_isr_look(hal2));
210 printk("rev: %08hx\n", hal2_rev_look(hal2));
211 printk("relay: %04hx\n", hal2_i_look16(hal2, H2I_RELAY_C));
212 printk("port en: %04hx ", hal2_i_look16(hal2, H2I_DMA_PORT_EN));
213 printk("dma end: %04hx ", hal2_i_look16(hal2, H2I_DMA_END));
214 printk("dma drv: %04hx\n", hal2_i_look16(hal2, H2I_DMA_DRV));
215 printk("syn ctl: %04hx ", hal2_i_look16(hal2, H2I_SYNTH_C));
216 printk("aesrx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESRX_C));
217 printk("aestx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESTX_C));
218 printk("dac ctl1: %04hx ", hal2_i_look16(hal2, H2I_ADC_C1));
219 printk("dac ctl2: %08lx ", hal2_i_look32(hal2, H2I_ADC_C2));
220 printk("adc ctl1: %04hx ", hal2_i_look16(hal2, H2I_DAC_C1));
221 printk("adc ctl2: %08lx ", hal2_i_look32(hal2, H2I_DAC_C2));
222 printk("syn map: %04hx\n", hal2_i_look16(hal2, H2I_SYNTH_MAP_C));
223 printk("bres1 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES1_C1));
224 printk("bres1 ctl2: %04lx ", hal2_i_look32(hal2, H2I_BRES1_C2));
225 printk("bres2 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES2_C1));
226 printk("bres2 ctl2: %04lx ", hal2_i_look32(hal2, H2I_BRES2_C2));
227 printk("bres3 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES3_C1));
228 printk("bres3 ctl2: %04lx\n", hal2_i_look32(hal2, H2I_BRES3_C2));
232 static hal2_card_t* hal2_dsp_find_card(int minor)
236 for (i = 0; i < MAXCARDS; i++)
237 if (hal2_card[i] != NULL && hal2_card[i]->dev_dsp == minor)
242 static hal2_card_t* hal2_mixer_find_card(int minor)
246 for (i = 0; i < MAXCARDS; i++)
247 if (hal2_card[i] != NULL && hal2_card[i]->dev_mixer == minor)
253 static void hal2_dac_interrupt(hal2_codec_t *dac)
257 spin_lock(&dac->lock);
259 /* if tail buffer contains zero samples DMA stream was already
261 running = dac->tail->info.cnt;
262 dac->tail->info.cnt = 0;
263 dac->tail->info.desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX;
264 dma_cache_wback_inv((unsigned long) dac->tail,
265 sizeof(struct hpc_dma_desc));
266 /* we just proccessed empty buffer, don't update tail pointer */
268 dac->tail = dac->tail->info.next;
270 spin_unlock(&dac->lock);
272 wake_up(&dac->dma_wait);
275 static void hal2_adc_interrupt(hal2_codec_t *adc)
279 spin_lock(&adc->lock);
281 /* if head buffer contains nonzero samples DMA stream was already
283 running = !adc->head->info.cnt;
284 adc->head->info.cnt = H2_BUFFER_SIZE;
285 adc->head->info.desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX;
286 dma_cache_wback_inv((unsigned long) adc->head,
287 sizeof(struct hpc_dma_desc));
288 /* we just proccessed empty buffer, don't update head pointer */
290 dma_cache_inv((unsigned long) adc->head->data, H2_BUFFER_SIZE);
291 adc->head = adc->head->info.next;
294 spin_unlock(&adc->lock);
296 wake_up(&adc->dma_wait);
299 static irqreturn_t hal2_interrupt(int irq, void *dev_id, struct pt_regs *regs)
301 hal2_card_t *hal2 = (hal2_card_t*)dev_id;
303 /* decide what caused this interrupt */
304 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT)
305 hal2_dac_interrupt(&hal2->dac);
306 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT)
307 hal2_adc_interrupt(&hal2->adc);
311 static int hal2_compute_rate(hal2_codec_t *codec, unsigned int rate)
315 /* We default to 44.1 kHz and if it isn't possible to fall back to
316 * 48.0 kHz with the needed adjustments of real_rate.
319 DEBUG("rate: %d\n", rate);
321 /* Refer to CS4216 data sheet */
327 /* Note: This is NOT the way they set up the bresenham clock generators
328 * in the specification. I've tried to implement that method but it
329 * doesn't work. It's probably another silly bug in the spec.
331 * I accidently discovered this method while I was testing and it seems
332 * to work very well with all frequencies, and thee shall follow rule #1
336 if (44100 % rate == 0) {
338 if (inc < 1) inc = 1;
339 codec->master = 44100;
342 if (inc < 1) inc = 1;
344 codec->master = 48000;
349 DEBUG("real_rate: %d\n", rate);
354 static void hal2_set_dac_rate(hal2_card_t *hal2)
356 unsigned int master = hal2->dac.master;
357 int inc = hal2->dac.inc;
358 int mod = hal2->dac.mod;
360 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
362 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
363 hal2_i_write32(hal2, H2I_BRES1_C2, ((0xffff & (mod - inc - 1)) << 16) | 1);
366 static void hal2_set_adc_rate(hal2_card_t *hal2)
368 unsigned int master = hal2->adc.master;
369 int inc = hal2->adc.inc;
370 int mod = hal2->adc.mod;
372 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
374 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
375 hal2_i_write32(hal2, H2I_BRES2_C2, ((0xffff & (mod - inc - 1)) << 16) | 1);
378 static void hal2_setup_dac(hal2_card_t *hal2)
380 unsigned int fifobeg, fifoend, highwater, sample_size;
381 hal2_pbus_t *pbus = &hal2->dac.pbus;
383 DEBUG("hal2_setup_dac\n");
385 /* Now we set up some PBUS information. The PBUS needs information about
386 * what portion of the fifo it will use. If it's receiving or
387 * transmitting, and finally whether the stream is little endian or big
388 * endian. The information is written later, on the start call.
390 sample_size = 2 * hal2->dac.voices;
392 /* Fifo should be set to hold exactly four samples. Highwater mark
393 * should be set to two samples. */
394 highwater = (sample_size * 2) >> 1; /* halfwords */
395 fifobeg = 0; /* playback is first */
396 fifoend = (sample_size * 4) >> 3; /* doublewords */
397 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
398 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
399 /* We disable everything before we do anything at all */
400 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
401 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
402 hal2_i_clearbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
403 /* Setup the HAL2 for playback */
404 hal2_set_dac_rate(hal2);
405 /* We are using 1st Bresenham clock generator for playback */
406 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
407 | (1 << H2I_C1_CLKID_SHIFT)
408 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
411 static void hal2_setup_adc(hal2_card_t *hal2)
413 unsigned int fifobeg, fifoend, highwater, sample_size;
414 hal2_pbus_t *pbus = &hal2->adc.pbus;
416 DEBUG("hal2_setup_adc\n");
418 sample_size = 2 * hal2->adc.voices;
420 highwater = (sample_size * 2) >> 1; /* halfwords */
421 fifobeg = (4 * 4) >> 3; /* record is second */
422 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
423 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
424 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
425 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
426 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
427 hal2_i_clearbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
428 /* Setup the HAL2 for record */
429 hal2_set_adc_rate(hal2);
430 /* We are using 2nd Bresenham clock generator for record */
431 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
432 | (2 << H2I_C1_CLKID_SHIFT)
433 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
436 static void hal2_start_dac(hal2_card_t *hal2)
438 hal2_pbus_t *pbus = &hal2->dac.pbus;
440 DEBUG("hal2_start_dac\n");
442 pbus->pbus->pbdma_dptr = PHYSADDR(hal2->dac.tail);
443 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
446 if (hal2->dac.format & AFMT_S16_LE)
447 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
449 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
451 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
453 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
456 static void hal2_start_adc(hal2_card_t *hal2)
458 hal2_pbus_t *pbus = &hal2->adc.pbus;
460 DEBUG("hal2_start_adc\n");
462 pbus->pbus->pbdma_dptr = PHYSADDR(hal2->adc.head);
463 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
466 if (hal2->adc.format & AFMT_S16_LE)
467 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
469 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
471 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
473 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
476 static inline void hal2_stop_dac(hal2_card_t *hal2)
478 DEBUG("hal2_stop_dac\n");
480 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
481 /* The HAL2 itself may remain enabled safely */
484 static inline void hal2_stop_adc(hal2_card_t *hal2)
486 DEBUG("hal2_stop_adc\n");
488 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
491 #define hal2_alloc_dac_dmabuf(hal2) hal2_alloc_dmabuf(hal2, 1)
492 #define hal2_alloc_adc_dmabuf(hal2) hal2_alloc_dmabuf(hal2, 0)
493 static int hal2_alloc_dmabuf(hal2_card_t *hal2, int is_dac)
495 int buffers, cntinfo;
496 hal2_buf_t *buf, *prev;
502 cntinfo = HPCDMA_XIE | HPCDMA_EOX;
506 cntinfo = HPCDMA_XIE | H2_BUFFER_SIZE;
509 DEBUG("allocating %d DMA buffers.\n", buffers);
511 buf = (hal2_buf_t*) get_zeroed_page(GFP_KERNEL);
518 buf->info.desc.pbuf = PHYSADDR(&buf->data);
519 buf->info.desc.cntinfo = cntinfo;
522 buf = (hal2_buf_t*) get_zeroed_page(GFP_KERNEL);
524 printk("HAL2: Not enough memory for DMA buffer.\n");
528 free_page((unsigned long) buf);
529 buf = prev->info.next;
533 prev->info.next = buf;
534 prev->info.desc.pnext = PHYSADDR(buf);
535 /* The PBUS can prolly not read this stuff when it's in
536 * the cache so we have to flush it back to main memory
538 dma_cache_wback_inv((unsigned long) prev, PAGE_SIZE);
540 buf->info.desc.pbuf = PHYSADDR(&buf->data);
541 buf->info.desc.cntinfo = cntinfo;
543 buf->info.next = codec->head;
544 buf->info.desc.pnext = PHYSADDR(codec->head);
545 dma_cache_wback_inv((unsigned long) buf, PAGE_SIZE);
550 #define hal2_free_dac_dmabuf(hal2) hal2_free_dmabuf(hal2, 1)
551 #define hal2_free_adc_dmabuf(hal2) hal2_free_dmabuf(hal2, 0)
552 static void hal2_free_dmabuf(hal2_card_t *hal2, int is_dac)
554 hal2_buf_t *buf, *next;
555 hal2_codec_t *codec = (is_dac) ? &hal2->dac : &hal2->adc;
560 buf = codec->head->info.next;
561 codec->head->info.next = NULL;
563 next = buf->info.next;
564 free_page((unsigned long) buf);
567 codec->head = codec->tail = NULL;
571 * Add 'count' bytes to 'buffer' from DMA ring buffers. Return number of
572 * bytes added or -EFAULT if copy_from_user failed.
574 static int hal2_get_buffer(hal2_card_t *hal2, char *buffer, int count)
578 hal2_codec_t *adc = &hal2->adc;
580 spin_lock_irqsave(&adc->lock, flags);
582 DEBUG("getting %d bytes ", count);
584 /* enable DMA stream if there are no data */
585 if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) &&
586 adc->tail->info.cnt == 0)
587 hal2_start_adc(hal2);
591 while (adc->tail->info.cnt > 0 && count > 0) {
592 size = min(adc->tail->info.cnt, count);
593 spin_unlock_irqrestore(&adc->lock, flags);
595 if (copy_to_user(buffer, &adc->tail->data[H2_BUFFER_SIZE-size],
601 spin_lock_irqsave(&adc->lock, flags);
603 adc->tail->info.cnt -= size;
604 /* buffer is empty, update tail pointer */
605 if (adc->tail->info.cnt == 0) {
606 adc->tail->info.desc.cntinfo = HPCDMA_XIE |
608 dma_cache_wback_inv((unsigned long) adc->tail,
609 sizeof(struct hpc_dma_desc));
610 adc->tail = adc->tail->info.next;
611 /* enable DMA stream again if needed */
612 if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
613 hal2_start_adc(hal2);
620 DEBUG("(%d) ", size);
622 spin_unlock_irqrestore(&adc->lock, flags);
630 * Add 'count' bytes from 'buffer' to DMA ring buffers. Return number of
631 * bytes added or -EFAULT if copy_from_user failed.
633 static int hal2_add_buffer(hal2_card_t *hal2, char *buffer, int count)
637 hal2_codec_t *dac = &hal2->dac;
639 spin_lock_irqsave(&dac->lock, flags);
641 DEBUG("adding %d bytes ", count);
643 while (dac->head->info.cnt == 0 && count > 0) {
644 size = min((int)H2_BUFFER_SIZE, count);
645 spin_unlock_irqrestore(&dac->lock, flags);
647 if (copy_from_user(dac->head->data, buffer, size)) {
651 spin_lock_irqsave(&dac->lock, flags);
653 dac->head->info.desc.cntinfo = size | HPCDMA_XIE;
654 dac->head->info.cnt = size;
655 dma_cache_wback_inv((unsigned long) dac->head,
656 size + PAGE_SIZE - H2_BUFFER_SIZE);
660 dac->head = dac->head->info.next;
662 DEBUG("(%d) ", size);
664 if (!(dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) && ret > 0)
665 hal2_start_dac(hal2);
667 spin_unlock_irqrestore(&dac->lock, flags);
674 #define hal2_reset_dac_pointer(hal2) hal2_reset_pointer(hal2, 1)
675 #define hal2_reset_adc_pointer(hal2) hal2_reset_pointer(hal2, 0)
676 static void hal2_reset_pointer(hal2_card_t *hal2, int is_dac)
678 hal2_codec_t *codec = (is_dac) ? &hal2->dac : &hal2->adc;
680 DEBUG("hal2_reset_pointer\n");
682 codec->tail = codec->head;
684 codec->tail->info.desc.cntinfo = HPCDMA_XIE | (is_dac) ?
685 HPCDMA_EOX : H2_BUFFER_SIZE;
686 codec->tail->info.cnt = 0;
687 dma_cache_wback_inv((unsigned long) codec->tail,
688 sizeof(struct hpc_dma_desc));
689 codec->tail = codec->tail->info.next;
690 } while (codec->tail != codec->head);
693 static int hal2_sync_dac(hal2_card_t *hal2)
695 DECLARE_WAITQUEUE(wait, current);
696 hal2_codec_t *dac = &hal2->dac;
698 signed long timeout = 1000 * H2_BUFFER_SIZE * 2 * dac->voices *
699 HZ / dac->sample_rate / 900;
703 while (dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) {
704 add_wait_queue(&dac->dma_wait, &wait);
705 set_current_state(TASK_INTERRUPTIBLE);
706 if (!schedule_timeout(timeout))
707 /* We may get bogus timeout when system is
709 if (dac->tail->info.cnt) {
710 printk("HAL2: timeout...\n");
713 if (signal_pending(current))
717 hal2_reset_dac_pointer(hal2);
719 remove_wait_queue(&dac->dma_wait, &wait);
727 static int hal2_write_mixer(hal2_card_t *hal2, int index, int vol)
731 DEBUG_MIX("mixer %d write\n", index);
733 if (index >= SOUND_MIXER_NRDEVICES || !mixtable[index].avail)
736 r = (vol >> 8) & 0xff;
743 hal2->mixer.volume[mixtable[index].idx] = l | (r << 8);
745 switch (mixtable[index].idx) {
746 case H2_MIX_OUTPUT_ATT: {
748 DEBUG_MIX("output attenuator %d,%d\n", l, r);
751 unsigned int tmp = hal2_i_look32(hal2, H2I_DAC_C2);
753 tmp &= ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
755 /* Attenuator has five bits */
756 l = (31 * (100 - l) / 99);
757 r = (31 * (100 - r) / 99);
759 DEBUG_MIX("left: %d, right %d\n", l, r);
761 tmp |= (l << H2I_C2_L_ATT_SHIFT) & H2I_C2_L_ATT_M;
762 tmp |= (r << H2I_C2_R_ATT_SHIFT) & H2I_C2_R_ATT_M;
763 hal2_i_write32(hal2, H2I_DAC_C2, tmp);
765 hal2_i_setbit32(hal2, H2I_DAC_C2, H2I_C2_MUTE);
767 case H2_MIX_INPUT_GAIN: {
774 static void hal2_init_mixer(hal2_card_t *hal2)
778 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
779 hal2_write_mixer(hal2, i, 100 | (100 << 8));
783 static int hal2_mixer_ioctl(hal2_card_t *hal2, unsigned int cmd,
788 if (cmd == SOUND_MIXER_INFO) {
790 memset(&info, 0, sizeof(info));
791 strlcpy(info.id, hal2str, sizeof(info.id));
792 strlcpy(info.name, hal2str, sizeof(info.name));
793 info.modify_counter = hal2->mixer.modcnt;
794 if (copy_to_user((void *)arg, &info, sizeof(info)))
798 if (cmd == SOUND_OLD_MIXER_INFO) {
799 _old_mixer_info info;
800 memset(&info, 0, sizeof(info));
801 strlcpy(info.id, hal2str, sizeof(info.id));
802 strlcpy(info.name, hal2str, sizeof(info.name));
803 if (copy_to_user((void *)arg, &info, sizeof(info)))
807 if (cmd == OSS_GETVERSION)
808 return put_user(SOUND_VERSION, (int *)arg);
810 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
813 if (_IOC_DIR(cmd) == _IOC_READ) {
814 switch (_IOC_NR(cmd)) {
815 /* Give the current record source */
816 case SOUND_MIXER_RECSRC:
819 /* Give the supported mixers, all of them support stereo */
820 case SOUND_MIXER_DEVMASK:
821 case SOUND_MIXER_STEREODEVS: {
824 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
825 if (mixtable[i].avail)
829 /* Arg contains a bit for each supported recording source */
830 case SOUND_MIXER_RECMASK:
833 case SOUND_MIXER_CAPS:
836 /* Read a specific mixer */
838 int i = _IOC_NR(cmd);
840 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail)
842 val = hal2->mixer.volume[mixtable[i].idx];
846 return put_user(val, (int *)arg);
849 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
852 hal2->mixer.modcnt++;
854 if (get_user(val, (int *)arg))
857 switch (_IOC_NR(cmd)) {
858 /* Arg contains a bit for each recording source */
859 case SOUND_MIXER_RECSRC:
860 return 0; /* FIXME */
862 return hal2_write_mixer(hal2, _IOC_NR(cmd), val);
868 static int hal2_open_mixdev(struct inode *inode, struct file *file)
870 hal2_card_t *hal2 = hal2_mixer_find_card(iminor(inode));
873 file->private_data = hal2;
879 static int hal2_release_mixdev(struct inode *inode, struct file *file)
884 static int hal2_ioctl_mixdev(struct inode *inode, struct file *file,
885 unsigned int cmd, unsigned long arg)
887 return hal2_mixer_ioctl((hal2_card_t *)file->private_data, cmd, arg);
891 static int hal2_ioctl(struct inode *inode, struct file *file,
892 unsigned int cmd, unsigned long arg)
895 hal2_card_t *hal2 = (hal2_card_t *) file->private_data;
899 return put_user(SOUND_VERSION, (int *)arg);
901 case SNDCTL_DSP_SYNC:
902 if (file->f_mode & FMODE_WRITE)
903 return hal2_sync_dac(hal2);
906 case SNDCTL_DSP_SETDUPLEX:
909 case SNDCTL_DSP_GETCAPS:
910 return put_user(DSP_CAP_DUPLEX | DSP_CAP_MULTI, (int *)arg);
912 case SNDCTL_DSP_RESET:
913 if (file->f_mode & FMODE_READ) {
915 hal2_reset_adc_pointer(hal2);
917 if (file->f_mode & FMODE_WRITE) {
919 hal2_reset_dac_pointer(hal2);
923 case SNDCTL_DSP_SPEED:
924 if (get_user(val, (int *)arg))
926 if (file->f_mode & FMODE_READ) {
928 val = hal2_compute_rate(&hal2->adc, val);
929 hal2->adc.sample_rate = val;
930 hal2_set_adc_rate(hal2);
932 if (file->f_mode & FMODE_WRITE) {
934 val = hal2_compute_rate(&hal2->dac, val);
935 hal2->dac.sample_rate = val;
936 hal2_set_dac_rate(hal2);
938 return put_user(val, (int *)arg);
940 case SNDCTL_DSP_STEREO:
941 if (get_user(val, (int *)arg))
943 if (file->f_mode & FMODE_READ) {
945 hal2->adc.voices = (val) ? 2 : 1;
946 hal2_setup_adc(hal2);
948 if (file->f_mode & FMODE_WRITE) {
950 hal2->dac.voices = (val) ? 2 : 1;
951 hal2_setup_dac(hal2);
955 case SNDCTL_DSP_CHANNELS:
956 if (get_user(val, (int *)arg))
959 if (file->f_mode & FMODE_READ) {
961 hal2->adc.voices = (val == 1) ? 1 : 2;
962 hal2_setup_adc(hal2);
964 if (file->f_mode & FMODE_WRITE) {
966 hal2->dac.voices = (val == 1) ? 1 : 2;
967 hal2_setup_dac(hal2);
971 if (file->f_mode & FMODE_READ)
972 val = hal2->adc.voices;
973 if (file->f_mode & FMODE_WRITE)
974 val = hal2->dac.voices;
975 return put_user(val, (int *)arg);
977 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
978 return put_user(H2_SUPPORTED_FORMATS, (int *)arg);
980 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
981 if (get_user(val, (int *)arg))
983 if (val != AFMT_QUERY) {
984 if (!(val & H2_SUPPORTED_FORMATS))
986 if (file->f_mode & FMODE_READ) {
988 hal2->adc.format = val;
989 hal2_setup_adc(hal2);
991 if (file->f_mode & FMODE_WRITE) {
993 hal2->dac.format = val;
994 hal2_setup_dac(hal2);
998 if (file->f_mode & FMODE_READ)
999 val = hal2->adc.format;
1000 if (file->f_mode & FMODE_WRITE)
1001 val = hal2->dac.format;
1003 return put_user(val, (int *)arg);
1005 case SNDCTL_DSP_POST:
1008 case SNDCTL_DSP_GETOSPACE: {
1009 unsigned long flags;
1010 audio_buf_info info;
1012 hal2_codec_t *dac = &hal2->dac;
1014 if (!(file->f_mode & FMODE_WRITE))
1017 spin_lock_irqsave(&dac->lock, flags);
1020 while (buf->info.cnt == 0 && buf != dac->tail) {
1022 buf = buf->info.next;
1024 spin_unlock_irqrestore(&dac->lock, flags);
1026 info.fragstotal = obuffers;
1027 info.fragsize = H2_BUFFER_SIZE;
1028 info.bytes = info.fragsize * info.fragments;
1030 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1033 case SNDCTL_DSP_GETISPACE: {
1034 unsigned long flags;
1035 audio_buf_info info;
1037 hal2_codec_t *adc = &hal2->adc;
1039 if (!(file->f_mode & FMODE_READ))
1042 spin_lock_irqsave(&adc->lock, flags);
1046 while (buf->info.cnt > 0 && buf != adc->head) {
1048 info.bytes += buf->info.cnt;
1049 buf = buf->info.next;
1051 spin_unlock_irqrestore(&adc->lock, flags);
1053 info.fragstotal = ibuffers;
1054 info.fragsize = H2_BUFFER_SIZE;
1056 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
1059 case SNDCTL_DSP_NONBLOCK:
1060 file->f_flags |= O_NONBLOCK;
1063 case SNDCTL_DSP_GETBLKSIZE:
1064 return put_user(H2_BUFFER_SIZE, (int *)arg);
1066 case SNDCTL_DSP_SETFRAGMENT:
1069 case SOUND_PCM_READ_RATE:
1071 if (file->f_mode & FMODE_READ)
1072 val = hal2->adc.sample_rate;
1073 if (file->f_mode & FMODE_WRITE)
1074 val = hal2->dac.sample_rate;
1075 return put_user(val, (int *)arg);
1077 case SOUND_PCM_READ_CHANNELS:
1079 if (file->f_mode & FMODE_READ)
1080 val = hal2->adc.voices;
1081 if (file->f_mode & FMODE_WRITE)
1082 val = hal2->dac.voices;
1083 return put_user(val, (int *)arg);
1085 case SOUND_PCM_READ_BITS:
1087 return put_user(val, (int *)arg);
1090 return hal2_mixer_ioctl(hal2, cmd, arg);
1093 static ssize_t hal2_read(struct file *file, char *buffer,
1094 size_t count, loff_t *ppos)
1097 hal2_card_t *hal2 = (hal2_card_t *) file->private_data;
1098 hal2_codec_t *adc = &hal2->adc;
1102 if (ppos != &file->f_pos)
1107 if (file->f_flags & O_NONBLOCK) {
1108 err = hal2_get_buffer(hal2, buffer, count);
1109 err = err == 0 ? -EAGAIN : err;
1113 signed long timeout = 1000 * H2_BUFFER_SIZE *
1114 2 * adc->voices * HZ / adc->sample_rate / 900;
1115 DECLARE_WAITQUEUE(wait, current);
1118 err = hal2_get_buffer(hal2, buffer, count);
1125 if (count > 0 && err >= 0) {
1126 add_wait_queue(&adc->dma_wait, &wait);
1127 set_current_state(TASK_INTERRUPTIBLE);
1128 /* Well, it is possible, that interrupt already
1129 * arrived. Hmm, shit happens, we have one more
1130 * buffer filled ;) */
1131 if (!schedule_timeout(timeout))
1132 /* We may get bogus timeout when system
1133 * is heavily loaded */
1134 if (!adc->tail->info.cnt) {
1135 printk("HAL2: timeout...\n");
1136 hal2_stop_adc(hal2);
1137 hal2_reset_adc_pointer(hal2);
1140 if (signal_pending(current))
1142 remove_wait_queue(&adc->dma_wait, &wait);
1144 } while (count > 0 && err >= 0);
1153 static ssize_t hal2_write(struct file *file, const char *buffer,
1154 size_t count, loff_t *ppos)
1157 char *buf = (char*) buffer;
1158 hal2_card_t *hal2 = (hal2_card_t *) file->private_data;
1159 hal2_codec_t *dac = &hal2->dac;
1163 if (ppos != &file->f_pos)
1168 if (file->f_flags & O_NONBLOCK) {
1169 err = hal2_add_buffer(hal2, buf, count);
1170 err = err == 0 ? -EAGAIN : err;
1174 signed long timeout = 1000 * H2_BUFFER_SIZE *
1175 2 * dac->voices * HZ / dac->sample_rate / 900;
1176 DECLARE_WAITQUEUE(wait, current);
1179 err = hal2_add_buffer(hal2, buf, count);
1186 if (count > 0 && err >= 0) {
1187 add_wait_queue(&dac->dma_wait, &wait);
1188 set_current_state(TASK_INTERRUPTIBLE);
1189 /* Well, it is possible, that interrupt already
1190 * arrived. Hmm, shit happens, we have one more
1192 if (!schedule_timeout(timeout))
1193 /* We may get bogus timeout when system
1194 * is heavily loaded */
1195 if (dac->head->info.cnt) {
1196 printk("HAL2: timeout...\n");
1197 hal2_stop_dac(hal2);
1198 hal2_reset_dac_pointer(hal2);
1201 if (signal_pending(current))
1203 remove_wait_queue(&dac->dma_wait, &wait);
1205 } while (count > 0 && err >= 0);
1213 static unsigned int hal2_poll(struct file *file, struct poll_table_struct *wait)
1215 unsigned long flags;
1216 unsigned int mask = 0;
1217 hal2_card_t *hal2 = (hal2_card_t *) file->private_data;
1219 if (file->f_mode & FMODE_READ) {
1220 hal2_codec_t *adc = &hal2->adc;
1222 poll_wait(file, &hal2->adc.dma_wait, wait);
1223 spin_lock_irqsave(&adc->lock, flags);
1224 if (adc->tail->info.cnt > 0)
1226 spin_unlock_irqrestore(&adc->lock, flags);
1229 if (file->f_mode & FMODE_WRITE) {
1230 hal2_codec_t *dac = &hal2->dac;
1232 poll_wait(file, &dac->dma_wait, wait);
1233 spin_lock_irqsave(&dac->lock, flags);
1234 if (dac->head->info.cnt == 0)
1236 spin_unlock_irqrestore(&dac->lock, flags);
1242 static int hal2_open(struct inode *inode, struct file *file)
1245 hal2_card_t *hal2 = hal2_dsp_find_card(iminor(inode));
1247 DEBUG("opening audio device.\n");
1250 printk("HAL2: Whee?! Open door and go away!\n");
1253 file->private_data = hal2;
1255 if (file->f_mode & FMODE_READ) {
1256 if (hal2->adc.usecount)
1259 /* OSS spec wanted us to use 8 bit, 8 kHz mono by default,
1260 * but HAL2 can't do 8bit audio */
1261 hal2->adc.format = AFMT_S16_BE;
1262 hal2->adc.voices = 1;
1263 hal2->adc.sample_rate = hal2_compute_rate(&hal2->adc, 8000);
1264 hal2_set_adc_rate(hal2);
1266 /* alloc DMA buffers */
1267 err = hal2_alloc_adc_dmabuf(hal2);
1270 hal2_setup_adc(hal2);
1272 hal2->adc.usecount++;
1275 if (file->f_mode & FMODE_WRITE) {
1276 if (hal2->dac.usecount)
1279 hal2->dac.format = AFMT_S16_BE;
1280 hal2->dac.voices = 1;
1281 hal2->dac.sample_rate = hal2_compute_rate(&hal2->dac, 8000);
1282 hal2_set_dac_rate(hal2);
1284 /* alloc DMA buffers */
1285 err = hal2_alloc_dac_dmabuf(hal2);
1288 hal2_setup_dac(hal2);
1290 hal2->dac.usecount++;
1296 static int hal2_release(struct inode *inode, struct file *file)
1298 hal2_card_t *hal2 = (hal2_card_t *) file->private_data;
1300 if (file->f_mode & FMODE_READ) {
1301 hal2_stop_adc(hal2);
1302 hal2_free_adc_dmabuf(hal2);
1303 hal2->adc.usecount--;
1306 if (file->f_mode & FMODE_WRITE) {
1307 hal2_sync_dac(hal2);
1308 hal2_free_dac_dmabuf(hal2);
1309 hal2->dac.usecount--;
1315 static struct file_operations hal2_audio_fops = {
1316 .owner = THIS_MODULE,
1317 .llseek = no_llseek,
1319 .write = hal2_write,
1321 .ioctl = hal2_ioctl,
1323 .release = hal2_release,
1326 static struct file_operations hal2_mixer_fops = {
1327 .owner = THIS_MODULE,
1328 .llseek = no_llseek,
1329 .ioctl = hal2_ioctl_mixdev,
1330 .open = hal2_open_mixdev,
1331 .release = hal2_release_mixdev,
1334 static int hal2_request_irq(hal2_card_t *hal2, int irq)
1336 unsigned long flags;
1339 save_and_cli(flags);
1340 if (request_irq(irq, hal2_interrupt, SA_SHIRQ, hal2str, hal2)) {
1341 printk(KERN_ERR "HAL2: Can't get irq %d\n", irq);
1344 restore_flags(flags);
1348 static int hal2_alloc_resources(hal2_card_t *hal2, struct hpc3_regs *hpc3)
1352 pbus = &hal2->dac.pbus;
1354 pbus->pbus = &hpc3->pbdma[pbus->pbusnr];
1355 /* The spec says that we should write 0x08248844 but that's WRONG. HAL2
1356 * does 8 bit DMA, not 16 bit even if it generates 16 bit audio. */
1357 hpc3->pbus_dmacfgs[pbus->pbusnr][0] = 0x08208844; /* Magic :-) */
1359 pbus = &hal2->adc.pbus;
1361 pbus->pbus = &hpc3->pbdma[pbus->pbusnr];
1362 hpc3->pbus_dmacfgs[pbus->pbusnr][0] = 0x08208844; /* Magic :-) */
1364 return hal2_request_irq(hal2, SGI_HPCDMA_IRQ);
1367 static void hal2_init_codec(hal2_codec_t *codec)
1369 init_waitqueue_head(&codec->dma_wait);
1370 init_MUTEX(&codec->sem);
1371 spin_lock_init(&codec->lock);
1374 static void hal2_free_resources(hal2_card_t *hal2)
1376 free_irq(SGI_HPCDMA_IRQ, hal2);
1379 static int hal2_detect(hal2_card_t *hal2)
1381 unsigned short board, major, minor;
1385 hal2_isr_write(hal2, 0);
1388 hal2_isr_write(hal2, H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N);
1390 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
1392 if ((rev = hal2_rev_look(hal2)) & H2_REV_AUDIO_PRESENT) {
1393 DEBUG("HAL2: no device detected, rev: 0x%04hx\n", rev);
1397 board = (rev & H2_REV_BOARD_M) >> 12;
1398 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
1399 minor = (rev & H2_REV_MINOR_CHIP_M);
1401 printk("SGI HAL2 Processor revision %i.%i.%i detected\n",
1402 board, major, minor);
1404 if (board != 4 || major != 1 || minor != 0)
1405 printk( "Other revision than 4.1.0 detected. "
1406 "Your card is probably unsupported\n");
1411 static int hal2_init_card(hal2_card_t **phal2, struct hpc3_regs *hpc3,
1412 unsigned long hpc3_base)
1417 hal2 = (hal2_card_t *) kmalloc(sizeof(hal2_card_t), GFP_KERNEL);
1420 memset(hal2, 0, sizeof(hal2_card_t));
1422 hal2->ctl_regs = (hal2_ctl_regs_t *) KSEG1ADDR(hpc3_base + H2_CTL_PIO);
1423 hal2->aes_regs = (hal2_aes_regs_t *) KSEG1ADDR(hpc3_base + H2_AES_PIO);
1424 hal2->vol_regs = (hal2_vol_regs_t *) KSEG1ADDR(hpc3_base + H2_VOL_PIO);
1425 hal2->syn_regs = (hal2_syn_regs_t *) KSEG1ADDR(hpc3_base + H2_SYN_PIO);
1427 if (hal2_detect(hal2) < 0) {
1428 printk("HAL2 audio processor not found\n");
1433 hal2_init_codec(&hal2->dac);
1434 hal2_init_codec(&hal2->adc);
1436 ret = hal2_alloc_resources(hal2, hpc3);
1440 hal2_init_mixer(hal2);
1442 hal2->dev_dsp = register_sound_dsp(&hal2_audio_fops, -1);
1443 if (hal2->dev_dsp < 0) {
1444 ret = hal2->dev_dsp;
1448 hal2->dev_mixer = register_sound_mixer(&hal2_mixer_fops, -1);
1449 if (hal2->dev_mixer < 0) {
1450 ret = hal2->dev_mixer;
1457 unregister_sound_dsp(hal2->dev_dsp);
1459 hal2_free_resources(hal2);
1467 * We are assuming only one HAL2 card. If you ever meet machine with more than
1468 * one, tell immediately about it to someone. Preferably to me. --ladis
1470 static int __init init_hal2(void)
1474 for (i = 0; i < MAXCARDS; i++)
1475 hal2_card[i] = NULL;
1477 return hal2_init_card(&hal2_card[0], hpc3c0, HPC3_CHIP0_PBASE);
1480 static void __exit exit_hal2(void)
1484 for (i = 0; i < MAXCARDS; i++)
1486 hal2_free_resources(hal2_card[i]);
1487 unregister_sound_dsp(hal2_card[i]->dev_dsp);
1488 unregister_sound_mixer(hal2_card[i]->dev_mixer);
1489 kfree(hal2_card[i]);
1493 module_init(init_hal2);
1494 module_exit(exit_hal2);
1496 MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio");
1497 MODULE_AUTHOR("Ladislav Michl");
1498 MODULE_LICENSE("GPL");