1 /***********************************************************************
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * drivers/sound/nec_vrc5477.c
6 * AC97 sound dirver for NEC Vrc5477 chip (an integrated,
7 * multi-function controller chip for MIPS CPUs)
9 * VRA support Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 ***********************************************************************
19 * This code is derived from ite8172.c, which is written by Steve Longerbeam.
22 * Currently we only support the following capabilities:
23 * . mono output to PCM L/R (line out).
24 * . stereo output to PCM L/R (line out).
25 * . mono input from PCM L (line in).
26 * . stereo output from PCM (line in).
27 * . sampling rate at 48k or variable sampling rate
28 * . support /dev/dsp, /dev/mixer devices, standard OSS devices.
29 * . only support 16-bit PCM format (hardware limit, no software
31 * . support duplex, but no trigger or realtime.
33 * Specifically the following are not supported:
34 * . app-set frag size.
35 * . mmap'ed buffer access
39 * Original comments from ite8172.c file.
46 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
47 * taken, slightly modified or not at all, from the ES1371 driver,
48 * so refer to the credits in es1371.c for those. The rest of the
49 * code (probe, open, read, write, the ISR, etc.) is new.
50 * 2. The following support is untested:
51 * * Memory mapping the audio buffers, and the ioctl controls that go
54 * 3. The following is not supported:
56 * * legacy audio mode.
57 * 4. Support for volume button interrupts is implemented but doesn't
61 * 02.08.2001 0.1 Initial release
64 #include <linux/module.h>
65 #include <linux/string.h>
66 #include <linux/kernel.h>
67 #include <linux/ioport.h>
68 #include <linux/sched.h>
69 #include <linux/delay.h>
70 #include <linux/sound.h>
71 #include <linux/slab.h>
72 #include <linux/soundcard.h>
73 #include <linux/pci.h>
74 #include <linux/init.h>
75 #include <linux/poll.h>
76 #include <linux/bitops.h>
77 #include <linux/proc_fs.h>
78 #include <linux/spinlock.h>
79 #include <linux/smp_lock.h>
80 #include <linux/ac97_codec.h>
81 #include <linux/interrupt.h>
84 #include <asm/uaccess.h>
85 #include <asm/hardirq.h>
87 /* -------------------debug macros -------------------------------------- */
88 /* #undef VRC5477_AC97_DEBUG */
89 #define VRC5477_AC97_DEBUG
91 #undef VRC5477_AC97_VERBOSE_DEBUG
92 /* #define VRC5477_AC97_VERBOSE_DEBUG */
94 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
95 #define VRC5477_AC97_DEBUG
98 #if defined(VRC5477_AC97_DEBUG)
99 #define ASSERT(x) if (!(x)) { \
100 panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); }
103 #endif /* VRC5477_AC97_DEBUG */
105 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
106 static u16 inTicket; /* check sync between intr & write */
107 static u16 outTicket;
110 /* --------------------------------------------------------------------- */
112 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
114 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
116 #define VRC5477_INT_CLR 0x0
117 #define VRC5477_INT_STATUS 0x0
118 #define VRC5477_CODEC_WR 0x4
119 #define VRC5477_CODEC_RD 0x8
120 #define VRC5477_CTRL 0x18
121 #define VRC5477_ACLINK_CTRL 0x1c
122 #define VRC5477_INT_MASK 0x24
124 #define VRC5477_DAC1_CTRL 0x30
125 #define VRC5477_DAC1L 0x34
126 #define VRC5477_DAC1_BADDR 0x38
127 #define VRC5477_DAC2_CTRL 0x3c
128 #define VRC5477_DAC2L 0x40
129 #define VRC5477_DAC2_BADDR 0x44
130 #define VRC5477_DAC3_CTRL 0x48
131 #define VRC5477_DAC3L 0x4c
132 #define VRC5477_DAC3_BADDR 0x50
134 #define VRC5477_ADC1_CTRL 0x54
135 #define VRC5477_ADC1L 0x58
136 #define VRC5477_ADC1_BADDR 0x5c
137 #define VRC5477_ADC2_CTRL 0x60
138 #define VRC5477_ADC2L 0x64
139 #define VRC5477_ADC2_BADDR 0x68
140 #define VRC5477_ADC3_CTRL 0x6c
141 #define VRC5477_ADC3L 0x70
142 #define VRC5477_ADC3_BADDR 0x74
144 #define VRC5477_CODEC_WR_RWC (1 << 23)
146 #define VRC5477_CODEC_RD_RRDYA (1 << 31)
147 #define VRC5477_CODEC_RD_RRDYD (1 << 30)
149 #define VRC5477_ACLINK_CTRL_RST_ON (1 << 15)
150 #define VRC5477_ACLINK_CTRL_RST_TIME 0x7f
151 #define VRC5477_ACLINK_CTRL_SYNC_ON (1 << 30)
152 #define VRC5477_ACLINK_CTRL_CK_STOP_ON (1 << 31)
154 #define VRC5477_CTRL_DAC2ENB (1 << 15)
155 #define VRC5477_CTRL_ADC2ENB (1 << 14)
156 #define VRC5477_CTRL_DAC1ENB (1 << 13)
157 #define VRC5477_CTRL_ADC1ENB (1 << 12)
159 #define VRC5477_INT_MASK_NMASK (1 << 31)
160 #define VRC5477_INT_MASK_DAC1END (1 << 5)
161 #define VRC5477_INT_MASK_DAC2END (1 << 4)
162 #define VRC5477_INT_MASK_DAC3END (1 << 3)
163 #define VRC5477_INT_MASK_ADC1END (1 << 2)
164 #define VRC5477_INT_MASK_ADC2END (1 << 1)
165 #define VRC5477_INT_MASK_ADC3END (1 << 0)
167 #define VRC5477_DMA_ACTIVATION (1 << 31)
168 #define VRC5477_DMA_WIP (1 << 30)
171 #define VRC5477_AC97_MODULE_NAME "NEC_Vrc5477_audio"
172 #define PFX VRC5477_AC97_MODULE_NAME ": "
174 /* --------------------------------------------------------------------- */
176 struct vrc5477_ac97_state {
177 /* list of vrc5477_ac97 devices */
178 struct list_head devs;
180 /* the corresponding pci_dev structure */
183 /* soundcore stuff */
186 /* hardware resources */
190 #ifdef VRC5477_AC97_DEBUG
191 /* debug /proc entry */
192 struct proc_dir_entry *ps;
193 struct proc_dir_entry *ac97_ps;
194 #endif /* VRC5477_AC97_DEBUG */
196 struct ac97_codec *codec;
198 unsigned dacChannels, adcChannels;
199 unsigned short dacRate, adcRate;
200 unsigned short extended_status;
203 struct semaphore open_sem;
205 wait_queue_head_t open_wait;
209 dma_addr_t lbufDma, rbufDma;
213 unsigned fragSize; /* redundant */
214 unsigned fragTotalSize; /* = numFrag * fragSize(real) */
218 unsigned error; /* over/underrun */
219 wait_queue_head_t wait;
225 #define WORK_BUF_SIZE 2048
229 } workBuf[WORK_BUF_SIZE/4];
232 /* --------------------------------------------------------------------- */
234 static LIST_HEAD(devs);
236 /* --------------------------------------------------------------------- */
238 static inline unsigned ld2(unsigned int x)
263 /* --------------------------------------------------------------------- */
265 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
267 struct vrc5477_ac97_state *s =
268 (struct vrc5477_ac97_state *)codec->private_data;
272 spin_lock_irqsave(&s->lock, flags);
274 /* wait until we can access codec registers */
275 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
277 /* write the address and "read" command to codec */
279 outl((addr << 16) | VRC5477_CODEC_WR_RWC, s->io + VRC5477_CODEC_WR);
281 /* get the return result */
282 udelay(100); /* workaround hardware bug */
283 while ( (result = inl(s->io + VRC5477_CODEC_RD)) &
284 (VRC5477_CODEC_RD_RRDYA | VRC5477_CODEC_RD_RRDYD) ) {
285 /* we get either addr or data, or both */
286 if (result & VRC5477_CODEC_RD_RRDYA) {
287 ASSERT(addr == ((result >> 16) & 0x7f) );
289 if (result & VRC5477_CODEC_RD_RRDYD) {
294 spin_unlock_irqrestore(&s->lock, flags);
296 return result & 0xffff;
300 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
302 struct vrc5477_ac97_state *s =
303 (struct vrc5477_ac97_state *)codec->private_data;
306 spin_lock_irqsave(&s->lock, flags);
308 /* wait until we can access codec registers */
309 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
311 /* write the address and value to codec */
312 outl((addr << 16) | data, s->io + VRC5477_CODEC_WR);
314 spin_unlock_irqrestore(&s->lock, flags);
318 static void waitcodec(struct ac97_codec *codec)
320 struct vrc5477_ac97_state *s =
321 (struct vrc5477_ac97_state *)codec->private_data;
323 /* wait until we can access codec registers */
324 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000);
327 static int ac97_codec_not_present(struct ac97_codec *codec)
329 struct vrc5477_ac97_state *s =
330 (struct vrc5477_ac97_state *)codec->private_data;
332 unsigned short count = 0xffff;
334 spin_lock_irqsave(&s->lock, flags);
336 /* wait until we can access codec registers */
338 if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
343 spin_unlock_irqrestore(&s->lock, flags);
347 /* write 0 to reset */
348 outl((AC97_RESET << 16) | 0, s->io + VRC5477_CODEC_WR);
350 /* test whether we get a response from ac97 chip */
353 if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000))
358 spin_unlock_irqrestore(&s->lock, flags);
361 spin_unlock_irqrestore(&s->lock, flags);
365 /* --------------------------------------------------------------------- */
367 static void vrc5477_ac97_delay(int msec)
375 tmo = jiffies + (msec*HZ)/1000;
377 tmo2 = tmo - jiffies;
380 schedule_timeout(tmo2);
385 static void set_adc_rate(struct vrc5477_ac97_state *s, unsigned rate)
387 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, rate);
392 static void set_dac_rate(struct vrc5477_ac97_state *s, unsigned rate)
394 if(s->extended_status & AC97_EXTSTAT_VRA) {
395 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, rate);
396 s->dacRate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
401 /* --------------------------------------------------------------------- */
404 stop_dac(struct vrc5477_ac97_state *s)
406 struct dmabuf* db = &s->dma_dac;
410 spin_lock_irqsave(&s->lock, flags);
413 spin_unlock_irqrestore(&s->lock, flags);
417 /* deactivate the dma */
418 outl(0, s->io + VRC5477_DAC1_CTRL);
419 outl(0, s->io + VRC5477_DAC2_CTRL);
421 /* wait for DAM completely stop */
422 while (inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
423 while (inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
425 /* disable dac slots in aclink */
426 temp = inl(s->io + VRC5477_CTRL);
427 temp &= ~ (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB);
428 outl (temp, s->io + VRC5477_CTRL);
430 /* disable interrupts */
431 temp = inl(s->io + VRC5477_INT_MASK);
432 temp &= ~ (VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END);
433 outl (temp, s->io + VRC5477_INT_MASK);
435 /* clear pending ones */
436 outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END,
437 s->io + VRC5477_INT_CLR);
441 spin_unlock_irqrestore(&s->lock, flags);
444 static void start_dac(struct vrc5477_ac97_state *s)
446 struct dmabuf* db = &s->dma_dac;
451 spin_lock_irqsave(&s->lock, flags);
454 spin_unlock_irqrestore(&s->lock, flags);
458 /* we should have some data to do the DMA trasnfer */
459 ASSERT(db->count >= db->fragSize);
461 /* clear pending fales interrupts */
462 outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END,
463 s->io + VRC5477_INT_CLR);
465 /* enable interrupts */
466 temp = inl(s->io + VRC5477_INT_MASK);
467 temp |= VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END;
468 outl(temp, s->io + VRC5477_INT_MASK);
470 /* setup dma base addr */
471 outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC1_BADDR);
472 if (s->dacChannels == 1) {
473 outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR);
475 outl(db->rbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR);
478 /* set dma length, in the unit of 0x10 bytes */
479 dmaLength = db->fragSize >> 4;
480 outl(dmaLength, s->io + VRC5477_DAC1L);
481 outl(dmaLength, s->io + VRC5477_DAC2L);
484 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC1_CTRL);
485 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC2_CTRL);
487 /* enable dac slots - we should hear the music now! */
488 temp = inl(s->io + VRC5477_CTRL);
489 temp |= (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB);
490 outl (temp, s->io + VRC5477_CTRL);
492 /* it is time to setup next dma transfer */
493 ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
494 ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
496 temp = db->nextOut + db->fragSize;
497 if (temp >= db->fragTotalSize) {
498 ASSERT(temp == db->fragTotalSize);
502 outl(db->lbufDma + temp, s->io + VRC5477_DAC1_BADDR);
503 if (s->dacChannels == 1) {
504 outl(db->lbufDma + temp, s->io + VRC5477_DAC2_BADDR);
506 outl(db->rbufDma + temp, s->io + VRC5477_DAC2_BADDR);
511 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
512 outTicket = *(u16*)(db->lbuf+db->nextOut);
513 if (db->count > db->fragSize) {
514 ASSERT((u16)(outTicket+1) == *(u16*)(db->lbuf+temp));
518 spin_unlock_irqrestore(&s->lock, flags);
521 static inline void stop_adc(struct vrc5477_ac97_state *s)
523 struct dmabuf* db = &s->dma_adc;
527 spin_lock_irqsave(&s->lock, flags);
530 spin_unlock_irqrestore(&s->lock, flags);
534 /* deactivate the dma */
535 outl(0, s->io + VRC5477_ADC1_CTRL);
536 outl(0, s->io + VRC5477_ADC2_CTRL);
538 /* disable adc slots in aclink */
539 temp = inl(s->io + VRC5477_CTRL);
540 temp &= ~ (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB);
541 outl (temp, s->io + VRC5477_CTRL);
543 /* disable interrupts */
544 temp = inl(s->io + VRC5477_INT_MASK);
545 temp &= ~ (VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END);
546 outl (temp, s->io + VRC5477_INT_MASK);
548 /* clear pending ones */
549 outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END,
550 s->io + VRC5477_INT_CLR);
554 spin_unlock_irqrestore(&s->lock, flags);
557 static void start_adc(struct vrc5477_ac97_state *s)
559 struct dmabuf* db = &s->dma_adc;
564 spin_lock_irqsave(&s->lock, flags);
567 spin_unlock_irqrestore(&s->lock, flags);
571 /* we should at least have some free space in the buffer */
572 ASSERT(db->count < db->fragTotalSize - db->fragSize * 2);
574 /* clear pending ones */
575 outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END,
576 s->io + VRC5477_INT_CLR);
578 /* enable interrupts */
579 temp = inl(s->io + VRC5477_INT_MASK);
580 temp |= VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END;
581 outl(temp, s->io + VRC5477_INT_MASK);
583 /* setup dma base addr */
584 outl(db->lbufDma + db->nextIn, s->io + VRC5477_ADC1_BADDR);
585 outl(db->rbufDma + db->nextIn, s->io + VRC5477_ADC2_BADDR);
587 /* setup dma length */
588 dmaLength = db->fragSize >> 4;
589 outl(dmaLength, s->io + VRC5477_ADC1L);
590 outl(dmaLength, s->io + VRC5477_ADC2L);
593 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC1_CTRL);
594 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC2_CTRL);
596 /* enable adc slots */
597 temp = inl(s->io + VRC5477_CTRL);
598 temp |= (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB);
599 outl (temp, s->io + VRC5477_CTRL);
601 /* it is time to setup next dma transfer */
602 temp = db->nextIn + db->fragSize;
603 if (temp >= db->fragTotalSize) {
604 ASSERT(temp == db->fragTotalSize);
607 outl(db->lbufDma + temp, s->io + VRC5477_ADC1_BADDR);
608 outl(db->rbufDma + temp, s->io + VRC5477_ADC2_BADDR);
612 spin_unlock_irqrestore(&s->lock, flags);
615 /* --------------------------------------------------------------------- */
617 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
618 #define DMABUF_MINORDER 1
620 static inline void dealloc_dmabuf(struct vrc5477_ac97_state *s,
625 pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder,
626 db->lbuf, db->lbufDma);
627 pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder,
628 db->rbuf, db->rbufDma);
629 db->lbuf = db->rbuf = NULL;
631 db->nextIn = db->nextOut = 0;
635 static int prog_dmabuf(struct vrc5477_ac97_state *s,
646 for (order = DMABUF_DEFAULTORDER;
647 order >= DMABUF_MINORDER;
649 db->lbuf = pci_alloc_consistent(s->dev,
652 db->rbuf = pci_alloc_consistent(s->dev,
655 if (db->lbuf && db->rbuf) break;
658 pci_free_consistent(s->dev,
669 db->bufOrder = order;
673 db->nextIn = db->nextOut = 0;
675 bufsize = PAGE_SIZE << db->bufOrder;
676 db->fragShift = ld2(rate * 2 / 100);
677 if (db->fragShift < 4) db->fragShift = 4;
679 db->numFrag = bufsize >> db->fragShift;
680 while (db->numFrag < 4 && db->fragShift > 4) {
682 db->numFrag = bufsize >> db->fragShift;
684 db->fragSize = 1 << db->fragShift;
685 db->fragTotalSize = db->numFrag << db->fragShift;
686 memset(db->lbuf, 0, db->fragTotalSize);
687 memset(db->rbuf, 0, db->fragTotalSize);
694 static inline int prog_dmabuf_adc(struct vrc5477_ac97_state *s)
697 return prog_dmabuf(s, &s->dma_adc, s->adcRate);
700 static inline int prog_dmabuf_dac(struct vrc5477_ac97_state *s)
703 return prog_dmabuf(s, &s->dma_dac, s->dacRate);
707 /* --------------------------------------------------------------------- */
708 /* hold spinlock for the following! */
710 static inline void vrc5477_ac97_adc_interrupt(struct vrc5477_ac97_state *s)
712 struct dmabuf* adc = &s->dma_adc;
715 /* we need two frags avaiable because one is already being used
716 * and the other will be used when next interrupt happens.
718 if (adc->count >= adc->fragTotalSize - adc->fragSize) {
721 printk(KERN_INFO PFX "adc overrun\n");
725 /* set the base addr for next DMA transfer */
726 temp = adc->nextIn + 2*adc->fragSize;
727 if (temp >= adc->fragTotalSize) {
728 ASSERT( (temp == adc->fragTotalSize) ||
729 (temp == adc->fragTotalSize + adc->fragSize) );
730 temp -= adc->fragTotalSize;
732 outl(adc->lbufDma + temp, s->io + VRC5477_ADC1_BADDR);
733 outl(adc->rbufDma + temp, s->io + VRC5477_ADC2_BADDR);
736 adc->nextIn += adc->fragSize;
737 if (adc->nextIn >= adc->fragTotalSize) {
738 ASSERT(adc->nextIn == adc->fragTotalSize);
743 adc->count += adc->fragSize;
745 /* wake up anybody listening */
746 if (waitqueue_active(&adc->wait)) {
747 wake_up_interruptible(&adc->wait);
751 static inline void vrc5477_ac97_dac_interrupt(struct vrc5477_ac97_state *s)
753 struct dmabuf* dac = &s->dma_dac;
756 /* next DMA transfer should already started */
757 // ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP);
758 // ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP);
760 /* let us set for next next DMA transfer */
761 temp = dac->nextOut + dac->fragSize*2;
762 if (temp >= dac->fragTotalSize) {
763 ASSERT( (temp == dac->fragTotalSize) ||
764 (temp == dac->fragTotalSize + dac->fragSize) );
765 temp -= dac->fragTotalSize;
767 outl(dac->lbufDma + temp, s->io + VRC5477_DAC1_BADDR);
768 if (s->dacChannels == 1) {
769 outl(dac->lbufDma + temp, s->io + VRC5477_DAC2_BADDR);
771 outl(dac->rbufDma + temp, s->io + VRC5477_DAC2_BADDR);
774 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
775 if (*(u16*)(dac->lbuf + dac->nextOut) != outTicket) {
776 printk("assert fail: - %d vs %d\n",
777 *(u16*)(dac->lbuf + dac->nextOut),
783 /* adjust nextOut pointer */
784 dac->nextOut += dac->fragSize;
785 if (dac->nextOut >= dac->fragTotalSize) {
786 ASSERT(dac->nextOut == dac->fragTotalSize);
791 dac->count -= dac->fragSize;
792 if (dac->count <=0 ) {
793 /* buffer under run */
795 dac->nextIn = dac->nextOut;
799 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
802 ASSERT(*(u16*)(dac->lbuf + dac->nextOut) == outTicket);
806 /* we cannot have both under run and someone is waiting on us */
807 ASSERT(! (waitqueue_active(&dac->wait) && (dac->count <= 0)) );
809 /* wake up anybody listening */
810 if (waitqueue_active(&dac->wait))
811 wake_up_interruptible(&dac->wait);
814 static irqreturn_t vrc5477_ac97_interrupt(int irq, void *dev_id, struct pt_regs *regs)
816 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)dev_id;
818 u32 adcInterrupts, dacInterrupts;
822 /* get irqStatus and clear the detected ones */
823 irqStatus = inl(s->io + VRC5477_INT_STATUS);
824 outl(irqStatus, s->io + VRC5477_INT_CLR);
826 /* let us see what we get */
827 dacInterrupts = VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END;
828 adcInterrupts = VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END;
829 if (irqStatus & dacInterrupts) {
830 /* we should get both interrupts, but just in case ... */
831 if (irqStatus & VRC5477_INT_MASK_DAC1END) {
832 vrc5477_ac97_dac_interrupt(s);
834 if ( (irqStatus & dacInterrupts) != dacInterrupts ) {
835 printk(KERN_WARNING "vrc5477_ac97 : dac interrupts not in sync!!!\n");
839 } else if (irqStatus & adcInterrupts) {
840 /* we should get both interrupts, but just in case ... */
841 if(irqStatus & VRC5477_INT_MASK_ADC1END) {
842 vrc5477_ac97_adc_interrupt(s);
844 if ( (irqStatus & adcInterrupts) != adcInterrupts ) {
845 printk(KERN_WARNING "vrc5477_ac97 : adc interrupts not in sync!!!\n");
851 spin_unlock(&s->lock);
855 /* --------------------------------------------------------------------- */
857 static int vrc5477_ac97_open_mixdev(struct inode *inode, struct file *file)
859 int minor = iminor(inode);
860 struct list_head *list;
861 struct vrc5477_ac97_state *s;
863 for (list = devs.next; ; list = list->next) {
866 s = list_entry(list, struct vrc5477_ac97_state, devs);
867 if (s->codec->dev_mixer == minor)
870 file->private_data = s;
874 static int vrc5477_ac97_release_mixdev(struct inode *inode, struct file *file)
880 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
883 return codec->mixer_ioctl(codec, cmd, arg);
886 static int vrc5477_ac97_ioctl_mixdev(struct inode *inode, struct file *file,
887 unsigned int cmd, unsigned long arg)
889 struct vrc5477_ac97_state *s =
890 (struct vrc5477_ac97_state *)file->private_data;
891 struct ac97_codec *codec = s->codec;
893 return mixdev_ioctl(codec, cmd, arg);
896 static /*const*/ struct file_operations vrc5477_ac97_mixer_fops = {
897 .owner = THIS_MODULE,
899 .ioctl = vrc5477_ac97_ioctl_mixdev,
900 .open = vrc5477_ac97_open_mixdev,
901 .release = vrc5477_ac97_release_mixdev,
904 /* --------------------------------------------------------------------- */
906 static int drain_dac(struct vrc5477_ac97_state *s, int nonblock)
911 if (!s->dma_dac.ready)
915 spin_lock_irqsave(&s->lock, flags);
916 count = s->dma_dac.count;
917 spin_unlock_irqrestore(&s->lock, flags);
920 if (signal_pending(current))
924 tmo = 1000 * count / s->dacRate / 2;
925 vrc5477_ac97_delay(tmo);
927 if (signal_pending(current))
932 /* --------------------------------------------------------------------- */
935 copy_two_channel_adc_to_user(struct vrc5477_ac97_state *s,
939 struct dmabuf *db = &s->dma_adc;
940 int bufStart = db->nextOut;
941 for (; copyCount > 0; ) {
943 int count = copyCount;
944 if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2;
945 for (i=0; i< count/2; i++) {
946 s->workBuf[i].lchannel =
947 *(u16*)(db->lbuf + bufStart + i*2);
948 s->workBuf[i].rchannel =
949 *(u16*)(db->rbuf + bufStart + i*2);
951 if (copy_to_user(buffer, s->workBuf, count*2)) {
957 ASSERT(bufStart <= db->fragTotalSize);
963 /* return the total bytes that is copied */
965 copy_adc_to_user(struct vrc5477_ac97_state *s,
970 struct dmabuf *db = &s->dma_adc;
973 int totalCopyCount = 0;
974 int totalCopyFragCount = 0;
977 /* adjust count to signel channel byte count */
978 count >>= s->adcChannels - 1;
980 /* we may have to "copy" twice as ring buffer wraps around */
981 for (; (avail > 0) && (count > 0); ) {
982 /* determine max possible copy count for single channel */
984 if (copyCount > avail) {
987 if (copyCount + db->nextOut > db->fragTotalSize) {
988 copyCount = db->fragTotalSize - db->nextOut;
989 ASSERT((copyCount % db->fragSize) == 0);
992 copyFragCount = (copyCount-1) >> db->fragShift;
993 copyFragCount = (copyFragCount+1) << db->fragShift;
994 ASSERT(copyFragCount >= copyCount);
996 /* we copy differently based on adc channels */
997 if (s->adcChannels == 1) {
998 if (copy_to_user(buffer,
999 db->lbuf + db->nextOut,
1003 /* *sigh* we have to mix two streams into one */
1004 if (copy_two_channel_adc_to_user(s, buffer, copyCount))
1009 totalCopyCount += copyCount;
1010 avail -= copyFragCount;
1011 totalCopyFragCount += copyFragCount;
1013 buffer += copyCount << (s->adcChannels-1);
1015 db->nextOut += copyFragCount;
1016 if (db->nextOut >= db->fragTotalSize) {
1017 ASSERT(db->nextOut == db->fragTotalSize);
1021 ASSERT((copyFragCount % db->fragSize) == 0);
1022 ASSERT( (count == 0) || (copyCount == copyFragCount));
1025 spin_lock_irqsave(&s->lock, flags);
1026 db->count -= totalCopyFragCount;
1027 spin_unlock_irqrestore(&s->lock, flags);
1029 return totalCopyCount << (s->adcChannels-1);
1033 vrc5477_ac97_read(struct file *file,
1038 struct vrc5477_ac97_state *s =
1039 (struct vrc5477_ac97_state *)file->private_data;
1040 struct dmabuf *db = &s->dma_adc;
1042 unsigned long flags;
1046 if (ppos != &file->f_pos)
1048 if (!access_ok(VERIFY_WRITE, buffer, count))
1054 // wait for samples in capture buffer
1056 spin_lock_irqsave(&s->lock, flags);
1060 spin_unlock_irqrestore(&s->lock, flags);
1062 if (file->f_flags & O_NONBLOCK) {
1067 interruptible_sleep_on(&db->wait);
1068 if (signal_pending(current)) {
1074 } while (avail <= 0);
1076 ASSERT( (avail % db->fragSize) == 0);
1077 copyCount = copy_adc_to_user(s, buffer, count, avail);
1078 if (copyCount <=0 ) {
1079 if (!ret) ret = -EFAULT;
1084 buffer += copyCount;
1086 } // while (count > 0)
1092 copy_two_channel_dac_from_user(struct vrc5477_ac97_state *s,
1096 struct dmabuf *db = &s->dma_dac;
1097 int bufStart = db->nextIn;
1101 for (; copyCount > 0; ) {
1103 int count = copyCount;
1104 if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2;
1105 if (copy_from_user(s->workBuf, buffer, count*2)) {
1108 for (i=0; i< count/2; i++) {
1109 *(u16*)(db->lbuf + bufStart + i*2) =
1110 s->workBuf[i].lchannel;
1111 *(u16*)(db->rbuf + bufStart + i*2) =
1112 s->workBuf[i].rchannel;
1117 ASSERT(bufStart <= db->fragTotalSize);
1124 /* return the total bytes that is copied */
1126 copy_dac_from_user(struct vrc5477_ac97_state *s,
1131 struct dmabuf *db = &s->dma_dac;
1133 int copyFragCount=0;
1134 int totalCopyCount = 0;
1135 int totalCopyFragCount = 0;
1136 unsigned long flags;
1137 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
1141 /* adjust count to signel channel byte count */
1142 count >>= s->dacChannels - 1;
1144 /* we may have to "copy" twice as ring buffer wraps around */
1145 for (; (avail > 0) && (count > 0); ) {
1146 /* determine max possible copy count for single channel */
1148 if (copyCount > avail) {
1151 if (copyCount + db->nextIn > db->fragTotalSize) {
1152 copyCount = db->fragTotalSize - db->nextIn;
1153 ASSERT(copyCount > 0);
1156 copyFragCount = copyCount;
1157 ASSERT(copyFragCount >= copyCount);
1159 /* we copy differently based on the number channels */
1160 if (s->dacChannels == 1) {
1161 if (copy_from_user(db->lbuf + db->nextIn,
1165 /* fill gaps with 0 */
1166 memset(db->lbuf + db->nextIn + copyCount,
1168 copyFragCount - copyCount);
1170 /* we have demux the stream into two separate ones */
1171 if (copy_two_channel_dac_from_user(s, buffer, copyCount))
1173 /* fill gaps with 0 */
1174 memset(db->lbuf + db->nextIn + copyCount,
1176 copyFragCount - copyCount);
1177 memset(db->rbuf + db->nextIn + copyCount,
1179 copyFragCount - copyCount);
1182 #if defined(VRC5477_AC97_VERBOSE_DEBUG)
1183 for (i=0; i< copyFragCount; i+= db->fragSize) {
1184 *(u16*)(db->lbuf + db->nextIn + i) = inTicket ++;
1189 totalCopyCount += copyCount;
1190 avail -= copyFragCount;
1191 totalCopyFragCount += copyFragCount;
1193 buffer += copyCount << (s->dacChannels - 1);
1195 db->nextIn += copyFragCount;
1196 if (db->nextIn >= db->fragTotalSize) {
1197 ASSERT(db->nextIn == db->fragTotalSize);
1201 ASSERT( (count == 0) || (copyCount == copyFragCount));
1204 spin_lock_irqsave(&s->lock, flags);
1205 db->count += totalCopyFragCount;
1210 /* nextIn should not be equal to nextOut unless we are full */
1211 ASSERT( ( (db->count == db->fragTotalSize) &&
1212 (db->nextIn == db->nextOut) ) ||
1213 ( (db->count < db->fragTotalSize) &&
1214 (db->nextIn != db->nextOut) ) );
1216 spin_unlock_irqrestore(&s->lock, flags);
1218 return totalCopyCount << (s->dacChannels-1);
1222 static ssize_t vrc5477_ac97_write(struct file *file, const char *buffer,
1223 size_t count, loff_t *ppos)
1225 struct vrc5477_ac97_state *s =
1226 (struct vrc5477_ac97_state *)file->private_data;
1227 struct dmabuf *db = &s->dma_dac;
1229 unsigned long flags;
1230 int copyCount, avail;
1232 if (ppos != &file->f_pos)
1234 if (!access_ok(VERIFY_READ, buffer, count))
1239 // wait for space in playback buffer
1241 spin_lock_irqsave(&s->lock, flags);
1242 avail = db->fragTotalSize - db->count;
1243 spin_unlock_irqrestore(&s->lock, flags);
1245 if (file->f_flags & O_NONBLOCK) {
1250 interruptible_sleep_on(&db->wait);
1251 if (signal_pending(current)) {
1257 } while (avail <= 0);
1259 copyCount = copy_dac_from_user(s, buffer, count, avail);
1260 if (copyCount < 0) {
1261 if (!ret) ret = -EFAULT;
1266 buffer += copyCount;
1268 } // while (count > 0)
1273 /* No kernel lock - we have our own spinlock */
1274 static unsigned int vrc5477_ac97_poll(struct file *file,
1275 struct poll_table_struct *wait)
1277 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data;
1278 unsigned long flags;
1279 unsigned int mask = 0;
1281 if (file->f_mode & FMODE_WRITE)
1282 poll_wait(file, &s->dma_dac.wait, wait);
1283 if (file->f_mode & FMODE_READ)
1284 poll_wait(file, &s->dma_adc.wait, wait);
1285 spin_lock_irqsave(&s->lock, flags);
1286 if (file->f_mode & FMODE_READ) {
1287 if (s->dma_adc.count >= (signed)s->dma_adc.fragSize)
1288 mask |= POLLIN | POLLRDNORM;
1290 if (file->f_mode & FMODE_WRITE) {
1291 if ((signed)s->dma_dac.fragTotalSize >=
1292 s->dma_dac.count + (signed)s->dma_dac.fragSize)
1293 mask |= POLLOUT | POLLWRNORM;
1295 spin_unlock_irqrestore(&s->lock, flags);
1299 #ifdef VRC5477_AC97_DEBUG
1300 static struct ioctl_str_t {
1304 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1305 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1306 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1307 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1308 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1309 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1310 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1311 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1312 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1313 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1314 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1315 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1316 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1317 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1318 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1319 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1320 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1321 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1322 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1323 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1324 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1325 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1326 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1327 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1328 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1329 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1330 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1331 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1332 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1333 {OSS_GETVERSION, "OSS_GETVERSION"},
1334 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1335 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1336 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1337 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1341 static int vrc5477_ac97_ioctl(struct inode *inode, struct file *file,
1342 unsigned int cmd, unsigned long arg)
1344 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data;
1345 unsigned long flags;
1346 audio_buf_info abinfo;
1350 #ifdef VRC5477_AC97_DEBUG
1351 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1352 if (ioctl_str[count].cmd == cmd)
1355 if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0]))
1356 printk(KERN_INFO PFX "ioctl %s\n", ioctl_str[count].str);
1358 printk(KERN_INFO PFX "ioctl unknown, 0x%x\n", cmd);
1362 case OSS_GETVERSION:
1363 return put_user(SOUND_VERSION, (int *)arg);
1365 case SNDCTL_DSP_SYNC:
1366 if (file->f_mode & FMODE_WRITE)
1367 return drain_dac(s, file->f_flags & O_NONBLOCK);
1370 case SNDCTL_DSP_SETDUPLEX:
1373 case SNDCTL_DSP_GETCAPS:
1374 return put_user(DSP_CAP_DUPLEX, (int *)arg);
1376 case SNDCTL_DSP_RESET:
1377 if (file->f_mode & FMODE_WRITE) {
1379 synchronize_irq(s->irq);
1380 s->dma_dac.count = 0;
1381 s->dma_dac.nextIn = s->dma_dac.nextOut = 0;
1383 if (file->f_mode & FMODE_READ) {
1385 synchronize_irq(s->irq);
1386 s->dma_adc.count = 0;
1387 s->dma_adc.nextIn = s->dma_adc.nextOut = 0;
1391 case SNDCTL_DSP_SPEED:
1392 if (get_user(val, (int *)arg))
1395 if (file->f_mode & FMODE_READ) {
1397 set_adc_rate(s, val);
1398 if ((ret = prog_dmabuf_adc(s)))
1401 if (file->f_mode & FMODE_WRITE) {
1403 set_dac_rate(s, val);
1404 if ((ret = prog_dmabuf_dac(s)))
1408 return put_user((file->f_mode & FMODE_READ) ?
1409 s->adcRate : s->dacRate, (int *)arg);
1411 case SNDCTL_DSP_STEREO:
1412 if (get_user(val, (int *)arg))
1414 if (file->f_mode & FMODE_READ) {
1420 if ((ret = prog_dmabuf_adc(s)))
1423 if (file->f_mode & FMODE_WRITE) {
1429 if ((ret = prog_dmabuf_dac(s)))
1434 case SNDCTL_DSP_CHANNELS:
1435 if (get_user(val, (int *)arg))
1438 if ( (val != 1) && (val != 2)) val = 2;
1440 if (file->f_mode & FMODE_READ) {
1442 s->dacChannels = val;
1443 if ((ret = prog_dmabuf_adc(s)))
1446 if (file->f_mode & FMODE_WRITE) {
1448 s->dacChannels = val;
1449 if ((ret = prog_dmabuf_dac(s)))
1453 return put_user(val, (int *)arg);
1455 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1456 return put_user(AFMT_S16_LE, (int *)arg);
1458 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1459 if (get_user(val, (int *)arg))
1461 if (val != AFMT_QUERY) {
1462 if (val != AFMT_S16_LE) return -EINVAL;
1463 if (file->f_mode & FMODE_READ) {
1465 if ((ret = prog_dmabuf_adc(s)))
1468 if (file->f_mode & FMODE_WRITE) {
1470 if ((ret = prog_dmabuf_dac(s)))
1476 return put_user(val, (int *)arg);
1478 case SNDCTL_DSP_POST:
1481 case SNDCTL_DSP_GETTRIGGER:
1482 case SNDCTL_DSP_SETTRIGGER:
1486 case SNDCTL_DSP_GETOSPACE:
1487 if (!(file->f_mode & FMODE_WRITE))
1489 abinfo.fragsize = s->dma_dac.fragSize << (s->dacChannels-1);
1490 spin_lock_irqsave(&s->lock, flags);
1491 count = s->dma_dac.count;
1492 spin_unlock_irqrestore(&s->lock, flags);
1493 abinfo.bytes = (s->dma_dac.fragTotalSize - count) <<
1495 abinfo.fragstotal = s->dma_dac.numFrag;
1496 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragShift >>
1498 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1500 case SNDCTL_DSP_GETISPACE:
1501 if (!(file->f_mode & FMODE_READ))
1503 abinfo.fragsize = s->dma_adc.fragSize << (s->adcChannels-1);
1504 spin_lock_irqsave(&s->lock, flags);
1505 count = s->dma_adc.count;
1506 spin_unlock_irqrestore(&s->lock, flags);
1509 abinfo.bytes = count << (s->adcChannels-1);
1510 abinfo.fragstotal = s->dma_adc.numFrag;
1511 abinfo.fragments = (abinfo.bytes >> s->dma_adc.fragShift) >>
1513 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1515 case SNDCTL_DSP_NONBLOCK:
1516 file->f_flags |= O_NONBLOCK;
1519 case SNDCTL_DSP_GETODELAY:
1520 if (!(file->f_mode & FMODE_WRITE))
1522 spin_lock_irqsave(&s->lock, flags);
1523 count = s->dma_dac.count;
1524 spin_unlock_irqrestore(&s->lock, flags);
1525 return put_user(count, (int *)arg);
1527 case SNDCTL_DSP_GETIPTR:
1528 case SNDCTL_DSP_GETOPTR:
1529 /* we cannot get DMA ptr */
1532 case SNDCTL_DSP_GETBLKSIZE:
1533 if (file->f_mode & FMODE_WRITE)
1534 return put_user(s->dma_dac.fragSize << (s->dacChannels-1), (int *)arg);
1536 return put_user(s->dma_adc.fragSize << (s->adcChannels-1), (int *)arg);
1538 case SNDCTL_DSP_SETFRAGMENT:
1539 /* we ignore fragment size request */
1542 case SNDCTL_DSP_SUBDIVIDE:
1543 /* what is this for? [jsun] */
1546 case SOUND_PCM_READ_RATE:
1547 return put_user((file->f_mode & FMODE_READ) ?
1548 s->adcRate : s->dacRate, (int *)arg);
1550 case SOUND_PCM_READ_CHANNELS:
1551 if (file->f_mode & FMODE_READ)
1552 return put_user(s->adcChannels, (int *)arg);
1554 return put_user(s->dacChannels ? 2 : 1, (int *)arg);
1556 case SOUND_PCM_READ_BITS:
1557 return put_user(16, (int *)arg);
1559 case SOUND_PCM_WRITE_FILTER:
1560 case SNDCTL_DSP_SETSYNCRO:
1561 case SOUND_PCM_READ_FILTER:
1565 return mixdev_ioctl(s->codec, cmd, arg);
1569 static int vrc5477_ac97_open(struct inode *inode, struct file *file)
1571 int minor = iminor(inode);
1572 DECLARE_WAITQUEUE(wait, current);
1573 unsigned long flags;
1574 struct list_head *list;
1575 struct vrc5477_ac97_state *s;
1578 for (list = devs.next; ; list = list->next) {
1581 s = list_entry(list, struct vrc5477_ac97_state, devs);
1582 if (!((s->dev_audio ^ minor) & ~0xf))
1585 file->private_data = s;
1587 /* wait for device to become free */
1589 while (s->open_mode & file->f_mode) {
1591 if (file->f_flags & O_NONBLOCK) {
1595 add_wait_queue(&s->open_wait, &wait);
1596 __set_current_state(TASK_INTERRUPTIBLE);
1599 remove_wait_queue(&s->open_wait, &wait);
1600 set_current_state(TASK_RUNNING);
1601 if (signal_pending(current))
1602 return -ERESTARTSYS;
1606 spin_lock_irqsave(&s->lock, flags);
1608 if (file->f_mode & FMODE_READ) {
1609 /* set default settings */
1610 set_adc_rate(s, 48000);
1613 ret = prog_dmabuf_adc(s);
1614 if (ret) goto bailout;
1616 if (file->f_mode & FMODE_WRITE) {
1617 /* set default settings */
1618 set_dac_rate(s, 48000);
1621 ret = prog_dmabuf_dac(s);
1622 if (ret) goto bailout;
1625 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1628 spin_unlock_irqrestore(&s->lock, flags);
1634 static int vrc5477_ac97_release(struct inode *inode, struct file *file)
1636 struct vrc5477_ac97_state *s =
1637 (struct vrc5477_ac97_state *)file->private_data;
1640 if (file->f_mode & FMODE_WRITE)
1641 drain_dac(s, file->f_flags & O_NONBLOCK);
1643 if (file->f_mode & FMODE_WRITE) {
1645 dealloc_dmabuf(s, &s->dma_dac);
1647 if (file->f_mode & FMODE_READ) {
1649 dealloc_dmabuf(s, &s->dma_adc);
1651 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
1653 wake_up(&s->open_wait);
1658 static /*const*/ struct file_operations vrc5477_ac97_audio_fops = {
1659 .owner = THIS_MODULE,
1660 .llseek = no_llseek,
1661 .read = vrc5477_ac97_read,
1662 .write = vrc5477_ac97_write,
1663 .poll = vrc5477_ac97_poll,
1664 .ioctl = vrc5477_ac97_ioctl,
1665 // .mmap = vrc5477_ac97_mmap,
1666 .open = vrc5477_ac97_open,
1667 .release = vrc5477_ac97_release,
1671 /* --------------------------------------------------------------------- */
1674 /* --------------------------------------------------------------------- */
1677 * for debugging purposes, we'll create a proc device that dumps the
1681 #ifdef VRC5477_AC97_DEBUG
1684 const char *regname;
1686 } vrc5477_ac97_regs[] = {
1687 {"VRC5477_INT_STATUS", VRC5477_INT_STATUS},
1688 {"VRC5477_CODEC_WR", VRC5477_CODEC_WR},
1689 {"VRC5477_CODEC_RD", VRC5477_CODEC_RD},
1690 {"VRC5477_CTRL", VRC5477_CTRL},
1691 {"VRC5477_ACLINK_CTRL", VRC5477_ACLINK_CTRL},
1692 {"VRC5477_INT_MASK", VRC5477_INT_MASK},
1693 {"VRC5477_DAC1_CTRL", VRC5477_DAC1_CTRL},
1694 {"VRC5477_DAC1L", VRC5477_DAC1L},
1695 {"VRC5477_DAC1_BADDR", VRC5477_DAC1_BADDR},
1696 {"VRC5477_DAC2_CTRL", VRC5477_DAC2_CTRL},
1697 {"VRC5477_DAC2L", VRC5477_DAC2L},
1698 {"VRC5477_DAC2_BADDR", VRC5477_DAC2_BADDR},
1699 {"VRC5477_DAC3_CTRL", VRC5477_DAC3_CTRL},
1700 {"VRC5477_DAC3L", VRC5477_DAC3L},
1701 {"VRC5477_DAC3_BADDR", VRC5477_DAC3_BADDR},
1702 {"VRC5477_ADC1_CTRL", VRC5477_ADC1_CTRL},
1703 {"VRC5477_ADC1L", VRC5477_ADC1L},
1704 {"VRC5477_ADC1_BADDR", VRC5477_ADC1_BADDR},
1705 {"VRC5477_ADC2_CTRL", VRC5477_ADC2_CTRL},
1706 {"VRC5477_ADC2L", VRC5477_ADC2L},
1707 {"VRC5477_ADC2_BADDR", VRC5477_ADC2_BADDR},
1708 {"VRC5477_ADC3_CTRL", VRC5477_ADC3_CTRL},
1709 {"VRC5477_ADC3L", VRC5477_ADC3L},
1710 {"VRC5477_ADC3_BADDR", VRC5477_ADC3_BADDR},
1714 static int proc_vrc5477_ac97_dump (char *buf, char **start, off_t fpos,
1715 int length, int *eof, void *data)
1717 struct vrc5477_ac97_state *s;
1720 if (list_empty(&devs))
1722 s = list_entry(devs.next, struct vrc5477_ac97_state, devs);
1724 /* print out header */
1725 len += sprintf(buf + len, "\n\t\tVrc5477 Audio Debug\n\n");
1727 // print out digital controller state
1728 len += sprintf (buf + len, "NEC Vrc5477 Audio Controller registers\n");
1729 len += sprintf (buf + len, "---------------------------------\n");
1730 for (cnt=0; vrc5477_ac97_regs[cnt].regname != NULL; cnt++) {
1731 len+= sprintf (buf + len, "%-20s = %08x\n",
1732 vrc5477_ac97_regs[cnt].regname,
1733 inl(s->io + vrc5477_ac97_regs[cnt].regaddr));
1736 /* print out driver state */
1737 len += sprintf (buf + len, "NEC Vrc5477 Audio driver states\n");
1738 len += sprintf (buf + len, "---------------------------------\n");
1739 len += sprintf (buf + len, "dacChannels = %d\n", s->dacChannels);
1740 len += sprintf (buf + len, "adcChannels = %d\n", s->adcChannels);
1741 len += sprintf (buf + len, "dacRate = %d\n", s->dacRate);
1742 len += sprintf (buf + len, "adcRate = %d\n", s->adcRate);
1744 len += sprintf (buf + len, "dma_dac is %s ready\n",
1745 s->dma_dac.ready? "" : "not");
1746 if (s->dma_dac.ready) {
1747 len += sprintf (buf + len, "dma_dac is %s stopped.\n",
1748 s->dma_dac.stopped? "" : "not");
1749 len += sprintf (buf + len, "dma_dac.fragSize = %x\n",
1750 s->dma_dac.fragSize);
1751 len += sprintf (buf + len, "dma_dac.fragShift = %x\n",
1752 s->dma_dac.fragShift);
1753 len += sprintf (buf + len, "dma_dac.numFrag = %x\n",
1754 s->dma_dac.numFrag);
1755 len += sprintf (buf + len, "dma_dac.fragTotalSize = %x\n",
1756 s->dma_dac.fragTotalSize);
1757 len += sprintf (buf + len, "dma_dac.nextIn = %x\n",
1759 len += sprintf (buf + len, "dma_dac.nextOut = %x\n",
1760 s->dma_dac.nextOut);
1761 len += sprintf (buf + len, "dma_dac.count = %x\n",
1765 len += sprintf (buf + len, "dma_adc is %s ready\n",
1766 s->dma_adc.ready? "" : "not");
1767 if (s->dma_adc.ready) {
1768 len += sprintf (buf + len, "dma_adc is %s stopped.\n",
1769 s->dma_adc.stopped? "" : "not");
1770 len += sprintf (buf + len, "dma_adc.fragSize = %x\n",
1771 s->dma_adc.fragSize);
1772 len += sprintf (buf + len, "dma_adc.fragShift = %x\n",
1773 s->dma_adc.fragShift);
1774 len += sprintf (buf + len, "dma_adc.numFrag = %x\n",
1775 s->dma_adc.numFrag);
1776 len += sprintf (buf + len, "dma_adc.fragTotalSize = %x\n",
1777 s->dma_adc.fragTotalSize);
1778 len += sprintf (buf + len, "dma_adc.nextIn = %x\n",
1780 len += sprintf (buf + len, "dma_adc.nextOut = %x\n",
1781 s->dma_adc.nextOut);
1782 len += sprintf (buf + len, "dma_adc.count = %x\n",
1786 /* print out CODEC state */
1787 len += sprintf (buf + len, "\nAC97 CODEC registers\n");
1788 len += sprintf (buf + len, "----------------------\n");
1789 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
1790 len+= sprintf (buf + len, "reg %02x = %04x\n",
1791 cnt, rdcodec(s->codec, cnt));
1798 *start = buf + fpos;
1799 if ((len -= fpos) > length)
1805 #endif /* VRC5477_AC97_DEBUG */
1807 /* --------------------------------------------------------------------- */
1809 /* maximum number of devices; only used for command line params */
1812 static unsigned int devindex;
1814 MODULE_AUTHOR("Monta Vista Software, jsun@mvista.com or jsun@junsun.net");
1815 MODULE_DESCRIPTION("NEC Vrc5477 audio (AC97) Driver");
1816 MODULE_LICENSE("GPL");
1818 static int __devinit vrc5477_ac97_probe(struct pci_dev *pcidev,
1819 const struct pci_device_id *pciid)
1821 struct vrc5477_ac97_state *s;
1822 #ifdef VRC5477_AC97_DEBUG
1826 if (pcidev->irq == 0)
1829 if (!(s = kmalloc(sizeof(struct vrc5477_ac97_state), GFP_KERNEL))) {
1830 printk(KERN_ERR PFX "alloc of device struct failed\n");
1833 memset(s, 0, sizeof(struct vrc5477_ac97_state));
1835 init_waitqueue_head(&s->dma_adc.wait);
1836 init_waitqueue_head(&s->dma_dac.wait);
1837 init_waitqueue_head(&s->open_wait);
1838 init_MUTEX(&s->open_sem);
1839 spin_lock_init(&s->lock);
1842 s->io = pci_resource_start(pcidev, 0);
1843 s->irq = pcidev->irq;
1845 s->codec = ac97_alloc_codec();
1847 s->codec->private_data = s;
1849 s->codec->codec_read = rdcodec;
1850 s->codec->codec_write = wrcodec;
1851 s->codec->codec_wait = waitcodec;
1853 /* setting some other default values such as
1854 * adcChannels, adcRate is done in open() so that
1855 * no persistent state across file opens.
1858 /* test if get response from ac97, if not return */
1859 if (ac97_codec_not_present(s->codec)) {
1860 printk(KERN_ERR PFX "no ac97 codec\n");
1865 if (!request_region(s->io, pci_resource_len(pcidev,0),
1866 VRC5477_AC97_MODULE_NAME)) {
1867 printk(KERN_ERR PFX "io ports %#lx->%#lx in use\n",
1868 s->io, s->io + pci_resource_len(pcidev,0)-1);
1871 if (request_irq(s->irq, vrc5477_ac97_interrupt, SA_INTERRUPT,
1872 VRC5477_AC97_MODULE_NAME, s)) {
1873 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
1877 printk(KERN_INFO PFX "IO at %#lx, IRQ %d\n", s->io, s->irq);
1879 /* register devices */
1880 if ((s->dev_audio = register_sound_dsp(&vrc5477_ac97_audio_fops, -1)) < 0)
1882 if ((s->codec->dev_mixer =
1883 register_sound_mixer(&vrc5477_ac97_mixer_fops, -1)) < 0)
1886 #ifdef VRC5477_AC97_DEBUG
1887 /* initialize the debug proc device */
1888 s->ps = create_proc_read_entry(VRC5477_AC97_MODULE_NAME, 0, NULL,
1889 proc_vrc5477_ac97_dump, NULL);
1890 #endif /* VRC5477_AC97_DEBUG */
1892 /* enable pci io and bus mastering */
1893 if (pci_enable_device(pcidev))
1895 pci_set_master(pcidev);
1897 /* cold reset the AC97 */
1898 outl(VRC5477_ACLINK_CTRL_RST_ON | VRC5477_ACLINK_CTRL_RST_TIME,
1899 s->io + VRC5477_ACLINK_CTRL);
1900 while (inl(s->io + VRC5477_ACLINK_CTRL) & VRC5477_ACLINK_CTRL_RST_ON);
1903 if (!ac97_probe_codec(s->codec))
1906 #ifdef VRC5477_AC97_DEBUG
1907 sprintf(proc_str, "driver/%s/%d/ac97",
1908 VRC5477_AC97_MODULE_NAME, s->codec->id);
1909 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
1910 ac97_read_proc, s->codec);
1911 /* TODO : why this proc file does not show up? */
1914 /* Try to enable variable rate audio mode. */
1915 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1916 rdcodec(s->codec, AC97_EXTENDED_STATUS) | AC97_EXTSTAT_VRA);
1917 /* Did we enable it? */
1918 if(rdcodec(s->codec, AC97_EXTENDED_STATUS) & AC97_EXTSTAT_VRA)
1919 s->extended_status |= AC97_EXTSTAT_VRA;
1922 printk(KERN_INFO PFX "VRA mode not enabled; rate fixed at %d.",
1926 /* let us get the default volumne louder */
1927 wrcodec(s->codec, 0x2, 0x1010); /* master volume, middle */
1928 wrcodec(s->codec, 0xc, 0x10); /* phone volume, middle */
1929 // wrcodec(s->codec, 0xe, 0x10); /* misc volume, middle */
1930 wrcodec(s->codec, 0x10, 0x8000); /* line-in 2 line-out disable */
1931 wrcodec(s->codec, 0x18, 0x0707); /* PCM out (line out) middle */
1934 /* by default we select line in the input */
1935 wrcodec(s->codec, 0x1a, 0x0404);
1936 wrcodec(s->codec, 0x1c, 0x0f0f);
1937 wrcodec(s->codec, 0x1e, 0x07);
1939 /* enable the master interrupt but disable all others */
1940 outl(VRC5477_INT_MASK_NMASK, s->io + VRC5477_INT_MASK);
1942 /* store it in the driver field */
1943 pci_set_drvdata(pcidev, s);
1944 pcidev->dma_mask = 0xffffffff;
1945 /* put it into driver list */
1946 list_add_tail(&s->devs, &devs);
1947 /* increment devindex */
1948 if (devindex < NR_DEVICE-1)
1953 unregister_sound_mixer(s->codec->dev_mixer);
1955 unregister_sound_dsp(s->dev_audio);
1957 printk(KERN_ERR PFX "cannot register misc device\n");
1958 free_irq(s->irq, s);
1960 release_region(s->io, pci_resource_len(pcidev,0));
1962 ac97_release_codec(codec);
1967 static void __devexit vrc5477_ac97_remove(struct pci_dev *dev)
1969 struct vrc5477_ac97_state *s = pci_get_drvdata(dev);
1975 #ifdef VRC5477_AC97_DEBUG
1977 remove_proc_entry(VRC5477_AC97_MODULE_NAME, NULL);
1978 #endif /* VRC5477_AC97_DEBUG */
1980 synchronize_irq(s->irq);
1981 free_irq(s->irq, s);
1982 release_region(s->io, pci_resource_len(dev,0));
1983 unregister_sound_dsp(s->dev_audio);
1984 unregister_sound_mixer(s->codec->dev_mixer);
1985 ac97_release_codec(s->codec);
1987 pci_set_drvdata(dev, NULL);
1991 static struct pci_device_id id_table[] = {
1992 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_VRC5477_AC97,
1993 PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
1997 MODULE_DEVICE_TABLE(pci, id_table);
1999 static struct pci_driver vrc5477_ac97_driver = {
2000 .name = VRC5477_AC97_MODULE_NAME,
2001 .id_table = id_table,
2002 .probe = vrc5477_ac97_probe,
2003 .remove = __devexit_p(vrc5477_ac97_remove),
2006 static int __init init_vrc5477_ac97(void)
2008 printk("Vrc5477 AC97 driver: version v0.2 time " __TIME__ " " __DATE__ " by Jun Sun\n");
2009 return pci_module_init(&vrc5477_ac97_driver);
2012 static void __exit cleanup_vrc5477_ac97(void)
2014 printk(KERN_INFO PFX "unloading\n");
2015 pci_unregister_driver(&vrc5477_ac97_driver);
2018 module_init(init_vrc5477_ac97);
2019 module_exit(cleanup_vrc5477_ac97);