2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU Library General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 Vortex core low level functions.
20 Author: Manuel Jander (mjander@users.sourceforge.cl)
21 These functions are mainly the result of translations made
22 from the original disassembly of the au88x0 binary drivers,
23 written by Aureal before they went down.
24 Many thanks to the Jeff Muizelar, Kester Maddock, and whoever
25 contributed to the OpenVortex project.
26 The author of this file, put the few available pieces together
27 and translated the rest of the riddle (Mix, Src and connection stuff).
28 Some things are still to be discovered, and their meanings are unclear.
30 Some of these functions aren't intended to be really used, rather
31 to help to understand how does the AU88X0 chips work. Keep them in, because
32 they could be used somewhere in the future.
34 This code hasn't been tested or proof read thoroughly. If you wanna help,
35 take a look at the AU88X0 assembly and check if this matches.
36 Functions tested ok so far are (they show the desired effect
38 vortex_routes(); (1 bug fixed).
39 vortex_adb_addroute();
40 vortex_adb_addroutes();
41 vortex_connect_codecplay();
42 vortex_src_flushbuffers();
43 vortex_adbdma_setmode(); note: still some unknown arguments!
44 vortex_adbdma_startfifo();
45 vortex_adbdma_stopfifo();
46 vortex_fifo_setadbctrl(); note: still some unknown arguments!
47 vortex_mix_setinputvolumebyte();
48 vortex_mix_enableinput();
49 vortex_mixer_addWTD(); (fixed)
50 vortex_connection_adbdma_src_src();
51 vortex_connection_adbdma_src();
52 vortex_src_change_convratio();
53 vortex_src_addWTD(); (fixed)
57 01-03-2003 First revision.
58 01-21-2003 Some bug fixes.
59 17-02-2003 many bugfixes after a big versioning mess.
60 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
61 (2 hours later...) I cant believe it! Im really lucky today.
62 Now the SRC is working too! Yeah! XMMS works !
63 20-02-2003 First steps into the ALSA world.
64 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
65 work :-). It was all wrong.
66 12-03-2003 ALSA driver starts working (2 channels).
67 16-03-2003 More srcblock_setupchannel discoveries.
68 12-04-2003 AU8830 playback support. Recording in the works.
69 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
70 works now, but chipn' dale effect is still there.
71 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
73 06-06-2003 Buffer shifter bugfix. Mixer volume fix.
74 07-12-2003 A3D routing finally fixed. Believed to be OK.
75 25-03-2004 Many thanks to Claudia, for such valuable bug reports.
80 #include "au88x0_a3d.h"
81 #include <linux/delay.h>
83 /* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
85 // FIXME: get rid of this.
86 static int mchannels[NR_MIXIN];
87 static int rampchs[NR_MIXIN];
89 static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
91 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
92 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
94 static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
96 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
97 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
102 vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
103 unsigned char channel)
105 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
107 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
111 static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
114 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
120 vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
121 int channel, int *vol)
124 if (!(mchannels[mix] & (1 << channel)))
126 a = hwread(vortex->mmio,
127 VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
129 if (rampchs[mix] == 0)
130 a = FP2LinearFrac(a);
132 a = FP2LinearFracWT(a);
138 static unsigned int vortex_mix_boost6db(unsigned char vol)
140 return (vol + 8); /* WOW! what a complex function! */
143 static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
147 // This function is intended for ramping down only (see vortex_disableinput()).
148 for (ch = 0; ch < 0x20; ch++) {
149 if (((1 << ch) & rampchs[mix]) == 0)
151 a = hwread(vortex->mmio,
152 VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
155 hwwrite(vortex->mmio,
157 (((mix << 5) + ch) << 2), a);
158 hwwrite(vortex->mmio,
160 (((mix << 5) + ch) << 2), a);
162 vortex_mix_killinput(vortex, mix, ch);
167 vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
174 addr = ((mix << 3) + (addr >> 2)) << 2;
175 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
176 return ((temp >> (mixin & 3)) & 1);
180 vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
184 hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
185 if (1) { /*if (this_10) */
186 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
187 if ((temp != 0x80) || (vol == 0x80))
190 hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
194 vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
195 int mixin, unsigned char vol)
199 hwwrite(vortex->mmio,
200 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
201 if (1) { /* this_10, initialized to 1. */
204 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
205 if ((temp != 0x80) || (vol == 0x80))
208 hwwrite(vortex->mmio,
209 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
213 vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
221 addr = ((mix << 3) + (addr >> 2)) << 2;
222 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
224 temp |= (1 << (mixin & 3));
226 temp &= ~(1 << (mixin & 3));
227 /* Mute input. Astatic void crackling? */
228 hwwrite(vortex->mmio,
229 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
230 /* Looks like clear buffer. */
231 hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
232 hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
233 /* Write enable bit. */
234 hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
238 vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
240 rampchs[mix] &= ~(1 << mixin);
241 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
242 mchannels[mix] &= ~(1 << mixin);
243 vortex_mix_setenablebit(vortex, mix, mixin, 0);
247 vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
249 vortex_mix_killinput(vortex, mix, mixin);
250 if ((mchannels[mix] & (1 << mixin)) == 0) {
251 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */
252 mchannels[mix] |= (1 << mixin);
254 vortex_mix_setenablebit(vortex, mix, mixin, 1);
258 vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
262 rampchs[mix] |= (1 << channel);
263 // Register callback.
264 //vortex_mix_startrampvolume(vortex);
265 vortex_mix_killinput(vortex, mix, channel);
267 vortex_mix_killinput(vortex, mix, channel);
271 vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
273 int temp, lifeboat = 0, prev;
275 temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
276 if ((temp & (1 << ch)) == 0) {
277 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
278 vortex_mixer_en_sr(vortex, ch);
281 prev = VORTEX_MIXER_CHNBASE + (ch << 2);
282 temp = hwread(vortex->mmio, prev);
283 while (temp & 0x10) {
284 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
285 temp = hwread(vortex->mmio, prev);
286 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
287 if ((++lifeboat) > 0xf) {
289 "vortex_mixer_addWTD: lifeboat overflow\n");
293 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
294 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
299 vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
301 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
302 //int esp1f=edi(while)=src, esp10=ch;
304 eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
305 if (((1 << ch) & eax) == 0) {
306 printk(KERN_ERR "mix ALARM %x\n", eax);
309 ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
310 esp18 = hwread(vortex->mmio, ebp);
314 ebx = VORTEX_MIXER_RTBASE + (mix << 2);
315 edx = hwread(vortex->mmio, ebx);
317 hwwrite(vortex->mmio, ebp, edx);
318 hwwrite(vortex->mmio, ebx, 0);
323 VORTEX_MIXER_RTBASE + (ebx << 2));
324 //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
325 while ((edx & 0xf) != mix) {
328 "vortex: mixdelWTD: error lifeboat overflow\n");
336 VORTEX_MIXER_RTBASE + ebp);
337 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
342 if (edx & 0x10) { /* Delete entry in between others */
343 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
344 edx = hwread(vortex->mmio, ebx);
346 hwwrite(vortex->mmio,
347 VORTEX_MIXER_RTBASE + ebp, edx);
348 hwwrite(vortex->mmio, ebx, 0);
349 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
350 } else { /* Delete last entry */
353 hwwrite(vortex->mmio,
354 VORTEX_MIXER_CHNBASE +
355 (ch << 2), esp18 & 0xef);
357 ebx = (0xffffffe0 & edx) | (0xf & ebx);
358 hwwrite(vortex->mmio,
359 VORTEX_MIXER_RTBASE +
361 //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
363 hwwrite(vortex->mmio,
364 VORTEX_MIXER_RTBASE + ebp, 0);
369 //printk(KERN_INFO "removed last mix\n");
371 vortex_mixer_dis_sr(vortex, ch);
372 hwwrite(vortex->mmio, ebp, 0);
377 static void vortex_mixer_init(vortex_t * vortex)
382 // FIXME: get rid of this crap.
383 memset(mchannels, 0, NR_MIXOUT * sizeof(int));
384 memset(rampchs, 0, NR_MIXOUT * sizeof(int));
386 addr = VORTEX_MIX_SMP + 0x17c;
387 for (x = 0x5f; x >= 0; x--) {
388 hwwrite(vortex->mmio, addr, 0);
391 addr = VORTEX_MIX_ENIN + 0x1fc;
392 for (x = 0x7f; x >= 0; x--) {
393 hwwrite(vortex->mmio, addr, 0);
396 addr = VORTEX_MIX_SMP + 0x17c;
397 for (x = 0x5f; x >= 0; x--) {
398 hwwrite(vortex->mmio, addr, 0);
401 addr = VORTEX_MIX_INVOL_A + 0x7fc;
402 for (x = 0x1ff; x >= 0; x--) {
403 hwwrite(vortex->mmio, addr, 0x80);
406 addr = VORTEX_MIX_VOL_A + 0x3c;
407 for (x = 0xf; x >= 0; x--) {
408 hwwrite(vortex->mmio, addr, 0x80);
411 addr = VORTEX_MIX_INVOL_B + 0x7fc;
412 for (x = 0x1ff; x >= 0; x--) {
413 hwwrite(vortex->mmio, addr, 0x80);
416 addr = VORTEX_MIX_VOL_B + 0x3c;
417 for (x = 0xf; x >= 0; x--) {
418 hwwrite(vortex->mmio, addr, 0x80);
421 addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
422 for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
423 hwwrite(vortex->mmio, addr, 0x0);
426 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
428 /* Set clipping ceiling (this may be all wrong). */
430 for (x = 0; x > 0x80; x++) {
431 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
435 call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
436 Register ISR callback for volume smooth fade out.
437 Maybe this avoids clicks when press "stop" ?
441 /* SRC (CAsp4Src.s and CAsp4SrcBlock) */
443 static void vortex_src_en_sr(vortex_t * vortex, int channel)
445 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
446 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
449 static void vortex_src_dis_sr(vortex_t * vortex, int channel)
451 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
452 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
455 static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
459 for (i = 0x1f; i >= 0; i--)
460 hwwrite(vortex->mmio,
461 VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
462 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
463 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
466 static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
468 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
469 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
470 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
474 vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
478 temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
483 hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
487 vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
489 int temp, lifeboat = 0;
492 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
493 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
494 if ((++lifeboat) > 0x9) {
495 printk(KERN_ERR "Vortex: Src cvr fail\n");
499 while (temp != ratio);
504 static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
508 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
509 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
510 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
512 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
517 vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
521 if ((ratio & 0x10000) && (ratio != 0x10000)) {
523 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
525 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
528 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
529 if (((temp >> 4) & 0xf) != a)
530 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
531 (temp & 0xf) | ((a & 0xf) << 4));
533 vortex_src_persist_convratio(vortex, src, ratio);
537 vortex_src_checkratio(vortex_t * vortex, unsigned char src,
538 unsigned int desired_ratio)
540 int hw_ratio, lifeboat = 0;
542 hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
544 while (hw_ratio != desired_ratio) {
545 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
547 if ((lifeboat++) > 15) {
548 printk(KERN_ERR "Vortex: could not set src-%d from %d to %d\n",
549 src, hw_ratio, desired_ratio);
559 Objective: Set samplerate for given SRC module.
561 card: pointer to vortex_t strcut.
562 src: Integer index of the SRC module.
563 cr: Current sample rate conversion factor.
564 b: unknown 16 bit value.
565 sweep: Enable Samplerate fade from cr toward tr flag.
566 dirplay: 1: playback, 0: recording.
568 tr: Target samplerate conversion.
569 thsource: Throttle source flag (no idea what that means).
571 static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
572 unsigned int cr, unsigned int b, int sweep, int d,
573 int dirplay, int sl, unsigned int tr, int thsource)
575 // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
576 // c: enables pitch sweep.
577 // looks like g is c related. Maybe g is a sweep parameter ?
579 // dirplay: 0 = recording, 1 = playback
582 int esi, ebp = 0, esp10;
584 vortex_src_flushbuffers(card, src);
587 if ((tr & 0x10000) && (tr != 0x10000)) {
591 if ((((short)tr) < 0) && (tr != 0x8000)) {
600 if ((cr & 0x10000) && (cr != 0x10000)) {
602 esi = 0x11 - ((cr >> 0xe) & 7);
612 vortex_src_cleardrift(card, src);
613 vortex_src_set_throttlesource(card, src, thsource);
615 if ((dirplay == 0) && (sweep == 0)) {
628 hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
629 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
630 /* 0xc0 esi=0xc c=f=0 d=0 */
631 vortex_src_persist_convratio(card, src, cr);
632 hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
634 hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
635 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
636 /* 0x30f00 e=g=1 esp10=0 ebp=f */
637 //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
640 static void vortex_srcblock_init(vortex_t * vortex)
644 hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
646 for (x=0; x<0x10; x++) {
647 vortex_src_init(&vortex_src[x], x);
652 addr = VORTEX_SRC_RTBASE + 0x3c;
653 for (x = 0xf; x >= 0; x--) {
654 hwwrite(vortex->mmio, addr, 0);
659 addr = VORTEX_SRC_CHNBASE + 0x54;
660 for (x = 0x15; x >= 0; x--) {
661 hwwrite(vortex->mmio, addr, 0);
667 vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
669 int temp, lifeboat = 0, prev;
672 temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
673 if ((temp & (1 << ch)) == 0) {
674 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
675 vortex_src_en_sr(vortex, ch);
678 prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */
679 temp = hwread(vortex->mmio, prev);
680 //while (temp & NR_SRC) {
681 while (temp & 0x10) {
682 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
683 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
684 temp = hwread(vortex->mmio, prev);
685 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
686 if ((++lifeboat) > 0xf) {
688 "vortex_src_addWTD: lifeboat overflow\n");
692 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
693 //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
694 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
699 vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
701 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
702 //int esp1f=edi(while)=src, esp10=ch;
704 eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
705 if (((1 << ch) & eax) == 0) {
706 printk(KERN_ERR "src alarm\n");
709 ebp = VORTEX_SRC_CHNBASE + (ch << 2);
710 esp18 = hwread(vortex->mmio, ebp);
714 ebx = VORTEX_SRC_RTBASE + (src << 2);
715 edx = hwread(vortex->mmio, ebx);
717 hwwrite(vortex->mmio, ebp, edx);
718 hwwrite(vortex->mmio, ebx, 0);
723 VORTEX_SRC_RTBASE + (ebx << 2));
724 //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
725 while ((edx & 0xf) != src) {
728 ("vortex: srcdelWTD: error, lifeboat overflow\n");
736 VORTEX_SRC_RTBASE + ebp);
737 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
742 if (edx & 0x10) { /* Delete entry in between others */
743 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
744 edx = hwread(vortex->mmio, ebx);
746 hwwrite(vortex->mmio,
747 VORTEX_SRC_RTBASE + ebp, edx);
748 hwwrite(vortex->mmio, ebx, 0);
749 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
750 } else { /* Delete last entry */
753 hwwrite(vortex->mmio,
755 (ch << 2), esp18 & 0xef);
757 ebx = (0xffffffe0 & edx) | (0xf & ebx);
758 hwwrite(vortex->mmio,
761 //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
763 hwwrite(vortex->mmio,
764 VORTEX_SRC_RTBASE + ebp, 0);
770 vortex_src_dis_sr(vortex, ch);
771 hwwrite(vortex->mmio, ebp, 0);
779 vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
781 for (x--; x >= 0; x--)
782 hwwrite(vortex->mmio,
783 VORTEX_FIFO_ADBDATA +
784 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
788 static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
790 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
792 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
793 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
795 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
796 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
800 static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
802 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
803 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
804 0xffffffef) | ((1 & en) << 4) | FIFO_U1);
808 vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int b, int priority,
809 int empty, int valid, int f)
811 int temp, lifeboat = 0;
812 //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
814 /* f seems priority related.
815 * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
816 * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
817 * is never called, thus the f related bits remain a mystery for now.
820 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
821 if (lifeboat++ > 0xbb8) {
823 "Vortex: vortex_fifo_setadbctrl fail\n");
827 while (temp & FIFO_RDONLY);
829 // AU8830 semes to take some special care about fifo content (data).
830 // But i'm just to lazy to translate that :)
832 if ((temp & FIFO_VALID) == 0) {
834 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4
836 temp = (this_4 & 0x1f) << 0xb;
838 temp = (this_4 & 0x3f) << 0xc;
840 temp = (temp & 0xfffffffd) | ((b & 1) << 1);
841 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
842 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
844 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
846 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
849 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
850 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
853 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
854 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
858 if (temp & FIFO_VALID) {
860 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
864 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
868 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
871 /*if (this_8[fifo]) */
872 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
874 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
875 hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
879 static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
883 for (x--; x >= 0; x--)
884 hwwrite(vortex->mmio,
886 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
889 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
891 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
893 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
894 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
896 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
897 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
901 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
903 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
904 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
905 0xffffffef) | ((en & 1) << 4) | FIFO_U1);
909 vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
910 int empty, int valid, int f)
912 int temp = 0, lifeboat = 0;
916 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
917 if (lifeboat++ > 0xbb8) {
918 printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail\n");
922 while (temp & FIFO_RDONLY);
925 if ((temp & FIFO_VALID) == 0) {
926 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4
928 temp = (this_4 & 0x1f) << 0xb;
930 temp = (this_4 & 0x3f) << 0xc;
932 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
933 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
934 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
936 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
938 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
941 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
942 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
945 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
946 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
950 if (temp & FIFO_VALID) {
952 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
956 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
960 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
963 /*if (this_8[fifo]) */
964 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
966 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
967 hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
971 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
972 if (lifeboat++ > 0xbb8) {
973 printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
976 } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
980 if (temp & FIFO_VALID) {
982 //temp |= 0x08000000;
983 //temp |= 0x10000000;
984 //temp |= 0x04000000;
985 //temp |= 0x00400000;
989 temp |= (valid & 1) << 4;
990 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
993 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
1002 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1003 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
1004 //((temp >> 6) & 0x3f)
1007 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
1008 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
1010 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1011 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1012 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1013 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1014 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1015 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1021 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1022 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1023 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1024 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1025 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1027 temp = temp | FIFO_BITS | 40000;
1029 // 0x1c440010, 0x1c400000
1030 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1035 static void vortex_fifo_init(vortex_t * vortex)
1040 /* ADB DMA channels fifos. */
1041 addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1042 for (x = NR_ADB - 1; x >= 0; x--) {
1043 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1044 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1045 printk(KERN_ERR "bad adb fifo reset!");
1046 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1051 /* WT DMA channels fifos. */
1052 addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1053 for (x = NR_WT - 1; x >= 0; x--) {
1054 hwwrite(vortex->mmio, addr, FIFO_U0);
1055 if (hwread(vortex->mmio, addr) != FIFO_U0)
1057 "bad wt fifo reset (0x%08lx, 0x%08x)!\n",
1058 addr, hwread(vortex->mmio, addr));
1059 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1065 hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b
1068 hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */
1069 hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */
1071 hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */
1077 static void vortex_adbdma_init(vortex_t * vortex)
1081 static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1083 stream_t *dma = &vortex->dma_adb[adbdma];
1085 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1089 static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1091 stream_t *dma = &vortex->dma_adb[adbdma];
1092 //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
1093 hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1094 sb << ((0xf - (adbdma & 0xf)) * 2));
1095 dma->period_real = dma->period_virt = sb;
1099 vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1100 snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1102 stream_t *dma = &vortex->dma_adb[adbdma];
1104 if (sgbuf == NULL) {
1105 printk(KERN_INFO "vortex: FATAL: sgbuf is NULL!\n");
1108 //printk(KERN_INFO "vortex: page count = %d, tblcount = %d\n", count, sgbuf->tblsize);
1110 dma->period_bytes = psize;
1111 dma->nr_periods = count;
1117 /* Four or more pages */
1120 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1121 hwwrite(vortex->mmio,
1122 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1123 snd_sgbuf_get_addr(sgbuf, psize * 3));
1126 dma->cfg0 |= 0x12000000;
1127 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1128 hwwrite(vortex->mmio,
1129 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1130 snd_sgbuf_get_addr(sgbuf, psize * 2));
1133 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1134 hwwrite(vortex->mmio,
1135 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1136 snd_sgbuf_get_addr(sgbuf, psize));
1139 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1140 hwwrite(vortex->mmio,
1141 VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1142 snd_sgbuf_get_addr(sgbuf, 0));
1145 //printk("vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", dma->cfg0, dma->cfg1);
1146 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1147 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1149 vortex_adbdma_setfirstbuffer(vortex, adbdma);
1150 vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1154 vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1155 int fmt, int d, unsigned long offset)
1157 stream_t *dma = &vortex->dma_adb[adbdma];
1159 dma->dma_unknown = d;
1161 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1162 /* Enable PCMOUT interrupts. */
1164 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1167 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1169 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1171 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1173 hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1176 static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1178 stream_t *dma = &vortex->dma_adb[adbdma];
1179 int page, p, pp, delta, i;
1182 (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1183 ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1184 if (dma->nr_periods >= 4)
1185 delta = (page - dma->period_real) & 3;
1187 delta = (page - dma->period_real);
1189 delta += dma->nr_periods;
1194 /* refresh hw page table */
1195 if (dma->nr_periods > 4) {
1196 for (i = 0; i < delta; i++) {
1197 /* p: audio buffer page index */
1198 p = dma->period_virt + i + 4;
1199 if (p >= dma->nr_periods)
1200 p -= dma->nr_periods;
1201 /* pp: hardware DMA page index. */
1202 pp = dma->period_real + i;
1205 //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1206 hwwrite(vortex->mmio,
1207 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1208 snd_sgbuf_get_addr(dma->sgbuf,
1209 dma->period_bytes * p));
1210 /* Force write thru cache. */
1211 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1212 (((adbdma << 2) + pp) << 2));
1215 dma->period_virt += delta;
1216 dma->period_real = page;
1217 if (dma->period_virt >= dma->nr_periods)
1218 dma->period_virt -= dma->nr_periods;
1220 printk(KERN_INFO "vortex: %d virt=%d, real=%d, delta=%d\n",
1221 adbdma, dma->period_virt, dma->period_real, delta);
1226 static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1228 stream_t *dma = &vortex->dma_adb[adbdma];
1231 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1232 temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK);
1236 static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1238 int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
1239 stream_t *dma = &vortex->dma_adb[adbdma];
1241 switch (dma->fifo_status) {
1243 vortex_fifo_setadbvalid(vortex, adbdma,
1244 dma->fifo_enabled ? 1 : 0);
1248 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1250 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1252 dma->fifo_enabled ? 1 : 0, 0);
1255 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1257 dma->fifo_enabled ? 1 : 0, 0);
1260 dma->fifo_status = FIFO_START;
1263 static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1265 stream_t *dma = &vortex->dma_adb[adbdma];
1267 int this_8 = 1, this_4 = 0;
1268 switch (dma->fifo_status) {
1270 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1272 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1274 dma->fifo_enabled ? 1 : 0, 0);
1277 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1279 dma->fifo_enabled ? 1 : 0, 0);
1282 dma->fifo_status = FIFO_START;
1285 static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1287 stream_t *dma = &vortex->dma_adb[adbdma];
1289 int this_8 = 0, this_4 = 0;
1290 switch (dma->fifo_status) {
1292 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1293 this_4, this_8, 0, 0);
1296 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1298 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1299 this_4, this_8, 0, 0);
1302 dma->fifo_status = FIFO_PAUSE;
1305 #if 0 // Using pause instead
1306 static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1308 stream_t *dma = &vortex->dma_adb[adbdma];
1310 int this_4 = 0, this_8 = 0;
1311 if (dma->fifo_status == FIFO_START)
1312 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1313 this_4, this_8, 0, 0);
1314 else if (dma->fifo_status == FIFO_STOP)
1316 dma->fifo_status = FIFO_STOP;
1317 dma->fifo_enabled = 0;
1324 static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1326 //int this_7c=dma_ctrl;
1327 stream_t *dma = &vortex->dma_wt[wtdma];
1329 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1332 static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1334 stream_t *dma = &vortex->dma_wt[wtdma];
1335 //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
1336 hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1337 sb << ((0xf - (wtdma & 0xf)) * 2));
1338 dma->period_real = dma->period_virt = sb;
1342 vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1343 snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1345 stream_t *dma = &vortex->dma_wt[wtdma];
1347 dma->period_bytes = psize;
1348 dma->nr_periods = count;
1354 /* Four or more pages */
1357 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1358 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
1359 snd_sgbuf_get_addr(sgbuf, psize * 3));
1362 dma->cfg0 |= 0x12000000;
1363 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1364 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8,
1365 snd_sgbuf_get_addr(sgbuf, psize * 2));
1368 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1369 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
1370 snd_sgbuf_get_addr(sgbuf, psize));
1373 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1374 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1375 snd_sgbuf_get_addr(sgbuf, 0));
1378 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1379 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1381 vortex_wtdma_setfirstbuffer(vortex, wtdma);
1382 vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1386 vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1387 /*int e, */ unsigned long offset)
1389 stream_t *dma = &vortex->dma_wt[wtdma];
1392 dma->dma_unknown = d;
1395 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1396 /* PCMOUT interrupt */
1398 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1399 /* Always playback. */
1400 dma->dma_ctrl |= (1 << DIR_SHIFT);
1403 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1404 /* Write into hardware */
1405 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1408 static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1410 stream_t *dma = &vortex->dma_wt[wtdma];
1411 int page, p, pp, delta, i;
1414 (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) &
1417 if (dma->nr_periods >= 4)
1418 delta = (page - dma->period_real) & 3;
1420 delta = (page - dma->period_real);
1422 delta += dma->nr_periods;
1427 /* refresh hw page table */
1428 if (dma->nr_periods > 4) {
1429 for (i = 0; i < delta; i++) {
1430 /* p: audio buffer page index */
1431 p = dma->period_virt + i + 4;
1432 if (p >= dma->nr_periods)
1433 p -= dma->nr_periods;
1434 /* pp: hardware DMA page index. */
1435 pp = dma->period_real + i;
1438 hwwrite(vortex->mmio,
1439 VORTEX_WTDMA_BUFBASE +
1440 (((wtdma << 2) + pp) << 2),
1441 snd_sgbuf_get_addr(dma->sgbuf, dma->period_bytes * p));
1442 /* Force write thru cache. */
1443 hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1444 (((wtdma << 2) + pp) << 2));
1447 dma->period_virt += delta;
1448 if (dma->period_virt >= dma->nr_periods)
1449 dma->period_virt -= dma->nr_periods;
1450 dma->period_real = page;
1453 printk(KERN_WARNING "vortex: wt virt = %d, delta = %d\n",
1454 dma->period_virt, delta);
1461 vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1464 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1465 *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1466 *pos = temp & POS_MASK;
1469 static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1471 return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1472 POS_SHIFT) & POS_MASK);
1475 static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1477 stream_t *dma = &vortex->dma_wt[wtdma];
1480 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1481 //temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK));
1482 temp = (temp & POS_MASK) + ((dma->period_virt) * (dma->period_bytes));
1486 static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1488 stream_t *dma = &vortex->dma_wt[wtdma];
1489 int this_8 = 0, this_4 = 0;
1491 switch (dma->fifo_status) {
1493 vortex_fifo_setwtvalid(vortex, wtdma,
1494 dma->fifo_enabled ? 1 : 0);
1498 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1500 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1502 dma->fifo_enabled ? 1 : 0, 0);
1505 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1507 dma->fifo_enabled ? 1 : 0, 0);
1510 dma->fifo_status = FIFO_START;
1513 static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1515 stream_t *dma = &vortex->dma_wt[wtdma];
1517 int this_8 = 0, this_4 = 0;
1518 switch (dma->fifo_status) {
1520 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1522 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1524 dma->fifo_enabled ? 1 : 0, 0);
1527 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1529 dma->fifo_enabled ? 1 : 0, 0);
1532 dma->fifo_status = FIFO_START;
1535 static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1537 stream_t *dma = &vortex->dma_wt[wtdma];
1539 int this_8 = 0, this_4 = 0;
1540 switch (dma->fifo_status) {
1542 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1543 this_4, this_8, 0, 0);
1546 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1548 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1549 this_4, this_8, 0, 0);
1552 dma->fifo_status = FIFO_PAUSE;
1555 static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1557 stream_t *dma = &vortex->dma_wt[wtdma];
1559 int this_4 = 0, this_8 = 0;
1560 if (dma->fifo_status == FIFO_START)
1561 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1562 this_4, this_8, 0, 0);
1563 else if (dma->fifo_status == FIFO_STOP)
1565 dma->fifo_status = FIFO_STOP;
1566 dma->fifo_enabled = 0;
1572 typedef int ADBRamLink;
1573 static void vortex_adb_init(vortex_t * vortex)
1576 /* it looks like we are writing more than we need to...
1577 * if we write what we are supposed to it breaks things... */
1578 hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1579 for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
1580 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1581 hwread(vortex->mmio,
1582 VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1583 for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
1584 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1585 hwread(vortex->mmio,
1586 VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1590 static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1592 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1593 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1596 static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1598 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1599 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1603 vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1604 ADBRamLink * route, int rnum)
1606 int temp, prev, lifeboat = 0;
1608 if ((rnum <= 0) || (route == NULL))
1610 /* Write last routes. */
1612 hwwrite(vortex->mmio,
1613 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1616 hwwrite(vortex->mmio,
1618 ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1621 /* Write first route. */
1623 hwread(vortex->mmio,
1624 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1625 if (temp == ADB_MASK) {
1626 /* First entry on this channel. */
1627 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1629 vortex_adb_en_sr(vortex, channel);
1632 /* Not first entry on this channel. Need to link. */
1636 hwread(vortex->mmio,
1637 VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1638 if ((lifeboat++) > ADB_MASK) {
1640 "vortex_adb_addroutes: unending route! 0x%x\n",
1645 while (temp != ADB_MASK);
1646 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1650 vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1651 ADBRamLink route0, ADBRamLink route1)
1653 int temp, lifeboat = 0, prev;
1657 hwread(vortex->mmio,
1658 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1659 if (temp == (route0 & ADB_MASK)) {
1661 hwread(vortex->mmio,
1662 VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1663 if ((temp & ADB_MASK) == ADB_MASK)
1664 vortex_adb_dis_sr(vortex, channel);
1665 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1672 hwread(vortex->mmio,
1673 VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1674 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1676 "vortex_adb_delroutes: route not found! 0x%x\n",
1681 while (temp != (route0 & ADB_MASK));
1682 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1683 if ((temp & ADB_MASK) == route1)
1684 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1685 /* Make bridge over deleted route. */
1686 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1690 vortex_route(vortex_t * vortex, int en, unsigned char channel,
1691 unsigned char source, unsigned char dest)
1695 route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1697 vortex_adb_addroutes(vortex, channel, &route, 1);
1698 if ((source < (OFFSET_SRCOUT + NR_SRC))
1699 && (source >= OFFSET_SRCOUT))
1700 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1702 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1703 && (source >= OFFSET_MIXOUT))
1704 vortex_mixer_addWTD(vortex,
1705 (source - OFFSET_MIXOUT), channel);
1707 vortex_adb_delroutes(vortex, channel, route, route);
1708 if ((source < (OFFSET_SRCOUT + NR_SRC))
1709 && (source >= OFFSET_SRCOUT))
1710 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1712 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1713 && (source >= OFFSET_MIXOUT))
1714 vortex_mixer_delWTD(vortex,
1715 (source - OFFSET_MIXOUT), channel);
1721 vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1722 unsigned char source, unsigned char dest0, unsigned char dest1)
1724 ADBRamLink route[2];
1726 route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1727 route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1730 vortex_adb_addroutes(vortex, channel, route, 2);
1731 if ((source < (OFFSET_SRCOUT + NR_SRC))
1732 && (source >= (OFFSET_SRCOUT)))
1733 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1735 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1736 && (source >= (OFFSET_MIXOUT)))
1737 vortex_mixer_addWTD(vortex,
1738 (source - OFFSET_MIXOUT), channel);
1740 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1741 if ((source < (OFFSET_SRCOUT + NR_SRC))
1742 && (source >= (OFFSET_SRCOUT)))
1743 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1745 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1746 && (source >= (OFFSET_MIXOUT)))
1747 vortex_mixer_delWTD(vortex,
1748 (source - OFFSET_MIXOUT), channel);
1753 /* Route two sources to same target. Sources must be of same class !!! */
1755 vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1756 unsigned char source0, unsigned char source1,
1759 ADBRamLink route[2];
1761 route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1762 route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1765 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */
1768 vortex_adb_addroutes(vortex, ch, route, 2);
1769 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1770 && (source0 >= OFFSET_SRCOUT)) {
1771 vortex_src_addWTD(vortex,
1772 (source0 - OFFSET_SRCOUT), ch);
1773 vortex_src_addWTD(vortex,
1774 (source1 - OFFSET_SRCOUT), ch);
1775 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1776 && (source0 >= OFFSET_MIXOUT)) {
1777 vortex_mixer_addWTD(vortex,
1778 (source0 - OFFSET_MIXOUT), ch);
1779 vortex_mixer_addWTD(vortex,
1780 (source1 - OFFSET_MIXOUT), ch);
1783 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1784 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1785 && (source0 >= OFFSET_SRCOUT)) {
1786 vortex_src_delWTD(vortex,
1787 (source0 - OFFSET_SRCOUT), ch);
1788 vortex_src_delWTD(vortex,
1789 (source1 - OFFSET_SRCOUT), ch);
1790 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1791 && (source0 >= OFFSET_MIXOUT)) {
1792 vortex_mixer_delWTD(vortex,
1793 (source0 - OFFSET_MIXOUT), ch);
1794 vortex_mixer_delWTD(vortex,
1795 (source1 - OFFSET_MIXOUT), ch);
1800 /* Connection stuff */
1802 // Connect adbdma to src('s).
1804 vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1805 unsigned char adbdma, unsigned char src)
1807 vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1810 // Connect SRC to mixin.
1812 vortex_connection_src_mixin(vortex_t * vortex, int en,
1813 unsigned char channel, unsigned char src,
1814 unsigned char mixin)
1816 vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1819 // Connect mixin with mix output.
1821 vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1822 unsigned char mix, int a)
1825 vortex_mix_enableinput(vortex, mix, mixin);
1826 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code.
1828 vortex_mix_disableinput(vortex, mix, mixin, a);
1831 // Connect absolut address to mixin.
1833 vortex_connection_adb_mixin(vortex_t * vortex, int en,
1834 unsigned char channel, unsigned char source,
1835 unsigned char mixin)
1837 vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1841 vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1842 unsigned char src, unsigned char adbdma)
1844 vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1848 vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1849 unsigned char ch, unsigned char src0,
1850 unsigned char src1, unsigned char adbdma)
1853 vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1857 // mix to absolut address.
1859 vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1860 unsigned char mix, unsigned char dest)
1862 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1863 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1868 vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1869 unsigned char mix, unsigned char src)
1871 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1872 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1877 vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1878 unsigned char channel,
1879 unsigned char adbdma, unsigned char src0,
1882 vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1883 ADB_SRCIN(src0), ADB_SRCIN(src1));
1886 // Connect two mix to AdbDma.
1888 vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1889 unsigned char ch, unsigned char mix0,
1890 unsigned char mix1, unsigned char adbdma)
1893 ADBRamLink routes[2];
1896 OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1898 (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1902 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1903 vortex_mixer_addWTD(vortex, mix0, ch);
1904 vortex_mixer_addWTD(vortex, mix1, ch);
1906 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1907 vortex_mixer_delWTD(vortex, mix0, ch);
1908 vortex_mixer_delWTD(vortex, mix1, ch);
1913 /* CODEC connect. */
1916 vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1919 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1920 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1923 // Connect front channels through EQ.
1924 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1925 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1926 /* Lower volume, since EQ has some gain. */
1927 vortex_mix_setvolumebyte(vortex, mixers[0], 0);
1928 vortex_mix_setvolumebyte(vortex, mixers[1], 0);
1929 vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1930 vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1932 /* Check if reg 0x28 has SDAC bit set. */
1933 if (VORTEX_IS_QUAD(vortex)) {
1934 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
1935 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1936 ADB_CODECOUT(0 + 4));
1937 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1938 ADB_CODECOUT(1 + 4));
1939 //printk("SDAC detected ");
1942 // Use plain direct output to codec.
1943 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1944 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1950 vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1951 unsigned char mixin1)
1956 ADB Source address: 0x48, 0x49
1957 Destination Asp4Topology_0x9c,0x98
1959 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1960 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1963 // Higher level ADB audio path (de)allocator.
1965 /* Resource manager */
1966 static int resnum[VORTEX_RESOURCE_LAST] =
1967 { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
1969 Checkout/Checkin resource of given type.
1970 resmap: resource map to be used. If NULL means that we want to allocate
1971 a DMA resource (root of all other resources of a dma channel).
1972 out: Mean checkout if != 0. Else mean Checkin resource.
1973 restype: Indicates type of resource to be checked in or out.
1976 vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
1978 int i, qty = resnum[restype], resinuse = 0;
1981 /* Gather used resources by all streams. */
1982 for (i = 0; i < NR_ADB; i++) {
1983 resinuse |= vortex->dma_adb[i].resources[restype];
1985 resinuse |= vortex->fixed_res[restype];
1986 /* Find and take free resource. */
1987 for (i = 0; i < qty; i++) {
1988 if ((resinuse & (1 << i)) == 0) {
1990 resmap[restype] |= (1 << i);
1992 vortex->dma_adb[i].resources[restype] |= (1 << i);
1993 //printk("vortex: ResManager: type %d out %d\n", restype, i);
2000 /* Checkin first resource of type restype. */
2001 for (i = 0; i < qty; i++) {
2002 if (resmap[restype] & (1 << i)) {
2003 resmap[restype] &= ~(1 << i);
2004 //printk("vortex: ResManager: type %d in %d\n",restype, i);
2009 printk("vortex: FATAL: ResManager: resource type %d exhausted.\n", restype);
2013 /* Default Connections */
2015 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type);
2017 static void vortex_connect_default(vortex_t * vortex, int en)
2019 // Connect AC97 codec.
2020 vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2021 VORTEX_RESOURCE_MIXOUT);
2022 vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2023 VORTEX_RESOURCE_MIXOUT);
2024 if (VORTEX_IS_QUAD(vortex)) {
2025 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2026 VORTEX_RESOURCE_MIXOUT);
2027 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2028 VORTEX_RESOURCE_MIXOUT);
2030 vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2032 vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2033 VORTEX_RESOURCE_MIXIN);
2034 vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2035 VORTEX_RESOURCE_MIXIN);
2036 vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2040 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2041 VORTEX_RESOURCE_MIXOUT);
2042 vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2043 VORTEX_RESOURCE_MIXOUT);
2044 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2046 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2051 vortex_wt_connect(vortex, en);
2053 // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now.
2055 vortex_Vort3D_connect(vortex, en);
2059 // Connect DSP interface for SQ3500 turbo (not here i think...)
2061 // Connect AC98 modem codec
2066 Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
2068 dma: DMA engine routes to be deallocated when dma >= 0.
2069 nr_ch: Number of channels to be de/allocated.
2070 dir: direction of stream. Uses same values as substream->stream.
2071 type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
2072 Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
2075 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type)
2081 || ((dir == SNDRV_PCM_STREAM_CAPTURE) && (nr_ch > 2)))
2086 vortex_adb_checkinout(vortex,
2087 vortex->dma_adb[dma].resources, en,
2088 VORTEX_RESOURCE_DMA);
2092 vortex_adb_checkinout(vortex, NULL, en,
2093 VORTEX_RESOURCE_DMA)) < 0)
2097 stream = &vortex->dma_adb[dma];
2100 stream->type = type;
2102 /* PLAYBACK ROUTES. */
2103 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2104 int src[4], mix[4], ch_top;
2108 /* Get SRC and MIXER hardware resources. */
2109 if (stream->type != VORTEX_PCM_SPDIF) {
2110 for (i = 0; i < nr_ch; i++) {
2111 if ((src[i] = vortex_adb_checkinout(vortex,
2112 stream->resources, en,
2113 VORTEX_RESOURCE_SRC)) < 0) {
2114 memset(stream->resources, 0,
2115 sizeof(unsigned char) *
2116 VORTEX_RESOURCE_LAST);
2119 if (stream->type != VORTEX_PCM_A3D) {
2120 if ((mix[i] = vortex_adb_checkinout(vortex,
2123 VORTEX_RESOURCE_MIXIN)) < 0) {
2124 memset(stream->resources,
2126 sizeof(unsigned char) * VORTEX_RESOURCE_LAST);
2133 if (stream->type == VORTEX_PCM_A3D) {
2135 vortex_adb_checkinout(vortex,
2136 stream->resources, en,
2137 VORTEX_RESOURCE_A3D)) < 0) {
2138 memset(stream->resources, 0,
2139 sizeof(unsigned char) *
2140 VORTEX_RESOURCE_LAST);
2141 printk("vortex: out of A3D sources. Sorry\n");
2144 /* (De)Initialize A3D hardware source. */
2145 vortex_Vort3D_InitializeSource(&(vortex->a3d[a3d]), en);
2147 /* Make SPDIF out exclusive to "spdif" device when in use. */
2148 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2149 vortex_route(vortex, 0, 0x14,
2150 ADB_MIXOUT(vortex->mixspdif[0]),
2152 vortex_route(vortex, 0, 0x14,
2153 ADB_MIXOUT(vortex->mixspdif[1]),
2157 /* Make playback routes. */
2158 for (i = 0; i < nr_ch; i++) {
2159 if (stream->type == VORTEX_PCM_ADB) {
2160 vortex_connection_adbdma_src(vortex, en,
2164 vortex_connection_src_mixin(vortex, en,
2167 vortex_connection_mixin_mix(vortex, en,
2171 vortex_connection_mixin_mix(vortex, en,
2173 MIX_SPDIF(i % 2), 0);
2174 vortex_mix_setinputvolumebyte(vortex,
2181 if (stream->type == VORTEX_PCM_A3D) {
2182 vortex_connection_adbdma_src(vortex, en,
2186 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2188 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
2189 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
2191 if (stream->type == VORTEX_PCM_SPDIF)
2192 vortex_route(vortex, en, 0x14,
2193 ADB_DMA(stream->dma),
2197 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2198 ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2199 for (i = nr_ch; i < ch_top; i++) {
2200 vortex_connection_mixin_mix(vortex, en,
2204 vortex_connection_mixin_mix(vortex, en,
2208 vortex_mix_setinputvolumebyte(vortex,
2217 if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2218 vortex_route(vortex, en, 0x14,
2219 ADB_DMA(stream->dma),
2222 /* Reconnect SPDIF out when "spdif" device is down. */
2223 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2224 vortex_route(vortex, 1, 0x14,
2225 ADB_MIXOUT(vortex->mixspdif[0]),
2227 vortex_route(vortex, 1, 0x14,
2228 ADB_MIXOUT(vortex->mixspdif[1]),
2232 /* CAPTURE ROUTES. */
2236 /* Get SRC and MIXER hardware resources. */
2237 for (i = 0; i < nr_ch; i++) {
2239 vortex_adb_checkinout(vortex,
2240 stream->resources, en,
2241 VORTEX_RESOURCE_MIXOUT))
2243 memset(stream->resources, 0,
2244 sizeof(unsigned char) *
2245 VORTEX_RESOURCE_LAST);
2249 vortex_adb_checkinout(vortex,
2250 stream->resources, en,
2251 VORTEX_RESOURCE_SRC)) < 0) {
2252 memset(stream->resources, 0,
2253 sizeof(unsigned char) *
2254 VORTEX_RESOURCE_LAST);
2259 /* Make capture routes. */
2260 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2261 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2263 vortex_connection_mixin_mix(vortex, en,
2264 MIX_CAPT(1), mix[0], 0);
2265 vortex_connection_src_adbdma(vortex, en,
2269 vortex_connection_mixin_mix(vortex, en,
2270 MIX_CAPT(1), mix[1], 0);
2271 vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2273 vortex_connection_src_src_adbdma(vortex, en,
2278 vortex->dma_adb[dma].nr_ch = nr_ch;
2281 /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
2283 /* Copy stereo to rear channel (surround) */
2284 snd_ac97_write_cache(vortex->codec,
2285 AC97_SIGMATEL_DAC2INVERT,
2286 snd_ac97_read(vortex->codec,
2287 AC97_SIGMATEL_DAC2INVERT)
2290 /* Allow separate front and rear channels. */
2291 snd_ac97_write_cache(vortex->codec,
2292 AC97_SIGMATEL_DAC2INVERT,
2293 snd_ac97_read(vortex->codec,
2294 AC97_SIGMATEL_DAC2INVERT)
2303 Set the SampleRate of the SRC's attached to the given DMA engine.
2306 vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2308 stream_t *stream = &(vortex->dma_adb[adbdma]);
2311 /* dir=1:play ; dir=0:rec */
2313 cvrt = SRC_RATIO(rate, 48000);
2315 cvrt = SRC_RATIO(48000, rate);
2318 for (i = 0; i < NR_SRC; i++) {
2319 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2320 vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2324 // Timer and ISR functions.
2326 static void vortex_settimer(vortex_t * vortex, int period)
2328 //set the timer period to <period> 48000ths of a second.
2329 hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2333 static void vortex_enable_timer_int(vortex_t * card)
2335 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2336 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2339 static void vortex_disable_timer_int(vortex_t * card)
2341 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2342 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2346 static void vortex_enable_int(vortex_t * card)
2348 // CAsp4ISR__EnableVortexInt_void_
2349 hwwrite(card->mmio, VORTEX_CTRL,
2350 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2351 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2352 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2355 static void vortex_disable_int(vortex_t * card)
2357 hwwrite(card->mmio, VORTEX_CTRL,
2358 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2361 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2363 vortex_t *vortex = dev_id;
2367 //check if the interrupt is ours.
2368 if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2371 // This is the Interrrupt Enable flag we set before (consistency check).
2372 if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2375 source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2377 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2378 hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2379 // Is at least one IRQ flag set?
2381 printk(KERN_ERR "vortex: missing irq source\n");
2386 // Attend every interrupt source.
2387 if (unlikely(source & IRQ_ERR_MASK)) {
2388 if (source & IRQ_FATAL) {
2389 printk(KERN_ERR "vortex: IRQ fatal error\n");
2391 if (source & IRQ_PARITY) {
2392 printk(KERN_ERR "vortex: IRQ parity error\n");
2394 if (source & IRQ_REG) {
2395 printk(KERN_ERR "vortex: IRQ reg error\n");
2397 if (source & IRQ_FIFO) {
2398 printk(KERN_ERR "vortex: IRQ fifo error\n");
2400 if (source & IRQ_DMA) {
2401 printk(KERN_ERR "vortex: IRQ dma error\n");
2405 if (source & IRQ_PCMOUT) {
2406 /* ALSA period acknowledge. */
2407 spin_lock(&vortex->lock);
2408 for (i = 0; i < NR_ADB; i++) {
2409 if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2410 if (vortex_adbdma_bufshift(vortex, i)) ;
2411 spin_unlock(&vortex->lock);
2412 snd_pcm_period_elapsed(vortex->dma_adb[i].
2414 spin_lock(&vortex->lock);
2418 for (i = 0; i < NR_WT; i++) {
2419 if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2420 if (vortex_wtdma_bufshift(vortex, i)) ;
2421 spin_unlock(&vortex->lock);
2422 snd_pcm_period_elapsed(vortex->dma_wt[i].
2424 spin_lock(&vortex->lock);
2428 spin_unlock(&vortex->lock);
2431 //Acknowledge the Timer interrupt
2432 if (source & IRQ_TIMER) {
2433 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2436 if (source & IRQ_MIDI) {
2437 snd_mpu401_uart_interrupt(vortex->irq,
2438 vortex->rmidi->private_data, regs);
2443 printk(KERN_ERR "vortex: unknown irq source %x\n", source);
2445 return IRQ_RETVAL(handled);
2450 #define POLL_COUNT 1000
2451 static void vortex_codec_init(vortex_t * vortex)
2455 for (i = 0; i < 32; i++) {
2456 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2460 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2462 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2465 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2467 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2469 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2471 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2473 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2475 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2477 for (i = 0; i < 32; i++) {
2478 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2481 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2483 /* Enable codec channels 0 and 1. */
2484 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2485 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2489 vortex_codec_write(ac97_t * codec, unsigned short addr, unsigned short data)
2492 vortex_t *card = (vortex_t *) codec->private_data;
2493 unsigned int lifeboat = 0;
2495 /* wait for transactions to clear */
2496 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2498 if (lifeboat++ > POLL_COUNT) {
2499 printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2503 /* write register */
2504 hwwrite(card->mmio, VORTEX_CODEC_IO,
2505 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2506 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2507 VORTEX_CODEC_WRITE);
2510 hwread(card->mmio, VORTEX_CODEC_IO);
2513 static unsigned short vortex_codec_read(ac97_t * codec, unsigned short addr)
2516 vortex_t *card = (vortex_t *) codec->private_data;
2517 u32 read_addr, data;
2518 unsigned lifeboat = 0;
2520 /* wait for transactions to clear */
2521 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2523 if (lifeboat++ > POLL_COUNT) {
2524 printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2528 /* set up read address */
2529 read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK);
2530 hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2532 /* wait for address */
2535 data = hwread(card->mmio, VORTEX_CODEC_IO);
2536 if (lifeboat++ > POLL_COUNT) {
2537 printk(KERN_ERR "vortex: ac97 address never arrived\n");
2540 } while ((data & VORTEX_CODEC_ADDMASK) !=
2541 (addr << VORTEX_CODEC_ADDSHIFT));
2544 return (u16) (data & VORTEX_CODEC_DATMASK);
2549 static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2551 int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2553 /* CAsp4Spdif::InitializeSpdifHardware(void) */
2554 hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2555 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2556 //for (i=0x291D4; i<0x29200; i+=4)
2557 for (i = 0; i < 11; i++)
2558 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2559 //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
2560 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2561 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2563 /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */
2564 if (this_04 && this_08) {
2567 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2576 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
2577 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2578 this_0c, 1, 0, edi, 1);
2579 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2580 this_0c, 1, 0, edi, 1);
2587 this_38 &= 0xFFFFFFFE;
2588 this_38 &= 0xFFFFFFFD;
2589 this_38 &= 0xF3FFFFFF;
2590 this_38 |= 0x03000000; /* set 32khz samplerate */
2591 this_38 &= 0xFFFFFF3F;
2592 spdif_sr &= 0xFFFFFFFD;
2596 this_38 &= 0xFFFFFFFE;
2597 this_38 &= 0xFFFFFFFD;
2598 this_38 &= 0xF0FFFFFF;
2599 this_38 |= 0x03000000;
2600 this_38 &= 0xFFFFFF3F;
2601 spdif_sr &= 0xFFFFFFFC;
2604 if (spdif_mode == 1) {
2605 this_38 &= 0xFFFFFFFE;
2606 this_38 &= 0xFFFFFFFD;
2607 this_38 &= 0xF2FFFFFF;
2608 this_38 |= 0x02000000; /* set 48khz samplerate */
2609 this_38 &= 0xFFFFFF3F;
2611 /* J. Gordon Wolfe: I think this stuff is for AC3 */
2612 this_38 |= 0x00000003;
2613 this_38 &= 0xFFFFFFBF;
2617 spdif_sr &= 0xFFFFFFFE;
2621 /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
2622 registers. seems to be for the standard IEC/SPDIF initialization
2624 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2625 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2626 hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2629 /* Initialization */
2631 static int vortex_core_init(vortex_t * vortex)
2634 printk(KERN_INFO "Vortex: init.... ");
2635 /* Hardware Init. */
2636 hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2638 hwwrite(vortex->mmio, VORTEX_CTRL,
2639 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2641 /* Reset IRQ flags */
2642 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2643 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2645 vortex_codec_init(vortex);
2648 hwwrite(vortex->mmio, VORTEX_CTRL,
2649 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2652 /* Init audio engine. */
2653 vortex_adbdma_init(vortex);
2654 hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
2655 vortex_adb_init(vortex);
2656 /* Init processing blocks. */
2657 vortex_fifo_init(vortex);
2658 vortex_mixer_init(vortex);
2659 vortex_srcblock_init(vortex);
2661 vortex_eq_init(vortex);
2662 vortex_spdif_init(vortex, 48000, 1);
2663 vortex_Vort3D(vortex, 1);
2666 vortex_wt_init(vortex);
2668 // Moved to au88x0.c
2669 //vortex_connect_default(vortex, 1);
2671 vortex_settimer(vortex, 0x90);
2672 // Enable Interrupts.
2673 // vortex_enable_int() must be first !!
2674 // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2675 // vortex_enable_int(vortex);
2676 //vortex_enable_timer_int(vortex);
2677 //vortex_disable_timer_int(vortex);
2679 printk(KERN_INFO "done.\n");
2680 spin_lock_init(&vortex->lock);
2685 static int vortex_core_shutdown(vortex_t * vortex)
2688 printk(KERN_INFO "Vortex: shutdown...");
2690 vortex_eq_free(vortex);
2691 vortex_Vort3D(vortex, 0);
2693 //vortex_disable_timer_int(vortex);
2694 vortex_disable_int(vortex);
2695 vortex_connect_default(vortex, 0);
2696 /* Reset all DMA fifos. */
2697 vortex_fifo_init(vortex);
2698 /* Erase all audio routes. */
2699 vortex_adb_init(vortex);
2701 /* Disable MPU401 */
2702 //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
2703 //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
2705 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2706 hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2708 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2710 printk(KERN_INFO "done.\n");
2716 static int vortex_alsafmt_aspfmt(int alsafmt)
2721 case SNDRV_PCM_FORMAT_U8:
2724 case SNDRV_PCM_FORMAT_MU_LAW:
2727 case SNDRV_PCM_FORMAT_A_LAW:
2730 case SNDRV_PCM_FORMAT_SPECIAL:
2731 fmt = 0x4; /* guess. */
2733 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2734 fmt = 0x5; /* guess. */
2736 case SNDRV_PCM_FORMAT_S16_LE:
2739 case SNDRV_PCM_FORMAT_S16_BE:
2740 fmt = 0x9; /* check this... */
2744 printk(KERN_ERR "vortex: format unsupported %d\n", alsafmt);
2750 /* Some not yet useful translations. */
2753 ASPFMTLINEAR16 = 0, /* 0x8 */
2754 ASPFMTLINEAR8, /* 0x1 */
2755 ASPFMTULAW, /* 0x2 */
2756 ASPFMTALAW, /* 0x3 */
2757 ASPFMTSPORT, /* ? */
2758 ASPFMTSPDIF, /* ? */
2762 vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2766 if ((bits != 8) || (bits != 16))
2802 static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2804 short int d, this_148;
2806 d = ((bits >> 3) * nch);
2807 this_148 = 0xbb80 / d;