2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <sound/driver.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/moduleparam.h>
31 #include <sound/core.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/rawmidi.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/opl3.h>
37 #include <sound/initval.h>
40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
42 MODULE_LICENSE("GPL");
43 MODULE_CLASSES("{sound}");
44 MODULE_DEVICES("{{Cirrus Logic,CS4281}}");
46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
49 static int dual_codec[SNDRV_CARDS]; /* dual codec */
52 module_param_array(index, int, boot_devs, 0444);
53 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
54 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
55 module_param_array(id, charp, boot_devs, 0444);
56 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
57 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
58 module_param_array(enable, bool, boot_devs, 0444);
59 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
60 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
61 module_param_array(dual_codec, bool, boot_devs, 0444);
62 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
63 MODULE_PARM_SYNTAX(dual_codec, SNDRV_ENABLED ",allows:{{0,3}}");
69 #ifndef PCI_VENDOR_ID_CIRRUS
70 #define PCI_VENDOR_ID_CIRRUS 0x1013
72 #ifndef PCI_DEVICE_ID_CIRRUS_4281
73 #define PCI_DEVICE_ID_CIRRUS_4281 0x6005
80 #define CS4281_BA0_SIZE 0x1000
81 #define CS4281_BA1_SIZE 0x10000
86 #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
87 #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
88 #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
89 #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
90 #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
91 #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
92 #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
93 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
94 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
95 #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
96 #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
97 #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
98 #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
100 #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
101 #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
102 #define BA0_HICR_IEV (1<<0) /* INTENA Value */
103 #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
105 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
106 /* Use same contants as for BA0_HISR */
108 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
110 #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
111 #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
112 #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
113 #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
115 #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
116 #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
117 #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
118 #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
119 #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
120 #define BA0_HDSR_RQ (1<<7) /* Pending Request */
122 #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
123 #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
124 #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
125 #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
126 #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
127 #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
128 #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
129 #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
130 #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
131 #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
132 #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
133 #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
134 #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
135 #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
136 #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
137 #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
138 #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
139 #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
140 #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
141 #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
142 #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
143 #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
144 #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
145 #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
147 #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
148 #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
149 #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
150 #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
151 #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
152 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
153 #define BA0_DMR_USIGN (1<<19) /* Unsigned */
154 #define BA0_DMR_BEND (1<<18) /* Big Endian */
155 #define BA0_DMR_MONO (1<<17) /* Mono */
156 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
157 #define BA0_DMR_TYPE_DEMAND (0<<6)
158 #define BA0_DMR_TYPE_SINGLE (1<<6)
159 #define BA0_DMR_TYPE_BLOCK (2<<6)
160 #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
161 #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
162 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
163 #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
164 #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
165 #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
167 #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
168 #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
169 #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
171 #define BA0_FCR0 0x0180 /* FIFO Control 0 */
172 #define BA0_FCR1 0x0184 /* FIFO Control 1 */
173 #define BA0_FCR2 0x0188 /* FIFO Control 2 */
174 #define BA0_FCR3 0x018c /* FIFO Control 3 */
176 #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
177 #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
178 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
179 #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
180 #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
181 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
182 #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
184 #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
185 #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
186 #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
187 #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
189 #define BA0_FCHS 0x020c /* FIFO Channel Status */
190 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
191 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
192 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
193 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
194 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
195 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
196 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
197 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
199 #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
200 #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
201 #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
202 #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
204 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
205 #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
206 #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
207 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
208 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
209 #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
210 #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
211 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
213 #define BA0_PMCS 0x0344 /* Power Management Control/Status */
214 #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
215 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
216 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
218 #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
219 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
220 #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
221 #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
222 #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
223 #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
224 #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
225 #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
226 #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
227 #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
229 #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
230 #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
231 #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
232 #define BA0_TMS 0x03f8 /* Test Register */
233 #define BA0_SSVID 0x03fc /* Subsystem ID register */
235 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
236 #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
237 #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
238 #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
239 #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
240 #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
241 #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
243 #define BA0_FRR 0x0410 /* Feature Reporting Register */
244 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
246 #define BA0_SERMC 0x0420 /* Serial Port Master Control */
247 #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
248 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
249 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
250 #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
251 #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
252 #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
253 #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
254 #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
255 #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
256 #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
257 #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
258 #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
260 #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
261 #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
262 #define BA0_SERC1_AC97 (1<<1)
263 #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
265 #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
266 #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
267 #define BA0_SERC2_AC97 (1<<1)
268 #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
270 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
272 #define BA0_ACCTL 0x0460 /* AC'97 Control */
273 #define BA0_ACCTL_TC (1<<6) /* Target Codec */
274 #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
275 #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
276 #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
277 #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
279 #define BA0_ACSTS 0x0464 /* AC'97 Status */
280 #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
281 #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
283 #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
284 #define BA0_ACOSV_SLV(x) (1<<((x)-3))
286 #define BA0_ACCAD 0x046c /* AC'97 Command Address */
287 #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
289 #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
290 #define BA0_ACISV_SLV(x) (1<<((x)-3))
292 #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
293 #define BA0_ACSDA 0x047c /* AC'97 Status Data */
294 #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
295 #define BA0_JSCTL 0x0484 /* Joystick control */
296 #define BA0_JSC1 0x0488 /* Joystick control */
297 #define BA0_JSC2 0x048c /* Joystick control */
298 #define BA0_JSIO 0x04a0
300 #define BA0_MIDCR 0x0490 /* MIDI Control */
301 #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
302 #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
303 #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
304 #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
305 #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
306 #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
308 #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
310 #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
311 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
312 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
313 #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
314 #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
316 #define BA0_MIDWP 0x0498 /* MIDI Write */
317 #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
319 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
320 #define BA0_AODSD1_NDS(x) (1<<((x)-3))
322 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
323 #define BA0_AODSD2_NDS(x) (1<<((x)-3))
325 #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
326 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
327 #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
328 #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
329 #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
330 #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
331 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
332 #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
333 #define BA0_FMDP 0x0734 /* FM Data Port */
334 #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
335 #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
337 #define BA0_SSPM 0x0740 /* Sound System Power Management */
338 #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
339 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
340 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
341 #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
342 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
343 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
345 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
346 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
348 #define BA0_SSCR 0x074c /* Sound System Control Register */
349 #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
350 #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
351 #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
352 #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
353 #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
354 #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
355 #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
356 #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
357 #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
359 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
360 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
361 #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
362 #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
363 #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
364 #define BA0_PASR 0x0768 /* playback sample rate */
365 #define BA0_CASR 0x076C /* capture sample rate */
367 /* Source Slot Numbers - Playback */
368 #define SRCSLOT_LEFT_PCM_PLAYBACK 0
369 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
370 #define SRCSLOT_PHONE_LINE_1_DAC 2
371 #define SRCSLOT_CENTER_PCM_PLAYBACK 3
372 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
373 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
374 #define SRCSLOT_LFE_PCM_PLAYBACK 6
375 #define SRCSLOT_PHONE_LINE_2_DAC 7
376 #define SRCSLOT_HEADSET_DAC 8
377 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
378 #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
380 /* Source Slot Numbers - Capture */
381 #define SRCSLOT_LEFT_PCM_RECORD 10
382 #define SRCSLOT_RIGHT_PCM_RECORD 11
383 #define SRCSLOT_PHONE_LINE_1_ADC 12
384 #define SRCSLOT_MIC_ADC 13
385 #define SRCSLOT_PHONE_LINE_2_ADC 17
386 #define SRCSLOT_HEADSET_ADC 18
387 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
388 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
389 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
390 #define SRCSLOT_SECONDARY_MIC_ADC 23
391 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
392 #define SRCSLOT_SECONDARY_HEADSET_ADC 28
394 /* Source Slot Numbers - Others */
395 #define SRCSLOT_POWER_DOWN 31
398 #define CS4281_MODE_OUTPUT (1<<0)
399 #define CS4281_MODE_INPUT (1<<1)
403 #define JSPT_CAX 0x00000001
404 #define JSPT_CAY 0x00000002
405 #define JSPT_CBX 0x00000004
406 #define JSPT_CBY 0x00000008
407 #define JSPT_BA1 0x00000010
408 #define JSPT_BA2 0x00000020
409 #define JSPT_BB1 0x00000040
410 #define JSPT_BB2 0x00000080
413 #define JSCTL_SP_MASK 0x00000003
414 #define JSCTL_SP_SLOW 0x00000000
415 #define JSCTL_SP_MEDIUM_SLOW 0x00000001
416 #define JSCTL_SP_MEDIUM_FAST 0x00000002
417 #define JSCTL_SP_FAST 0x00000003
418 #define JSCTL_ARE 0x00000004
420 /* Data register pairs masks */
421 #define JSC1_Y1V_MASK 0x0000FFFF
422 #define JSC1_X1V_MASK 0xFFFF0000
423 #define JSC1_Y1V_SHIFT 0
424 #define JSC1_X1V_SHIFT 16
425 #define JSC2_Y2V_MASK 0x0000FFFF
426 #define JSC2_X2V_MASK 0xFFFF0000
427 #define JSC2_Y2V_SHIFT 0
428 #define JSC2_X2V_SHIFT 16
431 #define JSIO_DAX 0x00000001
432 #define JSIO_DAY 0x00000002
433 #define JSIO_DBX 0x00000004
434 #define JSIO_DBY 0x00000008
435 #define JSIO_AXOE 0x00000010
436 #define JSIO_AYOE 0x00000020
437 #define JSIO_BXOE 0x00000040
438 #define JSIO_BYOE 0x00000080
444 #define chip_t cs4281_t
446 typedef struct snd_cs4281 cs4281_t;
447 typedef struct snd_cs4281_dma cs4281_dma_t;
449 struct snd_cs4281_dma {
450 snd_pcm_substream_t *substream;
451 unsigned int regDBA; /* offset to DBA register */
452 unsigned int regDCA; /* offset to DCA register */
453 unsigned int regDBC; /* offset to DBC register */
454 unsigned int regDCC; /* offset to DCC register */
455 unsigned int regDMR; /* offset to DMR register */
456 unsigned int regDCR; /* offset to DCR register */
457 unsigned int regHDSR; /* offset to HDSR register */
458 unsigned int regFCR; /* offset to FCR register */
459 unsigned int regFSIC; /* offset to FSIC register */
460 unsigned int valDMR; /* DMA mode */
461 unsigned int valDCR; /* DMA command */
462 unsigned int valFCR; /* FIFO control */
463 unsigned int fifo_offset; /* FIFO offset within BA1 */
464 unsigned char left_slot; /* FIFO left slot */
465 unsigned char right_slot; /* FIFO right slot */
466 int frag; /* period number */
469 #define SUSPEND_REGISTERS 20
474 unsigned long ba0; /* virtual (accessible) address */
475 unsigned long ba1; /* virtual (accessible) address */
476 unsigned long ba0_addr;
477 unsigned long ba1_addr;
478 struct resource *ba0_res;
479 struct resource *ba1_res;
483 ac97_bus_t *ac97_bus;
485 ac97_t *ac97_secondary;
490 snd_rawmidi_t *rmidi;
491 snd_rawmidi_substream_t *midi_input;
492 snd_rawmidi_substream_t *midi_output;
496 unsigned char src_left_play_slot;
497 unsigned char src_right_play_slot;
498 unsigned char src_left_rec_slot;
499 unsigned char src_right_rec_slot;
501 unsigned int spurious_dhtc_irq;
502 unsigned int spurious_dtc_irq;
508 struct snd_cs4281_gameport *gameport;
511 u32 suspend_regs[SUSPEND_REGISTERS];
516 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
518 static struct pci_device_id snd_cs4281_ids[] = {
519 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
523 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
529 #define CS4281_FIFO_SIZE 32
532 * common I/O routines
535 static void snd_cs4281_delay(unsigned int delay)
538 unsigned long end_time;
539 delay = (delay * HZ) / 1000000;
542 end_time = jiffies + delay;
544 set_current_state(TASK_UNINTERRUPTIBLE);
546 } while (time_after_eq(end_time, jiffies));
552 inline static void snd_cs4281_delay_long(void)
554 set_current_state(TASK_UNINTERRUPTIBLE);
558 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
560 writel(val, chip->ba0 + offset);
563 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
565 return readl(chip->ba0 + offset);
568 static void snd_cs4281_ac97_write(ac97_t *ac97,
569 unsigned short reg, unsigned short val)
572 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
573 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
574 * 3. Write ACCTL = Control Register = 460h for initiating the write
575 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
576 * 5. if DCV not cleared, break and return error
578 cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
582 * Setup the AC97 control registers on the CS461x to send the
583 * appropriate command to the AC97 to perform the read.
584 * ACCAD = Command Address Register = 46Ch
585 * ACCDA = Command Data Register = 470h
586 * ACCTL = Control Register = 460h
587 * set DCV - will clear when process completed
588 * reset CRW - Write command
589 * set VFRM - valid frame enabled
590 * set ESYN - ASYNC generation enabled
591 * set RSTN - ARST# inactive, AC97 codec not reset
593 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
594 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
595 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
596 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
597 for (count = 0; count < 2000; count++) {
599 * First, we want to wait for a short time.
603 * Now, check to see if the write has completed.
604 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
606 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
610 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
613 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
616 cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return -ENXIO);
618 unsigned short result;
619 // FIXME: volatile is necessary in the following due to a bug of
621 volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
624 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
625 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
626 * 3. Write ACCTL = Control Register = 460h for initiating the write
627 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
628 * 5. if DCV not cleared, break and return error
629 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
632 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
635 * Setup the AC97 control registers on the CS461x to send the
636 * appropriate command to the AC97 to perform the read.
637 * ACCAD = Command Address Register = 46Ch
638 * ACCDA = Command Data Register = 470h
639 * ACCTL = Control Register = 460h
640 * set DCV - will clear when process completed
641 * set CRW - Read command
642 * set VFRM - valid frame enabled
643 * set ESYN - ASYNC generation enabled
644 * set RSTN - ARST# inactive, AC97 codec not reset
647 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
648 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
649 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
650 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
651 (ac97_num ? BA0_ACCTL_TC : 0));
655 * Wait for the read to occur.
657 for (count = 0; count < 500; count++) {
659 * First, we want to wait for a short time.
663 * Now, check to see if the read has completed.
664 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
666 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
670 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
676 * Wait for the valid status bit to go active.
678 for (count = 0; count < 100; count++) {
680 * Read the AC97 status register.
681 * ACSTS = Status Register = 464h
682 * VSTS - Valid Status
684 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
689 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
695 * Read the data returned from the AC97 register.
696 * ACSDA = Status Data Register = 474h
698 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
708 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
710 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
711 cs4281_t *chip = snd_pcm_substream_chip(substream);
714 spin_lock_irqsave(&chip->reg_lock, flags);
716 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
717 dma->valDCR |= BA0_DCR_MSK;
718 dma->valFCR |= BA0_FCR_FEN;
720 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
721 dma->valDCR &= ~BA0_DCR_MSK;
722 dma->valFCR &= ~BA0_FCR_FEN;
724 case SNDRV_PCM_TRIGGER_START:
725 case SNDRV_PCM_TRIGGER_RESUME:
726 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
727 dma->valDMR |= BA0_DMR_DMA;
728 dma->valDCR &= ~BA0_DCR_MSK;
729 dma->valFCR |= BA0_FCR_FEN;
731 case SNDRV_PCM_TRIGGER_STOP:
732 case SNDRV_PCM_TRIGGER_SUSPEND:
733 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
734 dma->valDCR |= BA0_DCR_MSK;
735 dma->valFCR &= ~BA0_FCR_FEN;
736 /* Leave wave playback FIFO enabled for FM */
737 if (dma->regFCR != BA0_FCR0)
738 dma->valFCR &= ~BA0_FCR_FEN;
741 spin_unlock_irqrestore(&chip->reg_lock, flags);
744 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
745 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
746 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
747 spin_unlock_irqrestore(&chip->reg_lock, flags);
751 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
753 unsigned int val = ~0;
757 /* special "hardcoded" rates */
760 case 11025: return 4;
761 case 16000: return 3;
762 case 22050: return 2;
763 case 44100: return 1;
764 case 48000: return 0;
769 val = 1536000 / rate;
771 *real_rate = 1536000 / val;
775 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
779 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
780 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
781 if (runtime->channels == 1)
782 dma->valDMR |= BA0_DMR_MONO;
783 if (snd_pcm_format_unsigned(runtime->format) > 0)
784 dma->valDMR |= BA0_DMR_USIGN;
785 if (snd_pcm_format_big_endian(runtime->format) > 0)
786 dma->valDMR |= BA0_DMR_BEND;
787 switch (snd_pcm_format_width(runtime->format)) {
788 case 8: dma->valDMR |= BA0_DMR_SIZE8;
789 if (runtime->channels == 1)
790 dma->valDMR |= BA0_DMR_SWAPC;
792 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
794 dma->frag = 0; /* for workaround */
795 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
796 if (runtime->buffer_size != runtime->period_size)
797 dma->valDCR |= BA0_DCR_HTCIE;
799 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
800 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
801 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
802 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
803 (chip->src_right_play_slot << 8) |
804 (chip->src_left_rec_slot << 16) |
805 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
809 if (dma->left_slot == chip->src_left_play_slot) {
810 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
811 snd_assert(dma->right_slot == chip->src_right_play_slot, );
812 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
815 if (dma->left_slot == chip->src_left_rec_slot) {
816 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
817 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
818 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
822 /* Deactivate wave playback FIFO before changing slot assignments */
823 if (dma->regFCR == BA0_FCR0)
824 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
825 /* Initialize FIFO */
826 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
827 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
828 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
829 BA0_FCR_OF(dma->fifo_offset);
830 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
831 /* Activate FIFO again for FM playback */
832 if (dma->regFCR == BA0_FCR0)
833 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
834 /* Clear FIFO Status and Interrupt Control Register */
835 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
838 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
839 snd_pcm_hw_params_t * hw_params)
841 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
844 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
846 return snd_pcm_lib_free_pages(substream);
849 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
851 snd_pcm_runtime_t *runtime = substream->runtime;
852 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
853 cs4281_t *chip = snd_pcm_substream_chip(substream);
856 spin_lock_irqsave(&chip->reg_lock, flags);
857 snd_cs4281_mode(chip, dma, runtime, 0, 1);
858 spin_unlock_irqrestore(&chip->reg_lock, flags);
862 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
864 snd_pcm_runtime_t *runtime = substream->runtime;
865 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
866 cs4281_t *chip = snd_pcm_substream_chip(substream);
869 spin_lock_irqsave(&chip->reg_lock, flags);
870 snd_cs4281_mode(chip, dma, runtime, 1, 1);
871 spin_unlock_irqrestore(&chip->reg_lock, flags);
875 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
877 snd_pcm_runtime_t *runtime = substream->runtime;
878 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
879 cs4281_t *chip = snd_pcm_substream_chip(substream);
881 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
882 return runtime->buffer_size -
883 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
886 static snd_pcm_hardware_t snd_cs4281_playback =
888 .info = (SNDRV_PCM_INFO_MMAP |
889 SNDRV_PCM_INFO_INTERLEAVED |
890 SNDRV_PCM_INFO_MMAP_VALID |
891 SNDRV_PCM_INFO_PAUSE |
892 SNDRV_PCM_INFO_RESUME |
893 SNDRV_PCM_INFO_SYNC_START),
894 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
895 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
896 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
897 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
898 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
899 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
904 .buffer_bytes_max = (512*1024),
905 .period_bytes_min = 64,
906 .period_bytes_max = (512*1024),
909 .fifo_size = CS4281_FIFO_SIZE,
912 static snd_pcm_hardware_t snd_cs4281_capture =
914 .info = (SNDRV_PCM_INFO_MMAP |
915 SNDRV_PCM_INFO_INTERLEAVED |
916 SNDRV_PCM_INFO_MMAP_VALID |
917 SNDRV_PCM_INFO_PAUSE |
918 SNDRV_PCM_INFO_RESUME |
919 SNDRV_PCM_INFO_SYNC_START),
920 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
921 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
922 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
923 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
924 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
925 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
930 .buffer_bytes_max = (512*1024),
931 .period_bytes_min = 64,
932 .period_bytes_max = (512*1024),
935 .fifo_size = CS4281_FIFO_SIZE,
938 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
940 cs4281_t *chip = snd_pcm_substream_chip(substream);
941 snd_pcm_runtime_t *runtime = substream->runtime;
945 dma->substream = substream;
948 runtime->private_data = dma;
949 runtime->hw = snd_cs4281_playback;
950 snd_pcm_set_sync(substream);
951 /* should be detected from the AC'97 layer, but it seems
952 that although CS4297A rev B reports 18-bit ADC resolution,
953 samples are 20-bit */
954 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
958 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
960 cs4281_t *chip = snd_pcm_substream_chip(substream);
961 snd_pcm_runtime_t *runtime = substream->runtime;
965 dma->substream = substream;
967 dma->right_slot = 11;
968 runtime->private_data = dma;
969 runtime->hw = snd_cs4281_capture;
970 snd_pcm_set_sync(substream);
971 /* should be detected from the AC'97 layer, but it seems
972 that although CS4297A rev B reports 18-bit ADC resolution,
973 samples are 20-bit */
974 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
978 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
980 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
982 dma->substream = NULL;
986 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
988 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
990 dma->substream = NULL;
994 static snd_pcm_ops_t snd_cs4281_playback_ops = {
995 .open = snd_cs4281_playback_open,
996 .close = snd_cs4281_playback_close,
997 .ioctl = snd_pcm_lib_ioctl,
998 .hw_params = snd_cs4281_hw_params,
999 .hw_free = snd_cs4281_hw_free,
1000 .prepare = snd_cs4281_playback_prepare,
1001 .trigger = snd_cs4281_trigger,
1002 .pointer = snd_cs4281_pointer,
1005 static snd_pcm_ops_t snd_cs4281_capture_ops = {
1006 .open = snd_cs4281_capture_open,
1007 .close = snd_cs4281_capture_close,
1008 .ioctl = snd_pcm_lib_ioctl,
1009 .hw_params = snd_cs4281_hw_params,
1010 .hw_free = snd_cs4281_hw_free,
1011 .prepare = snd_cs4281_capture_prepare,
1012 .trigger = snd_cs4281_trigger,
1013 .pointer = snd_cs4281_pointer,
1016 static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1018 cs4281_t *chip = snd_magic_cast(cs4281_t, pcm->private_data, return);
1020 snd_pcm_lib_preallocate_free_for_all(pcm);
1023 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1030 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1034 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1035 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1037 pcm->private_data = chip;
1038 pcm->private_free = snd_cs4281_pcm_free;
1039 pcm->info_flags = 0;
1040 strcpy(pcm->name, "CS4281");
1043 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1044 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1055 #define CS_VOL_MASK 0x1f
1057 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1059 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1061 uinfo->value.integer.min = 0;
1062 uinfo->value.integer.max = CS_VOL_MASK;
1066 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1068 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1069 int regL = (kcontrol->private_value >> 16) & 0xffff;
1070 int regR = kcontrol->private_value & 0xffff;
1073 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1074 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1076 ucontrol->value.integer.value[0] = volL;
1077 ucontrol->value.integer.value[1] = volR;
1081 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1083 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1085 int regL = (kcontrol->private_value >> 16) & 0xffff;
1086 int regR = kcontrol->private_value & 0xffff;
1089 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1090 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1092 if (ucontrol->value.integer.value[0] != volL) {
1093 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1094 snd_cs4281_pokeBA0(chip, regL, volL);
1097 if (ucontrol->value.integer.value[0] != volL) {
1098 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1099 snd_cs4281_pokeBA0(chip, regR, volR);
1105 static snd_kcontrol_new_t snd_cs4281_fm_vol =
1107 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1108 .name = "Synth Playback Volume",
1109 .info = snd_cs4281_info_volume,
1110 .get = snd_cs4281_get_volume,
1111 .put = snd_cs4281_put_volume,
1112 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1115 static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1117 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1118 .name = "PCM Stream Playback Volume",
1119 .info = snd_cs4281_info_volume,
1120 .get = snd_cs4281_get_volume,
1121 .put = snd_cs4281_put_volume,
1122 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1125 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1127 cs4281_t *chip = snd_magic_cast(cs4281_t, bus->private_data, return);
1128 chip->ac97_bus = NULL;
1131 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1133 cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
1135 chip->ac97_secondary = NULL;
1140 static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1142 snd_card_t *card = chip->card;
1147 memset(&bus, 0, sizeof(bus));
1148 bus.write = snd_cs4281_ac97_write;
1149 bus.read = snd_cs4281_ac97_read;
1150 bus.private_data = chip;
1151 bus.private_free = snd_cs4281_mixer_free_ac97_bus;
1152 if ((err = snd_ac97_bus(card, &bus, &chip->ac97_bus)) < 0)
1155 memset(&ac97, 0, sizeof(ac97));
1156 ac97.private_data = chip;
1157 ac97.private_free = snd_cs4281_mixer_free_ac97;
1158 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1160 if (chip->dual_codec) {
1162 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1165 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1167 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1177 static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1178 snd_info_buffer_t * buffer)
1180 cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return);
1182 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1183 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1184 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1187 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1188 struct file *file, char __user *buf, long count)
1191 cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1194 if (file->f_pos + size > CS4281_BA0_SIZE)
1195 size = (long)CS4281_BA0_SIZE - file->f_pos;
1197 if (copy_to_user_fromio(buf, chip->ba0 + file->f_pos, size))
1199 file->f_pos += size;
1204 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1205 struct file *file, char __user *buf, long count)
1208 cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1211 if (file->f_pos + size > CS4281_BA1_SIZE)
1212 size = (long)CS4281_BA1_SIZE - file->f_pos;
1214 if (copy_to_user_fromio(buf, chip->ba1 + file->f_pos, size))
1216 file->f_pos += size;
1221 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1222 .read = snd_cs4281_BA0_read,
1225 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1226 .read = snd_cs4281_BA1_read,
1229 static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1231 snd_info_entry_t *entry;
1233 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1234 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1235 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1236 entry->content = SNDRV_INFO_CONTENT_DATA;
1237 entry->private_data = chip;
1238 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1239 entry->size = CS4281_BA0_SIZE;
1241 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1242 entry->content = SNDRV_INFO_CONTENT_DATA;
1243 entry->private_data = chip;
1244 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1245 entry->size = CS4281_BA1_SIZE;
1253 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1255 typedef struct snd_cs4281_gameport {
1256 struct gameport info;
1258 } cs4281_gameport_t;
1260 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1262 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1264 snd_assert(gp, return);
1265 chip = snd_magic_cast(cs4281_t, gp->chip, return);
1266 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1269 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1271 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1273 snd_assert(gp, return 0);
1274 chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1275 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1279 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1281 cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1283 unsigned js1, js2, jst;
1285 snd_assert(gp, return 0);
1286 chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1288 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1289 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1290 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1292 *buttons = (~jst >> 4) & 0x0F;
1294 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1295 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1296 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1297 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1299 for(jst=0;jst<4;++jst)
1300 if(axes[jst]==0xFFFF) axes[jst] = -1;
1305 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1309 case GAMEPORT_MODE_COOKED:
1312 case GAMEPORT_MODE_RAW:
1320 static void __devinit snd_cs4281_gameport(cs4281_t *chip)
1322 cs4281_gameport_t *gp;
1323 gp = kmalloc(sizeof(*gp), GFP_KERNEL);
1325 snd_printk(KERN_ERR "cannot allocate gameport area\n");
1328 memset(gp, 0, sizeof(*gp));
1329 gp->info.open = snd_cs4281_gameport_open;
1330 gp->info.read = snd_cs4281_gameport_read;
1331 gp->info.trigger = snd_cs4281_gameport_trigger;
1333 gp->info.cooked_read = snd_cs4281_gameport_cooked_read;
1336 chip->gameport = gp;
1338 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1339 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1340 gameport_register_port(&gp->info);
1344 #define snd_cs4281_gameport(chip) /*NOP*/
1345 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1352 static int snd_cs4281_free(cs4281_t *chip)
1354 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1355 if (chip->gameport) {
1356 gameport_unregister_port(&chip->gameport->info);
1357 kfree(chip->gameport);
1361 synchronize_irq(chip->irq);
1363 /* Mask interrupts */
1364 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1365 /* Stop the DLL Clock logic. */
1366 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1367 /* Sound System Power Management - Turn Everything OFF */
1368 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1369 /* PCI interface - D3 state */
1370 pci_set_power_state(chip->pci, 3);
1373 iounmap((void *) chip->ba0);
1375 iounmap((void *) chip->ba1);
1376 if (chip->ba0_res) {
1377 release_resource(chip->ba0_res);
1378 kfree_nocheck(chip->ba0_res);
1380 if (chip->ba1_res) {
1381 release_resource(chip->ba1_res);
1382 kfree_nocheck(chip->ba1_res);
1385 free_irq(chip->irq, (void *)chip);
1387 snd_magic_kfree(chip);
1391 static int snd_cs4281_dev_free(snd_device_t *device)
1393 cs4281_t *chip = snd_magic_cast(cs4281_t, device->device_data, return -ENXIO);
1394 return snd_cs4281_free(chip);
1397 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1399 static int cs4281_suspend(snd_card_t *card, unsigned int state);
1400 static int cs4281_resume(snd_card_t *card, unsigned int state);
1403 static int __devinit snd_cs4281_create(snd_card_t * card,
1404 struct pci_dev *pci,
1411 static snd_device_ops_t ops = {
1412 .dev_free = snd_cs4281_dev_free,
1416 if ((err = pci_enable_device(pci)) < 0)
1418 chip = snd_magic_kcalloc(cs4281_t, 0, GFP_KERNEL);
1421 spin_lock_init(&chip->reg_lock);
1425 chip->ba0_addr = pci_resource_start(pci, 0);
1426 chip->ba1_addr = pci_resource_start(pci, 1);
1427 pci_set_master(pci);
1428 if (dual_codec < 0 || dual_codec > 3) {
1429 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1432 chip->dual_codec = dual_codec;
1434 if ((chip->ba0_res = request_mem_region(chip->ba0_addr, CS4281_BA0_SIZE, "CS4281 BA0")) == NULL) {
1435 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba0_addr, chip->ba0_addr + CS4281_BA0_SIZE - 1);
1436 snd_cs4281_free(chip);
1439 if ((chip->ba1_res = request_mem_region(chip->ba1_addr, CS4281_BA1_SIZE, "CS4281 BA1")) == NULL) {
1440 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba1_addr, chip->ba1_addr + CS4281_BA1_SIZE - 1);
1441 snd_cs4281_free(chip);
1444 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1445 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1446 snd_cs4281_free(chip);
1449 chip->irq = pci->irq;
1451 chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, CS4281_BA0_SIZE);
1452 chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, CS4281_BA1_SIZE);
1453 if (!chip->ba0 || !chip->ba1) {
1454 snd_cs4281_free(chip);
1458 tmp = snd_cs4281_chip_init(chip);
1460 snd_cs4281_free(chip);
1464 snd_cs4281_proc_init(chip);
1466 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1468 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1469 snd_cs4281_free(chip);
1473 snd_card_set_dev(card, &pci->dev);
1479 static int snd_cs4281_chip_init(cs4281_t *chip)
1483 int retry_count = 2;
1486 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1487 if (tmp != BA0_CFLR_DEFAULT) {
1488 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1489 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1490 if (tmp != BA0_CFLR_DEFAULT) {
1491 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1496 /* Set the 'Configuration Write Protect' register
1497 * to 4281h. Allows vendor-defined configuration
1498 * space between 0e4h and 0ffh to be written. */
1499 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1501 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1502 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1505 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1506 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1510 /* Sound System Power Management */
1511 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1512 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1513 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1515 /* Serial Port Power Management */
1516 /* Blast the clock control register to zero so that the
1517 * PLL starts out in a known state, and blast the master serial
1518 * port control register to zero so that the serial ports also
1519 * start out in a known state. */
1520 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1521 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1523 /* Make ESYN go to zero to turn off
1524 * the Sync pulse on the AC97 link. */
1525 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1528 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1529 * spec) and then drive it high. This is done for non AC97 modes since
1530 * there might be logic external to the CS4281 that uses the ARST# line
1532 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1534 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1535 snd_cs4281_delay(50000);
1537 if (chip->dual_codec)
1538 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1541 * Set the serial port timing configuration.
1543 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1544 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1545 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1548 * Start the DLL Clock logic.
1550 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1551 snd_cs4281_delay(50000);
1552 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1555 * Wait for the DLL ready signal from the clock logic.
1560 * Read the AC97 status register to see if we've seen a CODEC
1561 * signal from the AC97 codec.
1563 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1565 snd_cs4281_delay_long();
1566 } while (timeout-- > 0);
1568 snd_printk(KERN_ERR "DLLRDY not seen\n");
1574 * The first thing we do here is to enable sync generation. As soon
1575 * as we start receiving bit clock, we'll start producing the SYNC
1578 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1581 * Wait for the codec ready signal from the AC97 codec.
1586 * Read the AC97 status register to see if we've seen a CODEC
1587 * signal from the AC97 codec.
1589 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1591 snd_cs4281_delay_long();
1592 } while (timeout-- > 0);
1594 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1598 if (chip->dual_codec) {
1601 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1603 snd_cs4281_delay_long();
1604 } while (timeout-- > 0);
1605 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1606 chip->dual_codec = 0;
1611 * Assert the valid frame signal so that we can start sending commands
1612 * to the AC97 codec.
1615 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1618 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1619 * the codec is pumping ADC data across the AC-link.
1625 * Read the input slot valid register and see if input slots 3
1628 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1630 snd_cs4281_delay_long();
1631 } while (timeout-- > 0);
1633 if (--retry_count > 0)
1635 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1641 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1642 * commense the transfer of digital audio data to the AC97 codec.
1644 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1647 * Initialize DMA structures
1649 for (tmp = 0; tmp < 4; tmp++) {
1650 cs4281_dma_t *dma = &chip->dma[tmp];
1651 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1652 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1653 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1654 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1655 dma->regDMR = BA0_DMR0 + (tmp * 8);
1656 dma->regDCR = BA0_DCR0 + (tmp * 8);
1657 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1658 dma->regFCR = BA0_FCR0 + (tmp * 4);
1659 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1660 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1661 snd_cs4281_pokeBA0(chip, dma->regFCR,
1664 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1665 BA0_FCR_OF(dma->fifo_offset));
1668 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1669 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1670 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1671 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1673 /* Activate wave playback FIFO for FM playback */
1674 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1676 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1677 BA0_FCR_OF(chip->dma[0].fifo_offset);
1678 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1679 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1680 (chip->src_right_play_slot << 8) |
1681 (chip->src_left_rec_slot << 16) |
1682 (chip->src_right_rec_slot << 24));
1684 /* Initialize digital volume */
1685 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1686 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1689 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1690 /* Unmask interrupts */
1691 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1698 synchronize_irq(chip->irq);
1707 static void snd_cs4281_midi_reset(cs4281_t *chip)
1709 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1711 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1714 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1716 unsigned long flags;
1717 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1719 spin_lock_irqsave(&chip->reg_lock, flags);
1720 chip->midcr |= BA0_MIDCR_RXE;
1721 chip->midi_input = substream;
1722 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1723 snd_cs4281_midi_reset(chip);
1725 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1727 spin_unlock_irqrestore(&chip->reg_lock, flags);
1731 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1733 unsigned long flags;
1734 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1736 spin_lock_irqsave(&chip->reg_lock, flags);
1737 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1738 chip->midi_input = NULL;
1739 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1740 snd_cs4281_midi_reset(chip);
1742 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1744 chip->uartm &= ~CS4281_MODE_INPUT;
1745 spin_unlock_irqrestore(&chip->reg_lock, flags);
1749 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1751 unsigned long flags;
1752 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1754 spin_lock_irqsave(&chip->reg_lock, flags);
1755 chip->uartm |= CS4281_MODE_OUTPUT;
1756 chip->midcr |= BA0_MIDCR_TXE;
1757 chip->midi_output = substream;
1758 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1759 snd_cs4281_midi_reset(chip);
1761 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1763 spin_unlock_irqrestore(&chip->reg_lock, flags);
1767 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1769 unsigned long flags;
1770 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1772 spin_lock_irqsave(&chip->reg_lock, flags);
1773 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1774 chip->midi_output = NULL;
1775 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1776 snd_cs4281_midi_reset(chip);
1778 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1780 chip->uartm &= ~CS4281_MODE_OUTPUT;
1781 spin_unlock_irqrestore(&chip->reg_lock, flags);
1785 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1787 unsigned long flags;
1788 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1790 spin_lock_irqsave(&chip->reg_lock, flags);
1792 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1793 chip->midcr |= BA0_MIDCR_RIE;
1794 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1797 if (chip->midcr & BA0_MIDCR_RIE) {
1798 chip->midcr &= ~BA0_MIDCR_RIE;
1799 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1802 spin_unlock_irqrestore(&chip->reg_lock, flags);
1805 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1807 unsigned long flags;
1808 cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1811 spin_lock_irqsave(&chip->reg_lock, flags);
1813 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1814 chip->midcr |= BA0_MIDCR_TIE;
1815 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1816 while ((chip->midcr & BA0_MIDCR_TIE) &&
1817 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1818 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1819 chip->midcr &= ~BA0_MIDCR_TIE;
1821 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1824 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1827 if (chip->midcr & BA0_MIDCR_TIE) {
1828 chip->midcr &= ~BA0_MIDCR_TIE;
1829 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1832 spin_unlock_irqrestore(&chip->reg_lock, flags);
1835 static snd_rawmidi_ops_t snd_cs4281_midi_output =
1837 .open = snd_cs4281_midi_output_open,
1838 .close = snd_cs4281_midi_output_close,
1839 .trigger = snd_cs4281_midi_output_trigger,
1842 static snd_rawmidi_ops_t snd_cs4281_midi_input =
1844 .open = snd_cs4281_midi_input_open,
1845 .close = snd_cs4281_midi_input_close,
1846 .trigger = snd_cs4281_midi_input_trigger,
1849 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1851 snd_rawmidi_t *rmidi;
1856 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1858 strcpy(rmidi->name, "CS4281");
1859 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1860 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1861 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1862 rmidi->private_data = chip;
1863 chip->rmidi = rmidi;
1873 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1875 cs4281_t *chip = snd_magic_cast(cs4281_t, dev_id, return IRQ_NONE);
1876 unsigned int status, dma, val;
1881 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1882 if ((status & 0x7fffffff) == 0) {
1883 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1887 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1888 for (dma = 0; dma < 4; dma++)
1889 if (status & BA0_HISR_DMA(dma)) {
1890 cdma = &chip->dma[dma];
1891 spin_lock(&chip->reg_lock);
1893 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1894 /* workaround, sometimes CS4281 acknowledges */
1895 /* end or middle transfer position twice */
1897 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1899 chip->spurious_dhtc_irq++;
1900 spin_unlock(&chip->reg_lock);
1903 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1905 chip->spurious_dtc_irq++;
1906 spin_unlock(&chip->reg_lock);
1909 spin_unlock(&chip->reg_lock);
1910 snd_pcm_period_elapsed(cdma->substream);
1914 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1917 spin_lock(&chip->reg_lock);
1918 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1919 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1920 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1922 snd_rawmidi_receive(chip->midi_input, &c, 1);
1924 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1925 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1927 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1928 chip->midcr &= ~BA0_MIDCR_TIE;
1929 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1932 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1934 spin_unlock(&chip->reg_lock);
1937 /* EOI to the PCI part... reenables interrupts */
1938 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1944 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1945 const struct pci_device_id *pci_id)
1953 if (dev >= SNDRV_CARDS)
1960 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1964 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1965 snd_card_free(card);
1969 if ((err = snd_cs4281_mixer(chip)) < 0) {
1970 snd_card_free(card);
1973 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1974 snd_card_free(card);
1977 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1978 snd_card_free(card);
1981 if ((err = snd_opl3_create(card,
1982 (chip->ba0 + BA0_B0AP) >> 2,
1983 (chip->ba0 + BA0_B1AP) >> 2,
1984 OPL3_HW_OPL3_CS4281, 1, &opl3)) < 0) {
1985 snd_card_free(card);
1988 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1989 snd_card_free(card);
1992 snd_cs4281_gameport(chip);
1993 strcpy(card->driver, "CS4281");
1994 strcpy(card->shortname, "Cirrus Logic CS4281");
1995 sprintf(card->longname, "%s at 0x%lx, irq %d",
2000 if ((err = snd_card_register(card)) < 0) {
2001 snd_card_free(card);
2005 pci_set_drvdata(pci, card);
2010 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2012 snd_card_free(pci_get_drvdata(pci));
2013 pci_set_drvdata(pci, NULL);
2021 static int saved_regs[SUSPEND_REGISTERS] = {
2037 #define number_of(array) (sizeof(array) / sizeof(array[0]))
2039 #define CLKCR1_CKRA 0x00010000L
2041 static int cs4281_suspend(snd_card_t *card, unsigned int state)
2043 cs4281_t *chip = snd_magic_cast(cs4281_t, card->pm_private_data, return -EINVAL);
2047 snd_pcm_suspend_all(chip->pcm);
2050 snd_ac97_suspend(chip->ac97);
2051 if (chip->ac97_secondary)
2052 snd_ac97_suspend(chip->ac97_secondary);
2054 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2055 ulCLK |= CLKCR1_CKRA;
2056 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2058 /* Disable interrupts. */
2059 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2061 /* remember the status registers */
2062 for (i = 0; i < number_of(saved_regs); i++)
2064 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2066 /* Turn off the serial ports. */
2067 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2069 /* Power off FM, Joystick, AC link, */
2070 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2073 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2076 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2078 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2079 ulCLK &= ~CLKCR1_CKRA;
2080 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2082 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2086 static int cs4281_resume(snd_card_t *card, unsigned int state)
2088 cs4281_t *chip = snd_magic_cast(cs4281_t, card->pm_private_data, return -EINVAL);
2092 pci_enable_device(chip->pci);
2094 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2095 ulCLK |= CLKCR1_CKRA;
2096 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2098 snd_cs4281_chip_init(chip);
2100 /* restore the status registers */
2101 for (i = 0; i < number_of(saved_regs); i++)
2103 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2106 snd_ac97_resume(chip->ac97);
2107 if (chip->ac97_secondary)
2108 snd_ac97_resume(chip->ac97_secondary);
2110 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2111 ulCLK &= ~CLKCR1_CKRA;
2112 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2114 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2117 #endif /* CONFIG_PM */
2119 static struct pci_driver driver = {
2121 .id_table = snd_cs4281_ids,
2122 .probe = snd_cs4281_probe,
2123 .remove = __devexit_p(snd_cs4281_remove),
2124 SND_PCI_PM_CALLBACKS
2127 static int __init alsa_card_cs4281_init(void)
2129 return pci_module_init(&driver);
2132 static void __exit alsa_card_cs4281_exit(void)
2134 pci_unregister_driver(&driver);
2137 module_init(alsa_card_cs4281_init)
2138 module_exit(alsa_card_cs4281_exit)