sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer controll.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <sound/driver.h>
  49 #include <linux/delay.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/init.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/slab.h>
  55 #include <linux/gameport.h>
  56
  57 #include <sound/core.h>
  58 #include <sound/control.h>
  59 #include <sound/info.h>
  60 #include <sound/pcm.h>
  61 #include <sound/pcm_params.h>
  62 #include <sound/cs46xx.h>
  63
  64 #include <asm/io.h>
  65
  66 #include "cs46xx_lib.h"
  67 #include "dsp_spos.h"
  68
  69 static void amp_voyetra(cs46xx_t *chip, int change);
  70
  71 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
  72                                             unsigned short reg,
  73                                             int codec_index)
  74 {
  75         int count;
  76         unsigned short result,tmp;
  77         u32 offset = 0;
  78         snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  79                      (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  80                      return -EINVAL);
  81
  82         chip->active_ctrl(chip, 1);
  83
  84         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  85                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
  86
  87         /*
  88          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  89          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
  90          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
  91          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  92          *  5. if DCV not cleared, break and return error
  93          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
  94          */
  95
  96         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
  97
  98         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
  99         if ((tmp & ACCTL_VFRM) == 0) {
 100                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
 101                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 102                 mdelay(50);
 103                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 104                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 105
 106         }
 107
 108         /*
 109          *  Setup the AC97 control registers on the CS461x to send the
 110          *  appropriate command to the AC97 to perform the read.
 111          *  ACCAD = Command Address Register = 46Ch
 112          *  ACCDA = Command Data Register = 470h
 113          *  ACCTL = Control Register = 460h
 114          *  set DCV - will clear when process completed
 115          *  set CRW - Read command
 116          *  set VFRM - valid frame enabled
 117          *  set ESYN - ASYNC generation enabled
 118          *  set RSTN - ARST# inactive, AC97 codec not reset
 119          */
 120
 121         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 122         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 123         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 124                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 125                                    ACCTL_VFRM | ACCTL_ESYN |
 126                                    ACCTL_RSTN);
 127                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 128                                    ACCTL_VFRM | ACCTL_ESYN |
 129                                    ACCTL_RSTN);
 130         } else {
 131                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 132                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 133                                    ACCTL_RSTN);
 134         }
 135
 136         /*
 137          *  Wait for the read to occur.
 138          */
 139         for (count = 0; count < 1000; count++) {
 140                 /*
 141                  *  First, we want to wait for a short time.
 142                  */
 143                 udelay(10);
 144                 /*
 145                  *  Now, check to see if the read has completed.
 146                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 147                  */
 148                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 149                         goto ok1;
 150         }
 151
 152         snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 153         result = 0xffff;
 154         goto end;
 155
 156  ok1:
 157         /*
 158          *  Wait for the valid status bit to go active.
 159          */
 160         for (count = 0; count < 100; count++) {
 161                 /*
 162                  *  Read the AC97 status register.
 163                  *  ACSTS = Status Register = 464h
 164                  *  VSTS - Valid Status
 165                  */
 166                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 167                         goto ok2;
 168                 udelay(10);
 169         }
 170
 171         snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 172         result = 0xffff;
 173         goto end;
 174
 175  ok2:
 176         /*
 177          *  Read the data returned from the AC97 register.
 178          *  ACSDA = Status Data Register = 474h
 179          */
 180 #if 0
 181         printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 182                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 183                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 184 #endif
 185
 186         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 187         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 188  end:
 189         chip->active_ctrl(chip, -1);
 190         return result;
 191 }
 192
 193 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
 194                                             unsigned short reg)
 195 {
 196         cs46xx_t *chip = ac97->private_data;
 197         unsigned short val;
 198         int codec_index = ac97->num;
 199
 200         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 201                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 202                    return 0xffff);
 203
 204         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 205
 206         return val;
 207 }
 208
 209
 210 static void snd_cs46xx_codec_write(cs46xx_t *chip,
 211                                    unsigned short reg,
 212                                    unsigned short val,
 213                                    int codec_index)
 214 {
 215         int count;
 216
 217         snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
 218                     (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
 219                     return);
 220
 221         chip->active_ctrl(chip, 1);
 222
 223         /*
 224          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 225          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 226          *  3. Write ACCTL = Control Register = 460h for initiating the write
 227          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 228          *  5. if DCV not cleared, break and return error
 229          */
 230
 231         /*
 232          *  Setup the AC97 control registers on the CS461x to send the
 233          *  appropriate command to the AC97 to perform the read.
 234          *  ACCAD = Command Address Register = 46Ch
 235          *  ACCDA = Command Data Register = 470h
 236          *  ACCTL = Control Register = 460h
 237          *  set DCV - will clear when process completed
 238          *  reset CRW - Write command
 239          *  set VFRM - valid frame enabled
 240          *  set ESYN - ASYNC generation enabled
 241          *  set RSTN - ARST# inactive, AC97 codec not reset
 242          */
 243         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 244         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 245         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 246
 247         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 248                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 249                                    ACCTL_ESYN | ACCTL_RSTN);
 250                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 251                                    ACCTL_ESYN | ACCTL_RSTN);
 252         } else {
 253                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 254                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 255         }
 256
 257         for (count = 0; count < 4000; count++) {
 258                 /*
 259                  *  First, we want to wait for a short time.
 260                  */
 261                 udelay(10);
 262                 /*
 263                  *  Now, check to see if the write has completed.
 264                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 265                  */
 266                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 267                         goto end;
 268                 }
 269         }
 270         snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 271  end:
 272         chip->active_ctrl(chip, -1);
 273 }
 274
 275 static void snd_cs46xx_ac97_write(ac97_t *ac97,
 276                                    unsigned short reg,
 277                                    unsigned short val)
 278 {
 279         cs46xx_t *chip = ac97->private_data;
 280         int codec_index = ac97->num;
 281
 282         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 283                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 284                    return);
 285
 286         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 287 }
 288
 289
 290 /*
 291  *  Chip initialization
 292  */
 293
 294 int snd_cs46xx_download(cs46xx_t *chip,
 295                         u32 *src,
 296                         unsigned long offset,
 297                         unsigned long len)
 298 {
 299         void __iomem *dst;
 300         unsigned int bank = offset >> 16;
 301         offset = offset & 0xffff;
 302
 303         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 304         dst = chip->region.idx[bank+1].remap_addr + offset;
 305         len /= sizeof(u32);
 306
 307         /* writel already converts 32-bit value to right endianess */
 308         while (len-- > 0) {
 309                 writel(*src++, dst);
 310                 dst += sizeof(u32);
 311         }
 312         return 0;
 313 }
 314
 315 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 316
 317 #include "imgs/cwc4630.h"
 318 #include "imgs/cwcasync.h"
 319 #include "imgs/cwcsnoop.h"
 320 #include "imgs/cwcbinhack.h"
 321 #include "imgs/cwcdma.h"
 322
 323 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
 324                          unsigned long offset,
 325                          unsigned long len)
 326 {
 327         void __iomem *dst;
 328         unsigned int bank = offset >> 16;
 329         offset = offset & 0xffff;
 330
 331         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 332         dst = chip->region.idx[bank+1].remap_addr + offset;
 333         len /= sizeof(u32);
 334
 335         /* writel already converts 32-bit value to right endianess */
 336         while (len-- > 0) {
 337                 writel(0, dst);
 338                 dst += sizeof(u32);
 339         }
 340         return 0;
 341 }
 342
 343 #else /* old DSP image */
 344
 345 #include "cs46xx_image.h"
 346
 347 int snd_cs46xx_download_image(cs46xx_t *chip)
 348 {
 349         int idx, err;
 350         unsigned long offset = 0;
 351
 352         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 353                 if ((err = snd_cs46xx_download(chip,
 354                                                &BA1Struct.map[offset],
 355                                                BA1Struct.memory[idx].offset,
 356                                                BA1Struct.memory[idx].size)) < 0)
 357                         return err;
 358                 offset += BA1Struct.memory[idx].size >> 2;
 359         }
 360         return 0;
 361 }
 362 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 363
 364 /*
 365  *  Chip reset
 366  */
 367
 368 static void snd_cs46xx_reset(cs46xx_t *chip)
 369 {
 370         int idx;
 371
 372         /*
 373          *  Write the reset bit of the SP control register.
 374          */
 375         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 376
 377         /*
 378          *  Write the control register.
 379          */
 380         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 381
 382         /*
 383          *  Clear the trap registers.
 384          */
 385         for (idx = 0; idx < 8; idx++) {
 386                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 387                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 388         }
 389         snd_cs46xx_poke(chip, BA1_DREG, 0);
 390
 391         /*
 392          *  Set the frame timer to reflect the number of cycles per frame.
 393          */
 394         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 395 }
 396
 397 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
 398 {
 399         u32 i, status = 0;
 400         /*
 401          * Make sure the previous FIFO write operation has completed.
 402          */
 403         for(i = 0; i < 50; i++){
 404                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 405
 406                 if( !(status & SERBST_WBSY) )
 407                         break;
 408
 409                 mdelay(retry_timeout);
 410         }
 411
 412         if(status & SERBST_WBSY) {
 413                 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
 414
 415                 return -EINVAL;
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
 422 {
 423         int idx, powerdown = 0;
 424         unsigned int tmp;
 425
 426         /*
 427          *  See if the devices are powered down.  If so, we must power them up first
 428          *  or they will not respond.
 429          */
 430         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 431         if (!(tmp & CLKCR1_SWCE)) {
 432                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 433                 powerdown = 1;
 434         }
 435
 436         /*
 437          *  We want to clear out the serial port FIFOs so we don't end up playing
 438          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 439          *  with zero (silence).
 440          */
 441         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 442
 443         /*
 444          *  Fill all 256 sample FIFO locations.
 445          */
 446         for (idx = 0; idx < 0xFF; idx++) {
 447                 /*
 448                  *  Make sure the previous FIFO write operation has completed.
 449                  */
 450                 if (cs46xx_wait_for_fifo(chip,1)) {
 451                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 452
 453                         if (powerdown)
 454                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 455
 456                         break;
 457                 }
 458                 /*
 459                  *  Write the serial port FIFO index.
 460                  */
 461                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 462                 /*
 463                  *  Tell the serial port to load the new value into the FIFO location.
 464                  */
 465                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 466         }
 467         /*
 468          *  Now, if we powered up the devices, then power them back down again.
 469          *  This is kinda ugly, but should never happen.
 470          */
 471         if (powerdown)
 472                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 473 }
 474
 475 static void snd_cs46xx_proc_start(cs46xx_t *chip)
 476 {
 477         int cnt;
 478
 479         /*
 480          *  Set the frame timer to reflect the number of cycles per frame.
 481          */
 482         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 483         /*
 484          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 485          *  the SP control register.
 486          */
 487         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 488         /*
 489          *  Wait until the run at frame bit resets itself in the SP control
 490          *  register.
 491          */
 492         for (cnt = 0; cnt < 25; cnt++) {
 493                 udelay(50);
 494                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 495                         break;
 496         }
 497
 498         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 499                 snd_printk("SPCR_RUNFR never reset\n");
 500 }
 501
 502 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
 503 {
 504         /*
 505          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 506          *  the SP control register.
 507          */
 508         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 509 }
 510
 511 /*
 512  *  Sample rate routines
 513  */
 514
 515 #define GOF_PER_SEC 200
 516
 517 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
 518 {
 519         unsigned long flags;
 520         unsigned int tmp1, tmp2;
 521         unsigned int phiIncr;
 522         unsigned int correctionPerGOF, correctionPerSec;
 523
 524         /*
 525          *  Compute the values used to drive the actual sample rate conversion.
 526          *  The following formulas are being computed, using inline assembly
 527          *  since we need to use 64 bit arithmetic to compute the values:
 528          *
 529          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 530          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 531          *                                   GOF_PER_SEC)
 532          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 533          *                       GOF_PER_SEC * correctionPerGOF
 534          *
 535          *  i.e.
 536          *
 537          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 538          *  correctionPerGOF:correctionPerSec =
 539          *      dividend:remainder(ulOther / GOF_PER_SEC)
 540          */
 541         tmp1 = rate << 16;
 542         phiIncr = tmp1 / 48000;
 543         tmp1 -= phiIncr * 48000;
 544         tmp1 <<= 10;
 545         phiIncr <<= 10;
 546         tmp2 = tmp1 / 48000;
 547         phiIncr += tmp2;
 548         tmp1 -= tmp2 * 48000;
 549         correctionPerGOF = tmp1 / GOF_PER_SEC;
 550         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 551         correctionPerSec = tmp1;
 552
 553         /*
 554          *  Fill in the SampleRateConverter control block.
 555          */
 556         spin_lock_irqsave(&chip->reg_lock, flags);
 557         snd_cs46xx_poke(chip, BA1_PSRC,
 558           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 559         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 560         spin_unlock_irqrestore(&chip->reg_lock, flags);
 561 }
 562
 563 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
 564 {
 565         unsigned long flags;
 566         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 567         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 568         unsigned int frameGroupLength, cnt;
 569
 570         /*
 571          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 572          *  Correct the value if an attempt is made to stray outside that limit.
 573          */
 574         if ((rate * 9) < 48000)
 575                 rate = 48000 / 9;
 576
 577         /*
 578          *  We can not capture at at rate greater than the Input Rate (48000).
 579          *  Return an error if an attempt is made to stray outside that limit.
 580          */
 581         if (rate > 48000)
 582                 rate = 48000;
 583
 584         /*
 585          *  Compute the values used to drive the actual sample rate conversion.
 586          *  The following formulas are being computed, using inline assembly
 587          *  since we need to use 64 bit arithmetic to compute the values:
 588          *
 589          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 590          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 591          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 592          *                                GOF_PER_SEC)
 593          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 594          *                          GOF_PER_SEC * correctionPerGOF
 595          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 596          *
 597          * i.e.
 598          *
 599          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 600          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 601          *     correctionPerGOF:correctionPerSec =
 602          *          dividend:remainder(ulOther / GOF_PER_SEC)
 603          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 604          */
 605
 606         tmp1 = rate << 16;
 607         coeffIncr = tmp1 / 48000;
 608         tmp1 -= coeffIncr * 48000;
 609         tmp1 <<= 7;
 610         coeffIncr <<= 7;
 611         coeffIncr += tmp1 / 48000;
 612         coeffIncr ^= 0xFFFFFFFF;
 613         coeffIncr++;
 614         tmp1 = 48000 << 16;
 615         phiIncr = tmp1 / rate;
 616         tmp1 -= phiIncr * rate;
 617         tmp1 <<= 10;
 618         phiIncr <<= 10;
 619         tmp2 = tmp1 / rate;
 620         phiIncr += tmp2;
 621         tmp1 -= tmp2 * rate;
 622         correctionPerGOF = tmp1 / GOF_PER_SEC;
 623         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 624         correctionPerSec = tmp1;
 625         initialDelay = ((48000 * 24) + rate - 1) / rate;
 626
 627         /*
 628          *  Fill in the VariDecimate control block.
 629          */
 630         spin_lock_irqsave(&chip->reg_lock, flags);
 631         snd_cs46xx_poke(chip, BA1_CSRC,
 632                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 633         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 634         snd_cs46xx_poke(chip, BA1_CD,
 635                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 636         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 637         spin_unlock_irqrestore(&chip->reg_lock, flags);
 638
 639         /*
 640          *  Figure out the frame group length for the write back task.  Basically,
 641          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 642          *  the output sample rate.
 643          */
 644         frameGroupLength = 1;
 645         for (cnt = 2; cnt <= 64; cnt *= 2) {
 646                 if (((rate / cnt) * cnt) != rate)
 647                         frameGroupLength *= 2;
 648         }
 649         if (((rate / 3) * 3) != rate) {
 650                 frameGroupLength *= 3;
 651         }
 652         for (cnt = 5; cnt <= 125; cnt *= 5) {
 653                 if (((rate / cnt) * cnt) != rate)
 654                         frameGroupLength *= 5;
 655         }
 656
 657         /*
 658          * Fill in the WriteBack control block.
 659          */
 660         spin_lock_irqsave(&chip->reg_lock, flags);
 661         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 662         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 663         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 664         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 665         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 666         spin_unlock_irqrestore(&chip->reg_lock, flags);
 667 }
 668
 669 /*
 670  *  PCM part
 671  */
 672
 673 static void snd_cs46xx_pb_trans_copy(snd_pcm_substream_t *substream,
 674                                      snd_pcm_indirect_t *rec, size_t bytes)
 675 {
 676         snd_pcm_runtime_t *runtime = substream->runtime;
 677         cs46xx_pcm_t * cpcm = runtime->private_data;
 678         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 679 }
 680
 681 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
 682 {
 683         snd_pcm_runtime_t *runtime = substream->runtime;
 684         cs46xx_pcm_t * cpcm = runtime->private_data;
 685         snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
 686         return 0;
 687 }
 688
 689 static void snd_cs46xx_cp_trans_copy(snd_pcm_substream_t *substream,
 690                                      snd_pcm_indirect_t *rec, size_t bytes)
 691 {
 692         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 693         snd_pcm_runtime_t *runtime = substream->runtime;
 694         memcpy(runtime->dma_area + rec->sw_data,
 695                chip->capt.hw_buf.area + rec->hw_data, bytes);
 696 }
 697
 698 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
 699 {
 700         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 701         snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
 702         return 0;
 703 }
 704
 705 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
 706 {
 707         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 708         size_t ptr;
 709         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 710         snd_assert (cpcm->pcm_channel,return -ENXIO);
 711
 712 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 713         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 714 #else
 715         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 716 #endif
 717         ptr -= cpcm->hw_buf.addr;
 718         return ptr >> cpcm->shift;
 719 }
 720
 721 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
 722 {
 723         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 724         size_t ptr;
 725         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 726
 727 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 728         snd_assert (cpcm->pcm_channel,return -ENXIO);
 729         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 730 #else
 731         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 732 #endif
 733         ptr -= cpcm->hw_buf.addr;
 734         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 735 }
 736
 737 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
 738 {
 739         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 740         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 741         return ptr >> chip->capt.shift;
 742 }
 743
 744 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
 745 {
 746         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 747         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 748         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 749 }
 750
 751 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
 752                                        int cmd)
 753 {
 754         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 755         /*snd_pcm_runtime_t *runtime = substream->runtime;*/
 756         int result = 0;
 757
 758 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 759         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 760         if (! cpcm->pcm_channel) {
 761                 return -ENXIO;
 762         }
 763 #endif
 764         switch (cmd) {
 765         case SNDRV_PCM_TRIGGER_START:
 766         case SNDRV_PCM_TRIGGER_RESUME:
 767 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 768                 /* magic value to unmute PCM stream  playback volume */
 769                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 770                                        SCBVolumeCtrl) << 2, 0x80008000);
 771
 772                 if (cpcm->pcm_channel->unlinked)
 773                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 774
 775                 if (substream->runtime->periods != CS46XX_FRAGS)
 776                         snd_cs46xx_playback_transfer(substream);
 777 #else
 778                 spin_lock(&chip->reg_lock);
 779                 if (substream->runtime->periods != CS46XX_FRAGS)
 780                         snd_cs46xx_playback_transfer(substream);
 781                 { unsigned int tmp;
 782                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 783                 tmp &= 0x0000ffff;
 784                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 785                 }
 786                 spin_unlock(&chip->reg_lock);
 787 #endif
 788                 break;
 789         case SNDRV_PCM_TRIGGER_STOP:
 790         case SNDRV_PCM_TRIGGER_SUSPEND:
 791 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 792                 /* magic mute channel */
 793                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 794                                        SCBVolumeCtrl) << 2, 0xffffffff);
 795
 796                 if (!cpcm->pcm_channel->unlinked)
 797                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 798 #else
 799                 spin_lock(&chip->reg_lock);
 800                 { unsigned int tmp;
 801                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 802                 tmp &= 0x0000ffff;
 803                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 804                 }
 805                 spin_unlock(&chip->reg_lock);
 806 #endif
 807                 break;
 808         default:
 809                 result = -EINVAL;
 810                 break;
 811         }
 812
 813         return result;
 814 }
 815
 816 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
 817                                       int cmd)
 818 {
 819         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 820         unsigned int tmp;
 821         int result = 0;
 822
 823         spin_lock(&chip->reg_lock);
 824         switch (cmd) {
 825         case SNDRV_PCM_TRIGGER_START:
 826         case SNDRV_PCM_TRIGGER_RESUME:
 827                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 828                 tmp &= 0xffff0000;
 829                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 830                 break;
 831         case SNDRV_PCM_TRIGGER_STOP:
 832         case SNDRV_PCM_TRIGGER_SUSPEND:
 833                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 834                 tmp &= 0xffff0000;
 835                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 836                 break;
 837         default:
 838                 result = -EINVAL;
 839                 break;
 840         }
 841         spin_unlock(&chip->reg_lock);
 842
 843         return result;
 844 }
 845
 846 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 847 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
 848                                        int sample_rate)
 849 {
 850
 851         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 852         if ( cpcm->pcm_channel == NULL) {
 853                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 854                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
 855                 if (cpcm->pcm_channel == NULL) {
 856                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 857                         return -ENOMEM;
 858                 }
 859                 cpcm->pcm_channel->sample_rate = sample_rate;
 860         } else
 861         /* if sample rate is changed */
 862         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 863                 int unlinked = cpcm->pcm_channel->unlinked;
 864                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 865
 866                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 867                                                                          cpcm->hw_buf.addr,
 868                                                                          cpcm->pcm_channel_id)) == NULL) {
 869                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 870                         return -ENOMEM;
 871                 }
 872
 873                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 874                 cpcm->pcm_channel->sample_rate = sample_rate;
 875         }
 876
 877         return 0;
 878 }
 879 #endif
 880
 881
 882 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
 883                                          snd_pcm_hw_params_t * hw_params)
 884 {
 885         snd_pcm_runtime_t *runtime = substream->runtime;
 886         cs46xx_pcm_t *cpcm;
 887         int err;
 888 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 889         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 890         int sample_rate = params_rate(hw_params);
 891         int period_size = params_period_bytes(hw_params);
 892 #endif
 893         cpcm = runtime->private_data;
 894
 895 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 896         snd_assert (sample_rate != 0, return -ENXIO);
 897
 898         down (&chip->spos_mutex);
 899
 900         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 901                 up (&chip->spos_mutex);
 902                 return -ENXIO;
 903         }
 904
 905         snd_assert (cpcm->pcm_channel != NULL);
 906         if (!cpcm->pcm_channel) {
 907                 up (&chip->spos_mutex);
 908                 return -ENXIO;
 909         }
 910
 911
 912         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
 913                  up (&chip->spos_mutex);
 914                  return -EINVAL;
 915          }
 916
 917         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
 918                      period_size, params_periods(hw_params),
 919                      params_buffer_bytes(hw_params));
 920 #endif
 921
 922         if (params_periods(hw_params) == CS46XX_FRAGS) {
 923                 if (runtime->dma_area != cpcm->hw_buf.area)
 924                         snd_pcm_lib_free_pages(substream);
 925                 runtime->dma_area = cpcm->hw_buf.area;
 926                 runtime->dma_addr = cpcm->hw_buf.addr;
 927                 runtime->dma_bytes = cpcm->hw_buf.bytes;
 928
 929
 930 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 931                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 932                         substream->ops = &snd_cs46xx_playback_ops;
 933                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 934                         substream->ops = &snd_cs46xx_playback_rear_ops;
 935                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 936                         substream->ops = &snd_cs46xx_playback_clfe_ops;
 937                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 938                         substream->ops = &snd_cs46xx_playback_iec958_ops;
 939                 } else {
 940                         snd_assert(0);
 941                 }
 942 #else
 943                 substream->ops = &snd_cs46xx_playback_ops;
 944 #endif
 945
 946         } else {
 947                 if (runtime->dma_area == cpcm->hw_buf.area) {
 948                         runtime->dma_area = NULL;
 949                         runtime->dma_addr = 0;
 950                         runtime->dma_bytes = 0;
 951                 }
 952                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
 953 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 954                         up (&chip->spos_mutex);
 955 #endif
 956                         return err;
 957                 }
 958
 959 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 960                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 961                         substream->ops = &snd_cs46xx_playback_indirect_ops;
 962                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 963                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
 964                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 965                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
 966                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 967                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
 968                 } else {
 969                         snd_assert(0);
 970                 }
 971 #else
 972                 substream->ops = &snd_cs46xx_playback_indirect_ops;
 973 #endif
 974
 975         }
 976
 977 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 978         up (&chip->spos_mutex);
 979 #endif
 980
 981         return 0;
 982 }
 983
 984 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
 985 {
 986         /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
 987         snd_pcm_runtime_t *runtime = substream->runtime;
 988         cs46xx_pcm_t *cpcm;
 989
 990         cpcm = runtime->private_data;
 991
 992         /* if play_back open fails, then this function
 993            is called and cpcm can actually be NULL here */
 994         if (!cpcm) return -ENXIO;
 995
 996         if (runtime->dma_area != cpcm->hw_buf.area)
 997                 snd_pcm_lib_free_pages(substream);
 998
 999         runtime->dma_area = NULL;
1000         runtime->dma_addr = 0;
1001         runtime->dma_bytes = 0;
1002
1003         return 0;
1004 }
1005
1006 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1007 {
1008         unsigned int tmp;
1009         unsigned int pfie;
1010         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1011         snd_pcm_runtime_t *runtime = substream->runtime;
1012         cs46xx_pcm_t *cpcm;
1013
1014         cpcm = runtime->private_data;
1015
1016 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1017     snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1018
1019         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1020         pfie &= ~0x0000f03f;
1021 #else
1022         /* old dsp */
1023         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1024         pfie &= ~0x0000f03f;
1025 #endif
1026
1027         cpcm->shift = 2;
1028         /* if to convert from stereo to mono */
1029         if (runtime->channels == 1) {
1030                 cpcm->shift--;
1031                 pfie |= 0x00002000;
1032         }
1033         /* if to convert from 8 bit to 16 bit */
1034         if (snd_pcm_format_width(runtime->format) == 8) {
1035                 cpcm->shift--;
1036                 pfie |= 0x00001000;
1037         }
1038         /* if to convert to unsigned */
1039         if (snd_pcm_format_unsigned(runtime->format))
1040                 pfie |= 0x00008000;
1041
1042         /* Never convert byte order when sample stream is 8 bit */
1043         if (snd_pcm_format_width(runtime->format) != 8) {
1044                 /* convert from big endian to little endian */
1045                 if (snd_pcm_format_big_endian(runtime->format))
1046                         pfie |= 0x00004000;
1047         }
1048
1049         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1050         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1051         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1052
1053 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1054
1055         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1056         tmp &= ~0x000003ff;
1057         tmp |= (4 << cpcm->shift) - 1;
1058         /* playback transaction count register */
1059         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1060
1061         /* playback format && interrupt enable */
1062         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1063 #else
1064         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1065         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1066         tmp &= ~0x000003ff;
1067         tmp |= (4 << cpcm->shift) - 1;
1068         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1069         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1070         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1071 #endif
1072
1073         return 0;
1074 }
1075
1076 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1077                                         snd_pcm_hw_params_t * hw_params)
1078 {
1079         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1080         snd_pcm_runtime_t *runtime = substream->runtime;
1081         int err;
1082
1083 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1084         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1085 #endif
1086         if (runtime->periods == CS46XX_FRAGS) {
1087                 if (runtime->dma_area != chip->capt.hw_buf.area)
1088                         snd_pcm_lib_free_pages(substream);
1089                 runtime->dma_area = chip->capt.hw_buf.area;
1090                 runtime->dma_addr = chip->capt.hw_buf.addr;
1091                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1092                 substream->ops = &snd_cs46xx_capture_ops;
1093         } else {
1094                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1095                         runtime->dma_area = NULL;
1096                         runtime->dma_addr = 0;
1097                         runtime->dma_bytes = 0;
1098                 }
1099                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1100                         return err;
1101                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1108 {
1109         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1110         snd_pcm_runtime_t *runtime = substream->runtime;
1111
1112         if (runtime->dma_area != chip->capt.hw_buf.area)
1113                 snd_pcm_lib_free_pages(substream);
1114         runtime->dma_area = NULL;
1115         runtime->dma_addr = 0;
1116         runtime->dma_bytes = 0;
1117
1118         return 0;
1119 }
1120
1121 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1122 {
1123         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1124         snd_pcm_runtime_t *runtime = substream->runtime;
1125
1126         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1127         chip->capt.shift = 2;
1128         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1129         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1130         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1131         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1132
1133         return 0;
1134 }
1135
1136 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1137 {
1138         cs46xx_t *chip = dev_id;
1139         u32 status1;
1140 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1141         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1142         u32 status2;
1143         int i;
1144         cs46xx_pcm_t *cpcm = NULL;
1145 #endif
1146
1147         /*
1148          *  Read the Interrupt Status Register to clear the interrupt
1149          */
1150         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1151         if ((status1 & 0x7fffffff) == 0) {
1152                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1153                 return IRQ_NONE;
1154         }
1155
1156 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1157         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1158
1159         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1160                 if (i <= 15) {
1161                         if ( status1 & (1 << i) ) {
1162                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1163                                         if (chip->capt.substream)
1164                                                 snd_pcm_period_elapsed(chip->capt.substream);
1165                                 } else {
1166                                         if (ins->pcm_channels[i].active &&
1167                                             ins->pcm_channels[i].private_data &&
1168                                             !ins->pcm_channels[i].unlinked) {
1169                                                 cpcm = ins->pcm_channels[i].private_data;
1170                                                 snd_pcm_period_elapsed(cpcm->substream);
1171                                         }
1172                                 }
1173                         }
1174                 } else {
1175                         if ( status2 & (1 << (i - 16))) {
1176                                 if (ins->pcm_channels[i].active &&
1177                                     ins->pcm_channels[i].private_data &&
1178                                     !ins->pcm_channels[i].unlinked) {
1179                                         cpcm = ins->pcm_channels[i].private_data;
1180                                         snd_pcm_period_elapsed(cpcm->substream);
1181                                 }
1182                         }
1183                 }
1184         }
1185
1186 #else
1187         /* old dsp */
1188         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1189                 if (chip->playback_pcm->substream)
1190                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1191         }
1192         if ((status1 & HISR_VC1) && chip->pcm) {
1193                 if (chip->capt.substream)
1194                         snd_pcm_period_elapsed(chip->capt.substream);
1195         }
1196 #endif
1197
1198         if ((status1 & HISR_MIDI) && chip->rmidi) {
1199                 unsigned char c;
1200
1201                 spin_lock(&chip->reg_lock);
1202                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1203                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1204                         if ((chip->midcr & MIDCR_RIE) == 0)
1205                                 continue;
1206                         spin_unlock(&chip->reg_lock);
1207                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1208                         spin_lock(&chip->reg_lock);
1209                 }
1210                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1211                         if ((chip->midcr & MIDCR_TIE) == 0)
1212                                 break;
1213                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1214                                 chip->midcr &= ~MIDCR_TIE;
1215                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1216                                 break;
1217                         }
1218                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1219                 }
1220                 spin_unlock(&chip->reg_lock);
1221         }
1222         /*
1223          *  EOI to the PCI part....reenables interrupts
1224          */
1225         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1226
1227         return IRQ_HANDLED;
1228 }
1229
1230 static snd_pcm_hardware_t snd_cs46xx_playback =
1231 {
1232         .info =                 (SNDRV_PCM_INFO_MMAP |
1233                                  SNDRV_PCM_INFO_INTERLEAVED |
1234                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1235                                  SNDRV_PCM_INFO_RESUME),
1236         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1237                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1238                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1239         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1240         .rate_min =             5500,
1241         .rate_max =             48000,
1242         .channels_min =         1,
1243         .channels_max =         2,
1244         .buffer_bytes_max =     (256 * 1024),
1245         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1246         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1247         .periods_min =          CS46XX_FRAGS,
1248         .periods_max =          1024,
1249         .fifo_size =            0,
1250 };
1251
1252 static snd_pcm_hardware_t snd_cs46xx_capture =
1253 {
1254         .info =                 (SNDRV_PCM_INFO_MMAP |
1255                                  SNDRV_PCM_INFO_INTERLEAVED |
1256                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1257                                  SNDRV_PCM_INFO_RESUME),
1258         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1259         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1260         .rate_min =             5500,
1261         .rate_max =             48000,
1262         .channels_min =         2,
1263         .channels_max =         2,
1264         .buffer_bytes_max =     (256 * 1024),
1265         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1266         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1267         .periods_min =          CS46XX_FRAGS,
1268         .periods_max =          1024,
1269         .fifo_size =            0,
1270 };
1271
1272 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1273
1274 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1275
1276 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1277         .count = ARRAY_SIZE(period_sizes),
1278         .list = period_sizes,
1279         .mask = 0
1280 };
1281
1282 #endif
1283
1284 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1285 {
1286         cs46xx_pcm_t * cpcm = runtime->private_data;
1287         kfree(cpcm);
1288 }
1289
1290 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1291 {
1292         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1293         cs46xx_pcm_t * cpcm;
1294         snd_pcm_runtime_t *runtime = substream->runtime;
1295
1296         cpcm = kcalloc(1, sizeof(*cpcm), GFP_KERNEL);
1297         if (cpcm == NULL)
1298                 return -ENOMEM;
1299         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1300                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1301                 kfree(cpcm);
1302                 return -ENOMEM;
1303         }
1304
1305         runtime->hw = snd_cs46xx_playback;
1306         runtime->private_data = cpcm;
1307         runtime->private_free = snd_cs46xx_pcm_free_substream;
1308
1309         cpcm->substream = substream;
1310 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1311         down (&chip->spos_mutex);
1312         cpcm->pcm_channel = NULL;
1313         cpcm->pcm_channel_id = pcm_channel_id;
1314
1315
1316         snd_pcm_hw_constraint_list(runtime, 0,
1317                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1318                                    &hw_constraints_period_sizes);
1319
1320         up (&chip->spos_mutex);
1321 #else
1322         chip->playback_pcm = cpcm; /* HACK */
1323 #endif
1324
1325         if (chip->accept_valid)
1326                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1327         chip->active_ctrl(chip, 1);
1328
1329         return 0;
1330 }
1331
1332 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1333 {
1334         snd_printdd("open front channel\n");
1335         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1336 }
1337
1338 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1339 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1340 {
1341         snd_printdd("open rear channel\n");
1342
1343         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1344 }
1345
1346 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1347 {
1348         snd_printdd("open center - LFE channel\n");
1349
1350         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1351 }
1352
1353 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1354 {
1355         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1356
1357         snd_printdd("open raw iec958 channel\n");
1358
1359         down (&chip->spos_mutex);
1360         cs46xx_iec958_pre_open (chip);
1361         up (&chip->spos_mutex);
1362
1363         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1364 }
1365
1366 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1367
1368 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1369 {
1370         int err;
1371         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1372
1373         snd_printdd("close raw iec958 channel\n");
1374
1375         err = snd_cs46xx_playback_close(substream);
1376
1377         down (&chip->spos_mutex);
1378         cs46xx_iec958_post_close (chip);
1379         up (&chip->spos_mutex);
1380
1381         return err;
1382 }
1383 #endif
1384
1385 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1386 {
1387         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1388
1389         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1390                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1391                 return -ENOMEM;
1392         chip->capt.substream = substream;
1393         substream->runtime->hw = snd_cs46xx_capture;
1394
1395         if (chip->accept_valid)
1396                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1397
1398         chip->active_ctrl(chip, 1);
1399
1400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1401         snd_pcm_hw_constraint_list(substream->runtime, 0,
1402                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1403                                    &hw_constraints_period_sizes);
1404 #endif
1405         return 0;
1406 }
1407
1408 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1409 {
1410         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1411         snd_pcm_runtime_t *runtime = substream->runtime;
1412         cs46xx_pcm_t * cpcm;
1413
1414         cpcm = runtime->private_data;
1415
1416         /* when playback_open fails, then cpcm can be NULL */
1417         if (!cpcm) return -ENXIO;
1418
1419 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1420         down (&chip->spos_mutex);
1421         if (cpcm->pcm_channel) {
1422                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1423                 cpcm->pcm_channel = NULL;
1424         }
1425         up (&chip->spos_mutex);
1426 #else
1427         chip->playback_pcm = NULL;
1428 #endif
1429
1430         cpcm->substream = NULL;
1431         snd_dma_free_pages(&cpcm->hw_buf);
1432         chip->active_ctrl(chip, -1);
1433
1434         return 0;
1435 }
1436
1437 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1438 {
1439         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1440
1441         chip->capt.substream = NULL;
1442         snd_dma_free_pages(&chip->capt.hw_buf);
1443         chip->active_ctrl(chip, -1);
1444
1445         return 0;
1446 }
1447
1448 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1449 snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1450         .open =                 snd_cs46xx_playback_open_rear,
1451         .close =                snd_cs46xx_playback_close,
1452         .ioctl =                snd_pcm_lib_ioctl,
1453         .hw_params =            snd_cs46xx_playback_hw_params,
1454         .hw_free =              snd_cs46xx_playback_hw_free,
1455         .prepare =              snd_cs46xx_playback_prepare,
1456         .trigger =              snd_cs46xx_playback_trigger,
1457         .pointer =              snd_cs46xx_playback_direct_pointer,
1458 };
1459
1460 snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1461         .open =                 snd_cs46xx_playback_open_rear,
1462         .close =                snd_cs46xx_playback_close,
1463         .ioctl =                snd_pcm_lib_ioctl,
1464         .hw_params =            snd_cs46xx_playback_hw_params,
1465         .hw_free =              snd_cs46xx_playback_hw_free,
1466         .prepare =              snd_cs46xx_playback_prepare,
1467         .trigger =              snd_cs46xx_playback_trigger,
1468         .pointer =              snd_cs46xx_playback_indirect_pointer,
1469         .ack =                  snd_cs46xx_playback_transfer,
1470 };
1471
1472 snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1473         .open =                 snd_cs46xx_playback_open_clfe,
1474         .close =                snd_cs46xx_playback_close,
1475         .ioctl =                snd_pcm_lib_ioctl,
1476         .hw_params =            snd_cs46xx_playback_hw_params,
1477         .hw_free =              snd_cs46xx_playback_hw_free,
1478         .prepare =              snd_cs46xx_playback_prepare,
1479         .trigger =              snd_cs46xx_playback_trigger,
1480         .pointer =              snd_cs46xx_playback_direct_pointer,
1481 };
1482
1483 snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1484         .open =                 snd_cs46xx_playback_open_clfe,
1485         .close =                snd_cs46xx_playback_close,
1486         .ioctl =                snd_pcm_lib_ioctl,
1487         .hw_params =            snd_cs46xx_playback_hw_params,
1488         .hw_free =              snd_cs46xx_playback_hw_free,
1489         .prepare =              snd_cs46xx_playback_prepare,
1490         .trigger =              snd_cs46xx_playback_trigger,
1491         .pointer =              snd_cs46xx_playback_indirect_pointer,
1492         .ack =                  snd_cs46xx_playback_transfer,
1493 };
1494
1495 snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1496         .open =                 snd_cs46xx_playback_open_iec958,
1497         .close =                snd_cs46xx_playback_close_iec958,
1498         .ioctl =                snd_pcm_lib_ioctl,
1499         .hw_params =            snd_cs46xx_playback_hw_params,
1500         .hw_free =              snd_cs46xx_playback_hw_free,
1501         .prepare =              snd_cs46xx_playback_prepare,
1502         .trigger =              snd_cs46xx_playback_trigger,
1503         .pointer =              snd_cs46xx_playback_direct_pointer,
1504 };
1505
1506 snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1507         .open =                 snd_cs46xx_playback_open_iec958,
1508         .close =                snd_cs46xx_playback_close_iec958,
1509         .ioctl =                snd_pcm_lib_ioctl,
1510         .hw_params =            snd_cs46xx_playback_hw_params,
1511         .hw_free =              snd_cs46xx_playback_hw_free,
1512         .prepare =              snd_cs46xx_playback_prepare,
1513         .trigger =              snd_cs46xx_playback_trigger,
1514         .pointer =              snd_cs46xx_playback_indirect_pointer,
1515         .ack =                  snd_cs46xx_playback_transfer,
1516 };
1517
1518 #endif
1519
1520 snd_pcm_ops_t snd_cs46xx_playback_ops = {
1521         .open =                 snd_cs46xx_playback_open,
1522         .close =                snd_cs46xx_playback_close,
1523         .ioctl =                snd_pcm_lib_ioctl,
1524         .hw_params =            snd_cs46xx_playback_hw_params,
1525         .hw_free =              snd_cs46xx_playback_hw_free,
1526         .prepare =              snd_cs46xx_playback_prepare,
1527         .trigger =              snd_cs46xx_playback_trigger,
1528         .pointer =              snd_cs46xx_playback_direct_pointer,
1529 };
1530
1531 snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1532         .open =                 snd_cs46xx_playback_open,
1533         .close =                snd_cs46xx_playback_close,
1534         .ioctl =                snd_pcm_lib_ioctl,
1535         .hw_params =            snd_cs46xx_playback_hw_params,
1536         .hw_free =              snd_cs46xx_playback_hw_free,
1537         .prepare =              snd_cs46xx_playback_prepare,
1538         .trigger =              snd_cs46xx_playback_trigger,
1539         .pointer =              snd_cs46xx_playback_indirect_pointer,
1540         .ack =                  snd_cs46xx_playback_transfer,
1541 };
1542
1543 snd_pcm_ops_t snd_cs46xx_capture_ops = {
1544         .open =                 snd_cs46xx_capture_open,
1545         .close =                snd_cs46xx_capture_close,
1546         .ioctl =                snd_pcm_lib_ioctl,
1547         .hw_params =            snd_cs46xx_capture_hw_params,
1548         .hw_free =              snd_cs46xx_capture_hw_free,
1549         .prepare =              snd_cs46xx_capture_prepare,
1550         .trigger =              snd_cs46xx_capture_trigger,
1551         .pointer =              snd_cs46xx_capture_direct_pointer,
1552 };
1553
1554 snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1555         .open =                 snd_cs46xx_capture_open,
1556         .close =                snd_cs46xx_capture_close,
1557         .ioctl =                snd_pcm_lib_ioctl,
1558         .hw_params =            snd_cs46xx_capture_hw_params,
1559         .hw_free =              snd_cs46xx_capture_hw_free,
1560         .prepare =              snd_cs46xx_capture_prepare,
1561         .trigger =              snd_cs46xx_capture_trigger,
1562         .pointer =              snd_cs46xx_capture_indirect_pointer,
1563         .ack =                  snd_cs46xx_capture_transfer,
1564 };
1565
1566 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1567 {
1568         cs46xx_t *chip = pcm->private_data;
1569         chip->pcm = NULL;
1570         snd_pcm_lib_preallocate_free_for_all(pcm);
1571 }
1572
1573 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1574 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1575 {
1576         cs46xx_t *chip = pcm->private_data;
1577         chip->pcm_rear = NULL;
1578         snd_pcm_lib_preallocate_free_for_all(pcm);
1579 }
1580
1581 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1582 {
1583         cs46xx_t *chip = pcm->private_data;
1584         chip->pcm_center_lfe = NULL;
1585         snd_pcm_lib_preallocate_free_for_all(pcm);
1586 }
1587
1588 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1589 {
1590         cs46xx_t *chip = pcm->private_data;
1591         chip->pcm_iec958 = NULL;
1592         snd_pcm_lib_preallocate_free_for_all(pcm);
1593 }
1594
1595 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1596 #else
1597 #define MAX_PLAYBACK_CHANNELS   1
1598 #endif
1599
1600 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1601 {
1602         snd_pcm_t *pcm;
1603         int err;
1604
1605         if (rpcm)
1606                 *rpcm = NULL;
1607         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1608                 return err;
1609
1610         pcm->private_data = chip;
1611         pcm->private_free = snd_cs46xx_pcm_free;
1612
1613         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1614         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1615
1616         /* global setup */
1617         pcm->info_flags = 0;
1618         strcpy(pcm->name, "CS46xx");
1619         chip->pcm = pcm;
1620
1621         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1622                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1623
1624         if (rpcm)
1625                 *rpcm = pcm;
1626
1627         return 0;
1628 }
1629
1630
1631 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1632 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1633 {
1634         snd_pcm_t *pcm;
1635         int err;
1636
1637         if (rpcm)
1638                 *rpcm = NULL;
1639
1640         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1641                 return err;
1642
1643         pcm->private_data = chip;
1644         pcm->private_free = snd_cs46xx_pcm_rear_free;
1645
1646         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1647
1648         /* global setup */
1649         pcm->info_flags = 0;
1650         strcpy(pcm->name, "CS46xx - Rear");
1651         chip->pcm_rear = pcm;
1652
1653         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1654                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1655
1656         if (rpcm)
1657                 *rpcm = pcm;
1658
1659         return 0;
1660 }
1661
1662 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1663 {
1664         snd_pcm_t *pcm;
1665         int err;
1666
1667         if (rpcm)
1668                 *rpcm = NULL;
1669
1670         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1671                 return err;
1672
1673         pcm->private_data = chip;
1674         pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1675
1676         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1677
1678         /* global setup */
1679         pcm->info_flags = 0;
1680         strcpy(pcm->name, "CS46xx - Center LFE");
1681         chip->pcm_center_lfe = pcm;
1682
1683         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1684                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1685
1686         if (rpcm)
1687                 *rpcm = pcm;
1688
1689         return 0;
1690 }
1691
1692 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1693 {
1694         snd_pcm_t *pcm;
1695         int err;
1696
1697         if (rpcm)
1698                 *rpcm = NULL;
1699
1700         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1701                 return err;
1702
1703         pcm->private_data = chip;
1704         pcm->private_free = snd_cs46xx_pcm_iec958_free;
1705
1706         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1707
1708         /* global setup */
1709         pcm->info_flags = 0;
1710         strcpy(pcm->name, "CS46xx - IEC958");
1711         chip->pcm_rear = pcm;
1712
1713         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1714                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1715
1716         if (rpcm)
1717                 *rpcm = pcm;
1718
1719         return 0;
1720 }
1721 #endif
1722
1723 /*
1724  *  Mixer routines
1725  */
1726 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t *bus)
1727 {
1728         cs46xx_t *chip = bus->private_data;
1729
1730         chip->ac97_bus = NULL;
1731 }
1732
1733 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1734 {
1735         cs46xx_t *chip = ac97->private_data;
1736
1737         snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1738                     (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1739                     return);
1740
1741         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1742                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1743                 chip->eapd_switch = NULL;
1744         }
1745         else
1746                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1747 }
1748
1749 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1750                                snd_ctl_elem_info_t *uinfo)
1751 {
1752         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1753         uinfo->count = 2;
1754         uinfo->value.integer.min = 0;
1755         uinfo->value.integer.max = 0x7fff;
1756         return 0;
1757 }
1758
1759 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1760 {
1761         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1762         int reg = kcontrol->private_value;
1763         unsigned int val = snd_cs46xx_peek(chip, reg);
1764         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1765         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1766         return 0;
1767 }
1768
1769 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1770 {
1771         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1772         int reg = kcontrol->private_value;
1773         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1774                             (0xffff - ucontrol->value.integer.value[1]));
1775         unsigned int old = snd_cs46xx_peek(chip, reg);
1776         int change = (old != val);
1777
1778         if (change) {
1779                 snd_cs46xx_poke(chip, reg, val);
1780         }
1781
1782         return change;
1783 }
1784
1785 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1786
1787 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1788 {
1789         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1790
1791         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1792         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1793
1794         return 0;
1795 }
1796
1797 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1798 {
1799         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1800         int change = 0;
1801
1802         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1803             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1804                 cs46xx_dsp_set_dac_volume(chip,
1805                                           ucontrol->value.integer.value[0],
1806                                           ucontrol->value.integer.value[1]);
1807                 change = 1;
1808         }
1809
1810         return change;
1811 }
1812
1813 #if 0
1814 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1815 {
1816         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1817
1818         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1819         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1820         return 0;
1821 }
1822
1823 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1824 {
1825         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1826         int change = 0;
1827
1828         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1829             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1830                 cs46xx_dsp_set_iec958_volume (chip,
1831                                               ucontrol->value.integer.value[0],
1832                                               ucontrol->value.integer.value[1]);
1833                 change = 1;
1834         }
1835
1836         return change;
1837 }
1838 #endif
1839
1840 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1841                                   snd_ctl_elem_info_t *uinfo)
1842 {
1843         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1844         uinfo->count = 1;
1845         uinfo->value.integer.min = 0;
1846         uinfo->value.integer.max = 1;
1847         return 0;
1848 }
1849
1850 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1851                                  snd_ctl_elem_value_t *ucontrol)
1852 {
1853         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1854         int reg = kcontrol->private_value;
1855
1856         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1857                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1858         else
1859                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1860
1861         return 0;
1862 }
1863
1864 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1865                                   snd_ctl_elem_value_t *ucontrol)
1866 {
1867         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1868         int change, res;
1869
1870         switch (kcontrol->private_value) {
1871         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1872                 down (&chip->spos_mutex);
1873                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1874                 if (ucontrol->value.integer.value[0] && !change)
1875                         cs46xx_dsp_enable_spdif_out(chip);
1876                 else if (change && !ucontrol->value.integer.value[0])
1877                         cs46xx_dsp_disable_spdif_out(chip);
1878
1879                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1880                 up (&chip->spos_mutex);
1881                 break;
1882         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1883                 change = chip->dsp_spos_instance->spdif_status_in;
1884                 if (ucontrol->value.integer.value[0] && !change) {
1885                         cs46xx_dsp_enable_spdif_in(chip);
1886                         /* restore volume */
1887                 }
1888                 else if (change && !ucontrol->value.integer.value[0])
1889                         cs46xx_dsp_disable_spdif_in(chip);
1890
1891                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1892                 break;
1893         default:
1894                 res = -EINVAL;
1895                 snd_assert(0, (void)0);
1896         }
1897
1898         return res;
1899 }
1900
1901 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
1902                                       snd_ctl_elem_value_t *ucontrol)
1903 {
1904         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1905         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1906
1907         if (ins->adc_input != NULL)
1908                 ucontrol->value.integer.value[0] = 1;
1909         else
1910                 ucontrol->value.integer.value[0] = 0;
1911
1912         return 0;
1913 }
1914
1915 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
1916                                       snd_ctl_elem_value_t *ucontrol)
1917 {
1918         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1919         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1920         int change = 0;
1921
1922         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1923                 cs46xx_dsp_enable_adc_capture(chip);
1924                 change = 1;
1925         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1926                 cs46xx_dsp_disable_adc_capture(chip);
1927                 change = 1;
1928         }
1929         return change;
1930 }
1931
1932 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
1933                                       snd_ctl_elem_value_t *ucontrol)
1934 {
1935         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1936         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1937
1938         if (ins->pcm_input != NULL)
1939                 ucontrol->value.integer.value[0] = 1;
1940         else
1941                 ucontrol->value.integer.value[0] = 0;
1942
1943         return 0;
1944 }
1945
1946
1947 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
1948                                       snd_ctl_elem_value_t *ucontrol)
1949 {
1950         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1951         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1952         int change = 0;
1953
1954         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1955                 cs46xx_dsp_enable_pcm_capture(chip);
1956                 change = 1;
1957         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1958                 cs46xx_dsp_disable_pcm_capture(chip);
1959                 change = 1;
1960         }
1961
1962         return change;
1963 }
1964
1965 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
1966                                      snd_ctl_elem_value_t *ucontrol)
1967 {
1968         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1969
1970         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1971
1972         if (val1 & EGPIODR_GPOE0)
1973                 ucontrol->value.integer.value[0] = 1;
1974         else
1975                 ucontrol->value.integer.value[0] = 0;
1976
1977         return 0;
1978 }
1979
1980 /*
1981  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1982  */
1983 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
1984                                        snd_ctl_elem_value_t *ucontrol)
1985 {
1986         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1987         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1988         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1989
1990         if (ucontrol->value.integer.value[0]) {
1991                 /* optical is default */
1992                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1993                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
1994                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1995                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1996         } else {
1997                 /* coaxial */
1998                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
1999                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2000         }
2001
2002         /* checking diff from the EGPIO direction register
2003            should be enough */
2004         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2005 }
2006
2007
2008 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2009 {
2010         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2011         uinfo->count = 1;
2012         return 0;
2013 }
2014
2015 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2016                                         snd_ctl_elem_value_t * ucontrol)
2017 {
2018         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2019         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2020
2021         down (&chip->spos_mutex);
2022         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2023         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2024         ucontrol->value.iec958.status[2] = 0;
2025         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2026         up (&chip->spos_mutex);
2027
2028         return 0;
2029 }
2030
2031 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2032                                         snd_ctl_elem_value_t * ucontrol)
2033 {
2034         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2035         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2036         unsigned int val;
2037         int change;
2038
2039         down (&chip->spos_mutex);
2040         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2041                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2042                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2043                 /* left and right validity bit */
2044                 (1 << 13) | (1 << 12);
2045
2046
2047         change = (unsigned int)ins->spdif_csuv_default != val;
2048         ins->spdif_csuv_default = val;
2049
2050         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2051                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2052
2053         up (&chip->spos_mutex);
2054
2055         return change;
2056 }
2057
2058 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2059                                      snd_ctl_elem_value_t * ucontrol)
2060 {
2061         ucontrol->value.iec958.status[0] = 0xff;
2062         ucontrol->value.iec958.status[1] = 0xff;
2063         ucontrol->value.iec958.status[2] = 0x00;
2064         ucontrol->value.iec958.status[3] = 0xff;
2065         return 0;
2066 }
2067
2068 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2069                                          snd_ctl_elem_value_t * ucontrol)
2070 {
2071         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2072         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2073
2074         down (&chip->spos_mutex);
2075         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2076         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2077         ucontrol->value.iec958.status[2] = 0;
2078         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2079         up (&chip->spos_mutex);
2080
2081         return 0;
2082 }
2083
2084 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2085                                         snd_ctl_elem_value_t * ucontrol)
2086 {
2087         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2088         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2089         unsigned int val;
2090         int change;
2091
2092         down (&chip->spos_mutex);
2093         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2094                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2095                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2096                 /* left and right validity bit */
2097                 (1 << 13) | (1 << 12);
2098
2099
2100         change = ins->spdif_csuv_stream != val;
2101         ins->spdif_csuv_stream = val;
2102
2103         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2104                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2105
2106         up (&chip->spos_mutex);
2107
2108         return change;
2109 }
2110
2111 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2112
2113
2114 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2115 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2116                                         snd_ctl_elem_info_t *uinfo)
2117 {
2118         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2119         uinfo->count = 1;
2120         uinfo->value.integer.min = 0;
2121         uinfo->value.integer.max = 8;
2122         return 0;
2123 }
2124
2125 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2126                                        snd_ctl_elem_value_t *ucontrol)
2127 {
2128         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2129         ucontrol->value.integer.value[0] = chip->current_gpio;
2130
2131         return 0;
2132 }
2133
2134 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2135                                        snd_ctl_elem_value_t *ucontrol)
2136 {
2137         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2138         int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2139         chip->current_gpio = ucontrol->value.integer.value[0];
2140
2141         return change;
2142 }
2143
2144
2145 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2146                                        snd_ctl_elem_value_t *ucontrol)
2147 {
2148         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2149         int reg = kcontrol->private_value;
2150
2151         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2152         ucontrol->value.integer.value[0] =
2153                 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2154
2155         return 0;
2156 }
2157
2158 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2159                                        snd_ctl_elem_value_t *ucontrol)
2160 {
2161         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2162         int reg = kcontrol->private_value;
2163         int val = snd_cs46xx_peekBA0(chip, reg);
2164         int oldval = val;
2165         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2166
2167         if (ucontrol->value.integer.value[0])
2168                 val |= (1 << chip->current_gpio);
2169         else
2170                 val &= ~(1 << chip->current_gpio);
2171
2172         snd_cs46xx_pokeBA0(chip, reg,val);
2173         snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2174
2175         return (oldval != val);
2176 }
2177 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2178
2179 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2180 {
2181         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2182         .name = "DAC Volume",
2183         .info = snd_cs46xx_vol_info,
2184 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2185         .get = snd_cs46xx_vol_get,
2186         .put = snd_cs46xx_vol_put,
2187         .private_value = BA1_PVOL,
2188 #else
2189         .get = snd_cs46xx_vol_dac_get,
2190         .put = snd_cs46xx_vol_dac_put,
2191 #endif
2192 },
2193
2194 {
2195         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2196         .name = "ADC Volume",
2197         .info = snd_cs46xx_vol_info,
2198         .get = snd_cs46xx_vol_get,
2199         .put = snd_cs46xx_vol_put,
2200 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2201         .private_value = BA1_CVOL,
2202 #else
2203         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2204 #endif
2205 },
2206 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2207 {
2208         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2209         .name = "ADC Capture Switch",
2210         .info = snd_mixer_boolean_info,
2211         .get = snd_cs46xx_adc_capture_get,
2212         .put = snd_cs46xx_adc_capture_put
2213 },
2214 {
2215         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2216         .name = "DAC Capture Switch",
2217         .info = snd_mixer_boolean_info,
2218         .get = snd_cs46xx_pcm_capture_get,
2219         .put = snd_cs46xx_pcm_capture_put
2220 },
2221 {
2222         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2223         .name = "IEC958 Output Switch",
2224         .info = snd_mixer_boolean_info,
2225         .get = snd_cs46xx_iec958_get,
2226         .put = snd_cs46xx_iec958_put,
2227         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2228 },
2229 {
2230         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2231         .name = "IEC958 Input Switch",
2232         .info = snd_mixer_boolean_info,
2233         .get = snd_cs46xx_iec958_get,
2234         .put = snd_cs46xx_iec958_put,
2235         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2236 },
2237 #if 0
2238 /* Input IEC958 volume does not work for the moment. (Benny) */
2239 {
2240         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2241         .name = "IEC958 Input Volume",
2242         .info = snd_cs46xx_vol_info,
2243         .get = snd_cs46xx_vol_iec958_get,
2244         .put = snd_cs46xx_vol_iec958_put,
2245         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2246 },
2247 #endif
2248 {
2249         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2250         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2251         .info =  snd_cs46xx_spdif_info,
2252         .get =   snd_cs46xx_spdif_default_get,
2253         .put =   snd_cs46xx_spdif_default_put,
2254 },
2255 {
2256         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2257         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2258         .info =  snd_cs46xx_spdif_info,
2259         .get =   snd_cs46xx_spdif_mask_get,
2260         .access = SNDRV_CTL_ELEM_ACCESS_READ
2261 },
2262 {
2263         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2264         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2265         .info =  snd_cs46xx_spdif_info,
2266         .get =   snd_cs46xx_spdif_stream_get,
2267         .put =   snd_cs46xx_spdif_stream_put
2268 },
2269
2270 #endif
2271 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2272 {
2273         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2274         .name = "EGPIO select",
2275         .info = snd_cs46xx_egpio_select_info,
2276         .get = snd_cs46xx_egpio_select_get,
2277         .put = snd_cs46xx_egpio_select_put,
2278         .private_value = 0,
2279 },
2280 {
2281         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2282         .name = "EGPIO Input/Output",
2283         .info = snd_mixer_boolean_info,
2284         .get = snd_cs46xx_egpio_get,
2285         .put = snd_cs46xx_egpio_put,
2286         .private_value = BA0_EGPIODR,
2287 },
2288 {
2289         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2290         .name = "EGPIO CMOS/Open drain",
2291         .info = snd_mixer_boolean_info,
2292         .get = snd_cs46xx_egpio_get,
2293         .put = snd_cs46xx_egpio_put,
2294         .private_value = BA0_EGPIOPTR,
2295 },
2296 {
2297         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2298         .name = "EGPIO On/Off",
2299         .info = snd_mixer_boolean_info,
2300         .get = snd_cs46xx_egpio_get,
2301         .put = snd_cs46xx_egpio_put,
2302         .private_value = BA0_EGPIOSR,
2303 },
2304 #endif
2305 };
2306
2307 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2308 /* Only available on the Hercules Game Theater XP soundcard */
2309 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2310 {
2311         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2312         .name = "Optical/Coaxial SPDIF Input Switch",
2313         .info = snd_mixer_boolean_info,
2314         .get = snd_herc_spdif_select_get,
2315         .put = snd_herc_spdif_select_put,
2316 },
2317 };
2318
2319
2320 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2321 {
2322         unsigned long end_time;
2323         int err;
2324
2325         /* reset to defaults */
2326         snd_ac97_write(ac97, AC97_RESET, 0);
2327
2328         /* set the desired CODEC mode */
2329         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2330                 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2331                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2332         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2333                 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2334                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2335         } else {
2336                 snd_assert(0); /* should never happen ... */
2337         }
2338
2339         udelay(50);
2340
2341         /* it's necessary to wait awhile until registers are accessible after RESET */
2342         /* because the PCM or MASTER volume registers can be modified, */
2343         /* the REC_GAIN register is used for tests */
2344         end_time = jiffies + HZ;
2345         do {
2346                 unsigned short ext_mid;
2347
2348                 /* use preliminary reads to settle the communication */
2349                 snd_ac97_read(ac97, AC97_RESET);
2350                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2351                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2352                 /* modem? */
2353                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2354                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2355                         return;
2356
2357                 /* test if we can write to the record gain volume register */
2358                 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2359                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2360                         return;
2361
2362                 set_current_state(TASK_UNINTERRUPTIBLE);
2363                 schedule_timeout(HZ/100);
2364         } while (time_after_eq(end_time, jiffies));
2365
2366         snd_printk("CS46xx secondary codec dont respond!\n");
2367 }
2368 #endif
2369
2370 static int __devinit cs46xx_detect_codec(cs46xx_t *chip, int codec)
2371 {
2372         int idx, err;
2373         ac97_template_t ac97;
2374
2375         memset(&ac97, 0, sizeof(ac97));
2376         ac97.private_data = chip;
2377         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2378         ac97.num = codec;
2379         if (chip->amplifier_ctrl == amp_voyetra)
2380                 ac97.scaps = AC97_SCAP_INV_EAPD;
2381
2382         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2383                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2384                 udelay(10);
2385                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2386                         snd_printdd("snd_cs46xx: seconadry codec not present\n");
2387                         return -ENXIO;
2388                 }
2389         }
2390
2391         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2392         for (idx = 0; idx < 100; ++idx) {
2393                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2394                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2395                         return err;
2396                 }
2397                 set_current_state(TASK_INTERRUPTIBLE);
2398                 schedule_timeout(HZ/100);
2399         }
2400         snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2401         return -ENXIO;
2402 }
2403
2404 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2405 {
2406         snd_card_t *card = chip->card;
2407         snd_ctl_elem_id_t id;
2408         int err;
2409         unsigned int idx;
2410         static ac97_bus_ops_t ops = {
2411 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2412                 .reset = snd_cs46xx_codec_reset,
2413 #endif
2414                 .write = snd_cs46xx_ac97_write,
2415                 .read = snd_cs46xx_ac97_read,
2416         };
2417
2418         /* detect primary codec */
2419         chip->nr_ac97_codecs = 0;
2420         snd_printdd("snd_cs46xx: detecting primary codec\n");
2421         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2422                 return err;
2423         chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2424
2425         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2426                 return -ENXIO;
2427         chip->nr_ac97_codecs = 1;
2428
2429 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2430         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2431         /* try detect a secondary codec */
2432         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2433                 chip->nr_ac97_codecs = 2;
2434 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2435
2436         /* add cs4630 mixer controls */
2437         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2438                 snd_kcontrol_t *kctl;
2439                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2440                 if ((err = snd_ctl_add(card, kctl)) < 0)
2441                         return err;
2442         }
2443
2444         /* get EAPD mixer switch (for voyetra hack) */
2445         memset(&id, 0, sizeof(id));
2446         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2447         strcpy(id.name, "External Amplifier");
2448         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2449
2450 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2451         if (chip->nr_ac97_codecs == 1) {
2452                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2453                 if (id2 == 0x592b || id2 == 0x592d) {
2454                         /* set primary cs4294 codec into Extended Audio Mode */
2455                         snd_printdd("setting EAM bit on cs4294 CODEC\n");
2456                         snd_cs46xx_codec_write(chip, AC97_CSR_ACMODE, 0x200,
2457                                                CS46XX_PRIMARY_CODEC_INDEX);
2458                 }
2459         }
2460         /* do soundcard specific mixer setup */
2461         if (chip->mixer_init) {
2462                 snd_printdd ("calling chip->mixer_init(chip);\n");
2463                 chip->mixer_init(chip);
2464         }
2465 #endif
2466
2467         /* turn on amplifier */
2468         chip->amplifier_ctrl(chip, 1);
2469
2470         return 0;
2471 }
2472
2473 /*
2474  *  RawMIDI interface
2475  */
2476
2477 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2478 {
2479         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2480         udelay(100);
2481         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2482 }
2483
2484 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2485 {
2486         cs46xx_t *chip = substream->rmidi->private_data;
2487
2488         chip->active_ctrl(chip, 1);
2489         spin_lock_irq(&chip->reg_lock);
2490         chip->uartm |= CS46XX_MODE_INPUT;
2491         chip->midcr |= MIDCR_RXE;
2492         chip->midi_input = substream;
2493         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2494                 snd_cs46xx_midi_reset(chip);
2495         } else {
2496                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2497         }
2498         spin_unlock_irq(&chip->reg_lock);
2499         return 0;
2500 }
2501
2502 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2503 {
2504         cs46xx_t *chip = substream->rmidi->private_data;
2505
2506         spin_lock_irq(&chip->reg_lock);
2507         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2508         chip->midi_input = NULL;
2509         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2510                 snd_cs46xx_midi_reset(chip);
2511         } else {
2512                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2513         }
2514         chip->uartm &= ~CS46XX_MODE_INPUT;
2515         spin_unlock_irq(&chip->reg_lock);
2516         chip->active_ctrl(chip, -1);
2517         return 0;
2518 }
2519
2520 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2521 {
2522         cs46xx_t *chip = substream->rmidi->private_data;
2523
2524         chip->active_ctrl(chip, 1);
2525
2526         spin_lock_irq(&chip->reg_lock);
2527         chip->uartm |= CS46XX_MODE_OUTPUT;
2528         chip->midcr |= MIDCR_TXE;
2529         chip->midi_output = substream;
2530         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2531                 snd_cs46xx_midi_reset(chip);
2532         } else {
2533                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2534         }
2535         spin_unlock_irq(&chip->reg_lock);
2536         return 0;
2537 }
2538
2539 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2540 {
2541         cs46xx_t *chip = substream->rmidi->private_data;
2542
2543         spin_lock_irq(&chip->reg_lock);
2544         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2545         chip->midi_output = NULL;
2546         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2547                 snd_cs46xx_midi_reset(chip);
2548         } else {
2549                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2550         }
2551         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2552         spin_unlock_irq(&chip->reg_lock);
2553         chip->active_ctrl(chip, -1);
2554         return 0;
2555 }
2556
2557 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2558 {
2559         unsigned long flags;
2560         cs46xx_t *chip = substream->rmidi->private_data;
2561
2562         spin_lock_irqsave(&chip->reg_lock, flags);
2563         if (up) {
2564                 if ((chip->midcr & MIDCR_RIE) == 0) {
2565                         chip->midcr |= MIDCR_RIE;
2566                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2567                 }
2568         } else {
2569                 if (chip->midcr & MIDCR_RIE) {
2570                         chip->midcr &= ~MIDCR_RIE;
2571                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2572                 }
2573         }
2574         spin_unlock_irqrestore(&chip->reg_lock, flags);
2575 }
2576
2577 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2578 {
2579         unsigned long flags;
2580         cs46xx_t *chip = substream->rmidi->private_data;
2581         unsigned char byte;
2582
2583         spin_lock_irqsave(&chip->reg_lock, flags);
2584         if (up) {
2585                 if ((chip->midcr & MIDCR_TIE) == 0) {
2586                         chip->midcr |= MIDCR_TIE;
2587                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2588                         while ((chip->midcr & MIDCR_TIE) &&
2589                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2590                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2591                                         chip->midcr &= ~MIDCR_TIE;
2592                                 } else {
2593                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2594                                 }
2595                         }
2596                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2597                 }
2598         } else {
2599                 if (chip->midcr & MIDCR_TIE) {
2600                         chip->midcr &= ~MIDCR_TIE;
2601                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2602                 }
2603         }
2604         spin_unlock_irqrestore(&chip->reg_lock, flags);
2605 }
2606
2607 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2608 {
2609         .open =         snd_cs46xx_midi_output_open,
2610         .close =        snd_cs46xx_midi_output_close,
2611         .trigger =      snd_cs46xx_midi_output_trigger,
2612 };
2613
2614 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2615 {
2616         .open =         snd_cs46xx_midi_input_open,
2617         .close =        snd_cs46xx_midi_input_close,
2618         .trigger =      snd_cs46xx_midi_input_trigger,
2619 };
2620
2621 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2622 {
2623         snd_rawmidi_t *rmidi;
2624         int err;
2625
2626         if (rrawmidi)
2627                 *rrawmidi = NULL;
2628         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2629                 return err;
2630         strcpy(rmidi->name, "CS46XX");
2631         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2632         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2633         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2634         rmidi->private_data = chip;
2635         chip->rmidi = rmidi;
2636         if (rrawmidi)
2637                 *rrawmidi = NULL;
2638         return 0;
2639 }
2640
2641
2642 /*
2643  * gameport interface
2644  */
2645
2646 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2647
2648 typedef struct snd_cs46xx_gameport {
2649         struct gameport info;
2650         cs46xx_t *chip;
2651 } cs46xx_gameport_t;
2652
2653 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2654 {
2655         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2656         cs46xx_t *chip;
2657         snd_assert(gp, return);
2658         chip = gp->chip;
2659         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2660 }
2661
2662 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2663 {
2664         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2665         cs46xx_t *chip;
2666         snd_assert(gp, return 0);
2667         chip = gp->chip;
2668         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2669 }
2670
2671 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2672 {
2673         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2674         cs46xx_t *chip;
2675         unsigned js1, js2, jst;
2676
2677         snd_assert(gp, return 0);
2678         chip = gp->chip;
2679
2680         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2681         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2682         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2683
2684         *buttons = (~jst >> 4) & 0x0F;
2685
2686         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2687         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2688         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2689         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2690
2691         for(jst=0;jst<4;++jst)
2692                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2693         return 0;
2694 }
2695
2696 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2697 {
2698         switch (mode) {
2699         case GAMEPORT_MODE_COOKED:
2700                 return 0;
2701         case GAMEPORT_MODE_RAW:
2702                 return 0;
2703         default:
2704                 return -1;
2705         }
2706         return 0;
2707 }
2708
2709 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2710 {
2711         cs46xx_gameport_t *gp;
2712         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
2713         if (! gp) {
2714                 snd_printk("cannot allocate gameport area\n");
2715                 return;
2716         }
2717         memset(gp, 0, sizeof(*gp));
2718         gp->info.open = snd_cs46xx_gameport_open;
2719         gp->info.read = snd_cs46xx_gameport_read;
2720         gp->info.trigger = snd_cs46xx_gameport_trigger;
2721         gp->info.cooked_read = snd_cs46xx_gameport_cooked_read;
2722         gp->chip = chip;
2723         chip->gameport = gp;
2724
2725         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2726         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2727         gameport_register_port(&gp->info);
2728 }
2729
2730 #else
2731
2732 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2733 {
2734 }
2735
2736 #endif /* CONFIG_GAMEPORT */
2737
2738 /*
2739  *  proc interface
2740  */
2741
2742 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2743                                struct file *file, char __user *buf,
2744                                unsigned long count, unsigned long pos)
2745 {
2746         long size;
2747         snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2748
2749         size = count;
2750         if (pos + (size_t)size > region->size)
2751                 size = region->size - pos;
2752         if (size > 0) {
2753                 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2754                         return -EFAULT;
2755         }
2756         return size;
2757 }
2758
2759 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2760         .read = snd_cs46xx_io_read,
2761 };
2762
2763 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2764 {
2765         snd_info_entry_t *entry;
2766         int idx;
2767
2768         for (idx = 0; idx < 5; idx++) {
2769                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2770                 if (! snd_card_proc_new(card, region->name, &entry)) {
2771                         entry->content = SNDRV_INFO_CONTENT_DATA;
2772                         entry->private_data = chip;
2773                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2774                         entry->size = region->size;
2775                         entry->mode = S_IFREG | S_IRUSR;
2776                 }
2777         }
2778 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2779         cs46xx_dsp_proc_init(card, chip);
2780 #endif
2781         return 0;
2782 }
2783
2784 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2785 {
2786 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2787         cs46xx_dsp_proc_done(chip);
2788 #endif
2789         return 0;
2790 }
2791
2792 /*
2793  * stop the h/w
2794  */
2795 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2796 {
2797         unsigned int tmp;
2798
2799         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2800         tmp &= ~0x0000f03f;
2801         tmp |=  0x00000010;
2802         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2803
2804         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2805         tmp &= ~0x0000003f;
2806         tmp |=  0x00000011;
2807         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2808
2809         /*
2810          *  Stop playback DMA.
2811          */
2812         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2813         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2814
2815         /*
2816          *  Stop capture DMA.
2817          */
2818         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2819         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2820
2821         /*
2822          *  Reset the processor.
2823          */
2824         snd_cs46xx_reset(chip);
2825
2826         snd_cs46xx_proc_stop(chip);
2827
2828         /*
2829          *  Power down the PLL.
2830          */
2831         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2832
2833         /*
2834          *  Turn off the Processor by turning off the software clock enable flag in
2835          *  the clock control register.
2836          */
2837         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2838         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2839 }
2840
2841
2842 static int snd_cs46xx_free(cs46xx_t *chip)
2843 {
2844         int idx;
2845
2846         snd_assert(chip != NULL, return -EINVAL);
2847
2848         if (chip->active_ctrl)
2849                 chip->active_ctrl(chip, 1);
2850
2851 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2852         if (chip->gameport) {
2853                 gameport_unregister_port(&chip->gameport->info);
2854                 kfree(chip->gameport);
2855         }
2856 #endif
2857
2858         if (chip->amplifier_ctrl)
2859                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2860
2861         snd_cs46xx_proc_done(chip);
2862
2863         if (chip->region.idx[0].resource)
2864                 snd_cs46xx_hw_stop(chip);
2865
2866         for (idx = 0; idx < 5; idx++) {
2867                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2868                 if (region->remap_addr)
2869                         iounmap(region->remap_addr);
2870                 if (region->resource) {
2871                         release_resource(region->resource);
2872                         kfree_nocheck(region->resource);
2873                 }
2874         }
2875         if (chip->irq >= 0)
2876                 free_irq(chip->irq, (void *)chip);
2877
2878         if (chip->active_ctrl)
2879                 chip->active_ctrl(chip, -chip->amplifier);
2880
2881 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2882         if (chip->dsp_spos_instance) {
2883                 cs46xx_dsp_spos_destroy(chip);
2884                 chip->dsp_spos_instance = NULL;
2885         }
2886 #endif
2887
2888         pci_disable_device(chip->pci);
2889         kfree(chip);
2890         return 0;
2891 }
2892
2893 static int snd_cs46xx_dev_free(snd_device_t *device)
2894 {
2895         cs46xx_t *chip = device->device_data;
2896         return snd_cs46xx_free(chip);
2897 }
2898
2899 /*
2900  *  initialize chip
2901  */
2902 static int snd_cs46xx_chip_init(cs46xx_t *chip)
2903 {
2904         int timeout;
2905
2906         /*
2907          *  First, blast the clock control register to zero so that the PLL starts
2908          *  out in a known state, and blast the master serial port control register
2909          *  to zero so that the serial ports also start out in a known state.
2910          */
2911         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2912         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2913
2914         /*
2915          *  If we are in AC97 mode, then we must set the part to a host controlled
2916          *  AC-link.  Otherwise, we won't be able to bring up the link.
2917          */
2918 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2919         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2920                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2921         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2922 #else
2923         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2924 #endif
2925
2926         /*
2927          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2928          *  spec) and then drive it high.  This is done for non AC97 modes since
2929          *  there might be logic external to the CS461x that uses the ARST# line
2930          *  for a reset.
2931          */
2932         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2933 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2934         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2935 #endif
2936         udelay(50);
2937         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2938 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2939         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2940 #endif
2941
2942         /*
2943          *  The first thing we do here is to enable sync generation.  As soon
2944          *  as we start receiving bit clock, we'll start producing the SYNC
2945          *  signal.
2946          */
2947         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2949         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2950 #endif
2951
2952         /*
2953          *  Now wait for a short while to allow the AC97 part to start
2954          *  generating bit clock (so we don't try to start the PLL without an
2955          *  input clock).
2956          */
2957         mdelay(10);
2958
2959         /*
2960          *  Set the serial port timing configuration, so that
2961          *  the clock control circuit gets its clock from the correct place.
2962          */
2963         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2964
2965         /*
2966          *  Write the selected clock control setup to the hardware.  Do not turn on
2967          *  SWCE yet (if requested), so that the devices clocked by the output of
2968          *  PLL are not clocked until the PLL is stable.
2969          */
2970         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2971         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2972         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2973
2974         /*
2975          *  Power up the PLL.
2976          */
2977         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2978
2979         /*
2980          *  Wait until the PLL has stabilized.
2981          */
2982         set_current_state(TASK_UNINTERRUPTIBLE);
2983         schedule_timeout(HZ/10); /* 100ms */
2984
2985         /*
2986          *  Turn on clocking of the core so that we can setup the serial ports.
2987          */
2988         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2989
2990         /*
2991          * Enable FIFO  Host Bypass
2992          */
2993         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2994
2995         /*
2996          *  Fill the serial port FIFOs with silence.
2997          */
2998         snd_cs46xx_clear_serial_FIFOs(chip);
2999
3000         /*
3001          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3002          */
3003         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3004
3005         /*
3006          *  Write the serial port configuration to the part.  The master
3007          *  enable bit is not set until all other values have been written.
3008          */
3009         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3010         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3011         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3012
3013
3014 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3015         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3016         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3017         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3018         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3019         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3020 #endif
3021
3022         mdelay(5);
3023
3024
3025         /*
3026          * Wait for the codec ready signal from the AC97 codec.
3027          */
3028         timeout = 150;
3029         while (timeout-- > 0) {
3030                 /*
3031                  *  Read the AC97 status register to see if we've seen a CODEC READY
3032                  *  signal from the AC97 codec.
3033                  */
3034                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3035                         goto ok1;
3036                 set_current_state(TASK_UNINTERRUPTIBLE);
3037                 schedule_timeout((HZ+99)/100);
3038         }
3039
3040
3041         snd_printk("create - never read codec ready from AC'97\n");
3042         snd_printk("it is not probably bug, try to use CS4236 driver\n");
3043         return -EIO;
3044  ok1:
3045 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3046         {
3047                 int count;
3048                 for (count = 0; count < 150; count++) {
3049                         /* First, we want to wait for a short time. */
3050                         udelay(25);
3051
3052                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3053                                 break;
3054                 }
3055
3056                 /*
3057                  *  Make sure CODEC is READY.
3058                  */
3059                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3060                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3061         }
3062 #endif
3063
3064         /*
3065          *  Assert the vaid frame signal so that we can start sending commands
3066          *  to the AC97 codec.
3067          */
3068         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3069 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3070         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3071 #endif
3072
3073
3074         /*
3075          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3076          *  the codec is pumping ADC data across the AC-link.
3077          */
3078         timeout = 150;
3079         while (timeout-- > 0) {
3080                 /*
3081                  *  Read the input slot valid register and see if input slots 3 and
3082                  *  4 are valid yet.
3083                  */
3084                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3085                         goto ok2;
3086                 set_current_state(TASK_UNINTERRUPTIBLE);
3087                 schedule_timeout((HZ+99)/100);
3088         }
3089
3090 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3091         snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3092         return -EIO;
3093 #else
3094         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3095            Reloading the driver may help, if there's other soundcards
3096            with the same problem I would like to know. (Benny) */
3097
3098         snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3099         snd_printk("       Try reloading the ALSA driver, if you find something\n");
3100         snd_printk("       broken or not working on your soundcard upon\n");
3101         snd_printk("       this message please report to alsa-devel@lists.sourceforge.net\n");
3102
3103         return -EIO;
3104 #endif
3105  ok2:
3106
3107         /*
3108          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3109          *  commense the transfer of digital audio data to the AC97 codec.
3110          */
3111
3112         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3113
3114
3115         /*
3116          *  Power down the DAC and ADC.  We will power them up (if) when we need
3117          *  them.
3118          */
3119         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3120
3121         /*
3122          *  Turn off the Processor by turning off the software clock enable flag in
3123          *  the clock control register.
3124          */
3125         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3126         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3127
3128         return 0;
3129 }
3130
3131 /*
3132  *  start and load DSP
3133  */
3134 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3135 {
3136         unsigned int tmp;
3137         /*
3138          *  Reset the processor.
3139          */
3140         snd_cs46xx_reset(chip);
3141         /*
3142          *  Download the image to the processor.
3143          */
3144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3145 #if 0
3146         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3147                 snd_printk(KERN_ERR "image download error\n");
3148                 return -EIO;
3149         }
3150 #endif
3151
3152         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3153                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3154                 return -EIO;
3155         }
3156
3157         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3158                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3159                 return -EIO;
3160         }
3161
3162         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3163                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3164                 return -EIO;
3165         }
3166
3167         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3168                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3169                 return -EIO;
3170         }
3171
3172         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3173                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3174                 return -EIO;
3175         }
3176
3177         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3178                 return -EIO;
3179 #else
3180         /* old image */
3181         if (snd_cs46xx_download_image(chip) < 0) {
3182                 snd_printk("image download error\n");
3183                 return -EIO;
3184         }
3185
3186         /*
3187          *  Stop playback DMA.
3188          */
3189         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3190         chip->play_ctl = tmp & 0xffff0000;
3191         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3192 #endif
3193
3194         /*
3195          *  Stop capture DMA.
3196          */
3197         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3198         chip->capt.ctl = tmp & 0x0000ffff;
3199         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3200
3201         mdelay(5);
3202
3203         snd_cs46xx_set_play_sample_rate(chip, 8000);
3204         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3205
3206         snd_cs46xx_proc_start(chip);
3207
3208         /*
3209          *  Enable interrupts on the part.
3210          */
3211         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3212
3213         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3214         tmp &= ~0x0000f03f;
3215         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3216
3217         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3218         tmp &= ~0x0000003f;
3219         tmp |=  0x00000001;
3220         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3221
3222 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3223         /* set the attenuation to 0dB */
3224         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3225         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3226 #endif
3227
3228         return 0;
3229 }
3230
3231
3232 /*
3233  *      AMP control - null AMP
3234  */
3235
3236 static void amp_none(cs46xx_t *chip, int change)
3237 {
3238 }
3239
3240 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3241 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3242 {
3243
3244         u32 idx, valid_slots,tmp,powerdown = 0;
3245         u16 modem_power,pin_config,logic_type;
3246
3247         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3248
3249         /*
3250          *  See if the devices are powered down.  If so, we must power them up first
3251          *  or they will not respond.
3252          */
3253         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3254
3255         if (!(tmp & CLKCR1_SWCE)) {
3256                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3257                 powerdown = 1;
3258         }
3259
3260         /*
3261          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3262          * stuff.
3263          */
3264         if(chip->nr_ac97_codecs != 2) {
3265                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3266                 return -EINVAL;
3267         }
3268
3269         modem_power = snd_cs46xx_codec_read (chip,
3270                                              AC97_EXTENDED_MSTATUS,
3271                                              CS46XX_SECONDARY_CODEC_INDEX);
3272         modem_power &=0xFEFF;
3273
3274         snd_cs46xx_codec_write(chip,
3275                                AC97_EXTENDED_MSTATUS, modem_power,
3276                                CS46XX_SECONDARY_CODEC_INDEX);
3277
3278         /*
3279          * Set GPIO pin's 7 and 8 so that they are configured for output.
3280          */
3281         pin_config = snd_cs46xx_codec_read (chip,
3282                                             AC97_GPIO_CFG,
3283                                             CS46XX_SECONDARY_CODEC_INDEX);
3284         pin_config &=0x27F;
3285
3286         snd_cs46xx_codec_write(chip,
3287                                AC97_GPIO_CFG, pin_config,
3288                                CS46XX_SECONDARY_CODEC_INDEX);
3289
3290         /*
3291          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3292          */
3293
3294         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3295                                            CS46XX_SECONDARY_CODEC_INDEX);
3296         logic_type &=0x27F;
3297
3298         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3299                                 CS46XX_SECONDARY_CODEC_INDEX);
3300
3301         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3302         valid_slots |= 0x200;
3303         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3304
3305         if ( cs46xx_wait_for_fifo(chip,1) ) {
3306           snd_printdd("FIFO is busy\n");
3307
3308           return -EINVAL;
3309         }
3310
3311         /*
3312          * Fill slots 12 with the correct value for the GPIO pins.
3313          */
3314         for(idx = 0x90; idx <= 0x9F; idx++) {
3315                 /*
3316                  * Initialize the fifo so that bits 7 and 8 are on.
3317                  *
3318                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3319                  * the left.  0x1800 corresponds to bits 7 and 8.
3320                  */
3321                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3322
3323                 /*
3324                  * Wait for command to complete
3325                  */
3326                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3327                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3328
3329                         return -EINVAL;
3330                 }
3331
3332                 /*
3333                  * Write the serial port FIFO index.
3334                  */
3335                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3336
3337                 /*
3338                  * Tell the serial port to load the new value into the FIFO location.
3339                  */
3340                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3341         }
3342
3343         /* wait for last command to complete */
3344         cs46xx_wait_for_fifo(chip,200);
3345
3346         /*
3347          *  Now, if we powered up the devices, then power them back down again.
3348          *  This is kinda ugly, but should never happen.
3349          */
3350         if (powerdown)
3351                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3352
3353         return 0;
3354 }
3355 #endif
3356
3357 /*
3358  *      Crystal EAPD mode
3359  */
3360
3361 static void amp_voyetra(cs46xx_t *chip, int change)
3362 {
3363         /* Manage the EAPD bit on the Crystal 4297
3364            and the Analog AD1885 */
3365
3366 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3367         int old = chip->amplifier;
3368 #endif
3369         int oval, val;
3370
3371         chip->amplifier += change;
3372         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3373                                      CS46XX_PRIMARY_CODEC_INDEX);
3374         val = oval;
3375         if (chip->amplifier) {
3376                 /* Turn the EAPD amp on */
3377                 val |= 0x8000;
3378         } else {
3379                 /* Turn the EAPD amp off */
3380                 val &= ~0x8000;
3381         }
3382         if (val != oval) {
3383                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3384                                        CS46XX_PRIMARY_CODEC_INDEX);
3385                 if (chip->eapd_switch)
3386                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3387                                        &chip->eapd_switch->id);
3388         }
3389
3390 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3391         if (chip->amplifier && !old) {
3392                 voyetra_setup_eapd_slot(chip);
3393         }
3394 #endif
3395 }
3396
3397 static void hercules_init(cs46xx_t *chip)
3398 {
3399         /* default: AMP off, and SPDIF input optical */
3400         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3401         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3402 }
3403
3404
3405 /*
3406  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3407  */
3408 static void amp_hercules(cs46xx_t *chip, int change)
3409 {
3410         int old = chip->amplifier;
3411         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3412         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3413
3414         chip->amplifier += change;
3415         if (chip->amplifier && !old) {
3416                 snd_printdd ("Hercules amplifier ON\n");
3417
3418                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3419                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3420                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3421                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3422         } else if (old && !chip->amplifier) {
3423                 snd_printdd ("Hercules amplifier OFF\n");
3424                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3425                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3426         }
3427 }
3428
3429 static void voyetra_mixer_init (cs46xx_t *chip)
3430 {
3431         snd_printdd ("initializing Voyetra mixer\n");
3432
3433         /* Enable SPDIF out */
3434         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3435         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3436 }
3437
3438 static void hercules_mixer_init (cs46xx_t *chip)
3439 {
3440 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3441         unsigned int idx;
3442         int err;
3443         snd_card_t *card = chip->card;
3444 #endif
3445
3446         /* set EGPIO to default */
3447         hercules_init(chip);
3448
3449         snd_printdd ("initializing Hercules mixer\n");
3450
3451 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3452         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3453                 snd_kcontrol_t *kctl;
3454
3455                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3456                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3457                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3458                         break;
3459                 }
3460         }
3461 #endif
3462 }
3463
3464
3465 #if 0
3466 /*
3467  *      Untested
3468  */
3469
3470 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3471 {
3472         chip->amplifier += change;
3473
3474         if (chip->amplifier) {
3475                 /* Switch the GPIO pins 7 and 8 to open drain */
3476                 snd_cs46xx_codec_write(chip, 0x4C,
3477                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3478                 snd_cs46xx_codec_write(chip, 0x4E,
3479                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3480                 /* Now wake the AMP (this might be backwards) */
3481                 snd_cs46xx_codec_write(chip, 0x54,
3482                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3483         } else {
3484                 snd_cs46xx_codec_write(chip, 0x54,
3485                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3486         }
3487 }
3488 #endif
3489
3490
3491 /*
3492  * piix4 pci ids
3493  */
3494 #ifndef PCI_VENDOR_ID_INTEL
3495 #define PCI_VENDOR_ID_INTEL 0x8086
3496 #endif /* PCI_VENDOR_ID_INTEL */
3497
3498 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3499 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3500 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3501
3502 /*
3503  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3504  *      whenever we need to beat on the chip.
3505  *
3506  *      The original idea and code for this hack comes from David Kaiser at
3507  *      Linuxcare. Perhaps one day Crystal will document their chips well
3508  *      enough to make them useful.
3509  */
3510
3511 static void clkrun_hack(cs46xx_t *chip, int change)
3512 {
3513         u16 control, nval;
3514
3515         if (chip->acpi_dev == NULL)
3516                 return;
3517
3518         chip->amplifier += change;
3519
3520         /* Read ACPI port */
3521         nval = control = inw(chip->acpi_port + 0x10);
3522
3523         /* Flip CLKRUN off while running */
3524         if (! chip->amplifier)
3525                 nval |= 0x2000;
3526         else
3527                 nval &= ~0x2000;
3528         if (nval != control)
3529                 outw(nval, chip->acpi_port + 0x10);
3530 }
3531
3532
3533 /*
3534  * detect intel piix4
3535  */
3536 static void clkrun_init(cs46xx_t *chip)
3537 {
3538         u8 pp;
3539
3540         chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3541         if (chip->acpi_dev == NULL)
3542                 return;         /* Not a thinkpad thats for sure */
3543
3544         /* Find the control port */
3545         pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3546         chip->acpi_port = pp << 8;
3547 }
3548
3549
3550 /*
3551  * Card subid table
3552  */
3553
3554 struct cs_card_type
3555 {
3556         u16 vendor;
3557         u16 id;
3558         char *name;
3559         void (*init)(cs46xx_t *);
3560         void (*amp)(cs46xx_t *, int);
3561         void (*active)(cs46xx_t *, int);
3562         void (*mixer_init)(cs46xx_t *);
3563 };
3564
3565 static struct cs_card_type __devinitdata cards[] = {
3566         {
3567                 .vendor = 0x1489,
3568                 .id = 0x7001,
3569                 .name = "Genius Soundmaker 128 value",
3570                 /* nothing special */
3571         },
3572         {
3573                 .vendor = 0x5053,
3574                 .id = 0x3357,
3575                 .name = "Voyetra",
3576                 .amp = amp_voyetra,
3577                 .mixer_init = voyetra_mixer_init,
3578         },
3579         {
3580                 .vendor = 0x1071,
3581                 .id = 0x6003,
3582                 .name = "Mitac MI6020/21",
3583                 .amp = amp_voyetra,
3584         },
3585         {
3586                 .vendor = 0x14AF,
3587                 .id = 0x0050,
3588                 .name = "Hercules Game Theatre XP",
3589                 .amp = amp_hercules,
3590                 .mixer_init = hercules_mixer_init,
3591         },
3592         {
3593                 .vendor = 0x1681,
3594                 .id = 0x0050,
3595                 .name = "Hercules Game Theatre XP",
3596                 .amp = amp_hercules,
3597                 .mixer_init = hercules_mixer_init,
3598         },
3599         {
3600                 .vendor = 0x1681,
3601                 .id = 0x0051,
3602                 .name = "Hercules Game Theatre XP",
3603                 .amp = amp_hercules,
3604                 .mixer_init = hercules_mixer_init,
3605
3606         },
3607         {
3608                 .vendor = 0x1681,
3609                 .id = 0x0052,
3610                 .name = "Hercules Game Theatre XP",
3611                 .amp = amp_hercules,
3612                 .mixer_init = hercules_mixer_init,
3613         },
3614         {
3615                 .vendor = 0x1681,
3616                 .id = 0x0053,
3617                 .name = "Hercules Game Theatre XP",
3618                 .amp = amp_hercules,
3619                 .mixer_init = hercules_mixer_init,
3620         },
3621         {
3622                 .vendor = 0x1681,
3623                 .id = 0x0054,
3624                 .name = "Hercules Game Theatre XP",
3625                 .amp = amp_hercules,
3626                 .mixer_init = hercules_mixer_init,
3627         },
3628         /* Teratec */
3629         {
3630                 .vendor = 0x153b,
3631                 .id = 0x1136,
3632                 .name = "Terratec SiXPack 5.1",
3633         },
3634         /* Not sure if the 570 needs the clkrun hack */
3635         {
3636                 .vendor = PCI_VENDOR_ID_IBM,
3637                 .id = 0x0132,
3638                 .name = "Thinkpad 570",
3639                 .init = clkrun_init,
3640                 .active = clkrun_hack,
3641         },
3642         {
3643                 .vendor = PCI_VENDOR_ID_IBM,
3644                 .id = 0x0153,
3645                 .name = "Thinkpad 600X/A20/T20",
3646                 .init = clkrun_init,
3647                 .active = clkrun_hack,
3648         },
3649         {
3650                 .vendor = PCI_VENDOR_ID_IBM,
3651                 .id = 0x1010,
3652                 .name = "Thinkpad 600E (unsupported)",
3653         },
3654         {} /* terminator */
3655 };
3656
3657
3658 /*
3659  * APM support
3660  */
3661 #ifdef CONFIG_PM
3662 static int snd_cs46xx_suspend(snd_card_t *card, unsigned int state)
3663 {
3664         cs46xx_t *chip = card->pm_private_data;
3665         int amp_saved;
3666
3667         snd_pcm_suspend_all(chip->pcm);
3668         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3669         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3670
3671         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3672         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3673                 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3674
3675         amp_saved = chip->amplifier;
3676         /* turn off amp */
3677         chip->amplifier_ctrl(chip, -chip->amplifier);
3678         snd_cs46xx_hw_stop(chip);
3679         /* disable CLKRUN */
3680         chip->active_ctrl(chip, -chip->amplifier);
3681         chip->amplifier = amp_saved; /* restore the status */
3682         pci_disable_device(chip->pci);
3683         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3684         return 0;
3685 }
3686
3687 static int snd_cs46xx_resume(snd_card_t *card, unsigned int state)
3688 {
3689         cs46xx_t *chip = card->pm_private_data;
3690         int amp_saved;
3691
3692         pci_enable_device(chip->pci);
3693         pci_set_master(chip->pci);
3694         amp_saved = chip->amplifier;
3695         chip->amplifier = 0;
3696         chip->active_ctrl(chip, 1); /* force to on */
3697
3698         snd_cs46xx_chip_init(chip);
3699
3700 #if 0
3701         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3702                                chip->ac97_general_purpose);
3703         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3704                                chip->ac97_powerdown);
3705         mdelay(10);
3706         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3707                                chip->ac97_powerdown);
3708         mdelay(5);
3709 #endif
3710
3711         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3712         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3713                 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3714
3715         if (amp_saved)
3716                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3717         else
3718                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3719         chip->amplifier = amp_saved;
3720         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3721         return 0;
3722 }
3723 #endif /* CONFIG_PM */
3724
3725
3726 /*
3727  */
3728
3729 int __devinit snd_cs46xx_create(snd_card_t * card,
3730                       struct pci_dev * pci,
3731                       int external_amp, int thinkpad,
3732                       cs46xx_t ** rchip)
3733 {
3734         cs46xx_t *chip;
3735         int err, idx;
3736         snd_cs46xx_region_t *region;
3737         struct cs_card_type *cp;
3738         u16 ss_card, ss_vendor;
3739         static snd_device_ops_t ops = {
3740                 .dev_free =     snd_cs46xx_dev_free,
3741         };
3742
3743         *rchip = NULL;
3744
3745         /* enable PCI device */
3746         if ((err = pci_enable_device(pci)) < 0)
3747                 return err;
3748
3749         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
3750         if (chip == NULL) {
3751                 pci_disable_device(pci);
3752                 return -ENOMEM;
3753         }
3754         spin_lock_init(&chip->reg_lock);
3755 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3756         init_MUTEX(&chip->spos_mutex);
3757 #endif
3758         chip->card = card;
3759         chip->pci = pci;
3760         chip->irq = -1;
3761         chip->ba0_addr = pci_resource_start(pci, 0);
3762         chip->ba1_addr = pci_resource_start(pci, 1);
3763         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3764             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3765                 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3766                 snd_cs46xx_free(chip);
3767                 return -ENOMEM;
3768         }
3769
3770         region = &chip->region.name.ba0;
3771         strcpy(region->name, "CS46xx_BA0");
3772         region->base = chip->ba0_addr;
3773         region->size = CS46XX_BA0_SIZE;
3774
3775         region = &chip->region.name.data0;
3776         strcpy(region->name, "CS46xx_BA1_data0");
3777         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3778         region->size = CS46XX_BA1_DATA0_SIZE;
3779
3780         region = &chip->region.name.data1;
3781         strcpy(region->name, "CS46xx_BA1_data1");
3782         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3783         region->size = CS46XX_BA1_DATA1_SIZE;
3784
3785         region = &chip->region.name.pmem;
3786         strcpy(region->name, "CS46xx_BA1_pmem");
3787         region->base = chip->ba1_addr + BA1_SP_PMEM;
3788         region->size = CS46XX_BA1_PRG_SIZE;
3789
3790         region = &chip->region.name.reg;
3791         strcpy(region->name, "CS46xx_BA1_reg");
3792         region->base = chip->ba1_addr + BA1_SP_REG;
3793         region->size = CS46XX_BA1_REG_SIZE;
3794
3795         /* set up amp and clkrun hack */
3796         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3797         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3798
3799         for (cp = &cards[0]; cp->name; cp++) {
3800                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3801                         snd_printdd ("hack for %s enabled\n", cp->name);
3802
3803                         chip->amplifier_ctrl = cp->amp;
3804                         chip->active_ctrl = cp->active;
3805                         chip->mixer_init = cp->mixer_init;
3806
3807                         if (cp->init)
3808                                 cp->init(chip);
3809                         break;
3810                 }
3811         }
3812
3813         if (external_amp) {
3814                 snd_printk("Crystal EAPD support forced on.\n");
3815                 chip->amplifier_ctrl = amp_voyetra;
3816         }
3817
3818         if (thinkpad) {
3819                 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3820                 chip->active_ctrl = clkrun_hack;
3821                 clkrun_init(chip);
3822         }
3823
3824         if (chip->amplifier_ctrl == NULL)
3825                 chip->amplifier_ctrl = amp_none;
3826         if (chip->active_ctrl == NULL)
3827                 chip->active_ctrl = amp_none;
3828
3829         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3830
3831         pci_set_master(pci);
3832
3833         for (idx = 0; idx < 5; idx++) {
3834                 region = &chip->region.idx[idx];
3835                 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3836                         snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3837                         snd_cs46xx_free(chip);
3838                         return -EBUSY;
3839                 }
3840                 region->remap_addr = ioremap_nocache(region->base, region->size);
3841                 if (region->remap_addr == NULL) {
3842                         snd_printk("%s ioremap problem\n", region->name);
3843                         snd_cs46xx_free(chip);
3844                         return -ENOMEM;
3845                 }
3846         }
3847
3848         if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3849                 snd_printk("unable to grab IRQ %d\n", pci->irq);
3850                 snd_cs46xx_free(chip);
3851                 return -EBUSY;
3852         }
3853         chip->irq = pci->irq;
3854
3855 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3856         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3857         if (chip->dsp_spos_instance == NULL) {
3858                 snd_cs46xx_free(chip);
3859                 return -ENOMEM;
3860         }
3861 #endif
3862
3863         err = snd_cs46xx_chip_init(chip);
3864         if (err < 0) {
3865                 snd_cs46xx_free(chip);
3866                 return err;
3867         }
3868
3869         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3870                 snd_cs46xx_free(chip);
3871                 return err;
3872         }
3873
3874         snd_cs46xx_proc_init(card, chip);
3875
3876         snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3877
3878         chip->active_ctrl(chip, -1); /* disable CLKRUN */
3879
3880         snd_card_set_dev(card, &pci->dev);
3881
3882         *rchip = chip;
3883         return 0;
3884 }