2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
5 * Routines for control of Cirrus Logic CS461x chips
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer controll.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #include <sound/driver.h>
49 #include <linux/delay.h>
50 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/interrupt.h>
54 #include <linux/slab.h>
55 #include <linux/gameport.h>
57 #include <sound/core.h>
58 #include <sound/control.h>
59 #include <sound/info.h>
60 #include <sound/pcm.h>
61 #include <sound/pcm_params.h>
62 #include <sound/cs46xx.h>
66 #include "cs46xx_lib.h"
69 static void amp_voyetra(cs46xx_t *chip, int change);
71 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
76 unsigned short result,tmp;
78 snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
79 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
82 chip->active_ctrl(chip, 1);
84 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
85 offset = CS46XX_SECONDARY_CODEC_OFFSET;
88 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
89 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
90 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
91 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
92 * 5. if DCV not cleared, break and return error
93 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
96 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
98 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
99 if ((tmp & ACCTL_VFRM) == 0) {
100 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
101 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
103 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
104 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
109 * Setup the AC97 control registers on the CS461x to send the
110 * appropriate command to the AC97 to perform the read.
111 * ACCAD = Command Address Register = 46Ch
112 * ACCDA = Command Data Register = 470h
113 * ACCTL = Control Register = 460h
114 * set DCV - will clear when process completed
115 * set CRW - Read command
116 * set VFRM - valid frame enabled
117 * set ESYN - ASYNC generation enabled
118 * set RSTN - ARST# inactive, AC97 codec not reset
121 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
122 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
123 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
124 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
125 ACCTL_VFRM | ACCTL_ESYN |
127 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
128 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
132 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
137 * Wait for the read to occur.
139 for (count = 0; count < 1000; count++) {
141 * First, we want to wait for a short time.
145 * Now, check to see if the read has completed.
146 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
148 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
152 snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
158 * Wait for the valid status bit to go active.
160 for (count = 0; count < 100; count++) {
162 * Read the AC97 status register.
163 * ACSTS = Status Register = 464h
164 * VSTS - Valid Status
166 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
171 snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
177 * Read the data returned from the AC97 register.
178 * ACSDA = Status Data Register = 474h
181 printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
182 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
183 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
186 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
187 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
189 chip->active_ctrl(chip, -1);
193 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
196 cs46xx_t *chip = ac97->private_data;
198 int codec_index = ac97->num;
200 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
201 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
204 val = snd_cs46xx_codec_read(chip, reg, codec_index);
210 static void snd_cs46xx_codec_write(cs46xx_t *chip,
217 snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
218 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
221 chip->active_ctrl(chip, 1);
224 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
225 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
226 * 3. Write ACCTL = Control Register = 460h for initiating the write
227 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
228 * 5. if DCV not cleared, break and return error
232 * Setup the AC97 control registers on the CS461x to send the
233 * appropriate command to the AC97 to perform the read.
234 * ACCAD = Command Address Register = 46Ch
235 * ACCDA = Command Data Register = 470h
236 * ACCTL = Control Register = 460h
237 * set DCV - will clear when process completed
238 * reset CRW - Write command
239 * set VFRM - valid frame enabled
240 * set ESYN - ASYNC generation enabled
241 * set RSTN - ARST# inactive, AC97 codec not reset
243 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
244 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
245 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
247 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
248 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
249 ACCTL_ESYN | ACCTL_RSTN);
250 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
251 ACCTL_ESYN | ACCTL_RSTN);
253 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
254 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
257 for (count = 0; count < 4000; count++) {
259 * First, we want to wait for a short time.
263 * Now, check to see if the write has completed.
264 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
266 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
270 snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
272 chip->active_ctrl(chip, -1);
275 static void snd_cs46xx_ac97_write(ac97_t *ac97,
279 cs46xx_t *chip = ac97->private_data;
280 int codec_index = ac97->num;
282 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
283 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
286 snd_cs46xx_codec_write(chip, reg, val, codec_index);
291 * Chip initialization
294 int snd_cs46xx_download(cs46xx_t *chip,
296 unsigned long offset,
300 unsigned int bank = offset >> 16;
301 offset = offset & 0xffff;
303 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
304 dst = chip->region.idx[bank+1].remap_addr + offset;
307 /* writel already converts 32-bit value to right endianess */
315 #ifdef CONFIG_SND_CS46XX_NEW_DSP
317 #include "imgs/cwc4630.h"
318 #include "imgs/cwcasync.h"
319 #include "imgs/cwcsnoop.h"
320 #include "imgs/cwcbinhack.h"
321 #include "imgs/cwcdma.h"
323 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
324 unsigned long offset,
328 unsigned int bank = offset >> 16;
329 offset = offset & 0xffff;
331 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
332 dst = chip->region.idx[bank+1].remap_addr + offset;
335 /* writel already converts 32-bit value to right endianess */
343 #else /* old DSP image */
345 #include "cs46xx_image.h"
347 int snd_cs46xx_download_image(cs46xx_t *chip)
350 unsigned long offset = 0;
352 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
353 if ((err = snd_cs46xx_download(chip,
354 &BA1Struct.map[offset],
355 BA1Struct.memory[idx].offset,
356 BA1Struct.memory[idx].size)) < 0)
358 offset += BA1Struct.memory[idx].size >> 2;
362 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
368 static void snd_cs46xx_reset(cs46xx_t *chip)
373 * Write the reset bit of the SP control register.
375 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
378 * Write the control register.
380 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
383 * Clear the trap registers.
385 for (idx = 0; idx < 8; idx++) {
386 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
387 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
389 snd_cs46xx_poke(chip, BA1_DREG, 0);
392 * Set the frame timer to reflect the number of cycles per frame.
394 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
397 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
401 * Make sure the previous FIFO write operation has completed.
403 for(i = 0; i < 50; i++){
404 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
406 if( !(status & SERBST_WBSY) )
409 mdelay(retry_timeout);
412 if(status & SERBST_WBSY) {
413 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
421 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
423 int idx, powerdown = 0;
427 * See if the devices are powered down. If so, we must power them up first
428 * or they will not respond.
430 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
431 if (!(tmp & CLKCR1_SWCE)) {
432 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
437 * We want to clear out the serial port FIFOs so we don't end up playing
438 * whatever random garbage happens to be in them. We fill the sample FIFOS
439 * with zero (silence).
441 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
444 * Fill all 256 sample FIFO locations.
446 for (idx = 0; idx < 0xFF; idx++) {
448 * Make sure the previous FIFO write operation has completed.
450 if (cs46xx_wait_for_fifo(chip,1)) {
451 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
454 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
459 * Write the serial port FIFO index.
461 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
463 * Tell the serial port to load the new value into the FIFO location.
465 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
468 * Now, if we powered up the devices, then power them back down again.
469 * This is kinda ugly, but should never happen.
472 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
475 static void snd_cs46xx_proc_start(cs46xx_t *chip)
480 * Set the frame timer to reflect the number of cycles per frame.
482 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
484 * Turn on the run, run at frame, and DMA enable bits in the local copy of
485 * the SP control register.
487 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
489 * Wait until the run at frame bit resets itself in the SP control
492 for (cnt = 0; cnt < 25; cnt++) {
494 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
498 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
499 snd_printk("SPCR_RUNFR never reset\n");
502 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
505 * Turn off the run, run at frame, and DMA enable bits in the local copy of
506 * the SP control register.
508 snd_cs46xx_poke(chip, BA1_SPCR, 0);
512 * Sample rate routines
515 #define GOF_PER_SEC 200
517 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
520 unsigned int tmp1, tmp2;
521 unsigned int phiIncr;
522 unsigned int correctionPerGOF, correctionPerSec;
525 * Compute the values used to drive the actual sample rate conversion.
526 * The following formulas are being computed, using inline assembly
527 * since we need to use 64 bit arithmetic to compute the values:
529 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
530 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
532 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
533 * GOF_PER_SEC * correctionPerGOF
537 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
538 * correctionPerGOF:correctionPerSec =
539 * dividend:remainder(ulOther / GOF_PER_SEC)
542 phiIncr = tmp1 / 48000;
543 tmp1 -= phiIncr * 48000;
548 tmp1 -= tmp2 * 48000;
549 correctionPerGOF = tmp1 / GOF_PER_SEC;
550 tmp1 -= correctionPerGOF * GOF_PER_SEC;
551 correctionPerSec = tmp1;
554 * Fill in the SampleRateConverter control block.
556 spin_lock_irqsave(&chip->reg_lock, flags);
557 snd_cs46xx_poke(chip, BA1_PSRC,
558 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
559 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
560 spin_unlock_irqrestore(&chip->reg_lock, flags);
563 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
566 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
567 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
568 unsigned int frameGroupLength, cnt;
571 * We can only decimate by up to a factor of 1/9th the hardware rate.
572 * Correct the value if an attempt is made to stray outside that limit.
574 if ((rate * 9) < 48000)
578 * We can not capture at at rate greater than the Input Rate (48000).
579 * Return an error if an attempt is made to stray outside that limit.
585 * Compute the values used to drive the actual sample rate conversion.
586 * The following formulas are being computed, using inline assembly
587 * since we need to use 64 bit arithmetic to compute the values:
589 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
590 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
591 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
593 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
594 * GOF_PER_SEC * correctionPerGOF
595 * initialDelay = ceil((24 * Fs,in) / Fs,out)
599 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
600 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
601 * correctionPerGOF:correctionPerSec =
602 * dividend:remainder(ulOther / GOF_PER_SEC)
603 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
607 coeffIncr = tmp1 / 48000;
608 tmp1 -= coeffIncr * 48000;
611 coeffIncr += tmp1 / 48000;
612 coeffIncr ^= 0xFFFFFFFF;
615 phiIncr = tmp1 / rate;
616 tmp1 -= phiIncr * rate;
622 correctionPerGOF = tmp1 / GOF_PER_SEC;
623 tmp1 -= correctionPerGOF * GOF_PER_SEC;
624 correctionPerSec = tmp1;
625 initialDelay = ((48000 * 24) + rate - 1) / rate;
628 * Fill in the VariDecimate control block.
630 spin_lock_irqsave(&chip->reg_lock, flags);
631 snd_cs46xx_poke(chip, BA1_CSRC,
632 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
633 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
634 snd_cs46xx_poke(chip, BA1_CD,
635 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
636 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
637 spin_unlock_irqrestore(&chip->reg_lock, flags);
640 * Figure out the frame group length for the write back task. Basically,
641 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
642 * the output sample rate.
644 frameGroupLength = 1;
645 for (cnt = 2; cnt <= 64; cnt *= 2) {
646 if (((rate / cnt) * cnt) != rate)
647 frameGroupLength *= 2;
649 if (((rate / 3) * 3) != rate) {
650 frameGroupLength *= 3;
652 for (cnt = 5; cnt <= 125; cnt *= 5) {
653 if (((rate / cnt) * cnt) != rate)
654 frameGroupLength *= 5;
658 * Fill in the WriteBack control block.
660 spin_lock_irqsave(&chip->reg_lock, flags);
661 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
662 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
663 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
664 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
665 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
666 spin_unlock_irqrestore(&chip->reg_lock, flags);
673 static void snd_cs46xx_pb_trans_copy(snd_pcm_substream_t *substream,
674 snd_pcm_indirect_t *rec, size_t bytes)
676 snd_pcm_runtime_t *runtime = substream->runtime;
677 cs46xx_pcm_t * cpcm = runtime->private_data;
678 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
681 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
683 snd_pcm_runtime_t *runtime = substream->runtime;
684 cs46xx_pcm_t * cpcm = runtime->private_data;
685 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
689 static void snd_cs46xx_cp_trans_copy(snd_pcm_substream_t *substream,
690 snd_pcm_indirect_t *rec, size_t bytes)
692 cs46xx_t *chip = snd_pcm_substream_chip(substream);
693 snd_pcm_runtime_t *runtime = substream->runtime;
694 memcpy(runtime->dma_area + rec->sw_data,
695 chip->capt.hw_buf.area + rec->hw_data, bytes);
698 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
700 cs46xx_t *chip = snd_pcm_substream_chip(substream);
701 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
705 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
707 cs46xx_t *chip = snd_pcm_substream_chip(substream);
709 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
710 snd_assert (cpcm->pcm_channel,return -ENXIO);
712 #ifdef CONFIG_SND_CS46XX_NEW_DSP
713 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
715 ptr = snd_cs46xx_peek(chip, BA1_PBA);
717 ptr -= cpcm->hw_buf.addr;
718 return ptr >> cpcm->shift;
721 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
723 cs46xx_t *chip = snd_pcm_substream_chip(substream);
725 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
727 #ifdef CONFIG_SND_CS46XX_NEW_DSP
728 snd_assert (cpcm->pcm_channel,return -ENXIO);
729 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
731 ptr = snd_cs46xx_peek(chip, BA1_PBA);
733 ptr -= cpcm->hw_buf.addr;
734 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
737 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
739 cs46xx_t *chip = snd_pcm_substream_chip(substream);
740 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
741 return ptr >> chip->capt.shift;
744 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
746 cs46xx_t *chip = snd_pcm_substream_chip(substream);
747 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
748 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
751 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
754 cs46xx_t *chip = snd_pcm_substream_chip(substream);
755 /*snd_pcm_runtime_t *runtime = substream->runtime;*/
758 #ifdef CONFIG_SND_CS46XX_NEW_DSP
759 cs46xx_pcm_t *cpcm = substream->runtime->private_data;
760 if (! cpcm->pcm_channel) {
765 case SNDRV_PCM_TRIGGER_START:
766 case SNDRV_PCM_TRIGGER_RESUME:
767 #ifdef CONFIG_SND_CS46XX_NEW_DSP
768 /* magic value to unmute PCM stream playback volume */
769 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
770 SCBVolumeCtrl) << 2, 0x80008000);
772 if (cpcm->pcm_channel->unlinked)
773 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
775 if (substream->runtime->periods != CS46XX_FRAGS)
776 snd_cs46xx_playback_transfer(substream);
778 spin_lock(&chip->reg_lock);
779 if (substream->runtime->periods != CS46XX_FRAGS)
780 snd_cs46xx_playback_transfer(substream);
782 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
784 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
786 spin_unlock(&chip->reg_lock);
789 case SNDRV_PCM_TRIGGER_STOP:
790 case SNDRV_PCM_TRIGGER_SUSPEND:
791 #ifdef CONFIG_SND_CS46XX_NEW_DSP
792 /* magic mute channel */
793 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
794 SCBVolumeCtrl) << 2, 0xffffffff);
796 if (!cpcm->pcm_channel->unlinked)
797 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
799 spin_lock(&chip->reg_lock);
801 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
803 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
805 spin_unlock(&chip->reg_lock);
816 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
819 cs46xx_t *chip = snd_pcm_substream_chip(substream);
823 spin_lock(&chip->reg_lock);
825 case SNDRV_PCM_TRIGGER_START:
826 case SNDRV_PCM_TRIGGER_RESUME:
827 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
829 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
831 case SNDRV_PCM_TRIGGER_STOP:
832 case SNDRV_PCM_TRIGGER_SUSPEND:
833 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
835 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
841 spin_unlock(&chip->reg_lock);
846 #ifdef CONFIG_SND_CS46XX_NEW_DSP
847 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
851 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
852 if ( cpcm->pcm_channel == NULL) {
853 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
854 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
855 if (cpcm->pcm_channel == NULL) {
856 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
859 cpcm->pcm_channel->sample_rate = sample_rate;
861 /* if sample rate is changed */
862 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
863 int unlinked = cpcm->pcm_channel->unlinked;
864 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
866 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
868 cpcm->pcm_channel_id)) == NULL) {
869 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
873 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
874 cpcm->pcm_channel->sample_rate = sample_rate;
882 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
883 snd_pcm_hw_params_t * hw_params)
885 snd_pcm_runtime_t *runtime = substream->runtime;
888 #ifdef CONFIG_SND_CS46XX_NEW_DSP
889 cs46xx_t *chip = snd_pcm_substream_chip(substream);
890 int sample_rate = params_rate(hw_params);
891 int period_size = params_period_bytes(hw_params);
893 cpcm = runtime->private_data;
895 #ifdef CONFIG_SND_CS46XX_NEW_DSP
896 snd_assert (sample_rate != 0, return -ENXIO);
898 down (&chip->spos_mutex);
900 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
901 up (&chip->spos_mutex);
905 snd_assert (cpcm->pcm_channel != NULL);
906 if (!cpcm->pcm_channel) {
907 up (&chip->spos_mutex);
912 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
913 up (&chip->spos_mutex);
917 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
918 period_size, params_periods(hw_params),
919 params_buffer_bytes(hw_params));
922 if (params_periods(hw_params) == CS46XX_FRAGS) {
923 if (runtime->dma_area != cpcm->hw_buf.area)
924 snd_pcm_lib_free_pages(substream);
925 runtime->dma_area = cpcm->hw_buf.area;
926 runtime->dma_addr = cpcm->hw_buf.addr;
927 runtime->dma_bytes = cpcm->hw_buf.bytes;
930 #ifdef CONFIG_SND_CS46XX_NEW_DSP
931 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
932 substream->ops = &snd_cs46xx_playback_ops;
933 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
934 substream->ops = &snd_cs46xx_playback_rear_ops;
935 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
936 substream->ops = &snd_cs46xx_playback_clfe_ops;
937 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
938 substream->ops = &snd_cs46xx_playback_iec958_ops;
943 substream->ops = &snd_cs46xx_playback_ops;
947 if (runtime->dma_area == cpcm->hw_buf.area) {
948 runtime->dma_area = NULL;
949 runtime->dma_addr = 0;
950 runtime->dma_bytes = 0;
952 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
953 #ifdef CONFIG_SND_CS46XX_NEW_DSP
954 up (&chip->spos_mutex);
959 #ifdef CONFIG_SND_CS46XX_NEW_DSP
960 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
961 substream->ops = &snd_cs46xx_playback_indirect_ops;
962 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
963 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
964 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
965 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
966 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
967 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
972 substream->ops = &snd_cs46xx_playback_indirect_ops;
977 #ifdef CONFIG_SND_CS46XX_NEW_DSP
978 up (&chip->spos_mutex);
984 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
986 /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
987 snd_pcm_runtime_t *runtime = substream->runtime;
990 cpcm = runtime->private_data;
992 /* if play_back open fails, then this function
993 is called and cpcm can actually be NULL here */
994 if (!cpcm) return -ENXIO;
996 if (runtime->dma_area != cpcm->hw_buf.area)
997 snd_pcm_lib_free_pages(substream);
999 runtime->dma_area = NULL;
1000 runtime->dma_addr = 0;
1001 runtime->dma_bytes = 0;
1006 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1010 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1011 snd_pcm_runtime_t *runtime = substream->runtime;
1014 cpcm = runtime->private_data;
1016 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1017 snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1019 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1020 pfie &= ~0x0000f03f;
1023 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1024 pfie &= ~0x0000f03f;
1028 /* if to convert from stereo to mono */
1029 if (runtime->channels == 1) {
1033 /* if to convert from 8 bit to 16 bit */
1034 if (snd_pcm_format_width(runtime->format) == 8) {
1038 /* if to convert to unsigned */
1039 if (snd_pcm_format_unsigned(runtime->format))
1042 /* Never convert byte order when sample stream is 8 bit */
1043 if (snd_pcm_format_width(runtime->format) != 8) {
1044 /* convert from big endian to little endian */
1045 if (snd_pcm_format_big_endian(runtime->format))
1049 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1050 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1051 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1053 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1055 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1057 tmp |= (4 << cpcm->shift) - 1;
1058 /* playback transaction count register */
1059 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1061 /* playback format && interrupt enable */
1062 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1064 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1065 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1067 tmp |= (4 << cpcm->shift) - 1;
1068 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1069 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1070 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1076 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1077 snd_pcm_hw_params_t * hw_params)
1079 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1080 snd_pcm_runtime_t *runtime = substream->runtime;
1083 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1084 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1086 if (runtime->periods == CS46XX_FRAGS) {
1087 if (runtime->dma_area != chip->capt.hw_buf.area)
1088 snd_pcm_lib_free_pages(substream);
1089 runtime->dma_area = chip->capt.hw_buf.area;
1090 runtime->dma_addr = chip->capt.hw_buf.addr;
1091 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1092 substream->ops = &snd_cs46xx_capture_ops;
1094 if (runtime->dma_area == chip->capt.hw_buf.area) {
1095 runtime->dma_area = NULL;
1096 runtime->dma_addr = 0;
1097 runtime->dma_bytes = 0;
1099 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1101 substream->ops = &snd_cs46xx_capture_indirect_ops;
1107 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1109 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1110 snd_pcm_runtime_t *runtime = substream->runtime;
1112 if (runtime->dma_area != chip->capt.hw_buf.area)
1113 snd_pcm_lib_free_pages(substream);
1114 runtime->dma_area = NULL;
1115 runtime->dma_addr = 0;
1116 runtime->dma_bytes = 0;
1121 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1123 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1124 snd_pcm_runtime_t *runtime = substream->runtime;
1126 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1127 chip->capt.shift = 2;
1128 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1129 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1130 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1131 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1136 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1138 cs46xx_t *chip = dev_id;
1140 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1141 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1144 cs46xx_pcm_t *cpcm = NULL;
1148 * Read the Interrupt Status Register to clear the interrupt
1150 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1151 if ((status1 & 0x7fffffff) == 0) {
1152 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1156 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1157 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1159 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1161 if ( status1 & (1 << i) ) {
1162 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1163 if (chip->capt.substream)
1164 snd_pcm_period_elapsed(chip->capt.substream);
1166 if (ins->pcm_channels[i].active &&
1167 ins->pcm_channels[i].private_data &&
1168 !ins->pcm_channels[i].unlinked) {
1169 cpcm = ins->pcm_channels[i].private_data;
1170 snd_pcm_period_elapsed(cpcm->substream);
1175 if ( status2 & (1 << (i - 16))) {
1176 if (ins->pcm_channels[i].active &&
1177 ins->pcm_channels[i].private_data &&
1178 !ins->pcm_channels[i].unlinked) {
1179 cpcm = ins->pcm_channels[i].private_data;
1180 snd_pcm_period_elapsed(cpcm->substream);
1188 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1189 if (chip->playback_pcm->substream)
1190 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1192 if ((status1 & HISR_VC1) && chip->pcm) {
1193 if (chip->capt.substream)
1194 snd_pcm_period_elapsed(chip->capt.substream);
1198 if ((status1 & HISR_MIDI) && chip->rmidi) {
1201 spin_lock(&chip->reg_lock);
1202 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1203 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1204 if ((chip->midcr & MIDCR_RIE) == 0)
1206 spin_unlock(&chip->reg_lock);
1207 snd_rawmidi_receive(chip->midi_input, &c, 1);
1208 spin_lock(&chip->reg_lock);
1210 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1211 if ((chip->midcr & MIDCR_TIE) == 0)
1213 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1214 chip->midcr &= ~MIDCR_TIE;
1215 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1218 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1220 spin_unlock(&chip->reg_lock);
1223 * EOI to the PCI part....reenables interrupts
1225 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1230 static snd_pcm_hardware_t snd_cs46xx_playback =
1232 .info = (SNDRV_PCM_INFO_MMAP |
1233 SNDRV_PCM_INFO_INTERLEAVED |
1234 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1235 SNDRV_PCM_INFO_RESUME),
1236 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1237 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1238 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1239 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1244 .buffer_bytes_max = (256 * 1024),
1245 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1246 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1247 .periods_min = CS46XX_FRAGS,
1248 .periods_max = 1024,
1252 static snd_pcm_hardware_t snd_cs46xx_capture =
1254 .info = (SNDRV_PCM_INFO_MMAP |
1255 SNDRV_PCM_INFO_INTERLEAVED |
1256 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1257 SNDRV_PCM_INFO_RESUME),
1258 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1259 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1264 .buffer_bytes_max = (256 * 1024),
1265 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1266 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1267 .periods_min = CS46XX_FRAGS,
1268 .periods_max = 1024,
1272 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1274 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1276 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1277 .count = ARRAY_SIZE(period_sizes),
1278 .list = period_sizes,
1284 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1286 cs46xx_pcm_t * cpcm = runtime->private_data;
1290 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1292 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1293 cs46xx_pcm_t * cpcm;
1294 snd_pcm_runtime_t *runtime = substream->runtime;
1296 cpcm = kcalloc(1, sizeof(*cpcm), GFP_KERNEL);
1299 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1300 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1305 runtime->hw = snd_cs46xx_playback;
1306 runtime->private_data = cpcm;
1307 runtime->private_free = snd_cs46xx_pcm_free_substream;
1309 cpcm->substream = substream;
1310 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1311 down (&chip->spos_mutex);
1312 cpcm->pcm_channel = NULL;
1313 cpcm->pcm_channel_id = pcm_channel_id;
1316 snd_pcm_hw_constraint_list(runtime, 0,
1317 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1318 &hw_constraints_period_sizes);
1320 up (&chip->spos_mutex);
1322 chip->playback_pcm = cpcm; /* HACK */
1325 if (chip->accept_valid)
1326 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1327 chip->active_ctrl(chip, 1);
1332 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1334 snd_printdd("open front channel\n");
1335 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1338 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1339 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1341 snd_printdd("open rear channel\n");
1343 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1346 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1348 snd_printdd("open center - LFE channel\n");
1350 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1353 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1355 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1357 snd_printdd("open raw iec958 channel\n");
1359 down (&chip->spos_mutex);
1360 cs46xx_iec958_pre_open (chip);
1361 up (&chip->spos_mutex);
1363 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1366 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1368 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1371 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1373 snd_printdd("close raw iec958 channel\n");
1375 err = snd_cs46xx_playback_close(substream);
1377 down (&chip->spos_mutex);
1378 cs46xx_iec958_post_close (chip);
1379 up (&chip->spos_mutex);
1385 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1387 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1389 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1390 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1392 chip->capt.substream = substream;
1393 substream->runtime->hw = snd_cs46xx_capture;
1395 if (chip->accept_valid)
1396 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1398 chip->active_ctrl(chip, 1);
1400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1401 snd_pcm_hw_constraint_list(substream->runtime, 0,
1402 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1403 &hw_constraints_period_sizes);
1408 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1410 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1411 snd_pcm_runtime_t *runtime = substream->runtime;
1412 cs46xx_pcm_t * cpcm;
1414 cpcm = runtime->private_data;
1416 /* when playback_open fails, then cpcm can be NULL */
1417 if (!cpcm) return -ENXIO;
1419 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1420 down (&chip->spos_mutex);
1421 if (cpcm->pcm_channel) {
1422 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1423 cpcm->pcm_channel = NULL;
1425 up (&chip->spos_mutex);
1427 chip->playback_pcm = NULL;
1430 cpcm->substream = NULL;
1431 snd_dma_free_pages(&cpcm->hw_buf);
1432 chip->active_ctrl(chip, -1);
1437 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1439 cs46xx_t *chip = snd_pcm_substream_chip(substream);
1441 chip->capt.substream = NULL;
1442 snd_dma_free_pages(&chip->capt.hw_buf);
1443 chip->active_ctrl(chip, -1);
1448 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1449 snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1450 .open = snd_cs46xx_playback_open_rear,
1451 .close = snd_cs46xx_playback_close,
1452 .ioctl = snd_pcm_lib_ioctl,
1453 .hw_params = snd_cs46xx_playback_hw_params,
1454 .hw_free = snd_cs46xx_playback_hw_free,
1455 .prepare = snd_cs46xx_playback_prepare,
1456 .trigger = snd_cs46xx_playback_trigger,
1457 .pointer = snd_cs46xx_playback_direct_pointer,
1460 snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1461 .open = snd_cs46xx_playback_open_rear,
1462 .close = snd_cs46xx_playback_close,
1463 .ioctl = snd_pcm_lib_ioctl,
1464 .hw_params = snd_cs46xx_playback_hw_params,
1465 .hw_free = snd_cs46xx_playback_hw_free,
1466 .prepare = snd_cs46xx_playback_prepare,
1467 .trigger = snd_cs46xx_playback_trigger,
1468 .pointer = snd_cs46xx_playback_indirect_pointer,
1469 .ack = snd_cs46xx_playback_transfer,
1472 snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1473 .open = snd_cs46xx_playback_open_clfe,
1474 .close = snd_cs46xx_playback_close,
1475 .ioctl = snd_pcm_lib_ioctl,
1476 .hw_params = snd_cs46xx_playback_hw_params,
1477 .hw_free = snd_cs46xx_playback_hw_free,
1478 .prepare = snd_cs46xx_playback_prepare,
1479 .trigger = snd_cs46xx_playback_trigger,
1480 .pointer = snd_cs46xx_playback_direct_pointer,
1483 snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1484 .open = snd_cs46xx_playback_open_clfe,
1485 .close = snd_cs46xx_playback_close,
1486 .ioctl = snd_pcm_lib_ioctl,
1487 .hw_params = snd_cs46xx_playback_hw_params,
1488 .hw_free = snd_cs46xx_playback_hw_free,
1489 .prepare = snd_cs46xx_playback_prepare,
1490 .trigger = snd_cs46xx_playback_trigger,
1491 .pointer = snd_cs46xx_playback_indirect_pointer,
1492 .ack = snd_cs46xx_playback_transfer,
1495 snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1496 .open = snd_cs46xx_playback_open_iec958,
1497 .close = snd_cs46xx_playback_close_iec958,
1498 .ioctl = snd_pcm_lib_ioctl,
1499 .hw_params = snd_cs46xx_playback_hw_params,
1500 .hw_free = snd_cs46xx_playback_hw_free,
1501 .prepare = snd_cs46xx_playback_prepare,
1502 .trigger = snd_cs46xx_playback_trigger,
1503 .pointer = snd_cs46xx_playback_direct_pointer,
1506 snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1507 .open = snd_cs46xx_playback_open_iec958,
1508 .close = snd_cs46xx_playback_close_iec958,
1509 .ioctl = snd_pcm_lib_ioctl,
1510 .hw_params = snd_cs46xx_playback_hw_params,
1511 .hw_free = snd_cs46xx_playback_hw_free,
1512 .prepare = snd_cs46xx_playback_prepare,
1513 .trigger = snd_cs46xx_playback_trigger,
1514 .pointer = snd_cs46xx_playback_indirect_pointer,
1515 .ack = snd_cs46xx_playback_transfer,
1520 snd_pcm_ops_t snd_cs46xx_playback_ops = {
1521 .open = snd_cs46xx_playback_open,
1522 .close = snd_cs46xx_playback_close,
1523 .ioctl = snd_pcm_lib_ioctl,
1524 .hw_params = snd_cs46xx_playback_hw_params,
1525 .hw_free = snd_cs46xx_playback_hw_free,
1526 .prepare = snd_cs46xx_playback_prepare,
1527 .trigger = snd_cs46xx_playback_trigger,
1528 .pointer = snd_cs46xx_playback_direct_pointer,
1531 snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1532 .open = snd_cs46xx_playback_open,
1533 .close = snd_cs46xx_playback_close,
1534 .ioctl = snd_pcm_lib_ioctl,
1535 .hw_params = snd_cs46xx_playback_hw_params,
1536 .hw_free = snd_cs46xx_playback_hw_free,
1537 .prepare = snd_cs46xx_playback_prepare,
1538 .trigger = snd_cs46xx_playback_trigger,
1539 .pointer = snd_cs46xx_playback_indirect_pointer,
1540 .ack = snd_cs46xx_playback_transfer,
1543 snd_pcm_ops_t snd_cs46xx_capture_ops = {
1544 .open = snd_cs46xx_capture_open,
1545 .close = snd_cs46xx_capture_close,
1546 .ioctl = snd_pcm_lib_ioctl,
1547 .hw_params = snd_cs46xx_capture_hw_params,
1548 .hw_free = snd_cs46xx_capture_hw_free,
1549 .prepare = snd_cs46xx_capture_prepare,
1550 .trigger = snd_cs46xx_capture_trigger,
1551 .pointer = snd_cs46xx_capture_direct_pointer,
1554 snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1555 .open = snd_cs46xx_capture_open,
1556 .close = snd_cs46xx_capture_close,
1557 .ioctl = snd_pcm_lib_ioctl,
1558 .hw_params = snd_cs46xx_capture_hw_params,
1559 .hw_free = snd_cs46xx_capture_hw_free,
1560 .prepare = snd_cs46xx_capture_prepare,
1561 .trigger = snd_cs46xx_capture_trigger,
1562 .pointer = snd_cs46xx_capture_indirect_pointer,
1563 .ack = snd_cs46xx_capture_transfer,
1566 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1568 cs46xx_t *chip = pcm->private_data;
1570 snd_pcm_lib_preallocate_free_for_all(pcm);
1573 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1574 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1576 cs46xx_t *chip = pcm->private_data;
1577 chip->pcm_rear = NULL;
1578 snd_pcm_lib_preallocate_free_for_all(pcm);
1581 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1583 cs46xx_t *chip = pcm->private_data;
1584 chip->pcm_center_lfe = NULL;
1585 snd_pcm_lib_preallocate_free_for_all(pcm);
1588 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1590 cs46xx_t *chip = pcm->private_data;
1591 chip->pcm_iec958 = NULL;
1592 snd_pcm_lib_preallocate_free_for_all(pcm);
1595 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1597 #define MAX_PLAYBACK_CHANNELS 1
1600 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1607 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1610 pcm->private_data = chip;
1611 pcm->private_free = snd_cs46xx_pcm_free;
1613 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1614 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1617 pcm->info_flags = 0;
1618 strcpy(pcm->name, "CS46xx");
1621 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1622 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1631 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1632 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1640 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1643 pcm->private_data = chip;
1644 pcm->private_free = snd_cs46xx_pcm_rear_free;
1646 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1649 pcm->info_flags = 0;
1650 strcpy(pcm->name, "CS46xx - Rear");
1651 chip->pcm_rear = pcm;
1653 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1654 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1662 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1670 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1673 pcm->private_data = chip;
1674 pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1676 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1679 pcm->info_flags = 0;
1680 strcpy(pcm->name, "CS46xx - Center LFE");
1681 chip->pcm_center_lfe = pcm;
1683 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1684 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1692 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1700 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1703 pcm->private_data = chip;
1704 pcm->private_free = snd_cs46xx_pcm_iec958_free;
1706 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1709 pcm->info_flags = 0;
1710 strcpy(pcm->name, "CS46xx - IEC958");
1711 chip->pcm_rear = pcm;
1713 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1714 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1726 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t *bus)
1728 cs46xx_t *chip = bus->private_data;
1730 chip->ac97_bus = NULL;
1733 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1735 cs46xx_t *chip = ac97->private_data;
1737 snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1738 (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1741 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1742 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1743 chip->eapd_switch = NULL;
1746 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1749 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1750 snd_ctl_elem_info_t *uinfo)
1752 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1754 uinfo->value.integer.min = 0;
1755 uinfo->value.integer.max = 0x7fff;
1759 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1761 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1762 int reg = kcontrol->private_value;
1763 unsigned int val = snd_cs46xx_peek(chip, reg);
1764 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1765 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1769 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1771 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1772 int reg = kcontrol->private_value;
1773 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1774 (0xffff - ucontrol->value.integer.value[1]));
1775 unsigned int old = snd_cs46xx_peek(chip, reg);
1776 int change = (old != val);
1779 snd_cs46xx_poke(chip, reg, val);
1785 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1787 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1789 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1791 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1792 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1797 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1799 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1802 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1803 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1804 cs46xx_dsp_set_dac_volume(chip,
1805 ucontrol->value.integer.value[0],
1806 ucontrol->value.integer.value[1]);
1814 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1816 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1818 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1819 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1823 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1825 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1828 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1829 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1830 cs46xx_dsp_set_iec958_volume (chip,
1831 ucontrol->value.integer.value[0],
1832 ucontrol->value.integer.value[1]);
1840 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1841 snd_ctl_elem_info_t *uinfo)
1843 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1845 uinfo->value.integer.min = 0;
1846 uinfo->value.integer.max = 1;
1850 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1851 snd_ctl_elem_value_t *ucontrol)
1853 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1854 int reg = kcontrol->private_value;
1856 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1857 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1859 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1864 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1865 snd_ctl_elem_value_t *ucontrol)
1867 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1870 switch (kcontrol->private_value) {
1871 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1872 down (&chip->spos_mutex);
1873 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1874 if (ucontrol->value.integer.value[0] && !change)
1875 cs46xx_dsp_enable_spdif_out(chip);
1876 else if (change && !ucontrol->value.integer.value[0])
1877 cs46xx_dsp_disable_spdif_out(chip);
1879 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1880 up (&chip->spos_mutex);
1882 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1883 change = chip->dsp_spos_instance->spdif_status_in;
1884 if (ucontrol->value.integer.value[0] && !change) {
1885 cs46xx_dsp_enable_spdif_in(chip);
1886 /* restore volume */
1888 else if (change && !ucontrol->value.integer.value[0])
1889 cs46xx_dsp_disable_spdif_in(chip);
1891 res = (change != chip->dsp_spos_instance->spdif_status_in);
1895 snd_assert(0, (void)0);
1901 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
1902 snd_ctl_elem_value_t *ucontrol)
1904 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1905 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1907 if (ins->adc_input != NULL)
1908 ucontrol->value.integer.value[0] = 1;
1910 ucontrol->value.integer.value[0] = 0;
1915 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
1916 snd_ctl_elem_value_t *ucontrol)
1918 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1919 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1922 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1923 cs46xx_dsp_enable_adc_capture(chip);
1925 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1926 cs46xx_dsp_disable_adc_capture(chip);
1932 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
1933 snd_ctl_elem_value_t *ucontrol)
1935 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1936 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1938 if (ins->pcm_input != NULL)
1939 ucontrol->value.integer.value[0] = 1;
1941 ucontrol->value.integer.value[0] = 0;
1947 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
1948 snd_ctl_elem_value_t *ucontrol)
1950 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1951 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1954 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1955 cs46xx_dsp_enable_pcm_capture(chip);
1957 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1958 cs46xx_dsp_disable_pcm_capture(chip);
1965 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
1966 snd_ctl_elem_value_t *ucontrol)
1968 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1970 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1972 if (val1 & EGPIODR_GPOE0)
1973 ucontrol->value.integer.value[0] = 1;
1975 ucontrol->value.integer.value[0] = 0;
1981 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1983 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
1984 snd_ctl_elem_value_t *ucontrol)
1986 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1987 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1988 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1990 if (ucontrol->value.integer.value[0]) {
1991 /* optical is default */
1992 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1993 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
1994 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1995 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1998 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
1999 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2002 /* checking diff from the EGPIO direction register
2004 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2008 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2010 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2015 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2016 snd_ctl_elem_value_t * ucontrol)
2018 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2019 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2021 down (&chip->spos_mutex);
2022 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2023 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2024 ucontrol->value.iec958.status[2] = 0;
2025 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2026 up (&chip->spos_mutex);
2031 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2032 snd_ctl_elem_value_t * ucontrol)
2034 cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2035 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2039 down (&chip->spos_mutex);
2040 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2041 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2042 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2043 /* left and right validity bit */
2044 (1 << 13) | (1 << 12);
2047 change = (unsigned int)ins->spdif_csuv_default != val;
2048 ins->spdif_csuv_default = val;
2050 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2051 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2053 up (&chip->spos_mutex);
2058 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2059 snd_ctl_elem_value_t * ucontrol)
2061 ucontrol->value.iec958.status[0] = 0xff;
2062 ucontrol->value.iec958.status[1] = 0xff;
2063 ucontrol->value.iec958.status[2] = 0x00;
2064 ucontrol->value.iec958.status[3] = 0xff;
2068 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2069 snd_ctl_elem_value_t * ucontrol)
2071 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2072 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2074 down (&chip->spos_mutex);
2075 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2076 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2077 ucontrol->value.iec958.status[2] = 0;
2078 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2079 up (&chip->spos_mutex);
2084 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2085 snd_ctl_elem_value_t * ucontrol)
2087 cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2088 dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2092 down (&chip->spos_mutex);
2093 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2094 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2095 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2096 /* left and right validity bit */
2097 (1 << 13) | (1 << 12);
2100 change = ins->spdif_csuv_stream != val;
2101 ins->spdif_csuv_stream = val;
2103 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2104 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2106 up (&chip->spos_mutex);
2111 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2114 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2115 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2116 snd_ctl_elem_info_t *uinfo)
2118 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2120 uinfo->value.integer.min = 0;
2121 uinfo->value.integer.max = 8;
2125 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2126 snd_ctl_elem_value_t *ucontrol)
2128 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2129 ucontrol->value.integer.value[0] = chip->current_gpio;
2134 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2135 snd_ctl_elem_value_t *ucontrol)
2137 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2138 int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2139 chip->current_gpio = ucontrol->value.integer.value[0];
2145 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2146 snd_ctl_elem_value_t *ucontrol)
2148 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2149 int reg = kcontrol->private_value;
2151 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2152 ucontrol->value.integer.value[0] =
2153 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2158 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2159 snd_ctl_elem_value_t *ucontrol)
2161 cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2162 int reg = kcontrol->private_value;
2163 int val = snd_cs46xx_peekBA0(chip, reg);
2165 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2167 if (ucontrol->value.integer.value[0])
2168 val |= (1 << chip->current_gpio);
2170 val &= ~(1 << chip->current_gpio);
2172 snd_cs46xx_pokeBA0(chip, reg,val);
2173 snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2175 return (oldval != val);
2177 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2179 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2181 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2182 .name = "DAC Volume",
2183 .info = snd_cs46xx_vol_info,
2184 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2185 .get = snd_cs46xx_vol_get,
2186 .put = snd_cs46xx_vol_put,
2187 .private_value = BA1_PVOL,
2189 .get = snd_cs46xx_vol_dac_get,
2190 .put = snd_cs46xx_vol_dac_put,
2195 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2196 .name = "ADC Volume",
2197 .info = snd_cs46xx_vol_info,
2198 .get = snd_cs46xx_vol_get,
2199 .put = snd_cs46xx_vol_put,
2200 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2201 .private_value = BA1_CVOL,
2203 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2206 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2208 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2209 .name = "ADC Capture Switch",
2210 .info = snd_mixer_boolean_info,
2211 .get = snd_cs46xx_adc_capture_get,
2212 .put = snd_cs46xx_adc_capture_put
2215 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2216 .name = "DAC Capture Switch",
2217 .info = snd_mixer_boolean_info,
2218 .get = snd_cs46xx_pcm_capture_get,
2219 .put = snd_cs46xx_pcm_capture_put
2222 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2223 .name = "IEC958 Output Switch",
2224 .info = snd_mixer_boolean_info,
2225 .get = snd_cs46xx_iec958_get,
2226 .put = snd_cs46xx_iec958_put,
2227 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2230 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2231 .name = "IEC958 Input Switch",
2232 .info = snd_mixer_boolean_info,
2233 .get = snd_cs46xx_iec958_get,
2234 .put = snd_cs46xx_iec958_put,
2235 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2238 /* Input IEC958 volume does not work for the moment. (Benny) */
2240 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2241 .name = "IEC958 Input Volume",
2242 .info = snd_cs46xx_vol_info,
2243 .get = snd_cs46xx_vol_iec958_get,
2244 .put = snd_cs46xx_vol_iec958_put,
2245 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2249 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2250 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2251 .info = snd_cs46xx_spdif_info,
2252 .get = snd_cs46xx_spdif_default_get,
2253 .put = snd_cs46xx_spdif_default_put,
2256 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2257 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2258 .info = snd_cs46xx_spdif_info,
2259 .get = snd_cs46xx_spdif_mask_get,
2260 .access = SNDRV_CTL_ELEM_ACCESS_READ
2263 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2264 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2265 .info = snd_cs46xx_spdif_info,
2266 .get = snd_cs46xx_spdif_stream_get,
2267 .put = snd_cs46xx_spdif_stream_put
2271 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2273 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2274 .name = "EGPIO select",
2275 .info = snd_cs46xx_egpio_select_info,
2276 .get = snd_cs46xx_egpio_select_get,
2277 .put = snd_cs46xx_egpio_select_put,
2281 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2282 .name = "EGPIO Input/Output",
2283 .info = snd_mixer_boolean_info,
2284 .get = snd_cs46xx_egpio_get,
2285 .put = snd_cs46xx_egpio_put,
2286 .private_value = BA0_EGPIODR,
2289 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2290 .name = "EGPIO CMOS/Open drain",
2291 .info = snd_mixer_boolean_info,
2292 .get = snd_cs46xx_egpio_get,
2293 .put = snd_cs46xx_egpio_put,
2294 .private_value = BA0_EGPIOPTR,
2297 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2298 .name = "EGPIO On/Off",
2299 .info = snd_mixer_boolean_info,
2300 .get = snd_cs46xx_egpio_get,
2301 .put = snd_cs46xx_egpio_put,
2302 .private_value = BA0_EGPIOSR,
2307 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2308 /* Only available on the Hercules Game Theater XP soundcard */
2309 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2311 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2312 .name = "Optical/Coaxial SPDIF Input Switch",
2313 .info = snd_mixer_boolean_info,
2314 .get = snd_herc_spdif_select_get,
2315 .put = snd_herc_spdif_select_put,
2320 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2322 unsigned long end_time;
2325 /* reset to defaults */
2326 snd_ac97_write(ac97, AC97_RESET, 0);
2328 /* set the desired CODEC mode */
2329 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2330 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2331 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2332 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2333 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2334 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2336 snd_assert(0); /* should never happen ... */
2341 /* it's necessary to wait awhile until registers are accessible after RESET */
2342 /* because the PCM or MASTER volume registers can be modified, */
2343 /* the REC_GAIN register is used for tests */
2344 end_time = jiffies + HZ;
2346 unsigned short ext_mid;
2348 /* use preliminary reads to settle the communication */
2349 snd_ac97_read(ac97, AC97_RESET);
2350 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2351 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2353 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2354 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2357 /* test if we can write to the record gain volume register */
2358 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2359 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2362 set_current_state(TASK_UNINTERRUPTIBLE);
2363 schedule_timeout(HZ/100);
2364 } while (time_after_eq(end_time, jiffies));
2366 snd_printk("CS46xx secondary codec dont respond!\n");
2370 static int __devinit cs46xx_detect_codec(cs46xx_t *chip, int codec)
2373 ac97_template_t ac97;
2375 memset(&ac97, 0, sizeof(ac97));
2376 ac97.private_data = chip;
2377 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2379 if (chip->amplifier_ctrl == amp_voyetra)
2380 ac97.scaps = AC97_SCAP_INV_EAPD;
2382 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2383 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2385 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2386 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2391 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2392 for (idx = 0; idx < 100; ++idx) {
2393 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2394 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2397 set_current_state(TASK_INTERRUPTIBLE);
2398 schedule_timeout(HZ/100);
2400 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2404 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2406 snd_card_t *card = chip->card;
2407 snd_ctl_elem_id_t id;
2410 static ac97_bus_ops_t ops = {
2411 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2412 .reset = snd_cs46xx_codec_reset,
2414 .write = snd_cs46xx_ac97_write,
2415 .read = snd_cs46xx_ac97_read,
2418 /* detect primary codec */
2419 chip->nr_ac97_codecs = 0;
2420 snd_printdd("snd_cs46xx: detecting primary codec\n");
2421 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2423 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2425 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2427 chip->nr_ac97_codecs = 1;
2429 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2430 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2431 /* try detect a secondary codec */
2432 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2433 chip->nr_ac97_codecs = 2;
2434 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2436 /* add cs4630 mixer controls */
2437 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2438 snd_kcontrol_t *kctl;
2439 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2440 if ((err = snd_ctl_add(card, kctl)) < 0)
2444 /* get EAPD mixer switch (for voyetra hack) */
2445 memset(&id, 0, sizeof(id));
2446 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2447 strcpy(id.name, "External Amplifier");
2448 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2450 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2451 if (chip->nr_ac97_codecs == 1) {
2452 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2453 if (id2 == 0x592b || id2 == 0x592d) {
2454 /* set primary cs4294 codec into Extended Audio Mode */
2455 snd_printdd("setting EAM bit on cs4294 CODEC\n");
2456 snd_cs46xx_codec_write(chip, AC97_CSR_ACMODE, 0x200,
2457 CS46XX_PRIMARY_CODEC_INDEX);
2460 /* do soundcard specific mixer setup */
2461 if (chip->mixer_init) {
2462 snd_printdd ("calling chip->mixer_init(chip);\n");
2463 chip->mixer_init(chip);
2467 /* turn on amplifier */
2468 chip->amplifier_ctrl(chip, 1);
2477 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2479 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2481 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2484 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2486 cs46xx_t *chip = substream->rmidi->private_data;
2488 chip->active_ctrl(chip, 1);
2489 spin_lock_irq(&chip->reg_lock);
2490 chip->uartm |= CS46XX_MODE_INPUT;
2491 chip->midcr |= MIDCR_RXE;
2492 chip->midi_input = substream;
2493 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2494 snd_cs46xx_midi_reset(chip);
2496 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2498 spin_unlock_irq(&chip->reg_lock);
2502 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2504 cs46xx_t *chip = substream->rmidi->private_data;
2506 spin_lock_irq(&chip->reg_lock);
2507 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2508 chip->midi_input = NULL;
2509 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2510 snd_cs46xx_midi_reset(chip);
2512 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2514 chip->uartm &= ~CS46XX_MODE_INPUT;
2515 spin_unlock_irq(&chip->reg_lock);
2516 chip->active_ctrl(chip, -1);
2520 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2522 cs46xx_t *chip = substream->rmidi->private_data;
2524 chip->active_ctrl(chip, 1);
2526 spin_lock_irq(&chip->reg_lock);
2527 chip->uartm |= CS46XX_MODE_OUTPUT;
2528 chip->midcr |= MIDCR_TXE;
2529 chip->midi_output = substream;
2530 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2531 snd_cs46xx_midi_reset(chip);
2533 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2535 spin_unlock_irq(&chip->reg_lock);
2539 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2541 cs46xx_t *chip = substream->rmidi->private_data;
2543 spin_lock_irq(&chip->reg_lock);
2544 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2545 chip->midi_output = NULL;
2546 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2547 snd_cs46xx_midi_reset(chip);
2549 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2551 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2552 spin_unlock_irq(&chip->reg_lock);
2553 chip->active_ctrl(chip, -1);
2557 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2559 unsigned long flags;
2560 cs46xx_t *chip = substream->rmidi->private_data;
2562 spin_lock_irqsave(&chip->reg_lock, flags);
2564 if ((chip->midcr & MIDCR_RIE) == 0) {
2565 chip->midcr |= MIDCR_RIE;
2566 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2569 if (chip->midcr & MIDCR_RIE) {
2570 chip->midcr &= ~MIDCR_RIE;
2571 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2574 spin_unlock_irqrestore(&chip->reg_lock, flags);
2577 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2579 unsigned long flags;
2580 cs46xx_t *chip = substream->rmidi->private_data;
2583 spin_lock_irqsave(&chip->reg_lock, flags);
2585 if ((chip->midcr & MIDCR_TIE) == 0) {
2586 chip->midcr |= MIDCR_TIE;
2587 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2588 while ((chip->midcr & MIDCR_TIE) &&
2589 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2590 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2591 chip->midcr &= ~MIDCR_TIE;
2593 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2596 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2599 if (chip->midcr & MIDCR_TIE) {
2600 chip->midcr &= ~MIDCR_TIE;
2601 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2604 spin_unlock_irqrestore(&chip->reg_lock, flags);
2607 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2609 .open = snd_cs46xx_midi_output_open,
2610 .close = snd_cs46xx_midi_output_close,
2611 .trigger = snd_cs46xx_midi_output_trigger,
2614 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2616 .open = snd_cs46xx_midi_input_open,
2617 .close = snd_cs46xx_midi_input_close,
2618 .trigger = snd_cs46xx_midi_input_trigger,
2621 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2623 snd_rawmidi_t *rmidi;
2628 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2630 strcpy(rmidi->name, "CS46XX");
2631 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2632 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2633 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2634 rmidi->private_data = chip;
2635 chip->rmidi = rmidi;
2643 * gameport interface
2646 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2648 typedef struct snd_cs46xx_gameport {
2649 struct gameport info;
2651 } cs46xx_gameport_t;
2653 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2655 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2657 snd_assert(gp, return);
2659 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2662 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2664 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2666 snd_assert(gp, return 0);
2668 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2671 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2673 cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2675 unsigned js1, js2, jst;
2677 snd_assert(gp, return 0);
2680 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2681 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2682 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2684 *buttons = (~jst >> 4) & 0x0F;
2686 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2687 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2688 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2689 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2691 for(jst=0;jst<4;++jst)
2692 if(axes[jst]==0xFFFF) axes[jst] = -1;
2696 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2699 case GAMEPORT_MODE_COOKED:
2701 case GAMEPORT_MODE_RAW:
2709 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2711 cs46xx_gameport_t *gp;
2712 gp = kmalloc(sizeof(*gp), GFP_KERNEL);
2714 snd_printk("cannot allocate gameport area\n");
2717 memset(gp, 0, sizeof(*gp));
2718 gp->info.open = snd_cs46xx_gameport_open;
2719 gp->info.read = snd_cs46xx_gameport_read;
2720 gp->info.trigger = snd_cs46xx_gameport_trigger;
2721 gp->info.cooked_read = snd_cs46xx_gameport_cooked_read;
2723 chip->gameport = gp;
2725 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2726 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2727 gameport_register_port(&gp->info);
2732 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2736 #endif /* CONFIG_GAMEPORT */
2742 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2743 struct file *file, char __user *buf,
2744 unsigned long count, unsigned long pos)
2747 snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2750 if (pos + (size_t)size > region->size)
2751 size = region->size - pos;
2753 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2759 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2760 .read = snd_cs46xx_io_read,
2763 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2765 snd_info_entry_t *entry;
2768 for (idx = 0; idx < 5; idx++) {
2769 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2770 if (! snd_card_proc_new(card, region->name, &entry)) {
2771 entry->content = SNDRV_INFO_CONTENT_DATA;
2772 entry->private_data = chip;
2773 entry->c.ops = &snd_cs46xx_proc_io_ops;
2774 entry->size = region->size;
2775 entry->mode = S_IFREG | S_IRUSR;
2778 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2779 cs46xx_dsp_proc_init(card, chip);
2784 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2786 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2787 cs46xx_dsp_proc_done(chip);
2795 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2799 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2802 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2804 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2807 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2810 * Stop playback DMA.
2812 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2813 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2818 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2819 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2822 * Reset the processor.
2824 snd_cs46xx_reset(chip);
2826 snd_cs46xx_proc_stop(chip);
2829 * Power down the PLL.
2831 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2834 * Turn off the Processor by turning off the software clock enable flag in
2835 * the clock control register.
2837 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2838 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2842 static int snd_cs46xx_free(cs46xx_t *chip)
2846 snd_assert(chip != NULL, return -EINVAL);
2848 if (chip->active_ctrl)
2849 chip->active_ctrl(chip, 1);
2851 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2852 if (chip->gameport) {
2853 gameport_unregister_port(&chip->gameport->info);
2854 kfree(chip->gameport);
2858 if (chip->amplifier_ctrl)
2859 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2861 snd_cs46xx_proc_done(chip);
2863 if (chip->region.idx[0].resource)
2864 snd_cs46xx_hw_stop(chip);
2866 for (idx = 0; idx < 5; idx++) {
2867 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2868 if (region->remap_addr)
2869 iounmap(region->remap_addr);
2870 if (region->resource) {
2871 release_resource(region->resource);
2872 kfree_nocheck(region->resource);
2876 free_irq(chip->irq, (void *)chip);
2878 if (chip->active_ctrl)
2879 chip->active_ctrl(chip, -chip->amplifier);
2881 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2882 if (chip->dsp_spos_instance) {
2883 cs46xx_dsp_spos_destroy(chip);
2884 chip->dsp_spos_instance = NULL;
2888 pci_disable_device(chip->pci);
2893 static int snd_cs46xx_dev_free(snd_device_t *device)
2895 cs46xx_t *chip = device->device_data;
2896 return snd_cs46xx_free(chip);
2902 static int snd_cs46xx_chip_init(cs46xx_t *chip)
2907 * First, blast the clock control register to zero so that the PLL starts
2908 * out in a known state, and blast the master serial port control register
2909 * to zero so that the serial ports also start out in a known state.
2911 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2912 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2915 * If we are in AC97 mode, then we must set the part to a host controlled
2916 * AC-link. Otherwise, we won't be able to bring up the link.
2918 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2919 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2920 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2921 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2923 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2927 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2928 * spec) and then drive it high. This is done for non AC97 modes since
2929 * there might be logic external to the CS461x that uses the ARST# line
2932 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2933 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2934 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2937 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2938 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2939 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2943 * The first thing we do here is to enable sync generation. As soon
2944 * as we start receiving bit clock, we'll start producing the SYNC
2947 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2949 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2953 * Now wait for a short while to allow the AC97 part to start
2954 * generating bit clock (so we don't try to start the PLL without an
2960 * Set the serial port timing configuration, so that
2961 * the clock control circuit gets its clock from the correct place.
2963 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2966 * Write the selected clock control setup to the hardware. Do not turn on
2967 * SWCE yet (if requested), so that the devices clocked by the output of
2968 * PLL are not clocked until the PLL is stable.
2970 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2971 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2972 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2977 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2980 * Wait until the PLL has stabilized.
2982 set_current_state(TASK_UNINTERRUPTIBLE);
2983 schedule_timeout(HZ/10); /* 100ms */
2986 * Turn on clocking of the core so that we can setup the serial ports.
2988 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2991 * Enable FIFO Host Bypass
2993 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2996 * Fill the serial port FIFOs with silence.
2998 snd_cs46xx_clear_serial_FIFOs(chip);
3001 * Set the serial port FIFO pointer to the first sample in the FIFO.
3003 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3006 * Write the serial port configuration to the part. The master
3007 * enable bit is not set until all other values have been written.
3009 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3010 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3011 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3014 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3015 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3016 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3017 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3018 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3019 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3026 * Wait for the codec ready signal from the AC97 codec.
3029 while (timeout-- > 0) {
3031 * Read the AC97 status register to see if we've seen a CODEC READY
3032 * signal from the AC97 codec.
3034 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3036 set_current_state(TASK_UNINTERRUPTIBLE);
3037 schedule_timeout((HZ+99)/100);
3041 snd_printk("create - never read codec ready from AC'97\n");
3042 snd_printk("it is not probably bug, try to use CS4236 driver\n");
3045 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3048 for (count = 0; count < 150; count++) {
3049 /* First, we want to wait for a short time. */
3052 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3057 * Make sure CODEC is READY.
3059 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3060 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3065 * Assert the vaid frame signal so that we can start sending commands
3066 * to the AC97 codec.
3068 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3069 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3070 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3075 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3076 * the codec is pumping ADC data across the AC-link.
3079 while (timeout-- > 0) {
3081 * Read the input slot valid register and see if input slots 3 and
3084 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3086 set_current_state(TASK_UNINTERRUPTIBLE);
3087 schedule_timeout((HZ+99)/100);
3090 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3091 snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3094 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3095 Reloading the driver may help, if there's other soundcards
3096 with the same problem I would like to know. (Benny) */
3098 snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3099 snd_printk(" Try reloading the ALSA driver, if you find something\n");
3100 snd_printk(" broken or not working on your soundcard upon\n");
3101 snd_printk(" this message please report to alsa-devel@lists.sourceforge.net\n");
3108 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3109 * commense the transfer of digital audio data to the AC97 codec.
3112 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3116 * Power down the DAC and ADC. We will power them up (if) when we need
3119 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3122 * Turn off the Processor by turning off the software clock enable flag in
3123 * the clock control register.
3125 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3126 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3132 * start and load DSP
3134 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3138 * Reset the processor.
3140 snd_cs46xx_reset(chip);
3142 * Download the image to the processor.
3144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3146 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3147 snd_printk(KERN_ERR "image download error\n");
3152 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3153 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3157 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3158 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3162 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3163 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3167 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3168 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3172 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3173 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3177 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3181 if (snd_cs46xx_download_image(chip) < 0) {
3182 snd_printk("image download error\n");
3187 * Stop playback DMA.
3189 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3190 chip->play_ctl = tmp & 0xffff0000;
3191 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3197 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3198 chip->capt.ctl = tmp & 0x0000ffff;
3199 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3203 snd_cs46xx_set_play_sample_rate(chip, 8000);
3204 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3206 snd_cs46xx_proc_start(chip);
3209 * Enable interrupts on the part.
3211 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3213 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3215 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3217 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3220 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3222 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3223 /* set the attenuation to 0dB */
3224 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3225 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3233 * AMP control - null AMP
3236 static void amp_none(cs46xx_t *chip, int change)
3240 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3241 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3244 u32 idx, valid_slots,tmp,powerdown = 0;
3245 u16 modem_power,pin_config,logic_type;
3247 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3250 * See if the devices are powered down. If so, we must power them up first
3251 * or they will not respond.
3253 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3255 if (!(tmp & CLKCR1_SWCE)) {
3256 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3261 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3264 if(chip->nr_ac97_codecs != 2) {
3265 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3269 modem_power = snd_cs46xx_codec_read (chip,
3270 AC97_EXTENDED_MSTATUS,
3271 CS46XX_SECONDARY_CODEC_INDEX);
3272 modem_power &=0xFEFF;
3274 snd_cs46xx_codec_write(chip,
3275 AC97_EXTENDED_MSTATUS, modem_power,
3276 CS46XX_SECONDARY_CODEC_INDEX);
3279 * Set GPIO pin's 7 and 8 so that they are configured for output.
3281 pin_config = snd_cs46xx_codec_read (chip,
3283 CS46XX_SECONDARY_CODEC_INDEX);
3286 snd_cs46xx_codec_write(chip,
3287 AC97_GPIO_CFG, pin_config,
3288 CS46XX_SECONDARY_CODEC_INDEX);
3291 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3294 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3295 CS46XX_SECONDARY_CODEC_INDEX);
3298 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3299 CS46XX_SECONDARY_CODEC_INDEX);
3301 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3302 valid_slots |= 0x200;
3303 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3305 if ( cs46xx_wait_for_fifo(chip,1) ) {
3306 snd_printdd("FIFO is busy\n");
3312 * Fill slots 12 with the correct value for the GPIO pins.
3314 for(idx = 0x90; idx <= 0x9F; idx++) {
3316 * Initialize the fifo so that bits 7 and 8 are on.
3318 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3319 * the left. 0x1800 corresponds to bits 7 and 8.
3321 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3324 * Wait for command to complete
3326 if ( cs46xx_wait_for_fifo(chip,200) ) {
3327 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3333 * Write the serial port FIFO index.
3335 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3338 * Tell the serial port to load the new value into the FIFO location.
3340 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3343 /* wait for last command to complete */
3344 cs46xx_wait_for_fifo(chip,200);
3347 * Now, if we powered up the devices, then power them back down again.
3348 * This is kinda ugly, but should never happen.
3351 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3361 static void amp_voyetra(cs46xx_t *chip, int change)
3363 /* Manage the EAPD bit on the Crystal 4297
3364 and the Analog AD1885 */
3366 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3367 int old = chip->amplifier;
3371 chip->amplifier += change;
3372 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3373 CS46XX_PRIMARY_CODEC_INDEX);
3375 if (chip->amplifier) {
3376 /* Turn the EAPD amp on */
3379 /* Turn the EAPD amp off */
3383 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3384 CS46XX_PRIMARY_CODEC_INDEX);
3385 if (chip->eapd_switch)
3386 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3387 &chip->eapd_switch->id);
3390 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3391 if (chip->amplifier && !old) {
3392 voyetra_setup_eapd_slot(chip);
3397 static void hercules_init(cs46xx_t *chip)
3399 /* default: AMP off, and SPDIF input optical */
3400 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3401 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3406 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3408 static void amp_hercules(cs46xx_t *chip, int change)
3410 int old = chip->amplifier;
3411 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3412 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3414 chip->amplifier += change;
3415 if (chip->amplifier && !old) {
3416 snd_printdd ("Hercules amplifier ON\n");
3418 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3419 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3420 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3421 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3422 } else if (old && !chip->amplifier) {
3423 snd_printdd ("Hercules amplifier OFF\n");
3424 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3425 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3429 static void voyetra_mixer_init (cs46xx_t *chip)
3431 snd_printdd ("initializing Voyetra mixer\n");
3433 /* Enable SPDIF out */
3434 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3435 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3438 static void hercules_mixer_init (cs46xx_t *chip)
3440 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3443 snd_card_t *card = chip->card;
3446 /* set EGPIO to default */
3447 hercules_init(chip);
3449 snd_printdd ("initializing Hercules mixer\n");
3451 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3452 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3453 snd_kcontrol_t *kctl;
3455 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3456 if ((err = snd_ctl_add(card, kctl)) < 0) {
3457 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3470 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3472 chip->amplifier += change;
3474 if (chip->amplifier) {
3475 /* Switch the GPIO pins 7 and 8 to open drain */
3476 snd_cs46xx_codec_write(chip, 0x4C,
3477 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3478 snd_cs46xx_codec_write(chip, 0x4E,
3479 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3480 /* Now wake the AMP (this might be backwards) */
3481 snd_cs46xx_codec_write(chip, 0x54,
3482 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3484 snd_cs46xx_codec_write(chip, 0x54,
3485 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3494 #ifndef PCI_VENDOR_ID_INTEL
3495 #define PCI_VENDOR_ID_INTEL 0x8086
3496 #endif /* PCI_VENDOR_ID_INTEL */
3498 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3499 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3500 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3503 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3504 * whenever we need to beat on the chip.
3506 * The original idea and code for this hack comes from David Kaiser at
3507 * Linuxcare. Perhaps one day Crystal will document their chips well
3508 * enough to make them useful.
3511 static void clkrun_hack(cs46xx_t *chip, int change)
3515 if (chip->acpi_dev == NULL)
3518 chip->amplifier += change;
3520 /* Read ACPI port */
3521 nval = control = inw(chip->acpi_port + 0x10);
3523 /* Flip CLKRUN off while running */
3524 if (! chip->amplifier)
3528 if (nval != control)
3529 outw(nval, chip->acpi_port + 0x10);
3534 * detect intel piix4
3536 static void clkrun_init(cs46xx_t *chip)
3540 chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3541 if (chip->acpi_dev == NULL)
3542 return; /* Not a thinkpad thats for sure */
3544 /* Find the control port */
3545 pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3546 chip->acpi_port = pp << 8;
3559 void (*init)(cs46xx_t *);
3560 void (*amp)(cs46xx_t *, int);
3561 void (*active)(cs46xx_t *, int);
3562 void (*mixer_init)(cs46xx_t *);
3565 static struct cs_card_type __devinitdata cards[] = {
3569 .name = "Genius Soundmaker 128 value",
3570 /* nothing special */
3577 .mixer_init = voyetra_mixer_init,
3582 .name = "Mitac MI6020/21",
3588 .name = "Hercules Game Theatre XP",
3589 .amp = amp_hercules,
3590 .mixer_init = hercules_mixer_init,
3595 .name = "Hercules Game Theatre XP",
3596 .amp = amp_hercules,
3597 .mixer_init = hercules_mixer_init,
3602 .name = "Hercules Game Theatre XP",
3603 .amp = amp_hercules,
3604 .mixer_init = hercules_mixer_init,
3610 .name = "Hercules Game Theatre XP",
3611 .amp = amp_hercules,
3612 .mixer_init = hercules_mixer_init,
3617 .name = "Hercules Game Theatre XP",
3618 .amp = amp_hercules,
3619 .mixer_init = hercules_mixer_init,
3624 .name = "Hercules Game Theatre XP",
3625 .amp = amp_hercules,
3626 .mixer_init = hercules_mixer_init,
3632 .name = "Terratec SiXPack 5.1",
3634 /* Not sure if the 570 needs the clkrun hack */
3636 .vendor = PCI_VENDOR_ID_IBM,
3638 .name = "Thinkpad 570",
3639 .init = clkrun_init,
3640 .active = clkrun_hack,
3643 .vendor = PCI_VENDOR_ID_IBM,
3645 .name = "Thinkpad 600X/A20/T20",
3646 .init = clkrun_init,
3647 .active = clkrun_hack,
3650 .vendor = PCI_VENDOR_ID_IBM,
3652 .name = "Thinkpad 600E (unsupported)",
3662 static int snd_cs46xx_suspend(snd_card_t *card, unsigned int state)
3664 cs46xx_t *chip = card->pm_private_data;
3667 snd_pcm_suspend_all(chip->pcm);
3668 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3669 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3671 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3672 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3673 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3675 amp_saved = chip->amplifier;
3677 chip->amplifier_ctrl(chip, -chip->amplifier);
3678 snd_cs46xx_hw_stop(chip);
3679 /* disable CLKRUN */
3680 chip->active_ctrl(chip, -chip->amplifier);
3681 chip->amplifier = amp_saved; /* restore the status */
3682 pci_disable_device(chip->pci);
3683 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3687 static int snd_cs46xx_resume(snd_card_t *card, unsigned int state)
3689 cs46xx_t *chip = card->pm_private_data;
3692 pci_enable_device(chip->pci);
3693 pci_set_master(chip->pci);
3694 amp_saved = chip->amplifier;
3695 chip->amplifier = 0;
3696 chip->active_ctrl(chip, 1); /* force to on */
3698 snd_cs46xx_chip_init(chip);
3701 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3702 chip->ac97_general_purpose);
3703 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3704 chip->ac97_powerdown);
3706 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3707 chip->ac97_powerdown);
3711 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3712 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3713 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3716 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3718 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3719 chip->amplifier = amp_saved;
3720 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3723 #endif /* CONFIG_PM */
3729 int __devinit snd_cs46xx_create(snd_card_t * card,
3730 struct pci_dev * pci,
3731 int external_amp, int thinkpad,
3736 snd_cs46xx_region_t *region;
3737 struct cs_card_type *cp;
3738 u16 ss_card, ss_vendor;
3739 static snd_device_ops_t ops = {
3740 .dev_free = snd_cs46xx_dev_free,
3745 /* enable PCI device */
3746 if ((err = pci_enable_device(pci)) < 0)
3749 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
3751 pci_disable_device(pci);
3754 spin_lock_init(&chip->reg_lock);
3755 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3756 init_MUTEX(&chip->spos_mutex);
3761 chip->ba0_addr = pci_resource_start(pci, 0);
3762 chip->ba1_addr = pci_resource_start(pci, 1);
3763 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3764 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3765 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3766 snd_cs46xx_free(chip);
3770 region = &chip->region.name.ba0;
3771 strcpy(region->name, "CS46xx_BA0");
3772 region->base = chip->ba0_addr;
3773 region->size = CS46XX_BA0_SIZE;
3775 region = &chip->region.name.data0;
3776 strcpy(region->name, "CS46xx_BA1_data0");
3777 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3778 region->size = CS46XX_BA1_DATA0_SIZE;
3780 region = &chip->region.name.data1;
3781 strcpy(region->name, "CS46xx_BA1_data1");
3782 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3783 region->size = CS46XX_BA1_DATA1_SIZE;
3785 region = &chip->region.name.pmem;
3786 strcpy(region->name, "CS46xx_BA1_pmem");
3787 region->base = chip->ba1_addr + BA1_SP_PMEM;
3788 region->size = CS46XX_BA1_PRG_SIZE;
3790 region = &chip->region.name.reg;
3791 strcpy(region->name, "CS46xx_BA1_reg");
3792 region->base = chip->ba1_addr + BA1_SP_REG;
3793 region->size = CS46XX_BA1_REG_SIZE;
3795 /* set up amp and clkrun hack */
3796 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3797 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3799 for (cp = &cards[0]; cp->name; cp++) {
3800 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3801 snd_printdd ("hack for %s enabled\n", cp->name);
3803 chip->amplifier_ctrl = cp->amp;
3804 chip->active_ctrl = cp->active;
3805 chip->mixer_init = cp->mixer_init;
3814 snd_printk("Crystal EAPD support forced on.\n");
3815 chip->amplifier_ctrl = amp_voyetra;
3819 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3820 chip->active_ctrl = clkrun_hack;
3824 if (chip->amplifier_ctrl == NULL)
3825 chip->amplifier_ctrl = amp_none;
3826 if (chip->active_ctrl == NULL)
3827 chip->active_ctrl = amp_none;
3829 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3831 pci_set_master(pci);
3833 for (idx = 0; idx < 5; idx++) {
3834 region = &chip->region.idx[idx];
3835 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3836 snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3837 snd_cs46xx_free(chip);
3840 region->remap_addr = ioremap_nocache(region->base, region->size);
3841 if (region->remap_addr == NULL) {
3842 snd_printk("%s ioremap problem\n", region->name);
3843 snd_cs46xx_free(chip);
3848 if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3849 snd_printk("unable to grab IRQ %d\n", pci->irq);
3850 snd_cs46xx_free(chip);
3853 chip->irq = pci->irq;
3855 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3856 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3857 if (chip->dsp_spos_instance == NULL) {
3858 snd_cs46xx_free(chip);
3863 err = snd_cs46xx_chip_init(chip);
3865 snd_cs46xx_free(chip);
3869 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3870 snd_cs46xx_free(chip);
3874 snd_cs46xx_proc_init(card, chip);
3876 snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3878 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3880 snd_card_set_dev(card, &pci->dev);