sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #ifdef CHIP1371
  36 #include <sound/ac97_codec.h>
  37 #else
  38 #include <sound/ak4531_codec.h>
  39 #endif
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #ifndef CHIP1371
  44 #undef CHIP1370
  45 #define CHIP1370
  46 #endif
  47
  48 #ifdef CHIP1370
  49 #define DRIVER_NAME "ENS1370"
  50 #else
  51 #define DRIVER_NAME "ENS1371"
  52 #endif
  53
  54
  55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  56 MODULE_LICENSE("GPL");
  57 #ifdef CHIP1370
  58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  60                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  61 #endif
  62 #ifdef CHIP1371
  63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  65                 "{Ensoniq,AudioPCI ES1373},"
  66                 "{Creative Labs,Ectiva EV1938},"
  67                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  68                 "{Creative Labs,Vibra PCI128},"
  69                 "{Ectiva,EV1938}}");
  70 #endif
  71
  72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  73 #define SUPPORT_JOYSTICK
  74 #endif
  75
  76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  79 #ifdef SUPPORT_JOYSTICK
  80 #ifdef CHIP1371
  81 static int joystick_port[SNDRV_CARDS];
  82 #else
  83 static int joystick[SNDRV_CARDS];
  84 #endif
  85 #endif
  86
  87 module_param_array(index, int, NULL, 0444);
  88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  89 module_param_array(id, charp, NULL, 0444);
  90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  91 module_param_array(enable, bool, NULL, 0444);
  92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  93 #ifdef SUPPORT_JOYSTICK
  94 #ifdef CHIP1371
  95 module_param_array(joystick_port, int, NULL, 0444);
  96 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  97 #else
  98 module_param_array(joystick, bool, NULL, 0444);
  99 MODULE_PARM_DESC(joystick, "Enable joystick.");
 100 #endif
 101 #endif /* SUPPORT_JOYSTICK */
 102
 103 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
 104 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
 105 #endif
 106 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
 107 #define PCI_DEVICE_ID_ENSONIQ_ES1371    0x1371
 108 #endif
 109
 110 /* ES1371 chip ID */
 111 /* This is a little confusing because all ES1371 compatible chips have the
 112    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 113    This is only significant if you want to enable features on the later parts.
 114    Yes, I know it's stupid and why didn't we use the sub IDs?
 115 */
 116 #define ES1371REV_ES1373_A  0x04
 117 #define ES1371REV_ES1373_B  0x06
 118 #define ES1371REV_CT5880_A  0x07
 119 #define CT5880REV_CT5880_C  0x02
 120 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 121 #define CT5880REV_CT5880_E  0x04        /* mw */
 122 #define ES1371REV_ES1371_B  0x09
 123 #define EV1938REV_EV1938_A  0x00
 124 #define ES1371REV_ES1373_8  0x08
 125
 126 /*
 127  * Direct registers
 128  */
 129
 130 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 131
 132 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 133 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 134 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 135 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 136 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 137 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 138 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 139 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 140 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 141 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 142 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 143 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 144 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 145 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 146 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 147 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 148 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 149 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 150 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 151 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 152 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 153 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 154 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 155 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 156 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 157 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 158 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 159 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 160 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 161 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 162 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 163 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 164 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 165 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 166 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 167 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 168 #define   ES_UART_EN            (1<<3)          /* UART enable */
 169 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 170 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 171 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 172 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 173 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 174 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 175 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 176 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 177 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 178 #define   ES_1373_REAR_BIT26    (1<<26)
 179 #define   ES_1373_REAR_BIT24    (1<<24)
 180 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 181 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 182 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 183 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 184 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 185 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 186 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 187 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 188 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 189 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 190 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 191 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 192 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 193 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 194 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 195 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 196 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 197 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 198 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 199 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 200 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 201 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 202 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 203 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 204 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 205 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 206 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 207 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 208 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 209 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 210 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 211 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 212 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 213 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 214 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 215 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 216 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 217 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 218 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 219 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 220 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 221 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 222 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 223 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 224 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 225
 226 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 227 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 228 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 229 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 230 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 231 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 232 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 233 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 234 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 235 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 236 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 237 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 238 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 239
 240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 241 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 242 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 243 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 244 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 245 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 246 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 247 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 248 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 249 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 250 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 251 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 252 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 253 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 254 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 255 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 256 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 257 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 258 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 259 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 260 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 261 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 262 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 263
 264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 265
 266 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 267 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 268 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 269 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 270 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 271 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 272 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 273 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 274 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 275 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 276 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 277 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 278 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 279 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 280 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 281 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 282 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 283 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 284 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 285 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 286 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 287 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 288 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 289 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 290 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 291 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 292 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 293
 294 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 295 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 296 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 297 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 298 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 299 #define   ES_REG_COUNTM         (0xffff<<0)
 300 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 301
 302 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 303 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 304 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 305 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 306 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 307 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 308 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 309 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 310 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 311 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 312 #define   ES_REG_FSIZEM          (0xffff<<0)
 313 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 316
 317 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 318 #define   ES_REG_UF_VALID        (1<<8)
 319 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 320 #define   ES_REG_UF_BYTEM        (0xff<<0)
 321 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 322
 323
 324 /*
 325  *  Pages
 326  */
 327
 328 #define ES_PAGE_DAC     0x0c
 329 #define ES_PAGE_ADC     0x0d
 330 #define ES_PAGE_UART    0x0e
 331 #define ES_PAGE_UART1   0x0f
 332
 333 /*
 334  *  Sample rate converter addresses
 335  */
 336
 337 #define ES_SMPREG_DAC1          0x70
 338 #define ES_SMPREG_DAC2          0x74
 339 #define ES_SMPREG_ADC           0x78
 340 #define ES_SMPREG_VOL_ADC       0x6c
 341 #define ES_SMPREG_VOL_DAC1      0x7c
 342 #define ES_SMPREG_VOL_DAC2      0x7e
 343 #define ES_SMPREG_TRUNC_N       0x00
 344 #define ES_SMPREG_INT_REGS      0x01
 345 #define ES_SMPREG_ACCUM_FRAC    0x02
 346 #define ES_SMPREG_VFREQ_FRAC    0x03
 347
 348 /*
 349  *  Some contants
 350  */
 351
 352 #define ES_1370_SRCLOCK    1411200
 353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 354
 355 /*
 356  *  Open modes
 357  */
 358
 359 #define ES_MODE_PLAY1   0x0001
 360 #define ES_MODE_PLAY2   0x0002
 361 #define ES_MODE_CAPTURE 0x0004
 362
 363 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 364 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 365
 366 /*
 367
 368  */
 369
 370 typedef struct _snd_ensoniq ensoniq_t;
 371
 372 struct _snd_ensoniq {
 373         spinlock_t reg_lock;
 374         struct semaphore src_mutex;
 375
 376         int irq;
 377
 378         unsigned long playback1size;
 379         unsigned long playback2size;
 380         unsigned long capture3size;
 381
 382         unsigned long port;
 383         unsigned int mode;
 384         unsigned int uartm;     /* UART mode */
 385
 386         unsigned int ctrl;      /* control register */
 387         unsigned int sctrl;     /* serial control register */
 388         unsigned int cssr;      /* control status register */
 389         unsigned int uartc;     /* uart control register */
 390         unsigned int rev;       /* chip revision */
 391
 392         union {
 393 #ifdef CHIP1371
 394                 struct {
 395                         ac97_t *ac97;
 396                 } es1371;
 397 #else
 398                 struct {
 399                         int pclkdiv_lock;
 400                         ak4531_t *ak4531;
 401                 } es1370;
 402 #endif
 403         } u;
 404
 405         struct pci_dev *pci;
 406         unsigned short subsystem_vendor_id;
 407         unsigned short subsystem_device_id;
 408         snd_card_t *card;
 409         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 410         snd_pcm_t *pcm2;        /* DAC2 PCM */
 411         snd_pcm_substream_t *playback1_substream;
 412         snd_pcm_substream_t *playback2_substream;
 413         snd_pcm_substream_t *capture_substream;
 414         unsigned int p1_dma_size;
 415         unsigned int p2_dma_size;
 416         unsigned int c_dma_size;
 417         unsigned int p1_period_size;
 418         unsigned int p2_period_size;
 419         unsigned int c_period_size;
 420         snd_rawmidi_t *rmidi;
 421         snd_rawmidi_substream_t *midi_input;
 422         snd_rawmidi_substream_t *midi_output;
 423
 424         unsigned int spdif;
 425         unsigned int spdif_default;
 426         unsigned int spdif_stream;
 427
 428 #ifdef CHIP1370
 429         struct snd_dma_buffer dma_bug;
 430 #endif
 431
 432 #ifdef SUPPORT_JOYSTICK
 433         struct gameport gameport;
 434 #endif
 435 };
 436
 437 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 438
 439 static struct pci_device_id snd_audiopci_ids[] = {
 440 #ifdef CHIP1370
 441         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 442 #endif
 443 #ifdef CHIP1371
 444         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 445         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 446         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 447 #endif
 448         { 0, }
 449 };
 450
 451 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 452
 453 /*
 454  *  constants
 455  */
 456
 457 #define POLL_COUNT      0xa000
 458
 459 #ifdef CHIP1370
 460 static unsigned int snd_es1370_fixed_rates[] =
 461         {5512, 11025, 22050, 44100};
 462 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 463         .count = 4,
 464         .list = snd_es1370_fixed_rates,
 465         .mask = 0,
 466 };
 467 static ratnum_t es1370_clock = {
 468         .num = ES_1370_SRCLOCK,
 469         .den_min = 29,
 470         .den_max = 353,
 471         .den_step = 1,
 472 };
 473 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 474         .nrats = 1,
 475         .rats = &es1370_clock,
 476 };
 477 #else
 478 static ratden_t es1371_dac_clock = {
 479         .num_min = 3000 * (1 << 15),
 480         .num_max = 48000 * (1 << 15),
 481         .num_step = 3000,
 482         .den = 1 << 15,
 483 };
 484 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 485         .nrats = 1,
 486         .rats = &es1371_dac_clock,
 487 };
 488 static ratnum_t es1371_adc_clock = {
 489         .num = 48000 << 15,
 490         .den_min = 32768,
 491         .den_max = 393216,
 492         .den_step = 1,
 493 };
 494 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_adc_clock,
 497 };
 498 #endif
 499 static const unsigned int snd_ensoniq_sample_shift[] =
 500         {0, 1, 1, 2};
 501
 502 /*
 503  *  common I/O routines
 504  */
 505
 506 #ifdef CHIP1371
 507
 508 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 509 {
 510         unsigned int t, r = 0;
 511
 512         for (t = 0; t < POLL_COUNT; t++) {
 513                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 514                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 515                         return r;
 516                 cond_resched();
 517         }
 518         snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 519         return 0;
 520 }
 521
 522 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 523 {
 524         unsigned int temp, i, orig, r;
 525
 526         /* wait for ready */
 527         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 528
 529         /* expose the SRC state bits */
 530         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 531                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 532         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 533         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 534
 535         /* now, wait for busy and the correct time to read */
 536         temp = snd_es1371_wait_src_ready(ensoniq);
 537
 538         if ((temp & 0x00870000) != 0x00010000) {
 539                 /* wait for the right state */
 540                 for (i = 0; i < POLL_COUNT; i++) {
 541                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 542                         if ((temp & 0x00870000) == 0x00010000)
 543                                 break;
 544                 }
 545         }
 546
 547         /* hide the state bits */
 548         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 549                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 550         r |= ES_1371_SRC_RAM_ADDRO(reg);
 551         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 552
 553         return temp;
 554 }
 555
 556 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 557                                  unsigned short reg, unsigned short data)
 558 {
 559         unsigned int r;
 560
 561         r = snd_es1371_wait_src_ready(ensoniq) &
 562             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 563              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 564         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 565         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 566 }
 567
 568 #endif /* CHIP1371 */
 569
 570 #ifdef CHIP1370
 571
 572 static void snd_es1370_codec_write(ak4531_t *ak4531,
 573                                    unsigned short reg, unsigned short val)
 574 {
 575         ensoniq_t *ensoniq = ak4531->private_data;
 576         unsigned long flags;
 577         unsigned long end_time = jiffies + HZ / 10;
 578
 579 #if 0
 580         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 581 #endif
 582         do {
 583                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 584                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 585                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 586                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 587                         return;
 588                 }
 589                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 590 #if 0
 591                 set_current_state(TASK_UNINTERRUPTIBLE);
 592                 schedule_timeout(1);
 593 #endif
 594         } while (time_after(end_time, jiffies));
 595         snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 596 }
 597
 598 #endif /* CHIP1370 */
 599
 600 #ifdef CHIP1371
 601
 602 static void snd_es1371_codec_write(ac97_t *ac97,
 603                                    unsigned short reg, unsigned short val)
 604 {
 605         ensoniq_t *ensoniq = ac97->private_data;
 606         unsigned long flags;
 607         unsigned int t, x;
 608
 609         for (t = 0; t < POLL_COUNT; t++) {
 610                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 611                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 612                         /* save the current state for latter */
 613                         x = snd_es1371_wait_src_ready(ensoniq);
 614                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 615                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 616                              ES_REG(ensoniq, 1371_SMPRATE));
 617                         /* wait for not busy (state 0) first to avoid
 618                            transition states */
 619                         for (t = 0; t < POLL_COUNT; t++) {
 620                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 621                                         break;
 622                         }
 623                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 624                         for (t = 0; t < POLL_COUNT; t++) {
 625                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 626                                         break;
 627                         }
 628                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 629                         /* restore SRC reg */
 630                         snd_es1371_wait_src_ready(ensoniq);
 631                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 632                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 633                         return;
 634                 }
 635                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 636         }
 637         snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 638 }
 639
 640 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 641                                             unsigned short reg)
 642 {
 643         ensoniq_t *ensoniq = ac97->private_data;
 644         unsigned long flags;
 645         unsigned int t, x, fail = 0;
 646
 647       __again:
 648         for (t = 0; t < POLL_COUNT; t++) {
 649                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 650                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 651                         /* save the current state for latter */
 652                         x = snd_es1371_wait_src_ready(ensoniq);
 653                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 654                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 655                              ES_REG(ensoniq, 1371_SMPRATE));
 656                         /* wait for not busy (state 0) first to avoid
 657                            transition states */
 658                         for (t = 0; t < POLL_COUNT; t++) {
 659                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 660                                         break;
 661                         }
 662                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 663                         for (t = 0; t < POLL_COUNT; t++) {
 664                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 665                                         break;
 666                         }
 667                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 668                         /* restore SRC reg */
 669                         snd_es1371_wait_src_ready(ensoniq);
 670                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 671                         /* wait for WIP again */
 672                         for (t = 0; t < POLL_COUNT; t++) {
 673                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 674                                         break;
 675                         }
 676                         /* now wait for the stinkin' data (RDY) */
 677                         for (t = 0; t < POLL_COUNT; t++) {
 678                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 679                                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 680                                         return ES_1371_CODEC_READ(x);
 681                                 }
 682                         }
 683                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 684                         if (++fail > 10) {
 685                                 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 686                                 return 0;
 687                         }
 688                         goto __again;
 689                 }
 690                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 691         }
 692         snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 693         return 0;
 694 }
 695
 696 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 697 {
 698         unsigned int n, truncm, freq, result;
 699
 700         down(&ensoniq->src_mutex);
 701         n = rate / 3000;
 702         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 703                 n--;
 704         truncm = (21 * n - 1) | 1;
 705         freq = ((48000UL << 15) / rate) * n;
 706         result = (48000UL << 15) / (freq / n);
 707         if (rate >= 24000) {
 708                 if (truncm > 239)
 709                         truncm = 239;
 710                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 711                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 712         } else {
 713                 if (truncm > 119)
 714                         truncm = 119;
 715                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 716                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 717         }
 718         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 719                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 720                                      ((freq >> 5) & 0xfc00));
 721         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 722         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 723         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 724         up(&ensoniq->src_mutex);
 725 }
 726
 727 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 728 {
 729         unsigned int freq, r;
 730
 731         down(&ensoniq->src_mutex);
 732         freq = ((rate << 15) + 1500) / 3000;
 733         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 734         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 735         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 736                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 737                              ((freq >> 5) & 0xfc00));
 738         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 739         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 740         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 741         up(&ensoniq->src_mutex);
 742 }
 743
 744 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 745 {
 746         unsigned int freq, r;
 747
 748         down(&ensoniq->src_mutex);
 749         freq = ((rate << 15) + 1500) / 3000;
 750         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 751         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 752         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 753                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 754                              ((freq >> 5) & 0xfc00));
 755         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 756         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 757         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 758         up(&ensoniq->src_mutex);
 759 }
 760
 761 #endif /* CHIP1371 */
 762
 763 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 764 {
 765         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 766         switch (cmd) {
 767         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 768         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 769         {
 770                 unsigned int what = 0;
 771                 struct list_head *pos;
 772                 snd_pcm_substream_t *s;
 773                 snd_pcm_group_for_each(pos, substream) {
 774                         s = snd_pcm_group_substream_entry(pos);
 775                         if (s == ensoniq->playback1_substream) {
 776                                 what |= ES_P1_PAUSE;
 777                                 snd_pcm_trigger_done(s, substream);
 778                         } else if (s == ensoniq->playback2_substream) {
 779                                 what |= ES_P2_PAUSE;
 780                                 snd_pcm_trigger_done(s, substream);
 781                         } else if (s == ensoniq->capture_substream)
 782                                 return -EINVAL;
 783                 }
 784                 spin_lock(&ensoniq->reg_lock);
 785                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 786                         ensoniq->sctrl |= what;
 787                 else
 788                         ensoniq->sctrl &= ~what;
 789                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 790                 spin_unlock(&ensoniq->reg_lock);
 791                 break;
 792         }
 793         case SNDRV_PCM_TRIGGER_START:
 794         case SNDRV_PCM_TRIGGER_STOP:
 795         {
 796                 unsigned int what = 0;
 797                 struct list_head *pos;
 798                 snd_pcm_substream_t *s;
 799                 snd_pcm_group_for_each(pos, substream) {
 800                         s = snd_pcm_group_substream_entry(pos);
 801                         if (s == ensoniq->playback1_substream) {
 802                                 what |= ES_DAC1_EN;
 803                                 snd_pcm_trigger_done(s, substream);
 804                         } else if (s == ensoniq->playback2_substream) {
 805                                 what |= ES_DAC2_EN;
 806                                 snd_pcm_trigger_done(s, substream);
 807                         } else if (s == ensoniq->capture_substream) {
 808                                 what |= ES_ADC_EN;
 809                                 snd_pcm_trigger_done(s, substream);
 810                         }
 811                 }
 812                 spin_lock(&ensoniq->reg_lock);
 813                 if (cmd == SNDRV_PCM_TRIGGER_START)
 814                         ensoniq->ctrl |= what;
 815                 else
 816                         ensoniq->ctrl &= ~what;
 817                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 818                 spin_unlock(&ensoniq->reg_lock);
 819                 break;
 820         }
 821         default:
 822                 return -EINVAL;
 823         }
 824         return 0;
 825 }
 826
 827 /*
 828  *  PCM part
 829  */
 830
 831 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 832                                  snd_pcm_hw_params_t * hw_params)
 833 {
 834         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 835 }
 836
 837 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 838 {
 839         return snd_pcm_lib_free_pages(substream);
 840 }
 841
 842 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 843 {
 844         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 845         snd_pcm_runtime_t *runtime = substream->runtime;
 846         unsigned int mode = 0;
 847
 848         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 849         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 850         if (snd_pcm_format_width(runtime->format) == 16)
 851                 mode |= 0x02;
 852         if (runtime->channels > 1)
 853                 mode |= 0x01;
 854         spin_lock_irq(&ensoniq->reg_lock);
 855         ensoniq->ctrl &= ~ES_DAC1_EN;
 856 #ifdef CHIP1371
 857         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 858         if (runtime->rate == 48000)
 859                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 860         else
 861                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 862 #endif
 863         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 864         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 865         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 866         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 867         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 868         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 869         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 870         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 871 #ifdef CHIP1370
 872         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 873         switch (runtime->rate) {
 874         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 875         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 876         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 877         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 878         default: snd_BUG();
 879         }
 880 #endif
 881         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 882         spin_unlock_irq(&ensoniq->reg_lock);
 883 #ifndef CHIP1370
 884         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 885 #endif
 886         return 0;
 887 }
 888
 889 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 890 {
 891         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 892         snd_pcm_runtime_t *runtime = substream->runtime;
 893         unsigned int mode = 0;
 894
 895         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 896         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 897         if (snd_pcm_format_width(runtime->format) == 16)
 898                 mode |= 0x02;
 899         if (runtime->channels > 1)
 900                 mode |= 0x01;
 901         spin_lock_irq(&ensoniq->reg_lock);
 902         ensoniq->ctrl &= ~ES_DAC2_EN;
 903         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 904         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 905         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 906         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 907         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 908                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 909         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 910                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 911         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 912         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 913 #ifdef CHIP1370
 914         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 915                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 916                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 917                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 918         }
 919 #endif
 920         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 921         spin_unlock_irq(&ensoniq->reg_lock);
 922 #ifndef CHIP1370
 923         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 924 #endif
 925         return 0;
 926 }
 927
 928 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 929 {
 930         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 931         snd_pcm_runtime_t *runtime = substream->runtime;
 932         unsigned int mode = 0;
 933
 934         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 935         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 936         if (snd_pcm_format_width(runtime->format) == 16)
 937                 mode |= 0x02;
 938         if (runtime->channels > 1)
 939                 mode |= 0x01;
 940         spin_lock_irq(&ensoniq->reg_lock);
 941         ensoniq->ctrl &= ~ES_ADC_EN;
 942         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 943         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 944         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 945         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 946         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 947         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 948         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 949         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 950 #ifdef CHIP1370
 951         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 952                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 953                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 954                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 955         }
 956 #endif
 957         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 958         spin_unlock_irq(&ensoniq->reg_lock);
 959 #ifndef CHIP1370
 960         snd_es1371_adc_rate(ensoniq, runtime->rate);
 961 #endif
 962         return 0;
 963 }
 964
 965 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 966 {
 967         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 968         size_t ptr;
 969
 970         spin_lock(&ensoniq->reg_lock);
 971         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 972                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 973                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 974                 ptr = bytes_to_frames(substream->runtime, ptr);
 975         } else {
 976                 ptr = 0;
 977         }
 978         spin_unlock(&ensoniq->reg_lock);
 979         return ptr;
 980 }
 981
 982 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 983 {
 984         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 985         size_t ptr;
 986
 987         spin_lock(&ensoniq->reg_lock);
 988         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 989                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 990                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 991                 ptr = bytes_to_frames(substream->runtime, ptr);
 992         } else {
 993                 ptr = 0;
 994         }
 995         spin_unlock(&ensoniq->reg_lock);
 996         return ptr;
 997 }
 998
 999 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
1000 {
1001         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1002         size_t ptr;
1003
1004         spin_lock(&ensoniq->reg_lock);
1005         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1006                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1007                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1008                 ptr = bytes_to_frames(substream->runtime, ptr);
1009         } else {
1010                 ptr = 0;
1011         }
1012         spin_unlock(&ensoniq->reg_lock);
1013         return ptr;
1014 }
1015
1016 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1017 {
1018         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1019                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1020                                  SNDRV_PCM_INFO_MMAP_VALID |
1021                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1022         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1023         .rates =
1024 #ifndef CHIP1370
1025                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1026 #else
1027                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1028                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1029                                  SNDRV_PCM_RATE_44100),
1030 #endif
1031         .rate_min =             4000,
1032         .rate_max =             48000,
1033         .channels_min =         1,
1034         .channels_max =         2,
1035         .buffer_bytes_max =     (128*1024),
1036         .period_bytes_min =     64,
1037         .period_bytes_max =     (128*1024),
1038         .periods_min =          1,
1039         .periods_max =          1024,
1040         .fifo_size =            0,
1041 };
1042
1043 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1044 {
1045         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1046                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1047                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1048                                  SNDRV_PCM_INFO_SYNC_START),
1049         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1050         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1051         .rate_min =             4000,
1052         .rate_max =             48000,
1053         .channels_min =         1,
1054         .channels_max =         2,
1055         .buffer_bytes_max =     (128*1024),
1056         .period_bytes_min =     64,
1057         .period_bytes_max =     (128*1024),
1058         .periods_min =          1,
1059         .periods_max =          1024,
1060         .fifo_size =            0,
1061 };
1062
1063 static snd_pcm_hardware_t snd_ensoniq_capture =
1064 {
1065         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1066                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1067                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1068         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1069         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1070         .rate_min =             4000,
1071         .rate_max =             48000,
1072         .channels_min =         1,
1073         .channels_max =         2,
1074         .buffer_bytes_max =     (128*1024),
1075         .period_bytes_min =     64,
1076         .period_bytes_max =     (128*1024),
1077         .periods_min =          1,
1078         .periods_max =          1024,
1079         .fifo_size =            0,
1080 };
1081
1082 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1083 {
1084         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1085         snd_pcm_runtime_t *runtime = substream->runtime;
1086
1087         ensoniq->mode |= ES_MODE_PLAY1;
1088         ensoniq->playback1_substream = substream;
1089         runtime->hw = snd_ensoniq_playback1;
1090         snd_pcm_set_sync(substream);
1091         spin_lock_irq(&ensoniq->reg_lock);
1092         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1093                 ensoniq->spdif_stream = ensoniq->spdif_default;
1094         spin_unlock_irq(&ensoniq->reg_lock);
1095 #ifdef CHIP1370
1096         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1097                                    &snd_es1370_hw_constraints_rates);
1098 #else
1099         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1100                                       &snd_es1371_hw_constraints_dac_clock);
1101 #endif
1102         return 0;
1103 }
1104
1105 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1106 {
1107         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1108         snd_pcm_runtime_t *runtime = substream->runtime;
1109
1110         ensoniq->mode |= ES_MODE_PLAY2;
1111         ensoniq->playback2_substream = substream;
1112         runtime->hw = snd_ensoniq_playback2;
1113         snd_pcm_set_sync(substream);
1114         spin_lock_irq(&ensoniq->reg_lock);
1115         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1116                 ensoniq->spdif_stream = ensoniq->spdif_default;
1117         spin_unlock_irq(&ensoniq->reg_lock);
1118 #ifdef CHIP1370
1119         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1120                                       &snd_es1370_hw_constraints_clock);
1121 #else
1122         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1123                                       &snd_es1371_hw_constraints_dac_clock);
1124 #endif
1125         return 0;
1126 }
1127
1128 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1129 {
1130         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1131         snd_pcm_runtime_t *runtime = substream->runtime;
1132
1133         ensoniq->mode |= ES_MODE_CAPTURE;
1134         ensoniq->capture_substream = substream;
1135         runtime->hw = snd_ensoniq_capture;
1136         snd_pcm_set_sync(substream);
1137 #ifdef CHIP1370
1138         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1139                                       &snd_es1370_hw_constraints_clock);
1140 #else
1141         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1142                                       &snd_es1371_hw_constraints_adc_clock);
1143 #endif
1144         return 0;
1145 }
1146
1147 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1148 {
1149         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1150
1151         ensoniq->playback1_substream = NULL;
1152         ensoniq->mode &= ~ES_MODE_PLAY1;
1153         return 0;
1154 }
1155
1156 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1157 {
1158         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1159
1160         ensoniq->playback2_substream = NULL;
1161         spin_lock_irq(&ensoniq->reg_lock);
1162 #ifdef CHIP1370
1163         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1164 #endif
1165         ensoniq->mode &= ~ES_MODE_PLAY2;
1166         spin_unlock_irq(&ensoniq->reg_lock);
1167         return 0;
1168 }
1169
1170 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1171 {
1172         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1173
1174         ensoniq->capture_substream = NULL;
1175         spin_lock_irq(&ensoniq->reg_lock);
1176 #ifdef CHIP1370
1177         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1178 #endif
1179         ensoniq->mode &= ~ES_MODE_CAPTURE;
1180         spin_unlock_irq(&ensoniq->reg_lock);
1181         return 0;
1182 }
1183
1184 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1185         .open =         snd_ensoniq_playback1_open,
1186         .close =        snd_ensoniq_playback1_close,
1187         .ioctl =        snd_pcm_lib_ioctl,
1188         .hw_params =    snd_ensoniq_hw_params,
1189         .hw_free =      snd_ensoniq_hw_free,
1190         .prepare =      snd_ensoniq_playback1_prepare,
1191         .trigger =      snd_ensoniq_trigger,
1192         .pointer =      snd_ensoniq_playback1_pointer,
1193 };
1194
1195 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1196         .open =         snd_ensoniq_playback2_open,
1197         .close =        snd_ensoniq_playback2_close,
1198         .ioctl =        snd_pcm_lib_ioctl,
1199         .hw_params =    snd_ensoniq_hw_params,
1200         .hw_free =      snd_ensoniq_hw_free,
1201         .prepare =      snd_ensoniq_playback2_prepare,
1202         .trigger =      snd_ensoniq_trigger,
1203         .pointer =      snd_ensoniq_playback2_pointer,
1204 };
1205
1206 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1207         .open =         snd_ensoniq_capture_open,
1208         .close =        snd_ensoniq_capture_close,
1209         .ioctl =        snd_pcm_lib_ioctl,
1210         .hw_params =    snd_ensoniq_hw_params,
1211         .hw_free =      snd_ensoniq_hw_free,
1212         .prepare =      snd_ensoniq_capture_prepare,
1213         .trigger =      snd_ensoniq_trigger,
1214         .pointer =      snd_ensoniq_capture_pointer,
1215 };
1216
1217 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1218 {
1219         ensoniq_t *ensoniq = pcm->private_data;
1220         ensoniq->pcm1 = NULL;
1221         snd_pcm_lib_preallocate_free_for_all(pcm);
1222 }
1223
1224 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1225 {
1226         snd_pcm_t *pcm;
1227         int err;
1228
1229         if (rpcm)
1230                 *rpcm = NULL;
1231 #ifdef CHIP1370
1232         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1233 #else
1234         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1235 #endif
1236         if (err < 0)
1237                 return err;
1238
1239 #ifdef CHIP1370
1240         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1241 #else
1242         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1243 #endif
1244         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1245
1246         pcm->private_data = ensoniq;
1247         pcm->private_free = snd_ensoniq_pcm_free;
1248         pcm->info_flags = 0;
1249 #ifdef CHIP1370
1250         strcpy(pcm->name, "ES1370 DAC2/ADC");
1251 #else
1252         strcpy(pcm->name, "ES1371 DAC2/ADC");
1253 #endif
1254         ensoniq->pcm1 = pcm;
1255
1256         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1257                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1258
1259         if (rpcm)
1260                 *rpcm = pcm;
1261         return 0;
1262 }
1263
1264 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1265 {
1266         ensoniq_t *ensoniq = pcm->private_data;
1267         ensoniq->pcm2 = NULL;
1268         snd_pcm_lib_preallocate_free_for_all(pcm);
1269 }
1270
1271 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1272 {
1273         snd_pcm_t *pcm;
1274         int err;
1275
1276         if (rpcm)
1277                 *rpcm = NULL;
1278 #ifdef CHIP1370
1279         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1280 #else
1281         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1282 #endif
1283         if (err < 0)
1284                 return err;
1285
1286 #ifdef CHIP1370
1287         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1288 #else
1289         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1290 #endif
1291         pcm->private_data = ensoniq;
1292         pcm->private_free = snd_ensoniq_pcm_free2;
1293         pcm->info_flags = 0;
1294 #ifdef CHIP1370
1295         strcpy(pcm->name, "ES1370 DAC1");
1296 #else
1297         strcpy(pcm->name, "ES1371 DAC1");
1298 #endif
1299         ensoniq->pcm2 = pcm;
1300
1301         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1302                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1303
1304         if (rpcm)
1305                 *rpcm = pcm;
1306         return 0;
1307 }
1308
1309 /*
1310  *  Mixer section
1311  */
1312
1313 /*
1314  * ENS1371 mixer (including SPDIF interface)
1315  */
1316 #ifdef CHIP1371
1317 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1318 {
1319         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1320         uinfo->count = 1;
1321         return 0;
1322 }
1323
1324 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1325                                          snd_ctl_elem_value_t * ucontrol)
1326 {
1327         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1328         spin_lock_irq(&ensoniq->reg_lock);
1329         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1330         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1331         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1332         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1333         spin_unlock_irq(&ensoniq->reg_lock);
1334         return 0;
1335 }
1336
1337 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1338                                          snd_ctl_elem_value_t * ucontrol)
1339 {
1340         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1341         unsigned int val;
1342         int change;
1343
1344         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1345               ((u32)ucontrol->value.iec958.status[1] << 8) |
1346               ((u32)ucontrol->value.iec958.status[2] << 16) |
1347               ((u32)ucontrol->value.iec958.status[3] << 24);
1348         spin_lock_irq(&ensoniq->reg_lock);
1349         change = ensoniq->spdif_default != val;
1350         ensoniq->spdif_default = val;
1351         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1352                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1353         spin_unlock_irq(&ensoniq->reg_lock);
1354         return change;
1355 }
1356
1357 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1358                                          snd_ctl_elem_value_t * ucontrol)
1359 {
1360         ucontrol->value.iec958.status[0] = 0xff;
1361         ucontrol->value.iec958.status[1] = 0xff;
1362         ucontrol->value.iec958.status[2] = 0xff;
1363         ucontrol->value.iec958.status[3] = 0xff;
1364         return 0;
1365 }
1366
1367 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1368                                          snd_ctl_elem_value_t * ucontrol)
1369 {
1370         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1371         spin_lock_irq(&ensoniq->reg_lock);
1372         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1373         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1374         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1375         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1376         spin_unlock_irq(&ensoniq->reg_lock);
1377         return 0;
1378 }
1379
1380 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1381                                         snd_ctl_elem_value_t * ucontrol)
1382 {
1383         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1384         unsigned int val;
1385         int change;
1386
1387         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1388               ((u32)ucontrol->value.iec958.status[1] << 8) |
1389               ((u32)ucontrol->value.iec958.status[2] << 16) |
1390               ((u32)ucontrol->value.iec958.status[3] << 24);
1391         spin_lock_irq(&ensoniq->reg_lock);
1392         change = ensoniq->spdif_stream != val;
1393         ensoniq->spdif_stream = val;
1394         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1395                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1396         spin_unlock_irq(&ensoniq->reg_lock);
1397         return change;
1398 }
1399
1400 #define ES1371_SPDIF(xname) \
1401 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1402   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1403
1404 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1405 {
1406         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1407         uinfo->count = 1;
1408         uinfo->value.integer.min = 0;
1409         uinfo->value.integer.max = 1;
1410         return 0;
1411 }
1412
1413 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1414 {
1415         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1416
1417         spin_lock_irq(&ensoniq->reg_lock);
1418         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1419         spin_unlock_irq(&ensoniq->reg_lock);
1420         return 0;
1421 }
1422
1423 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1424 {
1425         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1426         unsigned int nval1, nval2;
1427         int change;
1428
1429         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1430         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1431         spin_lock_irq(&ensoniq->reg_lock);
1432         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1433         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1434         ensoniq->ctrl |= nval1;
1435         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1436         ensoniq->cssr |= nval2;
1437         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1438         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1439         spin_unlock_irq(&ensoniq->reg_lock);
1440         return change;
1441 }
1442
1443
1444 /* spdif controls */
1445 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1446         ES1371_SPDIF("IEC958 Playback Switch"),
1447         {
1448                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1449                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1450                 .info =         snd_ens1373_spdif_info,
1451                 .get =          snd_ens1373_spdif_default_get,
1452                 .put =          snd_ens1373_spdif_default_put,
1453         },
1454         {
1455                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1456                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1457                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1458                 .info =         snd_ens1373_spdif_info,
1459                 .get =          snd_ens1373_spdif_mask_get
1460         },
1461         {
1462                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1463                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1464                 .info =         snd_ens1373_spdif_info,
1465                 .get =          snd_ens1373_spdif_stream_get,
1466                 .put =          snd_ens1373_spdif_stream_put
1467         },
1468 };
1469
1470
1471 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1472 {
1473         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1474         uinfo->count = 1;
1475         uinfo->value.integer.min = 0;
1476         uinfo->value.integer.max = 1;
1477         return 0;
1478 }
1479
1480 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1481 {
1482         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1483         int val = 0;
1484
1485         spin_lock_irq(&ensoniq->reg_lock);
1486         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1487                 val = 1;
1488         ucontrol->value.integer.value[0] = val;
1489         spin_unlock_irq(&ensoniq->reg_lock);
1490         return 0;
1491 }
1492
1493 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1494 {
1495         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1496         unsigned int nval1;
1497         int change;
1498
1499         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1500         spin_lock_irq(&ensoniq->reg_lock);
1501         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1502         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1503         ensoniq->cssr |= nval1;
1504         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1505         spin_unlock_irq(&ensoniq->reg_lock);
1506         return change;
1507 }
1508
1509 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1510 {
1511         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1512         .name =         "AC97 2ch->4ch Copy Switch",
1513         .info =         snd_es1373_rear_info,
1514         .get =          snd_es1373_rear_get,
1515         .put =          snd_es1373_rear_put,
1516 };
1517
1518 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1519 {
1520         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1521         uinfo->count = 1;
1522         uinfo->value.integer.min = 0;
1523         uinfo->value.integer.max = 1;
1524         return 0;
1525 }
1526
1527 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1528 {
1529         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1530         int val = 0;
1531
1532         spin_lock_irq(&ensoniq->reg_lock);
1533         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1534                 val = 1;
1535         ucontrol->value.integer.value[0] = val;
1536         spin_unlock_irq(&ensoniq->reg_lock);
1537         return 0;
1538 }
1539
1540 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1541 {
1542         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1543         int changed;
1544         unsigned int ctrl;
1545
1546         spin_lock_irq(&ensoniq->reg_lock);
1547         ctrl = ensoniq->ctrl;
1548         if (ucontrol->value.integer.value[0])
1549                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1550         else
1551                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1552         changed = (ctrl != ensoniq->ctrl);
1553         if (changed)
1554                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1555         spin_unlock_irq(&ensoniq->reg_lock);
1556         return changed;
1557 }
1558
1559 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1560 {
1561         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1562         .name =         "Line In->Rear Out Switch",
1563         .info =         snd_es1373_line_info,
1564         .get =          snd_es1373_line_get,
1565         .put =          snd_es1373_line_put,
1566 };
1567
1568 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1569 {
1570         ensoniq_t *ensoniq = ac97->private_data;
1571         ensoniq->u.es1371.ac97 = NULL;
1572 }
1573
1574 static struct {
1575         unsigned short vid;             /* vendor ID */
1576         unsigned short did;             /* device ID */
1577         unsigned char rev;              /* revision */
1578 } es1371_spdif_present[] __devinitdata = {
1579         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1580         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1581         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1582         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1583         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1584         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1585 };
1586
1587 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1588 {
1589         snd_card_t *card = ensoniq->card;
1590         ac97_bus_t *pbus;
1591         ac97_template_t ac97;
1592         int err, idx;
1593         static ac97_bus_ops_t ops = {
1594                 .write = snd_es1371_codec_write,
1595                 .read = snd_es1371_codec_read,
1596         };
1597
1598         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1599                 return err;
1600
1601         memset(&ac97, 0, sizeof(ac97));
1602         ac97.private_data = ensoniq;
1603         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1604         ac97.scaps = AC97_SCAP_AUDIO;
1605         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1606                 return err;
1607         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1608                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1609                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1610                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1611                         snd_kcontrol_t *kctl;
1612                         int i, index = 0;
1613
1614                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1615                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1616
1617                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1618                                 index++;
1619
1620                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1621                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1622                                 if (! kctl)
1623                                         return -ENOMEM;
1624                                 kctl->id.index = index;
1625                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1626                                         return err;
1627                         }
1628                         break;
1629                 }
1630         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1631                 /* mirror rear to front speakers */
1632                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1633                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1634                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1635                 if (err < 0)
1636                         return err;
1637         }
1638         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1639             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1640             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1641             (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1642                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1643                  if (err < 0)
1644                          return err;
1645         }
1646
1647         return 0;
1648 }
1649
1650 #endif /* CHIP1371 */
1651
1652 /* generic control callbacks for ens1370 */
1653 #ifdef CHIP1370
1654 #define ENSONIQ_CONTROL(xname, mask) \
1655 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1656   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1657   .private_value = mask }
1658
1659 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1660 {
1661         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1662         uinfo->count = 1;
1663         uinfo->value.integer.min = 0;
1664         uinfo->value.integer.max = 1;
1665         return 0;
1666 }
1667
1668 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1669 {
1670         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1671         int mask = kcontrol->private_value;
1672
1673         spin_lock_irq(&ensoniq->reg_lock);
1674         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1675         spin_unlock_irq(&ensoniq->reg_lock);
1676         return 0;
1677 }
1678
1679 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1680 {
1681         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1682         int mask = kcontrol->private_value;
1683         unsigned int nval;
1684         int change;
1685
1686         nval = ucontrol->value.integer.value[0] ? mask : 0;
1687         spin_lock_irq(&ensoniq->reg_lock);
1688         change = (ensoniq->ctrl & mask) != nval;
1689         ensoniq->ctrl &= ~mask;
1690         ensoniq->ctrl |= nval;
1691         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1692         spin_unlock_irq(&ensoniq->reg_lock);
1693         return change;
1694 }
1695
1696 /*
1697  * ENS1370 mixer
1698  */
1699
1700 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1701 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1702 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1703 };
1704
1705 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1706
1707 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1708 {
1709         ensoniq_t *ensoniq = ak4531->private_data;
1710         ensoniq->u.es1370.ak4531 = NULL;
1711 }
1712
1713 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1714 {
1715         snd_card_t *card = ensoniq->card;
1716         ak4531_t ak4531;
1717         unsigned int idx;
1718         int err;
1719
1720         /* try reset AK4531 */
1721         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1722         inw(ES_REG(ensoniq, 1370_CODEC));
1723         udelay(100);
1724         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1725         inw(ES_REG(ensoniq, 1370_CODEC));
1726         udelay(100);
1727
1728         memset(&ak4531, 0, sizeof(ak4531));
1729         ak4531.write = snd_es1370_codec_write;
1730         ak4531.private_data = ensoniq;
1731         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1732         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1733                 return err;
1734         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1735                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1736                 if (err < 0)
1737                         return err;
1738         }
1739         return 0;
1740 }
1741
1742 #endif /* CHIP1370 */
1743
1744 #ifdef SUPPORT_JOYSTICK
1745 static int snd_ensoniq_joystick(ensoniq_t *ensoniq, long port)
1746 {
1747 #ifdef CHIP1371
1748         if (port == 1) { /* auto-detect */
1749                 for (port = 0x200; port <= 0x218; port += 8)
1750                         if (request_region(port, 8, "ens137x: gameport"))
1751                                 break;
1752                 if (port > 0x218) {
1753                         snd_printk("no gameport available\n");
1754                         return -EBUSY;
1755                 }
1756         } else
1757 #endif
1758         {
1759                 if (!request_region(port, 8, "ens137x: gameport")) {
1760                         snd_printk("gameport io port 0x%03x in use", ensoniq->gameport.io);
1761                         return -EBUSY;
1762                 }
1763         }
1764         ensoniq->gameport.io = port;
1765         ensoniq->ctrl |= ES_JYSTK_EN;
1766 #ifdef CHIP1371
1767         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1768         ensoniq->ctrl |= ES_1371_JOY_ASEL((ensoniq->gameport.io - 0x200) / 8);
1769 #endif
1770         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1771         gameport_register_port(&ensoniq->gameport);
1772         return 0;
1773 }
1774
1775 static void snd_ensoniq_joystick_free(ensoniq_t *ensoniq)
1776 {
1777         gameport_unregister_port(&ensoniq->gameport);
1778         ensoniq->ctrl &= ~ES_JYSTK_EN;
1779         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1780         release_region(ensoniq->gameport.io, 8);
1781 }
1782 #endif /* SUPPORT_JOYSTICK */
1783
1784 /*
1785
1786  */
1787
1788 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1789                                   snd_info_buffer_t * buffer)
1790 {
1791         ensoniq_t *ensoniq = entry->private_data;
1792
1793 #ifdef CHIP1370
1794         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1795 #else
1796         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1797 #endif
1798         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1799 #ifdef CHIP1370
1800         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1801         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1802 #else
1803         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1804 #endif
1805 }
1806
1807 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1808 {
1809         snd_info_entry_t *entry;
1810
1811         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1812                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1813 }
1814
1815 /*
1816
1817  */
1818
1819 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1820 {
1821 #ifdef SUPPORT_JOYSTICK
1822         if (ensoniq->ctrl & ES_JYSTK_EN)
1823                 snd_ensoniq_joystick_free(ensoniq);
1824 #endif
1825         if (ensoniq->irq < 0)
1826                 goto __hw_end;
1827 #ifdef CHIP1370
1828         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1829         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1830 #else
1831         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1832         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1833 #endif
1834         synchronize_irq(ensoniq->irq);
1835         pci_set_power_state(ensoniq->pci, 3);
1836       __hw_end:
1837 #ifdef CHIP1370
1838         if (ensoniq->dma_bug.area)
1839                 snd_dma_free_pages(&ensoniq->dma_bug);
1840 #endif
1841         if (ensoniq->irq >= 0)
1842                 free_irq(ensoniq->irq, (void *)ensoniq);
1843         pci_release_regions(ensoniq->pci);
1844         pci_disable_device(ensoniq->pci);
1845         kfree(ensoniq);
1846         return 0;
1847 }
1848
1849 static int snd_ensoniq_dev_free(snd_device_t *device)
1850 {
1851         ensoniq_t *ensoniq = device->device_data;
1852         return snd_ensoniq_free(ensoniq);
1853 }
1854
1855 #ifdef CHIP1371
1856 static struct {
1857         unsigned short svid;            /* subsystem vendor ID */
1858         unsigned short sdid;            /* subsystem device ID */
1859 } es1371_amplifier_hack[] = {
1860         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1861         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1862         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1863         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1864         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1865 };
1866 static struct {
1867         unsigned short vid;             /* vendor ID */
1868         unsigned short did;             /* device ID */
1869         unsigned char rev;              /* revision */
1870 } es1371_ac97_reset_hack[] = {
1871         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1872         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1873         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1874         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1875         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1876         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1877 };
1878 #endif
1879
1880 static int __devinit snd_ensoniq_create(snd_card_t * card,
1881                                      struct pci_dev *pci,
1882                                      ensoniq_t ** rensoniq)
1883 {
1884         ensoniq_t *ensoniq;
1885         unsigned short cmdw;
1886         unsigned char cmdb;
1887 #ifdef CHIP1371
1888         int idx;
1889 #endif
1890         int err;
1891         static snd_device_ops_t ops = {
1892                 .dev_free =     snd_ensoniq_dev_free,
1893         };
1894
1895         *rensoniq = NULL;
1896         if ((err = pci_enable_device(pci)) < 0)
1897                 return err;
1898         ensoniq = kcalloc(1, sizeof(*ensoniq), GFP_KERNEL);
1899         if (ensoniq == NULL) {
1900                 pci_disable_device(pci);
1901                 return -ENOMEM;
1902         }
1903         spin_lock_init(&ensoniq->reg_lock);
1904         init_MUTEX(&ensoniq->src_mutex);
1905         ensoniq->card = card;
1906         ensoniq->pci = pci;
1907         ensoniq->irq = -1;
1908         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
1909                 kfree(ensoniq);
1910                 pci_disable_device(pci);
1911                 return err;
1912         }
1913         ensoniq->port = pci_resource_start(pci, 0);
1914         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1915                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1916                 snd_ensoniq_free(ensoniq);
1917                 return -EBUSY;
1918         }
1919         ensoniq->irq = pci->irq;
1920 #ifdef CHIP1370
1921         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1922                                 16, &ensoniq->dma_bug) < 0) {
1923                 snd_printk("unable to allocate space for phantom area - dma_bug\n");
1924                 snd_ensoniq_free(ensoniq);
1925                 return -EBUSY;
1926         }
1927 #endif
1928         pci_set_master(pci);
1929         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1930         ensoniq->rev = cmdb;
1931         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1932         ensoniq->subsystem_vendor_id = cmdw;
1933         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1934         ensoniq->subsystem_device_id = cmdw;
1935 #ifdef CHIP1370
1936 #if 0
1937         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1938 #else   /* get microphone working */
1939         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1940 #endif
1941         ensoniq->sctrl = 0;
1942         /* initialize the chips */
1943         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1944         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1945         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1946         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1947         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1948 #else
1949         ensoniq->ctrl = 0;
1950         ensoniq->sctrl = 0;
1951         ensoniq->cssr = 0;
1952         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
1953                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
1954                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
1955                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
1956                         break;
1957                 }
1958         /* initialize the chips */
1959         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1960         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1961         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1962         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1963                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1964                     pci->device == es1371_ac97_reset_hack[idx].did &&
1965                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1966                         unsigned long tmo;
1967                         signed long tmo2;
1968
1969                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
1970                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1971                         /* need to delay around 20ms(bleech) to give
1972                         some CODECs enough time to wakeup */
1973                         tmo = jiffies + (HZ / 50) + 1;
1974                         while (1) {
1975                                 tmo2 = tmo - jiffies;
1976                                 if (tmo2 <= 0)
1977                                         break;
1978                                 set_current_state(TASK_UNINTERRUPTIBLE);
1979                                 schedule_timeout(tmo2);
1980                         }
1981                         break;
1982                 }
1983         /* AC'97 warm reset to start the bitclk */
1984         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1985         inl(ES_REG(ensoniq, CONTROL));
1986         udelay(20);
1987         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1988         /* Init the sample rate converter */
1989         snd_es1371_wait_src_ready(ensoniq);
1990         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1991         for (idx = 0; idx < 0x80; idx++)
1992                 snd_es1371_src_write(ensoniq, idx, 0);
1993         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1994         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1995         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1996         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1997         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1998         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1999         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2000         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2001         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2002         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2003         snd_es1371_adc_rate(ensoniq, 22050);
2004         snd_es1371_dac1_rate(ensoniq, 22050);
2005         snd_es1371_dac2_rate(ensoniq, 22050);
2006         /* WARNING:
2007          * enabling the sample rate converter without properly programming
2008          * its parameters causes the chip to lock up (the SRC busy bit will
2009          * be stuck high, and I've found no way to rectify this other than
2010          * power cycle) - Thomas Sailer
2011          */
2012         snd_es1371_wait_src_ready(ensoniq);
2013         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2014         /* try reset codec directly */
2015         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2016 #endif
2017         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2018         outb(0x00, ES_REG(ensoniq, UART_RES));
2019         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2020         synchronize_irq(ensoniq->irq);
2021
2022         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2023                 snd_ensoniq_free(ensoniq);
2024                 return err;
2025         }
2026
2027         snd_ensoniq_proc_init(ensoniq);
2028
2029         snd_card_set_dev(card, &pci->dev);
2030
2031         *rensoniq = ensoniq;
2032         return 0;
2033 }
2034
2035 /*
2036  *  MIDI section
2037  */
2038
2039 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2040 {
2041         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2042         unsigned char status, mask, byte;
2043
2044         if (rmidi == NULL)
2045                 return;
2046         /* do Rx at first */
2047         spin_lock(&ensoniq->reg_lock);
2048         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2049         while (mask) {
2050                 status = inb(ES_REG(ensoniq, UART_STATUS));
2051                 if ((status & mask) == 0)
2052                         break;
2053                 byte = inb(ES_REG(ensoniq, UART_DATA));
2054                 spin_unlock(&ensoniq->reg_lock);
2055                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2056                 spin_lock(&ensoniq->reg_lock);
2057         }
2058         spin_unlock(&ensoniq->reg_lock);
2059
2060         /* do Tx at second */
2061         spin_lock(&ensoniq->reg_lock);
2062         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2063         while (mask) {
2064                 status = inb(ES_REG(ensoniq, UART_STATUS));
2065                 if ((status & mask) == 0)
2066                         break;
2067                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2068                         ensoniq->uartc &= ~ES_TXINTENM;
2069                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2070                         mask &= ~ES_TXRDY;
2071                 } else {
2072                         outb(byte, ES_REG(ensoniq, UART_DATA));
2073                 }
2074         }
2075         spin_unlock(&ensoniq->reg_lock);
2076 }
2077
2078 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2079 {
2080         ensoniq_t *ensoniq = substream->rmidi->private_data;
2081
2082         spin_lock_irq(&ensoniq->reg_lock);
2083         ensoniq->uartm |= ES_MODE_INPUT;
2084         ensoniq->midi_input = substream;
2085         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2086                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2087                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2088                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2089         }
2090         spin_unlock_irq(&ensoniq->reg_lock);
2091         return 0;
2092 }
2093
2094 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2095 {
2096         ensoniq_t *ensoniq = substream->rmidi->private_data;
2097
2098         spin_lock_irq(&ensoniq->reg_lock);
2099         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2100                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2101                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2102         } else {
2103                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2104         }
2105         ensoniq->midi_input = NULL;
2106         ensoniq->uartm &= ~ES_MODE_INPUT;
2107         spin_unlock_irq(&ensoniq->reg_lock);
2108         return 0;
2109 }
2110
2111 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2112 {
2113         ensoniq_t *ensoniq = substream->rmidi->private_data;
2114
2115         spin_lock_irq(&ensoniq->reg_lock);
2116         ensoniq->uartm |= ES_MODE_OUTPUT;
2117         ensoniq->midi_output = substream;
2118         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2119                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2120                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2121                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2122         }
2123         spin_unlock_irq(&ensoniq->reg_lock);
2124         return 0;
2125 }
2126
2127 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2128 {
2129         ensoniq_t *ensoniq = substream->rmidi->private_data;
2130
2131         spin_lock_irq(&ensoniq->reg_lock);
2132         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2133                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2134                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2135         } else {
2136                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2137         }
2138         ensoniq->midi_output = NULL;
2139         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2140         spin_unlock_irq(&ensoniq->reg_lock);
2141         return 0;
2142 }
2143
2144 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2145 {
2146         unsigned long flags;
2147         ensoniq_t *ensoniq = substream->rmidi->private_data;
2148         int idx;
2149
2150         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2151         if (up) {
2152                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2153                         /* empty input FIFO */
2154                         for (idx = 0; idx < 32; idx++)
2155                                 inb(ES_REG(ensoniq, UART_DATA));
2156                         ensoniq->uartc |= ES_RXINTEN;
2157                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2158                 }
2159         } else {
2160                 if (ensoniq->uartc & ES_RXINTEN) {
2161                         ensoniq->uartc &= ~ES_RXINTEN;
2162                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2163                 }
2164         }
2165         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2166 }
2167
2168 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2169 {
2170         unsigned long flags;
2171         ensoniq_t *ensoniq = substream->rmidi->private_data;
2172         unsigned char byte;
2173
2174         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2175         if (up) {
2176                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2177                         ensoniq->uartc |= ES_TXINTENO(1);
2178                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2179                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2180                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2181                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2182                                         ensoniq->uartc &= ~ES_TXINTENM;
2183                                 } else {
2184                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2185                                 }
2186                         }
2187                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2188                 }
2189         } else {
2190                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2191                         ensoniq->uartc &= ~ES_TXINTENM;
2192                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2193                 }
2194         }
2195         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2196 }
2197
2198 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2199 {
2200         .open =         snd_ensoniq_midi_output_open,
2201         .close =        snd_ensoniq_midi_output_close,
2202         .trigger =      snd_ensoniq_midi_output_trigger,
2203 };
2204
2205 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2206 {
2207         .open =         snd_ensoniq_midi_input_open,
2208         .close =        snd_ensoniq_midi_input_close,
2209         .trigger =      snd_ensoniq_midi_input_trigger,
2210 };
2211
2212 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2213 {
2214         snd_rawmidi_t *rmidi;
2215         int err;
2216
2217         if (rrawmidi)
2218                 *rrawmidi = NULL;
2219         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2220                 return err;
2221 #ifdef CHIP1370
2222         strcpy(rmidi->name, "ES1370");
2223 #else
2224         strcpy(rmidi->name, "ES1371");
2225 #endif
2226         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2227         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2228         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2229         rmidi->private_data = ensoniq;
2230         ensoniq->rmidi = rmidi;
2231         if (rrawmidi)
2232                 *rrawmidi = rmidi;
2233         return 0;
2234 }
2235
2236 /*
2237  *  Interrupt handler
2238  */
2239
2240 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2241 {
2242         ensoniq_t *ensoniq = dev_id;
2243         unsigned int status, sctrl;
2244
2245         if (ensoniq == NULL)
2246                 return IRQ_NONE;
2247
2248         status = inl(ES_REG(ensoniq, STATUS));
2249         if (!(status & ES_INTR))
2250                 return IRQ_NONE;
2251
2252         spin_lock(&ensoniq->reg_lock);
2253         sctrl = ensoniq->sctrl;
2254         if (status & ES_DAC1)
2255                 sctrl &= ~ES_P1_INT_EN;
2256         if (status & ES_DAC2)
2257                 sctrl &= ~ES_P2_INT_EN;
2258         if (status & ES_ADC)
2259                 sctrl &= ~ES_R1_INT_EN;
2260         outl(sctrl, ES_REG(ensoniq, SERIAL));
2261         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2262         spin_unlock(&ensoniq->reg_lock);
2263
2264         if (status & ES_UART)
2265                 snd_ensoniq_midi_interrupt(ensoniq);
2266         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2267                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2268         if ((status & ES_ADC) && ensoniq->capture_substream)
2269                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2270         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2271                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2272         return IRQ_HANDLED;
2273 }
2274
2275 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2276                                         const struct pci_device_id *pci_id)
2277 {
2278         static int dev;
2279         snd_card_t *card;
2280         ensoniq_t *ensoniq;
2281         int err, pcm_devs[2];
2282
2283         if (dev >= SNDRV_CARDS)
2284                 return -ENODEV;
2285         if (!enable[dev]) {
2286                 dev++;
2287                 return -ENOENT;
2288         }
2289
2290         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2291         if (card == NULL)
2292                 return -ENOMEM;
2293
2294         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2295                 snd_card_free(card);
2296                 return err;
2297         }
2298
2299         pcm_devs[0] = 0; pcm_devs[1] = 1;
2300 #ifdef CHIP1370
2301         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2302                 snd_card_free(card);
2303                 return err;
2304         }
2305 #endif
2306 #ifdef CHIP1371
2307         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2308                 snd_card_free(card);
2309                 return err;
2310         }
2311 #endif
2312         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2313                 snd_card_free(card);
2314                 return err;
2315         }
2316         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2317                 snd_card_free(card);
2318                 return err;
2319         }
2320         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2321                 snd_card_free(card);
2322                 return err;
2323         }
2324 #ifdef SUPPORT_JOYSTICK
2325 #ifdef CHIP1371
2326         switch (joystick_port[dev]) {
2327         case 1: /* auto-detect */
2328         case 0x200:
2329         case 0x208:
2330         case 0x210:
2331         case 0x218:
2332                 snd_ensoniq_joystick(ensoniq, joystick_port[dev]);
2333                 break;
2334         }
2335 #else
2336         if (joystick[dev])
2337                 snd_ensoniq_joystick(ensoniq, 0x200);
2338 #endif
2339 #endif /* SUPPORT_JOYSTICK */
2340         strcpy(card->driver, DRIVER_NAME);
2341
2342         strcpy(card->shortname, "Ensoniq AudioPCI");
2343         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2344                 card->shortname,
2345                 card->driver,
2346                 ensoniq->port,
2347                 ensoniq->irq);
2348
2349         if ((err = snd_card_register(card)) < 0) {
2350                 snd_card_free(card);
2351                 return err;
2352         }
2353
2354         pci_set_drvdata(pci, card);
2355         dev++;
2356         return 0;
2357 }
2358
2359 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2360 {
2361         snd_card_free(pci_get_drvdata(pci));
2362         pci_set_drvdata(pci, NULL);
2363 }
2364
2365 static struct pci_driver driver = {
2366         .name = DRIVER_NAME,
2367         .id_table = snd_audiopci_ids,
2368         .probe = snd_audiopci_probe,
2369         .remove = __devexit_p(snd_audiopci_remove),
2370 };
2371
2372 static int __init alsa_card_ens137x_init(void)
2373 {
2374         return pci_module_init(&driver);
2375 }
2376
2377 static void __exit alsa_card_ens137x_exit(void)
2378 {
2379         pci_unregister_driver(&driver);
2380 }
2381
2382 module_init(alsa_card_ens137x_init)
2383 module_exit(alsa_card_ens137x_exit)