2 * ALSA driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/gameport.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/mpu401.h>
43 #include <sound/initval.h>
44 /* for 440MX workaround */
45 #include <asm/pgtable.h>
46 #include <asm/cacheflush.h>
48 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
49 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
50 MODULE_LICENSE("GPL");
51 MODULE_CLASSES("{sound}");
52 MODULE_DEVICES("{{Intel,82801AA-ICH},"
53 "{Intel,82901AB-ICH0},"
54 "{Intel,82801BA-ICH2},"
55 "{Intel,82801CA-ICH3},"
56 "{Intel,82801DB-ICH4},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
68 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
69 #define SUPPORT_JOYSTICK 1
71 #define SUPPORT_MIDI 1
73 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
74 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
75 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
76 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
77 static int ac97_quirk[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = AC97_TUNE_DEFAULT};
78 #ifdef SUPPORT_JOYSTICK
79 static int joystick[SNDRV_CARDS];
82 static int mpu_port[SNDRV_CARDS]; /* disabled */
85 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
86 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
87 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
88 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
89 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
90 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
91 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
92 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
93 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
94 MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
95 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
96 MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
97 MODULE_PARM(ac97_quirk, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
98 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
99 MODULE_PARM_SYNTAX(ac97_quirk, SNDRV_ENABLED ",allows:{{-1,4}},dialog:list,default:-1");
100 #ifdef SUPPORT_JOYSTICK
101 MODULE_PARM(joystick, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
102 MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
103 MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
106 MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
107 MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
108 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
115 #ifndef PCI_DEVICE_ID_INTEL_82801
116 #define PCI_DEVICE_ID_INTEL_82801 0x2415
118 #ifndef PCI_DEVICE_ID_INTEL_82901
119 #define PCI_DEVICE_ID_INTEL_82901 0x2425
121 #ifndef PCI_DEVICE_ID_INTEL_82801BA
122 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
124 #ifndef PCI_DEVICE_ID_INTEL_440MX
125 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
127 #ifndef PCI_DEVICE_ID_INTEL_ICH3
128 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
130 #ifndef PCI_DEVICE_ID_INTEL_ICH4
131 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
133 #ifndef PCI_DEVICE_ID_INTEL_ICH5
134 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
136 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
137 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
139 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
140 #define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e
142 #ifndef PCI_DEVICE_ID_SI_7012
143 #define PCI_DEVICE_ID_SI_7012 0x7012
145 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
146 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
148 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
149 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
151 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
152 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
154 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
155 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
158 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
160 #define ICHREG(x) ICH_REG_##x
162 #define DEFINE_REGSET(name,base) \
164 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
165 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
166 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
167 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
168 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
169 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
170 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
173 /* busmaster blocks */
174 DEFINE_REGSET(OFF, 0); /* offset */
175 DEFINE_REGSET(PI, 0x00); /* PCM in */
176 DEFINE_REGSET(PO, 0x10); /* PCM out */
177 DEFINE_REGSET(MC, 0x20); /* Mic in */
179 /* ICH4 busmaster blocks */
180 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
181 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
182 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
184 /* values for each busmaster block */
187 #define ICH_REG_LVI_MASK 0x1f
190 #define ICH_FIFOE 0x10 /* FIFO error */
191 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
192 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
193 #define ICH_CELV 0x02 /* current equals last valid */
194 #define ICH_DCH 0x01 /* DMA controller halted */
197 #define ICH_REG_PIV_MASK 0x1f /* mask */
200 #define ICH_IOCE 0x10 /* interrupt on completion enable */
201 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
202 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
203 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
204 #define ICH_STARTBM 0x01 /* start busmaster operation */
208 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
209 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
210 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
211 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
212 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
213 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
214 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
215 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
216 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
217 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
218 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
219 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
220 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
221 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
222 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
223 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
224 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
225 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
226 #define ICH_ACLINK 0x00000008 /* AClink shut off */
227 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
228 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
229 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
230 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
231 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
232 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
233 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
234 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
235 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
236 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
237 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
238 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
239 #define ICH_MD3 0x00020000 /* modem power down semaphore */
240 #define ICH_AD3 0x00010000 /* audio power down semaphore */
241 #define ICH_RCS 0x00008000 /* read completion status */
242 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
243 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
244 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
245 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
246 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
247 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
248 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
249 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
250 #define ICH_POINT 0x00000040 /* playback interrupt */
251 #define ICH_PIINT 0x00000020 /* capture interrupt */
252 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
253 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
254 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
255 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
256 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
257 #define ICH_CAS 0x01 /* codec access semaphore */
258 #define ICH_REG_SDM 0x80
259 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
260 #define ICH_DI2L_SHIFT 6
261 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
262 #define ICH_DI1L_SHIFT 4
263 #define ICH_SE 0x00000008 /* steer enable */
264 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
266 #define ICH_MAX_FRAGS 32 /* max hw frags */
270 * registers for Ali5455
273 /* ALi 5455 busmaster blocks */
274 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
275 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
276 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
277 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
278 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
279 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
280 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
281 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
282 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
283 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
284 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
287 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
288 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
289 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
290 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
291 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
292 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
293 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
294 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
295 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
296 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
297 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
298 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
299 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
300 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
301 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
302 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
303 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
304 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
305 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
306 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
307 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
310 #define ALI_CAS_SEM_BUSY 0x80000000
311 #define ALI_CPR_ADDR_SECONDARY 0x100
312 #define ALI_CPR_ADDR_READ 0x80
313 #define ALI_CSPSR_CODEC_READY 0x08
314 #define ALI_CSPSR_READ_OK 0x02
315 #define ALI_CSPSR_WRITE_OK 0x01
317 /* interrupts for the whole chip by interrupt status register finish */
319 #define ALI_INT_MICIN2 (1<<26)
320 #define ALI_INT_PCMIN2 (1<<25)
321 #define ALI_INT_I2SIN (1<<24)
322 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
323 #define ALI_INT_SPDIFIN (1<<22)
324 #define ALI_INT_LFEOUT (1<<21)
325 #define ALI_INT_CENTEROUT (1<<20)
326 #define ALI_INT_CODECSPDIFOUT (1<<19)
327 #define ALI_INT_MICIN (1<<18)
328 #define ALI_INT_PCMOUT (1<<17)
329 #define ALI_INT_PCMIN (1<<16)
330 #define ALI_INT_CPRAIS (1<<7) /* command port available */
331 #define ALI_INT_SPRAIS (1<<5) /* status port available */
332 #define ALI_INT_GPIO (1<<1)
333 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
335 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
336 #define ICH_ALI_SC_AC97_DBL (1<<30)
337 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
338 #define ICH_ALI_SC_IN_BITS (3<<18)
339 #define ICH_ALI_SC_OUT_BITS (3<<16)
340 #define ICH_ALI_SC_6CH_CFG (3<<14)
341 #define ICH_ALI_SC_PCM_4 (1<<8)
342 #define ICH_ALI_SC_PCM_6 (2<<8)
343 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
345 #define ICH_ALI_SS_SEC_ID (3<<5)
346 #define ICH_ALI_SS_PRI_ID (3<<3)
348 #define ICH_ALI_IF_AC97SP (1<<21)
349 #define ICH_ALI_IF_MC (1<<20)
350 #define ICH_ALI_IF_PI (1<<19)
351 #define ICH_ALI_IF_MC2 (1<<18)
352 #define ICH_ALI_IF_PI2 (1<<17)
353 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
354 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
355 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
356 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
357 #define ICH_ALI_IF_PO_SPDF (1<<3)
358 #define ICH_ALI_IF_PO (1<<1)
364 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
365 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
366 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
368 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
371 unsigned int ichd; /* ich device number */
372 unsigned long reg_offset; /* offset to bmaddr */
373 u32 *bdbar; /* CPU address (32bit) */
374 unsigned int bdbar_addr; /* PCI bus address (32bit) */
375 snd_pcm_substream_t *substream;
376 unsigned int physbuf; /* physical address (32bit) */
378 unsigned int fragsize;
379 unsigned int fragsize1;
380 unsigned int position;
387 unsigned int ack_bit;
388 unsigned int roff_sr;
389 unsigned int roff_picb;
390 unsigned int int_sta_mask; /* interrupt status mask */
391 unsigned int ali_slot; /* ALI DMA slot */
392 struct ac97_pcm *pcm;
396 typedef struct _snd_intel8x0 intel8x0_t;
397 #define chip_t intel8x0_t
399 struct _snd_intel8x0 {
400 unsigned int device_type;
408 unsigned long remap_addr;
409 struct resource *res;
410 unsigned int bm_mmio;
411 unsigned long bmaddr;
412 unsigned long remap_bmaddr;
413 struct resource *res_bm;
415 struct snd_dma_device dma_dev;
429 int fix_nocache: 1; /* workaround for 440MX */
431 ac97_bus_t *ac97_bus;
433 unsigned int ac97_sdin[3];
435 snd_rawmidi_t *rmidi;
438 spinlock_t ac97_lock;
441 struct snd_dma_buffer bdbars;
442 u32 int_sta_reg; /* interrupt status register */
443 u32 int_sta_mask; /* interrupt status mask */
444 unsigned int pcm_pos_shift;
451 static struct pci_device_id snd_intel8x0_ids[] = {
452 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
453 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
454 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
455 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
456 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
457 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
458 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
459 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
460 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
461 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
462 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
463 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
464 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
465 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
466 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
467 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
468 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
472 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
475 * Lowlevel I/O - busmaster
478 static u8 igetbyte(intel8x0_t *chip, u32 offset)
481 return readb(chip->remap_bmaddr + offset);
483 return inb(chip->bmaddr + offset);
486 static u16 igetword(intel8x0_t *chip, u32 offset)
489 return readw(chip->remap_bmaddr + offset);
491 return inw(chip->bmaddr + offset);
494 static u32 igetdword(intel8x0_t *chip, u32 offset)
497 return readl(chip->remap_bmaddr + offset);
499 return inl(chip->bmaddr + offset);
502 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
505 writeb(val, chip->remap_bmaddr + offset);
507 outb(val, chip->bmaddr + offset);
510 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
513 writew(val, chip->remap_bmaddr + offset);
515 outw(val, chip->bmaddr + offset);
518 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
521 writel(val, chip->remap_bmaddr + offset);
523 outl(val, chip->bmaddr + offset);
527 * Lowlevel I/O - AC'97 registers
530 static u16 iagetword(intel8x0_t *chip, u32 offset)
533 return readw(chip->remap_addr + offset);
535 return inw(chip->addr + offset);
538 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
541 writew(val, chip->remap_addr + offset);
543 outw(val, chip->addr + offset);
551 * access to AC97 codec via normal i/o (for ICH and SIS7012)
554 /* return the GLOB_STA bit for the corresponding codec */
555 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
557 static unsigned int codec_bit[3] = {
558 ICH_PCR, ICH_SCR, ICH_TCR
560 snd_assert(codec < 3, return ICH_PCR);
561 if (chip->device_type == DEVICE_INTEL_ICH4)
562 codec = chip->ac97_sdin[codec];
563 return codec_bit[codec];
566 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
572 if (chip->in_sdin_init) {
573 /* we don't know the ready bit assignment at the moment */
574 /* so we check any */
575 codec = ICH_PCR | ICH_SCR | ICH_TCR;
577 codec = get_ich_codec_bit(chip, codec);
581 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
584 /* Anyone holding a semaphore for 1 msec should be shot... */
587 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
592 /* access to some forbidden (non existant) ac97 registers will not
593 * reset the semaphore. So even if you don't get the semaphore, still
594 * continue the access. We don't need the semaphore anyway. */
595 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
596 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
597 iagetword(chip, 0); /* clear semaphore flag */
598 /* I don't care about the semaphore */
602 static void snd_intel8x0_codec_write(ac97_t *ac97,
606 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
608 spin_lock(&chip->ac97_lock);
609 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
610 if (! chip->in_ac97_init)
611 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
613 iaputword(chip, reg + ac97->num * 0x80, val);
614 spin_unlock(&chip->ac97_lock);
617 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
620 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
624 spin_lock(&chip->ac97_lock);
625 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
626 if (! chip->in_ac97_init)
627 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
630 res = iagetword(chip, reg + ac97->num * 0x80);
631 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
632 /* reset RCS and preserve other R/WC bits */
633 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
634 if (! chip->in_ac97_init)
635 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
639 spin_unlock(&chip->ac97_lock);
644 * access to AC97 for Ali5455
646 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
649 for (count = 0; count < 0x7f; count++) {
650 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
654 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
658 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
661 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
664 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
665 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
668 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
670 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
671 unsigned short data = 0xffff;
673 spin_lock(&chip->ac97_lock);
674 if (snd_intel8x0_ali_codec_semaphore(chip))
676 reg |= ALI_CPR_ADDR_READ;
678 reg |= ALI_CPR_ADDR_SECONDARY;
679 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
680 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
682 data = igetword(chip, ICHREG(ALI_SPR));
684 spin_unlock(&chip->ac97_lock);
688 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
690 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
692 spin_lock(&chip->ac97_lock);
693 if (snd_intel8x0_ali_codec_semaphore(chip)) {
694 spin_unlock(&chip->ac97_lock);
697 iputword(chip, ICHREG(ALI_CPR), val);
699 reg |= ALI_CPR_ADDR_SECONDARY;
700 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
701 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
702 spin_unlock(&chip->ac97_lock);
709 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
712 u32 *bdbar = ichdev->bdbar;
713 unsigned long port = ichdev->reg_offset;
715 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
716 if (ichdev->size == ichdev->fragsize) {
717 ichdev->ack_reload = ichdev->ack = 2;
718 ichdev->fragsize1 = ichdev->fragsize >> 1;
719 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
720 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
721 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
722 ichdev->fragsize1 >> chip->pcm_pos_shift);
723 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
724 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
725 ichdev->fragsize1 >> chip->pcm_pos_shift);
729 ichdev->ack_reload = ichdev->ack = 1;
730 ichdev->fragsize1 = ichdev->fragsize;
731 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
732 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
733 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
734 ichdev->fragsize >> chip->pcm_pos_shift);
735 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
737 ichdev->frags = ichdev->size / ichdev->fragsize;
739 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
741 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
742 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
743 ichdev->position = 0;
745 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
746 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
748 /* clear interrupts */
749 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
754 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
755 * which aborts PCI busmaster for audio transfer. A workaround is to set
756 * the pages as non-cached. For details, see the errata in
757 * http://www.intel.com/design/chipsets/specupdt/245051.htm
759 static void fill_nocache(void *buf, int size, int nocache)
761 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
762 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
766 #define fill_nocache(buf,size,nocache)
773 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
775 unsigned long port = ichdev->reg_offset;
779 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
780 if (civ == ichdev->civ) {
781 // snd_printd("civ same %d\n", civ);
784 ichdev->civ &= ICH_REG_LVI_MASK;
786 step = civ - ichdev->civ;
788 step += ICH_REG_LVI_MASK + 1;
790 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
794 ichdev->position += step * ichdev->fragsize1;
795 ichdev->position %= ichdev->size;
797 ichdev->lvi &= ICH_REG_LVI_MASK;
798 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
799 for (i = 0; i < step; i++) {
801 ichdev->lvi_frag %= ichdev->frags;
802 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
803 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
804 if (--ichdev->ack == 0) {
805 ichdev->ack = ichdev->ack_reload;
809 if (ack && ichdev->substream) {
810 spin_unlock(&chip->reg_lock);
811 snd_pcm_period_elapsed(ichdev->substream);
812 spin_lock(&chip->reg_lock);
814 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
817 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
819 intel8x0_t *chip = snd_magic_cast(intel8x0_t, dev_id, return IRQ_NONE);
824 spin_lock(&chip->reg_lock);
825 status = igetdword(chip, chip->int_sta_reg);
826 if ((status & chip->int_sta_mask) == 0) {
829 iputdword(chip, chip->int_sta_reg, status);
830 /* some Nforce[2] boards have problems when
831 IRQ_NONE is returned here.
833 if (chip->device_type != DEVICE_NFORCE)
836 spin_unlock(&chip->reg_lock);
837 return IRQ_RETVAL(status);
840 for (i = 0; i < chip->bdbars_count; i++) {
841 ichdev = &chip->ichd[i];
842 if (status & ichdev->int_sta_mask)
843 snd_intel8x0_update(chip, ichdev);
847 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
848 spin_unlock(&chip->reg_lock);
857 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
859 intel8x0_t *chip = snd_pcm_substream_chip(substream);
860 ichdev_t *ichdev = get_ichdev(substream);
861 unsigned char val = 0;
862 unsigned long port = ichdev->reg_offset;
865 case SNDRV_PCM_TRIGGER_START:
866 case SNDRV_PCM_TRIGGER_RESUME:
867 val = ICH_IOCE | ICH_STARTBM;
869 case SNDRV_PCM_TRIGGER_STOP:
870 case SNDRV_PCM_TRIGGER_SUSPEND:
873 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
876 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
877 val = ICH_IOCE | ICH_STARTBM;
882 iputbyte(chip, port + ICH_REG_OFF_CR, val);
883 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
884 /* wait until DMA stopped */
885 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
886 /* reset whole DMA things */
887 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
892 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
894 intel8x0_t *chip = snd_pcm_substream_chip(substream);
895 ichdev_t *ichdev = get_ichdev(substream);
896 unsigned long port = ichdev->reg_offset;
897 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
898 unsigned int val, fifo;
900 val = igetdword(chip, ICHREG(ALI_DMACR));
902 case SNDRV_PCM_TRIGGER_START:
903 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
904 case SNDRV_PCM_TRIGGER_RESUME:
905 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
906 /* clear FIFO for synchronization of channels */
907 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
908 fifo &= ~(0xff << (ichdev->ali_slot % 4));
909 fifo |= 0x83 << (ichdev->ali_slot % 4);
910 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
912 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
913 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
914 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
916 case SNDRV_PCM_TRIGGER_STOP:
917 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
918 case SNDRV_PCM_TRIGGER_SUSPEND:
919 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
920 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
921 while (igetbyte(chip, port + ICH_REG_OFF_CR))
923 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
925 /* reset whole DMA things */
926 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
927 /* clear interrupts */
928 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
929 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
930 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
938 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
939 snd_pcm_hw_params_t * hw_params)
941 intel8x0_t *chip = snd_pcm_substream_chip(substream);
942 ichdev_t *ichdev = get_ichdev(substream);
943 snd_pcm_runtime_t *runtime = substream->runtime;
944 size_t size = params_buffer_bytes(hw_params);
947 if (chip->fix_nocache && runtime->dma_area && runtime->dma_bytes < size)
948 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
949 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
952 if (chip->fix_nocache && err > 0)
953 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
954 if (ichdev->pcm_open_flag) {
955 snd_ac97_pcm_close(ichdev->pcm);
956 ichdev->pcm_open_flag = 0;
958 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
959 params_channels(hw_params),
960 ichdev->pcm->r[0].slots);
962 ichdev->pcm_open_flag = 1;
963 /* FIXME: hack to enable spdif support */
964 if (ichdev->ichd == ICHD_PCMOUT && chip->device_type == DEVICE_SIS)
965 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
970 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
972 intel8x0_t *chip = snd_pcm_substream_chip(substream);
973 ichdev_t *ichdev = get_ichdev(substream);
975 if (ichdev->pcm_open_flag) {
976 snd_ac97_pcm_close(ichdev->pcm);
977 ichdev->pcm_open_flag = 0;
979 if (chip->fix_nocache && substream->runtime->dma_area)
980 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
981 return snd_pcm_lib_free_pages(substream);
984 static void snd_intel8x0_setup_multi_channels(intel8x0_t *chip, int channels)
987 switch (chip->device_type) {
989 cnt = igetdword(chip, ICHREG(ALI_SCR));
990 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
991 if (chip->multi4 && channels == 4)
992 cnt |= ICH_ALI_SC_PCM_4;
993 else if (chip->multi6 && channels == 6)
994 cnt |= ICH_ALI_SC_PCM_6;
995 iputdword(chip, ICHREG(ALI_SCR), cnt);
998 cnt = igetdword(chip, ICHREG(GLOB_CNT));
999 cnt &= ~ICH_SIS_PCM_246_MASK;
1000 if (chip->multi4 && channels == 4)
1001 cnt |= ICH_SIS_PCM_4;
1002 else if (chip->multi6 && channels == 6)
1003 cnt |= ICH_SIS_PCM_6;
1004 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1007 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1008 cnt &= ~ICH_PCM_246_MASK;
1009 if (chip->multi4 && channels == 4)
1011 else if (chip->multi6 && channels == 6)
1013 if (chip->device_type == DEVICE_NFORCE) {
1014 /* reset to 2ch once to keep the 6 channel data in alignment,
1015 * to start from Front Left always
1017 iputdword(chip, ICHREG(GLOB_CNT), (cnt & 0xcfffff));
1018 mdelay(50); /* grrr... */
1020 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1025 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1027 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1028 snd_pcm_runtime_t *runtime = substream->runtime;
1029 ichdev_t *ichdev = get_ichdev(substream);
1031 ichdev->physbuf = runtime->dma_addr;
1032 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1033 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1034 if (ichdev->ichd == ICHD_PCMOUT) {
1035 spin_lock(&chip->reg_lock);
1036 snd_intel8x0_setup_multi_channels(chip, runtime->channels);
1037 spin_unlock(&chip->reg_lock);
1039 snd_intel8x0_setup_periods(chip, ichdev);
1043 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1045 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1046 ichdev_t *ichdev = get_ichdev(substream);
1047 unsigned long flags;
1050 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
1052 ptr = ichdev->fragsize1 - ptr1;
1055 spin_lock_irqsave(&chip->reg_lock, flags);
1056 ptr += ichdev->position;
1057 spin_unlock_irqrestore(&chip->reg_lock, flags);
1058 if (ptr >= ichdev->size)
1060 return bytes_to_frames(substream->runtime, ptr);
1063 static snd_pcm_hardware_t snd_intel8x0_stream =
1065 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1066 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1067 SNDRV_PCM_INFO_MMAP_VALID |
1068 SNDRV_PCM_INFO_PAUSE |
1069 SNDRV_PCM_INFO_RESUME),
1070 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1071 .rates = SNDRV_PCM_RATE_48000,
1076 .buffer_bytes_max = 128 * 1024,
1077 .period_bytes_min = 32,
1078 .period_bytes_max = 128 * 1024,
1080 .periods_max = 1024,
1084 static unsigned int channels4[] = {
1088 #define CHANNELS4 sizeof(channels4) / sizeof(channels4[0])
1090 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1096 static unsigned int channels6[] = {
1100 #define CHANNELS6 sizeof(channels6) / sizeof(channels6[0])
1102 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1108 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1110 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1111 snd_pcm_runtime_t *runtime = substream->runtime;
1114 ichdev->substream = substream;
1115 runtime->hw = snd_intel8x0_stream;
1116 runtime->hw.rates = ichdev->pcm->rates;
1117 snd_pcm_limit_hw_rates(runtime);
1118 if (chip->device_type == DEVICE_SIS) {
1119 runtime->hw.buffer_bytes_max = 64*1024;
1120 runtime->hw.period_bytes_max = 64*1024;
1122 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1124 runtime->private_data = ichdev;
1128 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1130 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1131 snd_pcm_runtime_t *runtime = substream->runtime;
1134 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1139 runtime->hw.channels_max = 6;
1140 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1141 } else if (chip->multi4) {
1142 runtime->hw.channels_max = 4;
1143 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1148 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1150 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1152 chip->ichd[ICHD_PCMOUT].substream = NULL;
1156 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1158 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1160 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1163 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1165 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1167 chip->ichd[ICHD_PCMIN].substream = NULL;
1171 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1173 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1175 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1178 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1180 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1182 chip->ichd[ICHD_MIC].substream = NULL;
1186 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1188 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1190 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1193 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1195 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1197 chip->ichd[ICHD_MIC2].substream = NULL;
1201 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1203 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1205 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1208 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1210 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1212 chip->ichd[ICHD_PCM2IN].substream = NULL;
1216 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1218 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1219 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1221 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1224 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1226 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1227 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1229 chip->ichd[idx].substream = NULL;
1233 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1235 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1236 unsigned long flags;
1239 spin_lock_irqsave(&chip->reg_lock, flags);
1240 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1241 val |= ICH_ALI_IF_AC97SP;
1242 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1243 spin_unlock_irqrestore(&chip->reg_lock, flags);
1245 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1248 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1250 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1251 unsigned long flags;
1254 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1255 spin_lock_irqsave(&chip->reg_lock, flags);
1256 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1257 val &= ~ICH_ALI_IF_AC97SP;
1258 spin_unlock_irqrestore(&chip->reg_lock, flags);
1263 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1265 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1267 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1270 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1272 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1274 chip->ichd[ALID_SPDIFIN].substream = NULL;
1279 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1281 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1283 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1286 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1288 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1290 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1295 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1296 .open = snd_intel8x0_playback_open,
1297 .close = snd_intel8x0_playback_close,
1298 .ioctl = snd_pcm_lib_ioctl,
1299 .hw_params = snd_intel8x0_hw_params,
1300 .hw_free = snd_intel8x0_hw_free,
1301 .prepare = snd_intel8x0_pcm_prepare,
1302 .trigger = snd_intel8x0_pcm_trigger,
1303 .pointer = snd_intel8x0_pcm_pointer,
1306 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1307 .open = snd_intel8x0_capture_open,
1308 .close = snd_intel8x0_capture_close,
1309 .ioctl = snd_pcm_lib_ioctl,
1310 .hw_params = snd_intel8x0_hw_params,
1311 .hw_free = snd_intel8x0_hw_free,
1312 .prepare = snd_intel8x0_pcm_prepare,
1313 .trigger = snd_intel8x0_pcm_trigger,
1314 .pointer = snd_intel8x0_pcm_pointer,
1317 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1318 .open = snd_intel8x0_mic_open,
1319 .close = snd_intel8x0_mic_close,
1320 .ioctl = snd_pcm_lib_ioctl,
1321 .hw_params = snd_intel8x0_hw_params,
1322 .hw_free = snd_intel8x0_hw_free,
1323 .prepare = snd_intel8x0_pcm_prepare,
1324 .trigger = snd_intel8x0_pcm_trigger,
1325 .pointer = snd_intel8x0_pcm_pointer,
1328 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1329 .open = snd_intel8x0_mic2_open,
1330 .close = snd_intel8x0_mic2_close,
1331 .ioctl = snd_pcm_lib_ioctl,
1332 .hw_params = snd_intel8x0_hw_params,
1333 .hw_free = snd_intel8x0_hw_free,
1334 .prepare = snd_intel8x0_pcm_prepare,
1335 .trigger = snd_intel8x0_pcm_trigger,
1336 .pointer = snd_intel8x0_pcm_pointer,
1339 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1340 .open = snd_intel8x0_capture2_open,
1341 .close = snd_intel8x0_capture2_close,
1342 .ioctl = snd_pcm_lib_ioctl,
1343 .hw_params = snd_intel8x0_hw_params,
1344 .hw_free = snd_intel8x0_hw_free,
1345 .prepare = snd_intel8x0_pcm_prepare,
1346 .trigger = snd_intel8x0_pcm_trigger,
1347 .pointer = snd_intel8x0_pcm_pointer,
1350 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1351 .open = snd_intel8x0_spdif_open,
1352 .close = snd_intel8x0_spdif_close,
1353 .ioctl = snd_pcm_lib_ioctl,
1354 .hw_params = snd_intel8x0_hw_params,
1355 .hw_free = snd_intel8x0_hw_free,
1356 .prepare = snd_intel8x0_pcm_prepare,
1357 .trigger = snd_intel8x0_pcm_trigger,
1358 .pointer = snd_intel8x0_pcm_pointer,
1361 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1362 .open = snd_intel8x0_playback_open,
1363 .close = snd_intel8x0_playback_close,
1364 .ioctl = snd_pcm_lib_ioctl,
1365 .hw_params = snd_intel8x0_hw_params,
1366 .hw_free = snd_intel8x0_hw_free,
1367 .prepare = snd_intel8x0_pcm_prepare,
1368 .trigger = snd_intel8x0_ali_trigger,
1369 .pointer = snd_intel8x0_pcm_pointer,
1372 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1373 .open = snd_intel8x0_capture_open,
1374 .close = snd_intel8x0_capture_close,
1375 .ioctl = snd_pcm_lib_ioctl,
1376 .hw_params = snd_intel8x0_hw_params,
1377 .hw_free = snd_intel8x0_hw_free,
1378 .prepare = snd_intel8x0_pcm_prepare,
1379 .trigger = snd_intel8x0_ali_trigger,
1380 .pointer = snd_intel8x0_pcm_pointer,
1383 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1384 .open = snd_intel8x0_mic_open,
1385 .close = snd_intel8x0_mic_close,
1386 .ioctl = snd_pcm_lib_ioctl,
1387 .hw_params = snd_intel8x0_hw_params,
1388 .hw_free = snd_intel8x0_hw_free,
1389 .prepare = snd_intel8x0_pcm_prepare,
1390 .trigger = snd_intel8x0_ali_trigger,
1391 .pointer = snd_intel8x0_pcm_pointer,
1394 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1395 .open = snd_intel8x0_ali_ac97spdifout_open,
1396 .close = snd_intel8x0_ali_ac97spdifout_close,
1397 .ioctl = snd_pcm_lib_ioctl,
1398 .hw_params = snd_intel8x0_hw_params,
1399 .hw_free = snd_intel8x0_hw_free,
1400 .prepare = snd_intel8x0_pcm_prepare,
1401 .trigger = snd_intel8x0_ali_trigger,
1402 .pointer = snd_intel8x0_pcm_pointer,
1405 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1406 .open = snd_intel8x0_ali_spdifin_open,
1407 .close = snd_intel8x0_ali_spdifin_close,
1408 .ioctl = snd_pcm_lib_ioctl,
1409 .hw_params = snd_intel8x0_hw_params,
1410 .hw_free = snd_intel8x0_hw_free,
1411 .prepare = snd_intel8x0_pcm_prepare,
1412 .trigger = snd_intel8x0_pcm_trigger,
1413 .pointer = snd_intel8x0_pcm_pointer,
1417 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1418 .open = snd_intel8x0_ali_spdifout_open,
1419 .close = snd_intel8x0_ali_spdifout_close,
1420 .ioctl = snd_pcm_lib_ioctl,
1421 .hw_params = snd_intel8x0_hw_params,
1422 .hw_free = snd_intel8x0_hw_free,
1423 .prepare = snd_intel8x0_pcm_prepare,
1424 .trigger = snd_intel8x0_pcm_trigger,
1425 .pointer = snd_intel8x0_pcm_pointer,
1429 struct ich_pcm_table {
1431 snd_pcm_ops_t *playback_ops;
1432 snd_pcm_ops_t *capture_ops;
1433 size_t prealloc_size;
1434 size_t prealloc_max_size;
1438 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1445 sprintf(name, "Intel ICH - %s", rec->suffix);
1447 strcpy(name, "Intel ICH");
1448 err = snd_pcm_new(chip->card, name, device,
1449 rec->playback_ops ? 1 : 0,
1450 rec->capture_ops ? 1 : 0, &pcm);
1454 if (rec->playback_ops)
1455 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1456 if (rec->capture_ops)
1457 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1459 pcm->private_data = chip;
1460 pcm->info_flags = 0;
1462 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1464 strcpy(pcm->name, chip->card->shortname);
1465 chip->pcm[device] = pcm;
1467 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1468 rec->prealloc_size, rec->prealloc_max_size);
1473 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1475 .playback_ops = &snd_intel8x0_playback_ops,
1476 .capture_ops = &snd_intel8x0_capture_ops,
1477 .prealloc_size = 64 * 1024,
1478 .prealloc_max_size = 128 * 1024,
1481 .suffix = "MIC ADC",
1482 .capture_ops = &snd_intel8x0_capture_mic_ops,
1484 .prealloc_max_size = 128 * 1024,
1485 .ac97_idx = ICHD_MIC,
1488 .suffix = "MIC2 ADC",
1489 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1491 .prealloc_max_size = 128 * 1024,
1492 .ac97_idx = ICHD_MIC2,
1496 .capture_ops = &snd_intel8x0_capture2_ops,
1498 .prealloc_max_size = 128 * 1024,
1499 .ac97_idx = ICHD_PCM2IN,
1503 .playback_ops = &snd_intel8x0_spdif_ops,
1504 .prealloc_size = 64 * 1024,
1505 .prealloc_max_size = 128 * 1024,
1506 .ac97_idx = ICHD_SPBAR,
1510 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1512 .playback_ops = &snd_intel8x0_playback_ops,
1513 .capture_ops = &snd_intel8x0_capture_ops,
1514 .prealloc_size = 64 * 1024,
1515 .prealloc_max_size = 128 * 1024,
1518 .suffix = "MIC ADC",
1519 .capture_ops = &snd_intel8x0_capture_mic_ops,
1521 .prealloc_max_size = 128 * 1024,
1522 .ac97_idx = NVD_MIC,
1526 .playback_ops = &snd_intel8x0_spdif_ops,
1527 .prealloc_size = 64 * 1024,
1528 .prealloc_max_size = 128 * 1024,
1529 .ac97_idx = NVD_SPBAR,
1533 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1535 .playback_ops = &snd_intel8x0_ali_playback_ops,
1536 .capture_ops = &snd_intel8x0_ali_capture_ops,
1537 .prealloc_size = 64 * 1024,
1538 .prealloc_max_size = 128 * 1024,
1541 .suffix = "MIC ADC",
1542 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = ALID_MIC,
1549 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1550 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1551 .prealloc_size = 64 * 1024,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = ALID_AC97SPDIFOUT,
1557 .suffix = "HW IEC958",
1558 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1559 .prealloc_size = 64 * 1024,
1560 .prealloc_max_size = 128 * 1024,
1565 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1567 int i, tblsize, device, err;
1568 struct ich_pcm_table *tbl, *rec;
1570 switch (chip->device_type) {
1571 case DEVICE_INTEL_ICH4:
1573 tblsize = ARRAY_SIZE(intel_pcms);
1577 tblsize = ARRAY_SIZE(nforce_pcms);
1581 tblsize = ARRAY_SIZE(ali_pcms);
1590 for (i = 0; i < tblsize; i++) {
1592 if (i > 0 && rec->ac97_idx) {
1593 /* activate PCM only when associated AC'97 codec */
1594 if (! chip->ichd[rec->ac97_idx].pcm)
1597 err = snd_intel8x0_pcm1(chip, device, rec);
1603 chip->pcm_devs = device;
1612 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1614 intel8x0_t *chip = snd_magic_cast(intel8x0_t, bus->private_data, return);
1615 chip->ac97_bus = NULL;
1618 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1620 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
1621 chip->ac97[ac97->num] = NULL;
1624 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1629 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1630 (1 << AC97_SLOT_PCM_RIGHT) |
1631 (1 << AC97_SLOT_PCM_CENTER) |
1632 (1 << AC97_SLOT_PCM_SLEFT) |
1633 (1 << AC97_SLOT_PCM_SRIGHT) |
1634 (1 << AC97_SLOT_LFE)
1643 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1644 (1 << AC97_SLOT_PCM_RIGHT)
1653 .slots = (1 << AC97_SLOT_MIC)
1662 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1663 (1 << AC97_SLOT_SPDIF_RIGHT2)
1672 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1673 (1 << AC97_SLOT_PCM_RIGHT)
1682 .slots = (1 << AC97_SLOT_MIC)
1688 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1692 .name = "Compaq Evo D510C",
1693 .type = AC97_TUNE_HP_ONLY
1699 .type = AC97_TUNE_ALC_JACK
1704 .name = "Dell Precision 530", /* AD1885 */
1705 .type = AC97_TUNE_HP_ONLY
1710 .name = "Dell Optiplex GX260", /* AD1981A */
1711 .type = AC97_TUNE_HP_ONLY
1713 { /* FIXME: which codec? */
1716 .name = "Hewlett-Packard onboard",
1717 .type = AC97_TUNE_HP_ONLY
1722 .name = "ASUS ICH5/AD1985",
1723 .type = AC97_TUNE_AD_SHARING
1728 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1729 .type = AC97_TUNE_HP_ONLY
1734 .name = "AMD64 Mobo", /* ALC650 */
1735 .type = AC97_TUNE_HP_ONLY
1740 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1741 .type = AC97_TUNE_HP_ONLY
1746 .name = "ADI AD1985 (discrete)",
1747 .type = AC97_TUNE_HP_ONLY
1752 .name = "MSI P4 ATX 645 Ultra",
1753 .type = AC97_TUNE_HP_ONLY
1758 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1759 .type = AC97_TUNE_HP_ONLY
1765 .name = "Intel ICH5/AD1985",
1766 .type = AC97_TUNE_AD_SHARING
1772 .name = "Intel ICH5/AD1985",
1773 .type = AC97_TUNE_AD_SHARING
1778 .name = "Intel D845WN (82801BA)",
1779 .type = AC97_TUNE_SWAP_HP
1784 .name = "Intel D850EMV2", /* AD1885 */
1785 .type = AC97_TUNE_HP_ONLY
1791 .name = "Intel ICH5/AD1985",
1792 .type = AC97_TUNE_AD_SHARING
1798 .name = "Intel ICH5/AD1985",
1799 .type = AC97_TUNE_AD_SHARING
1801 #if 0 /* FIXME: this seems wrong on most boards */
1806 .name = "Intel ICH5/AD1985",
1807 .type = AC97_TUNE_HP_ONLY
1810 { } /* terminator */
1813 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, int ac97_quirk)
1815 ac97_bus_t bus, *pbus;
1818 unsigned int i, codecs;
1819 unsigned int glob_sta = 0;
1820 int spdif_idx = -1; /* disabled */
1822 switch (chip->device_type) {
1824 spdif_idx = NVD_SPBAR;
1827 spdif_idx = ALID_AC97SPDIFOUT;
1830 if (chip->device_type == DEVICE_INTEL_ICH4)
1831 spdif_idx = ICHD_SPBAR;
1835 chip->in_ac97_init = 1;
1836 memset(&bus, 0, sizeof(bus));
1837 bus.private_data = chip;
1838 bus.private_free = snd_intel8x0_mixer_free_ac97_bus;
1839 if (ac97_clock >= 8000 && ac97_clock <= 48000)
1840 bus.clock = ac97_clock;
1844 memset(&ac97, 0, sizeof(ac97));
1845 ac97.private_data = chip;
1846 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1847 if (chip->device_type != DEVICE_ALI) {
1848 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1849 bus.write = snd_intel8x0_codec_write;
1850 bus.read = snd_intel8x0_codec_read;
1851 if (chip->device_type == DEVICE_INTEL_ICH4) {
1853 if (glob_sta & ICH_PCR)
1855 if (glob_sta & ICH_SCR)
1857 if (glob_sta & ICH_TCR)
1859 chip->in_sdin_init = 1;
1860 for (i = 0; i < codecs; i++) {
1862 snd_intel8x0_codec_read(&ac97, 0);
1863 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1866 chip->in_sdin_init = 0;
1868 codecs = glob_sta & ICH_SCR ? 2 : 1;
1872 bus.write = snd_intel8x0_ali_codec_write;
1873 bus.read = snd_intel8x0_ali_codec_read;
1875 /* detect the secondary codec */
1876 for (i = 0; i < 100; i++) {
1877 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1882 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
1885 /* FIXME: my test board doens't work well with VRA... */
1888 if ((err = snd_ac97_bus(chip->card, &bus, &pbus)) < 0)
1890 chip->ac97_bus = pbus;
1891 ac97.pci = chip->pci;
1892 for (i = 0; i < codecs; i++) {
1894 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
1895 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
1900 chip->ac97[i] = x97;
1902 /* tune up the primary codec */
1903 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, ac97_quirk);
1904 /* enable separate SDINs for ICH4 */
1905 if (chip->device_type == DEVICE_INTEL_ICH4)
1907 /* find the available PCM streams */
1908 i = ARRAY_SIZE(ac97_pcm_defs);
1909 if (chip->device_type != DEVICE_INTEL_ICH4)
1910 i -= 2; /* do not allocate PCM2IN and MIC2 */
1912 i--; /* do not allocate S/PDIF */
1913 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
1916 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
1917 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
1918 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
1920 chip->ichd[spdif_idx].pcm = &pbus->pcms[3];
1921 if (chip->device_type == DEVICE_INTEL_ICH4) {
1922 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
1923 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
1925 /* enable separate SDINs for ICH4 */
1926 if (chip->device_type == DEVICE_INTEL_ICH4) {
1927 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
1928 u8 tmp = igetbyte(chip, ICHREG(SDM));
1929 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
1931 tmp |= ICH_SE; /* steer enable for multiple SDINs */
1932 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
1933 for (i = 1; i < 4; i++) {
1934 if (pcm->r[0].codec[i]) {
1935 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
1940 tmp &= ~ICH_SE; /* steer disable */
1942 iputbyte(chip, ICHREG(SDM), tmp);
1944 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1946 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
1949 if (chip->device_type == DEVICE_NFORCE) {
1951 chip->ichd[spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
1953 chip->in_ac97_init = 0;
1957 /* clear the cold-reset bit for the next chance */
1958 if (chip->device_type != DEVICE_ALI)
1959 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1968 static void do_ali_reset(intel8x0_t *chip)
1970 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
1971 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
1972 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
1973 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
1974 iputdword(chip, ICHREG(ALI_INTERFACECR),
1975 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1976 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
1977 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
1980 #define do_delay(chip) do {\
1981 set_current_state(TASK_UNINTERRUPTIBLE);\
1982 schedule_timeout(1);\
1985 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
1987 unsigned long end_time;
1988 unsigned int cnt, status, nstatus;
1990 /* put logic to right state */
1991 /* first clear status bits */
1992 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
1993 if (chip->device_type == DEVICE_NFORCE)
1994 status |= ICH_NVSPINT;
1995 cnt = igetdword(chip, ICHREG(GLOB_STA));
1996 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
1998 /* ACLink on, 2 channels */
1999 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2000 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2001 /* finish cold or do warm reset */
2002 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2003 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2004 end_time = (jiffies + (HZ / 4)) + 1;
2006 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2009 } while (time_after_eq(end_time, jiffies));
2010 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2015 /* wait for any codec ready status.
2016 * Once it becomes ready it should remain ready
2017 * as long as we do not disable the ac97 link.
2019 end_time = jiffies + HZ;
2021 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2025 } while (time_after_eq(end_time, jiffies));
2027 /* no codec is found */
2028 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2032 if (chip->device_type == DEVICE_INTEL_ICH4)
2033 /* ICH4 can have three codecs */
2034 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2036 /* others up to two codecs */
2037 nstatus = ICH_PCR | ICH_SCR;
2039 /* wait for other codecs ready status. */
2040 end_time = jiffies + HZ / 4;
2041 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2043 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2050 for (i = 0; i < 3; i++)
2052 status |= get_ich_codec_bit(chip, i);
2053 /* wait until all the probed codecs are ready */
2054 end_time = jiffies + HZ;
2056 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2057 if (status == nstatus)
2060 } while (time_after_eq(end_time, jiffies));
2063 if (chip->device_type == DEVICE_SIS) {
2064 /* unmute the output on SIS7012 */
2065 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2067 if (chip->device_type == DEVICE_NFORCE) {
2068 /* enable SPDIF interrupt */
2070 pci_read_config_dword(chip->pci, 0x4c, &val);
2072 pci_write_config_dword(chip->pci, 0x4c, val);
2077 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2082 reg = igetdword(chip, ICHREG(ALI_SCR));
2083 if ((reg & 2) == 0) /* Cold required */
2086 reg |= 1; /* Warm */
2087 reg &= ~0x80000000; /* ACLink on */
2088 iputdword(chip, ICHREG(ALI_SCR), reg);
2090 for (i = 0; i < HZ / 2; i++) {
2091 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2095 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2100 for (i = 0; i < HZ / 2; i++) {
2101 reg = igetdword(chip, ICHREG(ALI_RTSR));
2102 if (reg & 0x80) /* primary codec */
2104 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2112 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2117 if (chip->device_type != DEVICE_ALI) {
2118 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2120 iagetword(chip, 0); /* clear semaphore flag */
2122 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2126 /* disable interrupts */
2127 for (i = 0; i < chip->bdbars_count; i++)
2128 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2129 /* reset channels */
2130 for (i = 0; i < chip->bdbars_count; i++)
2131 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2132 /* initialize Buffer Descriptor Lists */
2133 for (i = 0; i < chip->bdbars_count; i++)
2134 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2138 static int snd_intel8x0_free(intel8x0_t *chip)
2144 /* disable interrupts */
2145 for (i = 0; i < chip->bdbars_count; i++)
2146 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2147 /* reset channels */
2148 for (i = 0; i < chip->bdbars_count; i++)
2149 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2150 if (chip->device_type == DEVICE_NFORCE) {
2151 /* stop the spdif interrupt */
2153 pci_read_config_dword(chip->pci, 0x4c, &val);
2155 pci_write_config_dword(chip->pci, 0x4c, val);
2158 synchronize_irq(chip->irq);
2160 if (chip->bdbars.area) {
2161 if (chip->fix_nocache)
2162 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2163 snd_dma_free_pages(&chip->dma_dev, &chip->bdbars);
2165 if (chip->remap_addr)
2166 iounmap((void *) chip->remap_addr);
2167 if (chip->remap_bmaddr)
2168 iounmap((void *) chip->remap_bmaddr);
2170 release_resource(chip->res);
2171 kfree_nocheck(chip->res);
2174 release_resource(chip->res_bm);
2175 kfree_nocheck(chip->res_bm);
2178 free_irq(chip->irq, (void *)chip);
2179 snd_magic_kfree(chip);
2187 static void intel8x0_suspend(intel8x0_t *chip)
2189 snd_card_t *card = chip->card;
2192 if (chip->in_suspend ||
2193 card->power_state == SNDRV_CTL_POWER_D3hot)
2196 chip->in_suspend = 1;
2197 for (i = 0; i < chip->pcm_devs; i++)
2198 snd_pcm_suspend_all(chip->pcm[i]);
2199 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2202 static void intel8x0_resume(intel8x0_t *chip)
2204 snd_card_t *card = chip->card;
2207 if (! chip->in_suspend ||
2208 card->power_state == SNDRV_CTL_POWER_D0)
2211 pci_enable_device(chip->pci);
2212 pci_set_master(chip->pci);
2213 snd_intel8x0_chip_init(chip, 0);
2214 for (i = 0; i < 3; i++)
2216 snd_ac97_resume(chip->ac97[i]);
2218 chip->in_suspend = 0;
2219 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2222 static int snd_intel8x0_suspend(struct pci_dev *dev, u32 state)
2224 intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
2225 intel8x0_suspend(chip);
2228 static int snd_intel8x0_resume(struct pci_dev *dev)
2230 intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
2231 intel8x0_resume(chip);
2236 static int snd_intel8x0_set_power_state(snd_card_t *card, unsigned int power_state)
2238 intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->power_state_private_data, return -ENXIO);
2239 switch (power_state) {
2240 case SNDRV_CTL_POWER_D0:
2241 case SNDRV_CTL_POWER_D1:
2242 case SNDRV_CTL_POWER_D2:
2243 intel8x0_resume(chip);
2245 case SNDRV_CTL_POWER_D3hot:
2246 case SNDRV_CTL_POWER_D3cold:
2247 intel8x0_suspend(chip);
2255 #endif /* CONFIG_PM */
2257 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2259 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2261 snd_pcm_substream_t *subs;
2264 unsigned long pos, t;
2265 unsigned long flags;
2266 struct timeval start_time, stop_time;
2268 if (chip->ac97_bus->clock != 48000)
2269 return; /* specified in module option */
2271 subs = chip->pcm[0]->streams[0].substream;
2272 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2273 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2276 ichdev = &chip->ichd[ICHD_PCMOUT];
2277 ichdev->physbuf = subs->dma_buffer.addr;
2278 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2279 ichdev->substream = NULL; /* don't process interrupts */
2282 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2283 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2286 snd_intel8x0_setup_periods(chip, ichdev);
2287 port = ichdev->reg_offset;
2288 spin_lock_irqsave(&chip->reg_lock, flags);
2290 if (chip->device_type != DEVICE_ALI)
2291 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2293 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2294 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2296 do_gettimeofday(&start_time);
2297 spin_unlock_irqrestore(&chip->reg_lock, flags);
2299 set_current_state(TASK_UNINTERRUPTIBLE);
2300 schedule_timeout(HZ / 20);
2302 /* FIXME: schedule() can take too long time and overlap the boundary.. */
2305 spin_lock_irqsave(&chip->reg_lock, flags);
2306 /* check the position */
2307 pos = ichdev->fragsize1;
2308 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
2309 pos += ichdev->position;
2310 do_gettimeofday(&stop_time);
2312 if (chip->device_type == DEVICE_ALI) {
2313 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2314 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2315 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2318 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2319 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2322 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2323 spin_unlock_irqrestore(&chip->reg_lock, flags);
2325 t = stop_time.tv_sec - start_time.tv_sec;
2327 t += stop_time.tv_usec - start_time.tv_usec;
2328 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2330 snd_printk(KERN_ERR "?? calculation error..\n");
2333 pos = (pos / 4) * 1000;
2334 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2335 if (pos < 40000 || pos >= 60000)
2336 /* abnormal value. hw problem? */
2337 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2338 else if (pos < 47500 || pos > 48500)
2339 /* not 48000Hz, tuning the clock.. */
2340 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2341 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2344 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2345 snd_info_buffer_t * buffer)
2347 intel8x0_t *chip = snd_magic_cast(intel8x0_t, entry->private_data, return);
2350 snd_iprintf(buffer, "Intel8x0\n\n");
2351 if (chip->device_type == DEVICE_ALI)
2353 tmp = igetdword(chip, ICHREG(GLOB_STA));
2354 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2355 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2356 if (chip->device_type == DEVICE_INTEL_ICH4)
2357 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2358 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2359 tmp & ICH_PCR ? " primary" : "",
2360 tmp & ICH_SCR ? " secondary" : "",
2361 tmp & ICH_TCR ? " tertiary" : "",
2362 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2363 if (chip->device_type == DEVICE_INTEL_ICH4)
2364 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2367 chip->ac97_sdin[2]);
2370 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2372 snd_info_entry_t *entry;
2374 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2375 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2378 static int snd_intel8x0_dev_free(snd_device_t *device)
2380 intel8x0_t *chip = snd_magic_cast(intel8x0_t, device->device_data, return -ENXIO);
2381 return snd_intel8x0_free(chip);
2384 struct ich_reg_info {
2385 unsigned int int_sta_mask;
2386 unsigned int offset;
2389 static int __devinit snd_intel8x0_create(snd_card_t * card,
2390 struct pci_dev *pci,
2391 unsigned long device_type,
2392 intel8x0_t ** r_intel8x0)
2397 unsigned int int_sta_masks;
2399 static snd_device_ops_t ops = {
2400 .dev_free = snd_intel8x0_dev_free,
2403 static unsigned int bdbars[] = {
2404 3, /* DEVICE_INTEL */
2405 6, /* DEVICE_INTEL_ICH4 */
2408 4, /* DEVICE_NFORCE */
2410 static struct ich_reg_info intel_regs[6] = {
2412 { ICH_POINT, 0x10 },
2413 { ICH_MCINT, 0x20 },
2414 { ICH_M2INT, 0x40 },
2415 { ICH_P2INT, 0x50 },
2416 { ICH_SPINT, 0x60 },
2418 static struct ich_reg_info nforce_regs[4] = {
2420 { ICH_POINT, 0x10 },
2421 { ICH_MCINT, 0x20 },
2422 { ICH_NVSPINT, 0x70 },
2424 static struct ich_reg_info ali_regs[6] = {
2425 { ALI_INT_PCMIN, 0x40 },
2426 { ALI_INT_PCMOUT, 0x50 },
2427 { ALI_INT_MICIN, 0x60 },
2428 { ALI_INT_CODECSPDIFOUT, 0x70 },
2429 { ALI_INT_SPDIFIN, 0xa0 },
2430 { ALI_INT_SPDIFOUT, 0xb0 },
2432 struct ich_reg_info *tbl;
2436 if ((err = pci_enable_device(pci)) < 0)
2439 chip = snd_magic_kcalloc(intel8x0_t, 0, GFP_KERNEL);
2442 spin_lock_init(&chip->reg_lock);
2443 spin_lock_init(&chip->ac97_lock);
2444 chip->device_type = device_type;
2448 snd_intel8x0_proc_init(chip);
2449 sprintf(chip->ac97_name, "%s - AC'97", card->shortname);
2450 sprintf(chip->ctrl_name, "%s - Controller", card->shortname);
2451 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2452 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2453 chip->fix_nocache = 1; /* enable workaround */
2454 if (device_type == DEVICE_ALI) {
2455 /* ALI5455 has no ac97 region */
2456 chip->bmaddr = pci_resource_start(pci, 0);
2457 if ((chip->res_bm = request_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2458 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2459 snd_intel8x0_free(chip);
2465 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2467 chip->addr = pci_resource_start(pci, 2);
2468 if ((chip->res = request_mem_region(chip->addr, 512, chip->ac97_name)) == NULL) {
2469 snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->addr, chip->addr + 512 - 1);
2470 snd_intel8x0_free(chip);
2473 chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr, 512);
2474 if (chip->remap_addr == 0) {
2475 snd_printk("AC'97 space ioremap problem\n");
2476 snd_intel8x0_free(chip);
2480 chip->addr = pci_resource_start(pci, 0);
2481 if ((chip->res = request_region(chip->addr, 256, chip->ac97_name)) == NULL) {
2482 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->addr, chip->addr + 256 - 1);
2483 snd_intel8x0_free(chip);
2487 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2489 chip->bmaddr = pci_resource_start(pci, 3);
2490 if ((chip->res_bm = request_mem_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2491 snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 512 - 1);
2492 snd_intel8x0_free(chip);
2495 chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr, 256);
2496 if (chip->remap_bmaddr == 0) {
2497 snd_printk("Controller space ioremap problem\n");
2498 snd_intel8x0_free(chip);
2502 chip->bmaddr = pci_resource_start(pci, 1);
2503 if ((chip->res_bm = request_region(chip->bmaddr, 64, chip->ctrl_name)) == NULL) {
2504 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2505 snd_intel8x0_free(chip);
2511 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2512 snd_printk("unable to grab IRQ %d\n", pci->irq);
2513 snd_intel8x0_free(chip);
2516 chip->irq = pci->irq;
2517 pci_set_master(pci);
2518 synchronize_irq(chip->irq);
2520 chip->bdbars_count = bdbars[device_type];
2522 /* initialize offsets */
2523 switch (device_type) {
2534 for (i = 0; i < chip->bdbars_count; i++) {
2535 ichdev = &chip->ichd[i];
2537 ichdev->reg_offset = tbl[i].offset;
2538 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2539 if (device_type == DEVICE_SIS) {
2540 /* SiS 7012 swaps the registers */
2541 ichdev->roff_sr = ICH_REG_OFF_PICB;
2542 ichdev->roff_picb = ICH_REG_OFF_SR;
2544 ichdev->roff_sr = ICH_REG_OFF_SR;
2545 ichdev->roff_picb = ICH_REG_OFF_PICB;
2547 if (device_type == DEVICE_ALI)
2548 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2550 /* SIS7012 handles the pcm data in bytes, others are in words */
2551 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2553 memset(&chip->dma_dev, 0, sizeof(chip->dma_dev));
2554 chip->dma_dev.type = SNDRV_DMA_TYPE_DEV;
2555 chip->dma_dev.dev = snd_dma_pci_data(pci);
2557 /* allocate buffer descriptor lists */
2558 /* the start of each lists must be aligned to 8 bytes */
2559 if (snd_dma_alloc_pages(&chip->dma_dev, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, &chip->bdbars) < 0) {
2560 snd_intel8x0_free(chip);
2561 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2564 /* tables must be aligned to 8 bytes here, but the kernel pages
2565 are much bigger, so we don't care (on i386) */
2566 /* workaround for 440MX */
2567 if (chip->fix_nocache)
2568 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2570 for (i = 0; i < chip->bdbars_count; i++) {
2571 ichdev = &chip->ichd[i];
2572 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2573 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2574 int_sta_masks |= ichdev->int_sta_mask;
2576 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2577 chip->int_sta_mask = int_sta_masks;
2579 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2580 snd_intel8x0_free(chip);
2585 card->set_power_state = snd_intel8x0_set_power_state;
2586 card->power_state_private_data = chip;
2589 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2590 snd_intel8x0_free(chip);
2594 snd_card_set_dev(card, &pci->dev);
2600 static struct shortname_table {
2603 } shortnames[] __devinitdata = {
2604 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2605 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2606 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2607 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2608 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2609 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2610 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2611 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2612 { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2613 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2614 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2615 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2616 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2617 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2618 { 0x746d, "AMD AMD8111" },
2619 { 0x7445, "AMD AMD768" },
2620 { 0x5455, "ALi M5455" },
2624 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2625 const struct pci_device_id *pci_id)
2631 struct shortname_table *name;
2633 if (dev >= SNDRV_CARDS)
2640 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2644 switch (pci_id->driver_data) {
2646 strcpy(card->driver, "NFORCE");
2649 strcpy(card->driver, "ICH");
2653 strcpy(card->shortname, "Intel ICH");
2654 for (name = shortnames; name->id; name++) {
2655 if (pci->device == name->id) {
2656 strcpy(card->shortname, name->s);
2661 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2662 snd_card_free(card);
2666 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2667 snd_card_free(card);
2670 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2671 snd_card_free(card);
2675 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2676 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
2678 -1, 0, &chip->rmidi)) < 0) {
2679 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
2685 sprintf(card->longname, "%s at 0x%lx, irq %i",
2686 card->shortname, chip->addr, chip->irq);
2688 if (! ac97_clock[dev])
2689 intel8x0_measure_ac97_clock(chip);
2691 if ((err = snd_card_register(card)) < 0) {
2692 snd_card_free(card);
2695 pci_set_drvdata(pci, chip);
2700 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2702 intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(pci), return);
2704 snd_card_free(chip->card);
2705 pci_set_drvdata(pci, NULL);
2708 static struct pci_driver driver = {
2709 .name = "Intel ICH",
2710 .id_table = snd_intel8x0_ids,
2711 .probe = snd_intel8x0_probe,
2712 .remove = __devexit_p(snd_intel8x0_remove),
2714 .suspend = snd_intel8x0_suspend,
2715 .resume = snd_intel8x0_resume,
2720 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2722 * initialize joystick/midi addresses
2725 #ifdef SUPPORT_JOYSTICK
2726 /* there is only one available device, so we keep it here */
2727 static struct pci_dev *ich_gameport_pci;
2728 static struct gameport ich_gameport = { .io = 0x200 };
2731 static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
2732 const struct pci_device_id *id)
2736 if (dev >= SNDRV_CARDS)
2743 pci_read_config_word(pci, 0xe6, &val);
2744 #ifdef SUPPORT_JOYSTICK
2746 if (joystick[dev]) {
2747 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
2748 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
2751 ich_gameport_pci = pci;
2752 gameport_register_port(&ich_gameport);
2759 if (mpu_port[dev] > 0) {
2760 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2763 pci_read_config_byte(pci, 0xe2, &b);
2764 if (mpu_port[dev] == 0x300)
2768 pci_write_config_byte(pci, 0xe2, b);
2772 pci_write_config_word(pci, 0xe6, val);
2776 static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
2779 #ifdef SUPPORT_JOYSTICK
2780 if (ich_gameport_pci == pci) {
2781 gameport_unregister_port(&ich_gameport);
2782 release_region(ich_gameport.io, 8);
2783 ich_gameport_pci = NULL;
2786 /* disable joystick and MIDI */
2787 pci_read_config_word(pci, 0xe6, &val);
2789 pci_write_config_word(pci, 0xe6, val);
2792 static struct pci_device_id snd_intel8x0_joystick_ids[] = {
2793 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
2794 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
2795 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
2796 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
2797 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
2798 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
2799 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
2800 { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
2801 { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
2802 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
2806 static struct pci_driver joystick_driver = {
2807 .name = "Intel ICH Joystick",
2808 .id_table = snd_intel8x0_joystick_ids,
2809 .probe = snd_intel8x0_joystick_probe,
2810 .remove = __devexit_p(snd_intel8x0_joystick_remove),
2813 static int have_joystick;
2816 static int __init alsa_card_intel8x0_init(void)
2820 if ((err = pci_module_init(&driver)) < 0) {
2822 printk(KERN_ERR "Intel ICH soundcard not found or device busy\n");
2826 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2827 if (pci_module_init(&joystick_driver) < 0) {
2828 snd_printdd(KERN_INFO "no joystick found\n");
2831 snd_printdd(KERN_INFO "joystick(s) found\n");
2839 static void __exit alsa_card_intel8x0_exit(void)
2841 pci_unregister_driver(&driver);
2842 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2844 pci_unregister_driver(&joystick_driver);
2848 module_init(alsa_card_intel8x0_init)
2849 module_exit(alsa_card_intel8x0_exit)
2853 /* format is: snd-intel8x0=enable,index,id,ac97_clock,ac97_quirk,mpu_port,joystick */
2855 static int __init alsa_card_intel8x0_setup(char *str)
2857 static unsigned __initdata nr_dev = 0;
2859 if (nr_dev >= SNDRV_CARDS)
2861 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2862 get_option(&str,&index[nr_dev]) == 2 &&
2863 get_id(&str,&id[nr_dev]) == 2 &&
2864 get_option(&str,&ac97_clock[nr_dev]) == 2 &&
2865 get_option(&str,&ac97_quirk[nr_dev]) == 2
2867 && get_option(&str,&mpu_port[nr_dev]) == 2
2869 #ifdef SUPPORT_JOYSTICK
2870 && get_option(&str,&joystick[nr_dev]) == 2
2877 __setup("snd-intel8x0=", alsa_card_intel8x0_setup);
2879 #endif /* ifndef MODULE */