2 * ALSA driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/gameport.h>
37 #include <linux/moduleparam.h>
38 #include <sound/core.h>
39 #include <sound/pcm.h>
40 #include <sound/ac97_codec.h>
41 #include <sound/info.h>
42 #include <sound/mpu401.h>
43 #include <sound/initval.h>
44 /* for 440MX workaround */
45 #include <asm/pgtable.h>
46 #include <asm/cacheflush.h>
48 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
49 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
50 MODULE_LICENSE("GPL");
51 MODULE_CLASSES("{sound}");
52 MODULE_DEVICES("{{Intel,82801AA-ICH},"
53 "{Intel,82901AB-ICH0},"
54 "{Intel,82801BA-ICH2},"
55 "{Intel,82801CA-ICH3},"
56 "{Intel,82801DB-ICH4},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
68 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
69 #define SUPPORT_JOYSTICK 1
71 #define SUPPORT_MIDI 1
73 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
74 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
75 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
76 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
77 static int ac97_quirk[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = AC97_TUNE_DEFAULT};
78 #ifdef SUPPORT_JOYSTICK
79 static int joystick[SNDRV_CARDS];
82 static int mpu_port[SNDRV_CARDS]; /* disabled */
86 module_param_array(index, int, boot_devs, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
88 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
89 module_param_array(id, charp, boot_devs, 0444);
90 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
91 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
92 module_param_array(enable, bool, boot_devs, 0444);
93 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
94 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
95 module_param_array(ac97_clock, int, boot_devs, 0444);
96 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
97 MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
98 module_param_array(ac97_quirk, int, boot_devs, 0444);
99 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
100 MODULE_PARM_SYNTAX(ac97_quirk, SNDRV_ENABLED ",allows:{{-1,4}},dialog:list,default:-1");
101 #ifdef SUPPORT_JOYSTICK
102 module_param_array(joystick, bool, boot_devs, 0444);
103 MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
104 MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
107 module_param_array(mpu_port, int, boot_devs, 0444);
108 MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
109 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
116 #ifndef PCI_DEVICE_ID_INTEL_82801
117 #define PCI_DEVICE_ID_INTEL_82801 0x2415
119 #ifndef PCI_DEVICE_ID_INTEL_82901
120 #define PCI_DEVICE_ID_INTEL_82901 0x2425
122 #ifndef PCI_DEVICE_ID_INTEL_82801BA
123 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
125 #ifndef PCI_DEVICE_ID_INTEL_440MX
126 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
128 #ifndef PCI_DEVICE_ID_INTEL_ICH3
129 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
131 #ifndef PCI_DEVICE_ID_INTEL_ICH4
132 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
134 #ifndef PCI_DEVICE_ID_INTEL_ICH5
135 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
137 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
138 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
140 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
141 #define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e
143 #ifndef PCI_DEVICE_ID_SI_7012
144 #define PCI_DEVICE_ID_SI_7012 0x7012
146 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
147 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
149 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
150 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
152 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
153 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
155 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
156 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
159 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
161 #define ICHREG(x) ICH_REG_##x
163 #define DEFINE_REGSET(name,base) \
165 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
166 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
167 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
168 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
169 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
170 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
171 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
174 /* busmaster blocks */
175 DEFINE_REGSET(OFF, 0); /* offset */
176 DEFINE_REGSET(PI, 0x00); /* PCM in */
177 DEFINE_REGSET(PO, 0x10); /* PCM out */
178 DEFINE_REGSET(MC, 0x20); /* Mic in */
180 /* ICH4 busmaster blocks */
181 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
182 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
183 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
185 /* values for each busmaster block */
188 #define ICH_REG_LVI_MASK 0x1f
191 #define ICH_FIFOE 0x10 /* FIFO error */
192 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
193 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
194 #define ICH_CELV 0x02 /* current equals last valid */
195 #define ICH_DCH 0x01 /* DMA controller halted */
198 #define ICH_REG_PIV_MASK 0x1f /* mask */
201 #define ICH_IOCE 0x10 /* interrupt on completion enable */
202 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
203 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
204 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
205 #define ICH_STARTBM 0x01 /* start busmaster operation */
209 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
210 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
211 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
212 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
213 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
214 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
215 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
216 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
217 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
218 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
219 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
220 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
221 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
222 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
223 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
224 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
225 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
226 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
227 #define ICH_ACLINK 0x00000008 /* AClink shut off */
228 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
229 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
230 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
231 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
232 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
233 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
234 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
235 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
236 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
237 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
238 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
239 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
240 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
241 #define ICH_MD3 0x00020000 /* modem power down semaphore */
242 #define ICH_AD3 0x00010000 /* audio power down semaphore */
243 #define ICH_RCS 0x00008000 /* read completion status */
244 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
245 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
246 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
247 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
248 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
249 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
250 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
251 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
252 #define ICH_POINT 0x00000040 /* playback interrupt */
253 #define ICH_PIINT 0x00000020 /* capture interrupt */
254 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
255 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
256 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
257 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
258 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
259 #define ICH_CAS 0x01 /* codec access semaphore */
260 #define ICH_REG_SDM 0x80
261 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
262 #define ICH_DI2L_SHIFT 6
263 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
264 #define ICH_DI1L_SHIFT 4
265 #define ICH_SE 0x00000008 /* steer enable */
266 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
268 #define ICH_MAX_FRAGS 32 /* max hw frags */
272 * registers for Ali5455
275 /* ALi 5455 busmaster blocks */
276 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
277 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
278 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
279 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
280 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
281 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
282 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
283 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
284 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
285 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
286 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
289 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
290 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
291 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
292 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
293 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
294 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
295 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
296 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
297 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
298 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
299 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
300 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
301 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
302 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
303 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
304 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
305 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
306 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
307 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
308 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
309 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
312 #define ALI_CAS_SEM_BUSY 0x80000000
313 #define ALI_CPR_ADDR_SECONDARY 0x100
314 #define ALI_CPR_ADDR_READ 0x80
315 #define ALI_CSPSR_CODEC_READY 0x08
316 #define ALI_CSPSR_READ_OK 0x02
317 #define ALI_CSPSR_WRITE_OK 0x01
319 /* interrupts for the whole chip by interrupt status register finish */
321 #define ALI_INT_MICIN2 (1<<26)
322 #define ALI_INT_PCMIN2 (1<<25)
323 #define ALI_INT_I2SIN (1<<24)
324 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
325 #define ALI_INT_SPDIFIN (1<<22)
326 #define ALI_INT_LFEOUT (1<<21)
327 #define ALI_INT_CENTEROUT (1<<20)
328 #define ALI_INT_CODECSPDIFOUT (1<<19)
329 #define ALI_INT_MICIN (1<<18)
330 #define ALI_INT_PCMOUT (1<<17)
331 #define ALI_INT_PCMIN (1<<16)
332 #define ALI_INT_CPRAIS (1<<7) /* command port available */
333 #define ALI_INT_SPRAIS (1<<5) /* status port available */
334 #define ALI_INT_GPIO (1<<1)
335 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
337 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
338 #define ICH_ALI_SC_AC97_DBL (1<<30)
339 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
340 #define ICH_ALI_SC_IN_BITS (3<<18)
341 #define ICH_ALI_SC_OUT_BITS (3<<16)
342 #define ICH_ALI_SC_6CH_CFG (3<<14)
343 #define ICH_ALI_SC_PCM_4 (1<<8)
344 #define ICH_ALI_SC_PCM_6 (2<<8)
345 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
347 #define ICH_ALI_SS_SEC_ID (3<<5)
348 #define ICH_ALI_SS_PRI_ID (3<<3)
350 #define ICH_ALI_IF_AC97SP (1<<21)
351 #define ICH_ALI_IF_MC (1<<20)
352 #define ICH_ALI_IF_PI (1<<19)
353 #define ICH_ALI_IF_MC2 (1<<18)
354 #define ICH_ALI_IF_PI2 (1<<17)
355 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
356 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
357 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
358 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
359 #define ICH_ALI_IF_PO_SPDF (1<<3)
360 #define ICH_ALI_IF_PO (1<<1)
366 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
367 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
368 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
370 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
373 unsigned int ichd; /* ich device number */
374 unsigned long reg_offset; /* offset to bmaddr */
375 u32 *bdbar; /* CPU address (32bit) */
376 unsigned int bdbar_addr; /* PCI bus address (32bit) */
377 snd_pcm_substream_t *substream;
378 unsigned int physbuf; /* physical address (32bit) */
380 unsigned int fragsize;
381 unsigned int fragsize1;
382 unsigned int position;
383 unsigned int pos_shift;
390 unsigned int ack_bit;
391 unsigned int roff_sr;
392 unsigned int roff_picb;
393 unsigned int int_sta_mask; /* interrupt status mask */
394 unsigned int ali_slot; /* ALI DMA slot */
395 struct ac97_pcm *pcm;
399 typedef struct _snd_intel8x0 intel8x0_t;
400 #define chip_t intel8x0_t
402 struct _snd_intel8x0 {
403 unsigned int device_type;
411 unsigned long remap_addr;
412 struct resource *res;
413 unsigned int bm_mmio;
414 unsigned long bmaddr;
415 unsigned long remap_bmaddr;
416 struct resource *res_bm;
418 struct snd_dma_device dma_dev;
432 int fix_nocache: 1; /* workaround for 440MX */
434 ac97_bus_t *ac97_bus;
436 unsigned int ac97_sdin[3];
438 snd_rawmidi_t *rmidi;
441 spinlock_t ac97_lock;
444 struct snd_dma_buffer bdbars;
445 u32 int_sta_reg; /* interrupt status register */
446 u32 int_sta_mask; /* interrupt status mask */
449 u32 pci_state[64 / sizeof(u32)];
453 static struct pci_device_id snd_intel8x0_ids[] = {
454 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
455 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
456 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
457 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
458 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
459 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
460 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
461 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
462 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
463 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
464 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
465 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
466 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
467 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
468 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
469 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
470 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
474 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
477 * Lowlevel I/O - busmaster
480 static u8 igetbyte(intel8x0_t *chip, u32 offset)
483 return readb(chip->remap_bmaddr + offset);
485 return inb(chip->bmaddr + offset);
488 static u16 igetword(intel8x0_t *chip, u32 offset)
491 return readw(chip->remap_bmaddr + offset);
493 return inw(chip->bmaddr + offset);
496 static u32 igetdword(intel8x0_t *chip, u32 offset)
499 return readl(chip->remap_bmaddr + offset);
501 return inl(chip->bmaddr + offset);
504 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
507 writeb(val, chip->remap_bmaddr + offset);
509 outb(val, chip->bmaddr + offset);
512 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
515 writew(val, chip->remap_bmaddr + offset);
517 outw(val, chip->bmaddr + offset);
520 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
523 writel(val, chip->remap_bmaddr + offset);
525 outl(val, chip->bmaddr + offset);
529 * Lowlevel I/O - AC'97 registers
532 static u16 iagetword(intel8x0_t *chip, u32 offset)
535 return readw(chip->remap_addr + offset);
537 return inw(chip->addr + offset);
540 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
543 writew(val, chip->remap_addr + offset);
545 outw(val, chip->addr + offset);
553 * access to AC97 codec via normal i/o (for ICH and SIS7012)
556 /* return the GLOB_STA bit for the corresponding codec */
557 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
559 static unsigned int codec_bit[3] = {
560 ICH_PCR, ICH_SCR, ICH_TCR
562 snd_assert(codec < 3, return ICH_PCR);
563 if (chip->device_type == DEVICE_INTEL_ICH4)
564 codec = chip->ac97_sdin[codec];
565 return codec_bit[codec];
568 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
574 if (chip->in_sdin_init) {
575 /* we don't know the ready bit assignment at the moment */
576 /* so we check any */
577 codec = ICH_PCR | ICH_SCR | ICH_TCR;
579 codec = get_ich_codec_bit(chip, codec);
583 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
586 /* Anyone holding a semaphore for 1 msec should be shot... */
589 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
594 /* access to some forbidden (non existant) ac97 registers will not
595 * reset the semaphore. So even if you don't get the semaphore, still
596 * continue the access. We don't need the semaphore anyway. */
597 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
598 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
599 iagetword(chip, 0); /* clear semaphore flag */
600 /* I don't care about the semaphore */
604 static void snd_intel8x0_codec_write(ac97_t *ac97,
608 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
610 spin_lock(&chip->ac97_lock);
611 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
612 if (! chip->in_ac97_init)
613 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
615 iaputword(chip, reg + ac97->num * 0x80, val);
616 spin_unlock(&chip->ac97_lock);
619 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
622 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
626 spin_lock(&chip->ac97_lock);
627 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
628 if (! chip->in_ac97_init)
629 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
632 res = iagetword(chip, reg + ac97->num * 0x80);
633 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
634 /* reset RCS and preserve other R/WC bits */
635 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
636 if (! chip->in_ac97_init)
637 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
641 spin_unlock(&chip->ac97_lock);
646 * access to AC97 for Ali5455
648 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
651 for (count = 0; count < 0x7f; count++) {
652 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
656 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
660 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
663 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
666 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
667 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
670 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
672 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
673 unsigned short data = 0xffff;
675 spin_lock(&chip->ac97_lock);
676 if (snd_intel8x0_ali_codec_semaphore(chip))
678 reg |= ALI_CPR_ADDR_READ;
680 reg |= ALI_CPR_ADDR_SECONDARY;
681 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
682 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
684 data = igetword(chip, ICHREG(ALI_SPR));
686 spin_unlock(&chip->ac97_lock);
690 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
692 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
694 spin_lock(&chip->ac97_lock);
695 if (snd_intel8x0_ali_codec_semaphore(chip)) {
696 spin_unlock(&chip->ac97_lock);
699 iputword(chip, ICHREG(ALI_CPR), val);
701 reg |= ALI_CPR_ADDR_SECONDARY;
702 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
703 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
704 spin_unlock(&chip->ac97_lock);
711 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
714 u32 *bdbar = ichdev->bdbar;
715 unsigned long port = ichdev->reg_offset;
717 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
718 if (ichdev->size == ichdev->fragsize) {
719 ichdev->ack_reload = ichdev->ack = 2;
720 ichdev->fragsize1 = ichdev->fragsize >> 1;
721 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
722 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
723 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
724 ichdev->fragsize1 >> ichdev->pos_shift);
725 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
726 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
727 ichdev->fragsize1 >> ichdev->pos_shift);
731 ichdev->ack_reload = ichdev->ack = 1;
732 ichdev->fragsize1 = ichdev->fragsize;
733 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
734 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
735 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
736 ichdev->fragsize >> ichdev->pos_shift);
737 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
739 ichdev->frags = ichdev->size / ichdev->fragsize;
741 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
743 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
744 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
745 ichdev->position = 0;
747 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
748 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
750 /* clear interrupts */
751 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
756 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
757 * which aborts PCI busmaster for audio transfer. A workaround is to set
758 * the pages as non-cached. For details, see the errata in
759 * http://www.intel.com/design/chipsets/specupdt/245051.htm
761 static void fill_nocache(void *buf, int size, int nocache)
763 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
764 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
768 #define fill_nocache(buf,size,nocache)
775 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
777 unsigned long port = ichdev->reg_offset;
778 int status, civ, i, step;
781 status = igetbyte(chip, port + ichdev->roff_sr);
782 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
783 if (!(status & ICH_BCIS)) {
785 } else if (civ == ichdev->civ) {
786 // snd_printd("civ same %d\n", civ);
789 ichdev->civ &= ICH_REG_LVI_MASK;
791 step = civ - ichdev->civ;
793 step += ICH_REG_LVI_MASK + 1;
795 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
799 ichdev->position += step * ichdev->fragsize1;
800 ichdev->position %= ichdev->size;
802 ichdev->lvi &= ICH_REG_LVI_MASK;
803 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
804 for (i = 0; i < step; i++) {
806 ichdev->lvi_frag %= ichdev->frags;
807 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
808 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
809 if (--ichdev->ack == 0) {
810 ichdev->ack = ichdev->ack_reload;
814 if (ack && ichdev->substream) {
815 spin_unlock(&chip->reg_lock);
816 snd_pcm_period_elapsed(ichdev->substream);
817 spin_lock(&chip->reg_lock);
819 iputbyte(chip, port + ichdev->roff_sr,
820 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
823 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
825 intel8x0_t *chip = snd_magic_cast(intel8x0_t, dev_id, return IRQ_NONE);
830 spin_lock(&chip->reg_lock);
831 status = igetdword(chip, chip->int_sta_reg);
832 if ((status & chip->int_sta_mask) == 0) {
835 iputdword(chip, chip->int_sta_reg, status);
836 /* some Nforce[2] boards have problems when
837 IRQ_NONE is returned here.
839 if (chip->device_type != DEVICE_NFORCE)
842 spin_unlock(&chip->reg_lock);
843 return IRQ_RETVAL(status);
846 for (i = 0; i < chip->bdbars_count; i++) {
847 ichdev = &chip->ichd[i];
848 if (status & ichdev->int_sta_mask)
849 snd_intel8x0_update(chip, ichdev);
853 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
854 spin_unlock(&chip->reg_lock);
863 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
865 intel8x0_t *chip = snd_pcm_substream_chip(substream);
866 ichdev_t *ichdev = get_ichdev(substream);
867 unsigned char val = 0;
868 unsigned long port = ichdev->reg_offset;
871 case SNDRV_PCM_TRIGGER_START:
872 case SNDRV_PCM_TRIGGER_RESUME:
873 val = ICH_IOCE | ICH_STARTBM;
875 case SNDRV_PCM_TRIGGER_STOP:
876 case SNDRV_PCM_TRIGGER_SUSPEND:
879 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
882 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
883 val = ICH_IOCE | ICH_STARTBM;
888 iputbyte(chip, port + ICH_REG_OFF_CR, val);
889 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
890 /* wait until DMA stopped */
891 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
892 /* reset whole DMA things */
893 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
898 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
900 intel8x0_t *chip = snd_pcm_substream_chip(substream);
901 ichdev_t *ichdev = get_ichdev(substream);
902 unsigned long port = ichdev->reg_offset;
903 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
904 unsigned int val, fifo;
906 val = igetdword(chip, ICHREG(ALI_DMACR));
908 case SNDRV_PCM_TRIGGER_START:
909 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
910 case SNDRV_PCM_TRIGGER_RESUME:
911 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
912 /* clear FIFO for synchronization of channels */
913 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
914 fifo &= ~(0xff << (ichdev->ali_slot % 4));
915 fifo |= 0x83 << (ichdev->ali_slot % 4);
916 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
918 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
919 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
920 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
922 case SNDRV_PCM_TRIGGER_STOP:
923 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
924 case SNDRV_PCM_TRIGGER_SUSPEND:
925 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
926 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
927 while (igetbyte(chip, port + ICH_REG_OFF_CR))
929 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
931 /* reset whole DMA things */
932 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
933 /* clear interrupts */
934 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
935 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
936 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
944 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
945 snd_pcm_hw_params_t * hw_params)
947 intel8x0_t *chip = snd_pcm_substream_chip(substream);
948 ichdev_t *ichdev = get_ichdev(substream);
949 snd_pcm_runtime_t *runtime = substream->runtime;
950 size_t size = params_buffer_bytes(hw_params);
953 if (chip->fix_nocache && runtime->dma_area && runtime->dma_bytes < size)
954 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
955 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
958 if (chip->fix_nocache && err > 0)
959 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
960 if (ichdev->pcm_open_flag) {
961 snd_ac97_pcm_close(ichdev->pcm);
962 ichdev->pcm_open_flag = 0;
964 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
965 params_channels(hw_params),
966 ichdev->pcm->r[0].slots);
968 ichdev->pcm_open_flag = 1;
969 /* FIXME: hack to enable spdif support */
970 if (ichdev->ichd == ICHD_PCMOUT && chip->device_type == DEVICE_SIS)
971 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
976 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
978 intel8x0_t *chip = snd_pcm_substream_chip(substream);
979 ichdev_t *ichdev = get_ichdev(substream);
981 if (ichdev->pcm_open_flag) {
982 snd_ac97_pcm_close(ichdev->pcm);
983 ichdev->pcm_open_flag = 0;
985 if (chip->fix_nocache && substream->runtime->dma_area)
986 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
987 return snd_pcm_lib_free_pages(substream);
990 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
991 int channels, int sample_bits)
994 switch (chip->device_type) {
996 cnt = igetdword(chip, ICHREG(ALI_SCR));
997 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
998 if (chip->multi4 && channels == 4)
999 cnt |= ICH_ALI_SC_PCM_4;
1000 else if (chip->multi6 && channels == 6)
1001 cnt |= ICH_ALI_SC_PCM_6;
1002 iputdword(chip, ICHREG(ALI_SCR), cnt);
1005 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1006 cnt &= ~ICH_SIS_PCM_246_MASK;
1007 if (chip->multi4 && channels == 4)
1008 cnt |= ICH_SIS_PCM_4;
1009 else if (chip->multi6 && channels == 6)
1010 cnt |= ICH_SIS_PCM_6;
1011 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1014 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1015 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1016 if (chip->multi4 && channels == 4)
1018 else if (chip->multi6 && channels == 6)
1020 if (chip->device_type == DEVICE_NFORCE) {
1021 /* reset to 2ch once to keep the 6 channel data in alignment,
1022 * to start from Front Left always
1024 iputdword(chip, ICHREG(GLOB_CNT), (cnt & 0xcfffff));
1025 mdelay(50); /* grrr... */
1026 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1027 if (sample_bits > 16)
1028 cnt |= ICH_PCM_20BIT;
1030 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1035 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1037 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1038 snd_pcm_runtime_t *runtime = substream->runtime;
1039 ichdev_t *ichdev = get_ichdev(substream);
1041 ichdev->physbuf = runtime->dma_addr;
1042 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1043 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1044 if (ichdev->ichd == ICHD_PCMOUT) {
1045 spin_lock(&chip->reg_lock);
1046 snd_intel8x0_setup_pcm_out(chip, runtime->channels,
1047 runtime->sample_bits);
1048 spin_unlock(&chip->reg_lock);
1049 if (chip->device_type == DEVICE_INTEL_ICH4) {
1050 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1053 snd_intel8x0_setup_periods(chip, ichdev);
1057 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1059 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1060 ichdev_t *ichdev = get_ichdev(substream);
1061 unsigned long flags;
1064 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
1066 ptr = ichdev->fragsize1 - ptr1;
1069 spin_lock_irqsave(&chip->reg_lock, flags);
1070 ptr += ichdev->position;
1071 spin_unlock_irqrestore(&chip->reg_lock, flags);
1072 if (ptr >= ichdev->size)
1074 return bytes_to_frames(substream->runtime, ptr);
1077 static snd_pcm_hardware_t snd_intel8x0_stream =
1079 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1080 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1081 SNDRV_PCM_INFO_MMAP_VALID |
1082 SNDRV_PCM_INFO_PAUSE |
1083 SNDRV_PCM_INFO_RESUME),
1084 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1085 .rates = SNDRV_PCM_RATE_48000,
1090 .buffer_bytes_max = 128 * 1024,
1091 .period_bytes_min = 32,
1092 .period_bytes_max = 128 * 1024,
1094 .periods_max = 1024,
1098 static unsigned int channels4[] = {
1102 #define CHANNELS4 sizeof(channels4) / sizeof(channels4[0])
1104 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1110 static unsigned int channels6[] = {
1114 #define CHANNELS6 sizeof(channels6) / sizeof(channels6[0])
1116 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1122 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1124 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1125 snd_pcm_runtime_t *runtime = substream->runtime;
1128 ichdev->substream = substream;
1129 runtime->hw = snd_intel8x0_stream;
1130 runtime->hw.rates = ichdev->pcm->rates;
1131 snd_pcm_limit_hw_rates(runtime);
1132 if (chip->device_type == DEVICE_SIS) {
1133 runtime->hw.buffer_bytes_max = 64*1024;
1134 runtime->hw.period_bytes_max = 64*1024;
1136 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1138 runtime->private_data = ichdev;
1142 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1144 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1145 snd_pcm_runtime_t *runtime = substream->runtime;
1148 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1153 runtime->hw.channels_max = 6;
1154 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1155 } else if (chip->multi4) {
1156 runtime->hw.channels_max = 4;
1157 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1160 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1164 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1166 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1168 chip->ichd[ICHD_PCMOUT].substream = NULL;
1172 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1174 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1176 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1179 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1181 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1183 chip->ichd[ICHD_PCMIN].substream = NULL;
1187 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1189 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1191 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1194 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1196 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1198 chip->ichd[ICHD_MIC].substream = NULL;
1202 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1204 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1206 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1209 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1211 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1213 chip->ichd[ICHD_MIC2].substream = NULL;
1217 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1219 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1221 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1224 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1226 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1228 chip->ichd[ICHD_PCM2IN].substream = NULL;
1232 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1234 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1235 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1237 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1240 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1242 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1243 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1245 chip->ichd[idx].substream = NULL;
1249 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1251 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1252 unsigned long flags;
1255 spin_lock_irqsave(&chip->reg_lock, flags);
1256 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1257 val |= ICH_ALI_IF_AC97SP;
1258 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1259 spin_unlock_irqrestore(&chip->reg_lock, flags);
1261 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1264 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1266 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1267 unsigned long flags;
1270 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1271 spin_lock_irqsave(&chip->reg_lock, flags);
1272 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1273 val &= ~ICH_ALI_IF_AC97SP;
1274 spin_unlock_irqrestore(&chip->reg_lock, flags);
1279 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1281 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1283 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1286 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1288 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1290 chip->ichd[ALID_SPDIFIN].substream = NULL;
1295 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1297 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1299 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1302 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1304 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1306 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1311 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1312 .open = snd_intel8x0_playback_open,
1313 .close = snd_intel8x0_playback_close,
1314 .ioctl = snd_pcm_lib_ioctl,
1315 .hw_params = snd_intel8x0_hw_params,
1316 .hw_free = snd_intel8x0_hw_free,
1317 .prepare = snd_intel8x0_pcm_prepare,
1318 .trigger = snd_intel8x0_pcm_trigger,
1319 .pointer = snd_intel8x0_pcm_pointer,
1322 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1323 .open = snd_intel8x0_capture_open,
1324 .close = snd_intel8x0_capture_close,
1325 .ioctl = snd_pcm_lib_ioctl,
1326 .hw_params = snd_intel8x0_hw_params,
1327 .hw_free = snd_intel8x0_hw_free,
1328 .prepare = snd_intel8x0_pcm_prepare,
1329 .trigger = snd_intel8x0_pcm_trigger,
1330 .pointer = snd_intel8x0_pcm_pointer,
1333 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1334 .open = snd_intel8x0_mic_open,
1335 .close = snd_intel8x0_mic_close,
1336 .ioctl = snd_pcm_lib_ioctl,
1337 .hw_params = snd_intel8x0_hw_params,
1338 .hw_free = snd_intel8x0_hw_free,
1339 .prepare = snd_intel8x0_pcm_prepare,
1340 .trigger = snd_intel8x0_pcm_trigger,
1341 .pointer = snd_intel8x0_pcm_pointer,
1344 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1345 .open = snd_intel8x0_mic2_open,
1346 .close = snd_intel8x0_mic2_close,
1347 .ioctl = snd_pcm_lib_ioctl,
1348 .hw_params = snd_intel8x0_hw_params,
1349 .hw_free = snd_intel8x0_hw_free,
1350 .prepare = snd_intel8x0_pcm_prepare,
1351 .trigger = snd_intel8x0_pcm_trigger,
1352 .pointer = snd_intel8x0_pcm_pointer,
1355 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1356 .open = snd_intel8x0_capture2_open,
1357 .close = snd_intel8x0_capture2_close,
1358 .ioctl = snd_pcm_lib_ioctl,
1359 .hw_params = snd_intel8x0_hw_params,
1360 .hw_free = snd_intel8x0_hw_free,
1361 .prepare = snd_intel8x0_pcm_prepare,
1362 .trigger = snd_intel8x0_pcm_trigger,
1363 .pointer = snd_intel8x0_pcm_pointer,
1366 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1367 .open = snd_intel8x0_spdif_open,
1368 .close = snd_intel8x0_spdif_close,
1369 .ioctl = snd_pcm_lib_ioctl,
1370 .hw_params = snd_intel8x0_hw_params,
1371 .hw_free = snd_intel8x0_hw_free,
1372 .prepare = snd_intel8x0_pcm_prepare,
1373 .trigger = snd_intel8x0_pcm_trigger,
1374 .pointer = snd_intel8x0_pcm_pointer,
1377 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1378 .open = snd_intel8x0_playback_open,
1379 .close = snd_intel8x0_playback_close,
1380 .ioctl = snd_pcm_lib_ioctl,
1381 .hw_params = snd_intel8x0_hw_params,
1382 .hw_free = snd_intel8x0_hw_free,
1383 .prepare = snd_intel8x0_pcm_prepare,
1384 .trigger = snd_intel8x0_ali_trigger,
1385 .pointer = snd_intel8x0_pcm_pointer,
1388 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1389 .open = snd_intel8x0_capture_open,
1390 .close = snd_intel8x0_capture_close,
1391 .ioctl = snd_pcm_lib_ioctl,
1392 .hw_params = snd_intel8x0_hw_params,
1393 .hw_free = snd_intel8x0_hw_free,
1394 .prepare = snd_intel8x0_pcm_prepare,
1395 .trigger = snd_intel8x0_ali_trigger,
1396 .pointer = snd_intel8x0_pcm_pointer,
1399 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1400 .open = snd_intel8x0_mic_open,
1401 .close = snd_intel8x0_mic_close,
1402 .ioctl = snd_pcm_lib_ioctl,
1403 .hw_params = snd_intel8x0_hw_params,
1404 .hw_free = snd_intel8x0_hw_free,
1405 .prepare = snd_intel8x0_pcm_prepare,
1406 .trigger = snd_intel8x0_ali_trigger,
1407 .pointer = snd_intel8x0_pcm_pointer,
1410 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1411 .open = snd_intel8x0_ali_ac97spdifout_open,
1412 .close = snd_intel8x0_ali_ac97spdifout_close,
1413 .ioctl = snd_pcm_lib_ioctl,
1414 .hw_params = snd_intel8x0_hw_params,
1415 .hw_free = snd_intel8x0_hw_free,
1416 .prepare = snd_intel8x0_pcm_prepare,
1417 .trigger = snd_intel8x0_ali_trigger,
1418 .pointer = snd_intel8x0_pcm_pointer,
1421 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1422 .open = snd_intel8x0_ali_spdifin_open,
1423 .close = snd_intel8x0_ali_spdifin_close,
1424 .ioctl = snd_pcm_lib_ioctl,
1425 .hw_params = snd_intel8x0_hw_params,
1426 .hw_free = snd_intel8x0_hw_free,
1427 .prepare = snd_intel8x0_pcm_prepare,
1428 .trigger = snd_intel8x0_pcm_trigger,
1429 .pointer = snd_intel8x0_pcm_pointer,
1433 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1434 .open = snd_intel8x0_ali_spdifout_open,
1435 .close = snd_intel8x0_ali_spdifout_close,
1436 .ioctl = snd_pcm_lib_ioctl,
1437 .hw_params = snd_intel8x0_hw_params,
1438 .hw_free = snd_intel8x0_hw_free,
1439 .prepare = snd_intel8x0_pcm_prepare,
1440 .trigger = snd_intel8x0_pcm_trigger,
1441 .pointer = snd_intel8x0_pcm_pointer,
1445 struct ich_pcm_table {
1447 snd_pcm_ops_t *playback_ops;
1448 snd_pcm_ops_t *capture_ops;
1449 size_t prealloc_size;
1450 size_t prealloc_max_size;
1454 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1461 sprintf(name, "Intel ICH - %s", rec->suffix);
1463 strcpy(name, "Intel ICH");
1464 err = snd_pcm_new(chip->card, name, device,
1465 rec->playback_ops ? 1 : 0,
1466 rec->capture_ops ? 1 : 0, &pcm);
1470 if (rec->playback_ops)
1471 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1472 if (rec->capture_ops)
1473 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1475 pcm->private_data = chip;
1476 pcm->info_flags = 0;
1478 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1480 strcpy(pcm->name, chip->card->shortname);
1481 chip->pcm[device] = pcm;
1483 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1484 rec->prealloc_size, rec->prealloc_max_size);
1489 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1491 .playback_ops = &snd_intel8x0_playback_ops,
1492 .capture_ops = &snd_intel8x0_capture_ops,
1493 .prealloc_size = 64 * 1024,
1494 .prealloc_max_size = 128 * 1024,
1497 .suffix = "MIC ADC",
1498 .capture_ops = &snd_intel8x0_capture_mic_ops,
1500 .prealloc_max_size = 128 * 1024,
1501 .ac97_idx = ICHD_MIC,
1504 .suffix = "MIC2 ADC",
1505 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1507 .prealloc_max_size = 128 * 1024,
1508 .ac97_idx = ICHD_MIC2,
1512 .capture_ops = &snd_intel8x0_capture2_ops,
1514 .prealloc_max_size = 128 * 1024,
1515 .ac97_idx = ICHD_PCM2IN,
1519 .playback_ops = &snd_intel8x0_spdif_ops,
1520 .prealloc_size = 64 * 1024,
1521 .prealloc_max_size = 128 * 1024,
1522 .ac97_idx = ICHD_SPBAR,
1526 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1528 .playback_ops = &snd_intel8x0_playback_ops,
1529 .capture_ops = &snd_intel8x0_capture_ops,
1530 .prealloc_size = 64 * 1024,
1531 .prealloc_max_size = 128 * 1024,
1534 .suffix = "MIC ADC",
1535 .capture_ops = &snd_intel8x0_capture_mic_ops,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = NVD_MIC,
1542 .playback_ops = &snd_intel8x0_spdif_ops,
1543 .prealloc_size = 64 * 1024,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = NVD_SPBAR,
1549 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1551 .playback_ops = &snd_intel8x0_ali_playback_ops,
1552 .capture_ops = &snd_intel8x0_ali_capture_ops,
1553 .prealloc_size = 64 * 1024,
1554 .prealloc_max_size = 128 * 1024,
1557 .suffix = "MIC ADC",
1558 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1560 .prealloc_max_size = 128 * 1024,
1561 .ac97_idx = ALID_MIC,
1565 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1566 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1567 .prealloc_size = 64 * 1024,
1568 .prealloc_max_size = 128 * 1024,
1569 .ac97_idx = ALID_AC97SPDIFOUT,
1573 .suffix = "HW IEC958",
1574 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1575 .prealloc_size = 64 * 1024,
1576 .prealloc_max_size = 128 * 1024,
1581 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1583 int i, tblsize, device, err;
1584 struct ich_pcm_table *tbl, *rec;
1586 switch (chip->device_type) {
1587 case DEVICE_INTEL_ICH4:
1589 tblsize = ARRAY_SIZE(intel_pcms);
1593 tblsize = ARRAY_SIZE(nforce_pcms);
1597 tblsize = ARRAY_SIZE(ali_pcms);
1606 for (i = 0; i < tblsize; i++) {
1608 if (i > 0 && rec->ac97_idx) {
1609 /* activate PCM only when associated AC'97 codec */
1610 if (! chip->ichd[rec->ac97_idx].pcm)
1613 err = snd_intel8x0_pcm1(chip, device, rec);
1619 chip->pcm_devs = device;
1628 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1630 intel8x0_t *chip = snd_magic_cast(intel8x0_t, bus->private_data, return);
1631 chip->ac97_bus = NULL;
1634 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1636 intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
1637 chip->ac97[ac97->num] = NULL;
1640 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1645 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1646 (1 << AC97_SLOT_PCM_RIGHT) |
1647 (1 << AC97_SLOT_PCM_CENTER) |
1648 (1 << AC97_SLOT_PCM_SLEFT) |
1649 (1 << AC97_SLOT_PCM_SRIGHT) |
1650 (1 << AC97_SLOT_LFE)
1659 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1660 (1 << AC97_SLOT_PCM_RIGHT)
1669 .slots = (1 << AC97_SLOT_MIC)
1678 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1679 (1 << AC97_SLOT_SPDIF_RIGHT2)
1688 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1689 (1 << AC97_SLOT_PCM_RIGHT)
1698 .slots = (1 << AC97_SLOT_MIC)
1704 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1708 .name = "Compaq Evo D510C",
1709 .type = AC97_TUNE_HP_ONLY
1715 .type = AC97_TUNE_ALC_JACK
1720 .name = "Dell Precision 530", /* AD1885 */
1721 .type = AC97_TUNE_HP_ONLY
1726 .name = "Dell Optiplex GX260", /* AD1981A */
1727 .type = AC97_TUNE_HP_ONLY
1729 { /* FIXME: which codec? */
1732 .name = "Hewlett-Packard onboard",
1733 .type = AC97_TUNE_HP_ONLY
1738 .name = "ASUS ICH5/AD1985",
1739 .type = AC97_TUNE_AD_SHARING
1744 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1745 .type = AC97_TUNE_HP_ONLY
1750 .name = "AMD64 Mobo", /* ALC650 */
1751 .type = AC97_TUNE_HP_ONLY
1756 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1757 .type = AC97_TUNE_HP_ONLY
1762 .name = "ADI AD1985 (discrete)",
1763 .type = AC97_TUNE_HP_ONLY
1768 .name = "MSI P4 ATX 645 Ultra",
1769 .type = AC97_TUNE_HP_ONLY
1774 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1775 .type = AC97_TUNE_HP_ONLY
1781 .name = "Intel ICH5/AD1985",
1782 .type = AC97_TUNE_AD_SHARING
1788 .name = "Intel ICH5/AD1985",
1789 .type = AC97_TUNE_AD_SHARING
1794 .name = "Intel D845WN (82801BA)",
1795 .type = AC97_TUNE_SWAP_HP
1800 .name = "Intel D850EMV2", /* AD1885 */
1801 .type = AC97_TUNE_HP_ONLY
1807 .name = "Intel ICH5/AD1985",
1808 .type = AC97_TUNE_AD_SHARING
1814 .name = "Intel ICH5/AD1985",
1815 .type = AC97_TUNE_AD_SHARING
1817 #if 0 /* FIXME: this seems wrong on most boards */
1822 .name = "Intel ICH5/AD1985",
1823 .type = AC97_TUNE_HP_ONLY
1826 { } /* terminator */
1829 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, int ac97_quirk)
1831 ac97_bus_t bus, *pbus;
1834 unsigned int i, codecs;
1835 unsigned int glob_sta = 0;
1836 int spdif_idx = -1; /* disabled */
1838 switch (chip->device_type) {
1840 spdif_idx = NVD_SPBAR;
1843 spdif_idx = ALID_AC97SPDIFOUT;
1846 if (chip->device_type == DEVICE_INTEL_ICH4)
1847 spdif_idx = ICHD_SPBAR;
1851 chip->in_ac97_init = 1;
1852 memset(&bus, 0, sizeof(bus));
1853 bus.private_data = chip;
1854 bus.private_free = snd_intel8x0_mixer_free_ac97_bus;
1855 if (ac97_clock >= 8000 && ac97_clock <= 48000)
1856 bus.clock = ac97_clock;
1860 memset(&ac97, 0, sizeof(ac97));
1861 ac97.private_data = chip;
1862 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1863 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1864 if (chip->device_type != DEVICE_ALI) {
1865 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1866 bus.write = snd_intel8x0_codec_write;
1867 bus.read = snd_intel8x0_codec_read;
1868 if (chip->device_type == DEVICE_INTEL_ICH4) {
1870 if (glob_sta & ICH_PCR)
1872 if (glob_sta & ICH_SCR)
1874 if (glob_sta & ICH_TCR)
1876 chip->in_sdin_init = 1;
1877 for (i = 0; i < codecs; i++) {
1879 snd_intel8x0_codec_read(&ac97, 0);
1880 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1883 chip->in_sdin_init = 0;
1885 codecs = glob_sta & ICH_SCR ? 2 : 1;
1889 bus.write = snd_intel8x0_ali_codec_write;
1890 bus.read = snd_intel8x0_ali_codec_read;
1892 /* detect the secondary codec */
1893 for (i = 0; i < 100; i++) {
1894 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1899 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
1902 /* FIXME: my test board doens't work well with VRA... */
1905 if ((err = snd_ac97_bus(chip->card, &bus, &pbus)) < 0)
1907 chip->ac97_bus = pbus;
1908 ac97.pci = chip->pci;
1909 for (i = 0; i < codecs; i++) {
1911 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
1913 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
1918 chip->ac97[i] = x97;
1920 /* tune up the primary codec */
1921 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, ac97_quirk);
1922 /* enable separate SDINs for ICH4 */
1923 if (chip->device_type == DEVICE_INTEL_ICH4)
1925 /* find the available PCM streams */
1926 i = ARRAY_SIZE(ac97_pcm_defs);
1927 if (chip->device_type != DEVICE_INTEL_ICH4)
1928 i -= 2; /* do not allocate PCM2IN and MIC2 */
1930 i--; /* do not allocate S/PDIF */
1931 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
1934 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
1935 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
1936 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
1938 chip->ichd[spdif_idx].pcm = &pbus->pcms[3];
1939 if (chip->device_type == DEVICE_INTEL_ICH4) {
1940 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
1941 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
1943 /* enable separate SDINs for ICH4 */
1944 if (chip->device_type == DEVICE_INTEL_ICH4) {
1945 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
1946 u8 tmp = igetbyte(chip, ICHREG(SDM));
1947 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
1949 tmp |= ICH_SE; /* steer enable for multiple SDINs */
1950 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
1951 for (i = 1; i < 4; i++) {
1952 if (pcm->r[0].codec[i]) {
1953 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
1958 tmp &= ~ICH_SE; /* steer disable */
1960 iputbyte(chip, ICHREG(SDM), tmp);
1962 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1964 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
1967 if (chip->device_type == DEVICE_INTEL_ICH4) {
1968 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
1971 if (chip->device_type == DEVICE_NFORCE) {
1973 chip->ichd[spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
1975 chip->in_ac97_init = 0;
1979 /* clear the cold-reset bit for the next chance */
1980 if (chip->device_type != DEVICE_ALI)
1981 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1990 static void do_ali_reset(intel8x0_t *chip)
1992 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
1993 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
1994 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
1995 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
1996 iputdword(chip, ICHREG(ALI_INTERFACECR),
1997 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1998 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
1999 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2002 #define do_delay(chip) do {\
2003 set_current_state(TASK_UNINTERRUPTIBLE);\
2004 schedule_timeout(1);\
2007 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2009 unsigned long end_time;
2010 unsigned int cnt, status, nstatus;
2012 /* put logic to right state */
2013 /* first clear status bits */
2014 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2015 if (chip->device_type == DEVICE_NFORCE)
2016 status |= ICH_NVSPINT;
2017 cnt = igetdword(chip, ICHREG(GLOB_STA));
2018 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2020 /* ACLink on, 2 channels */
2021 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2022 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2023 /* finish cold or do warm reset */
2024 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2025 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2026 end_time = (jiffies + (HZ / 4)) + 1;
2028 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2031 } while (time_after_eq(end_time, jiffies));
2032 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2037 /* wait for any codec ready status.
2038 * Once it becomes ready it should remain ready
2039 * as long as we do not disable the ac97 link.
2041 end_time = jiffies + HZ;
2043 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2047 } while (time_after_eq(end_time, jiffies));
2049 /* no codec is found */
2050 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2054 if (chip->device_type == DEVICE_INTEL_ICH4)
2055 /* ICH4 can have three codecs */
2056 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2058 /* others up to two codecs */
2059 nstatus = ICH_PCR | ICH_SCR;
2061 /* wait for other codecs ready status. */
2062 end_time = jiffies + HZ / 4;
2063 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2065 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2072 for (i = 0; i < 3; i++)
2074 status |= get_ich_codec_bit(chip, i);
2075 /* wait until all the probed codecs are ready */
2076 end_time = jiffies + HZ;
2078 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2079 if (status == nstatus)
2082 } while (time_after_eq(end_time, jiffies));
2085 if (chip->device_type == DEVICE_SIS) {
2086 /* unmute the output on SIS7012 */
2087 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2089 if (chip->device_type == DEVICE_NFORCE) {
2090 /* enable SPDIF interrupt */
2092 pci_read_config_dword(chip->pci, 0x4c, &val);
2094 pci_write_config_dword(chip->pci, 0x4c, val);
2099 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2104 reg = igetdword(chip, ICHREG(ALI_SCR));
2105 if ((reg & 2) == 0) /* Cold required */
2108 reg |= 1; /* Warm */
2109 reg &= ~0x80000000; /* ACLink on */
2110 iputdword(chip, ICHREG(ALI_SCR), reg);
2112 for (i = 0; i < HZ / 2; i++) {
2113 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2117 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2122 for (i = 0; i < HZ / 2; i++) {
2123 reg = igetdword(chip, ICHREG(ALI_RTSR));
2124 if (reg & 0x80) /* primary codec */
2126 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2134 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2139 if (chip->device_type != DEVICE_ALI) {
2140 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2142 iagetword(chip, 0); /* clear semaphore flag */
2144 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2148 /* disable interrupts */
2149 for (i = 0; i < chip->bdbars_count; i++)
2150 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2151 /* reset channels */
2152 for (i = 0; i < chip->bdbars_count; i++)
2153 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2154 /* initialize Buffer Descriptor Lists */
2155 for (i = 0; i < chip->bdbars_count; i++)
2156 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2160 static int snd_intel8x0_free(intel8x0_t *chip)
2166 /* disable interrupts */
2167 for (i = 0; i < chip->bdbars_count; i++)
2168 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2169 /* reset channels */
2170 for (i = 0; i < chip->bdbars_count; i++)
2171 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2172 if (chip->device_type == DEVICE_NFORCE) {
2173 /* stop the spdif interrupt */
2175 pci_read_config_dword(chip->pci, 0x4c, &val);
2177 pci_write_config_dword(chip->pci, 0x4c, val);
2180 synchronize_irq(chip->irq);
2182 if (chip->bdbars.area) {
2183 if (chip->fix_nocache)
2184 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2185 snd_dma_free_pages(&chip->dma_dev, &chip->bdbars);
2187 if (chip->remap_addr)
2188 iounmap((void *) chip->remap_addr);
2189 if (chip->remap_bmaddr)
2190 iounmap((void *) chip->remap_bmaddr);
2192 release_resource(chip->res);
2193 kfree_nocheck(chip->res);
2196 release_resource(chip->res_bm);
2197 kfree_nocheck(chip->res_bm);
2200 free_irq(chip->irq, (void *)chip);
2201 snd_magic_kfree(chip);
2209 static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2211 intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->pm_private_data, return -EINVAL);
2214 for (i = 0; i < chip->pcm_devs; i++)
2215 snd_pcm_suspend_all(chip->pcm[i]);
2216 for (i = 0; i < 3; i++)
2218 snd_ac97_suspend(chip->ac97[i]);
2219 pci_save_state(chip->pci, chip->pci_state);
2220 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2224 static int intel8x0_resume(snd_card_t *card, unsigned int state)
2226 intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->pm_private_data, return -EINVAL);
2229 pci_restore_state(chip->pci, chip->pci_state);
2230 pci_enable_device(chip->pci);
2231 pci_set_master(chip->pci);
2232 snd_intel8x0_chip_init(chip, 0);
2234 /* refill nocache */
2235 if (chip->fix_nocache)
2236 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2238 for (i = 0; i < 3; i++)
2240 snd_ac97_resume(chip->ac97[i]);
2242 /* refill nocache */
2243 if (chip->fix_nocache) {
2244 for (i = 0; i < chip->bdbars_count; i++) {
2245 ichdev_t *ichdev = &chip->ichd[i];
2246 if (ichdev->substream) {
2247 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2248 if (runtime->dma_area)
2249 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2254 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2257 #endif /* CONFIG_PM */
2259 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2261 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2263 snd_pcm_substream_t *subs;
2266 unsigned long pos, t;
2267 unsigned long flags;
2268 struct timeval start_time, stop_time;
2270 if (chip->ac97_bus->clock != 48000)
2271 return; /* specified in module option */
2273 subs = chip->pcm[0]->streams[0].substream;
2274 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2275 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2278 ichdev = &chip->ichd[ICHD_PCMOUT];
2279 ichdev->physbuf = subs->dma_buffer.addr;
2280 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2281 ichdev->substream = NULL; /* don't process interrupts */
2284 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2285 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2288 snd_intel8x0_setup_periods(chip, ichdev);
2289 port = ichdev->reg_offset;
2290 spin_lock_irqsave(&chip->reg_lock, flags);
2292 if (chip->device_type != DEVICE_ALI)
2293 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2295 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2296 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2298 do_gettimeofday(&start_time);
2299 spin_unlock_irqrestore(&chip->reg_lock, flags);
2301 set_current_state(TASK_UNINTERRUPTIBLE);
2302 schedule_timeout(HZ / 20);
2304 /* FIXME: schedule() can take too long time and overlap the boundary.. */
2307 spin_lock_irqsave(&chip->reg_lock, flags);
2308 /* check the position */
2309 pos = ichdev->fragsize1;
2310 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2311 pos += ichdev->position;
2312 do_gettimeofday(&stop_time);
2314 if (chip->device_type == DEVICE_ALI) {
2315 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2316 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2317 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2320 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2321 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2324 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2325 spin_unlock_irqrestore(&chip->reg_lock, flags);
2327 t = stop_time.tv_sec - start_time.tv_sec;
2329 t += stop_time.tv_usec - start_time.tv_usec;
2330 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2332 snd_printk(KERN_ERR "?? calculation error..\n");
2335 pos = (pos / 4) * 1000;
2336 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2337 if (pos < 40000 || pos >= 60000)
2338 /* abnormal value. hw problem? */
2339 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2340 else if (pos < 47500 || pos > 48500)
2341 /* not 48000Hz, tuning the clock.. */
2342 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2343 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2346 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2347 snd_info_buffer_t * buffer)
2349 intel8x0_t *chip = snd_magic_cast(intel8x0_t, entry->private_data, return);
2352 snd_iprintf(buffer, "Intel8x0\n\n");
2353 if (chip->device_type == DEVICE_ALI)
2355 tmp = igetdword(chip, ICHREG(GLOB_STA));
2356 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2357 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2358 if (chip->device_type == DEVICE_INTEL_ICH4)
2359 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2360 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2361 tmp & ICH_PCR ? " primary" : "",
2362 tmp & ICH_SCR ? " secondary" : "",
2363 tmp & ICH_TCR ? " tertiary" : "",
2364 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2365 if (chip->device_type == DEVICE_INTEL_ICH4)
2366 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2369 chip->ac97_sdin[2]);
2372 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2374 snd_info_entry_t *entry;
2376 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2377 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2380 static int snd_intel8x0_dev_free(snd_device_t *device)
2382 intel8x0_t *chip = snd_magic_cast(intel8x0_t, device->device_data, return -ENXIO);
2383 return snd_intel8x0_free(chip);
2386 struct ich_reg_info {
2387 unsigned int int_sta_mask;
2388 unsigned int offset;
2391 static int __devinit snd_intel8x0_create(snd_card_t * card,
2392 struct pci_dev *pci,
2393 unsigned long device_type,
2394 intel8x0_t ** r_intel8x0)
2399 unsigned int int_sta_masks;
2401 static snd_device_ops_t ops = {
2402 .dev_free = snd_intel8x0_dev_free,
2405 static unsigned int bdbars[] = {
2406 3, /* DEVICE_INTEL */
2407 6, /* DEVICE_INTEL_ICH4 */
2410 4, /* DEVICE_NFORCE */
2412 static struct ich_reg_info intel_regs[6] = {
2414 { ICH_POINT, 0x10 },
2415 { ICH_MCINT, 0x20 },
2416 { ICH_M2INT, 0x40 },
2417 { ICH_P2INT, 0x50 },
2418 { ICH_SPINT, 0x60 },
2420 static struct ich_reg_info nforce_regs[4] = {
2422 { ICH_POINT, 0x10 },
2423 { ICH_MCINT, 0x20 },
2424 { ICH_NVSPINT, 0x70 },
2426 static struct ich_reg_info ali_regs[6] = {
2427 { ALI_INT_PCMIN, 0x40 },
2428 { ALI_INT_PCMOUT, 0x50 },
2429 { ALI_INT_MICIN, 0x60 },
2430 { ALI_INT_CODECSPDIFOUT, 0x70 },
2431 { ALI_INT_SPDIFIN, 0xa0 },
2432 { ALI_INT_SPDIFOUT, 0xb0 },
2434 struct ich_reg_info *tbl;
2438 if ((err = pci_enable_device(pci)) < 0)
2441 chip = snd_magic_kcalloc(intel8x0_t, 0, GFP_KERNEL);
2444 spin_lock_init(&chip->reg_lock);
2445 spin_lock_init(&chip->ac97_lock);
2446 chip->device_type = device_type;
2450 snd_intel8x0_proc_init(chip);
2451 sprintf(chip->ac97_name, "%s - AC'97", card->shortname);
2452 sprintf(chip->ctrl_name, "%s - Controller", card->shortname);
2453 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2454 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2455 chip->fix_nocache = 1; /* enable workaround */
2456 if (device_type == DEVICE_ALI) {
2457 /* ALI5455 has no ac97 region */
2458 chip->bmaddr = pci_resource_start(pci, 0);
2459 if ((chip->res_bm = request_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2460 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2461 snd_intel8x0_free(chip);
2467 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2469 chip->addr = pci_resource_start(pci, 2);
2470 if ((chip->res = request_mem_region(chip->addr, 512, chip->ac97_name)) == NULL) {
2471 snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->addr, chip->addr + 512 - 1);
2472 snd_intel8x0_free(chip);
2475 chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr, 512);
2476 if (chip->remap_addr == 0) {
2477 snd_printk("AC'97 space ioremap problem\n");
2478 snd_intel8x0_free(chip);
2482 chip->addr = pci_resource_start(pci, 0);
2483 if ((chip->res = request_region(chip->addr, 256, chip->ac97_name)) == NULL) {
2484 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->addr, chip->addr + 256 - 1);
2485 snd_intel8x0_free(chip);
2489 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2491 chip->bmaddr = pci_resource_start(pci, 3);
2492 if ((chip->res_bm = request_mem_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
2493 snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 512 - 1);
2494 snd_intel8x0_free(chip);
2497 chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr, 256);
2498 if (chip->remap_bmaddr == 0) {
2499 snd_printk("Controller space ioremap problem\n");
2500 snd_intel8x0_free(chip);
2504 chip->bmaddr = pci_resource_start(pci, 1);
2505 if ((chip->res_bm = request_region(chip->bmaddr, 64, chip->ctrl_name)) == NULL) {
2506 snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 64 - 1);
2507 snd_intel8x0_free(chip);
2513 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2514 snd_printk("unable to grab IRQ %d\n", pci->irq);
2515 snd_intel8x0_free(chip);
2518 chip->irq = pci->irq;
2519 pci_set_master(pci);
2520 synchronize_irq(chip->irq);
2522 chip->bdbars_count = bdbars[device_type];
2524 /* initialize offsets */
2525 switch (device_type) {
2536 for (i = 0; i < chip->bdbars_count; i++) {
2537 ichdev = &chip->ichd[i];
2539 ichdev->reg_offset = tbl[i].offset;
2540 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2541 if (device_type == DEVICE_SIS) {
2542 /* SiS 7012 swaps the registers */
2543 ichdev->roff_sr = ICH_REG_OFF_PICB;
2544 ichdev->roff_picb = ICH_REG_OFF_SR;
2546 ichdev->roff_sr = ICH_REG_OFF_SR;
2547 ichdev->roff_picb = ICH_REG_OFF_PICB;
2549 if (device_type == DEVICE_ALI)
2550 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2551 /* SIS7012 handles the pcm data in bytes, others are in samples */
2552 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2555 memset(&chip->dma_dev, 0, sizeof(chip->dma_dev));
2556 chip->dma_dev.type = SNDRV_DMA_TYPE_DEV;
2557 chip->dma_dev.dev = snd_dma_pci_data(pci);
2559 /* allocate buffer descriptor lists */
2560 /* the start of each lists must be aligned to 8 bytes */
2561 if (snd_dma_alloc_pages(&chip->dma_dev, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, &chip->bdbars) < 0) {
2562 snd_intel8x0_free(chip);
2563 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2566 /* tables must be aligned to 8 bytes here, but the kernel pages
2567 are much bigger, so we don't care (on i386) */
2568 /* workaround for 440MX */
2569 if (chip->fix_nocache)
2570 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2572 for (i = 0; i < chip->bdbars_count; i++) {
2573 ichdev = &chip->ichd[i];
2574 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2575 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2576 int_sta_masks |= ichdev->int_sta_mask;
2578 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2579 chip->int_sta_mask = int_sta_masks;
2581 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2582 snd_intel8x0_free(chip);
2586 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2588 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2589 snd_intel8x0_free(chip);
2593 snd_card_set_dev(card, &pci->dev);
2599 static struct shortname_table {
2602 } shortnames[] __devinitdata = {
2603 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2604 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2605 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2606 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2607 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2608 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2609 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2610 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2611 { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2612 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2613 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2614 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2615 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2616 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2617 { 0x746d, "AMD AMD8111" },
2618 { 0x7445, "AMD AMD768" },
2619 { 0x5455, "ALi M5455" },
2623 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2624 const struct pci_device_id *pci_id)
2630 struct shortname_table *name;
2632 if (dev >= SNDRV_CARDS)
2639 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2643 switch (pci_id->driver_data) {
2645 strcpy(card->driver, "NFORCE");
2648 strcpy(card->driver, "ICH");
2652 strcpy(card->shortname, "Intel ICH");
2653 for (name = shortnames; name->id; name++) {
2654 if (pci->device == name->id) {
2655 strcpy(card->shortname, name->s);
2660 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2661 snd_card_free(card);
2665 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2666 snd_card_free(card);
2669 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2670 snd_card_free(card);
2674 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2675 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
2677 -1, 0, &chip->rmidi)) < 0) {
2678 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
2684 sprintf(card->longname, "%s at 0x%lx, irq %i",
2685 card->shortname, chip->addr, chip->irq);
2687 if (! ac97_clock[dev])
2688 intel8x0_measure_ac97_clock(chip);
2690 if ((err = snd_card_register(card)) < 0) {
2691 snd_card_free(card);
2694 pci_set_drvdata(pci, card);
2699 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2701 snd_card_free(pci_get_drvdata(pci));
2702 pci_set_drvdata(pci, NULL);
2705 static struct pci_driver driver = {
2706 .name = "Intel ICH",
2707 .id_table = snd_intel8x0_ids,
2708 .probe = snd_intel8x0_probe,
2709 .remove = __devexit_p(snd_intel8x0_remove),
2710 SND_PCI_PM_CALLBACKS
2714 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2716 * initialize joystick/midi addresses
2719 #ifdef SUPPORT_JOYSTICK
2720 /* there is only one available device, so we keep it here */
2721 static struct pci_dev *ich_gameport_pci;
2722 static struct gameport ich_gameport = { .io = 0x200 };
2725 static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
2726 const struct pci_device_id *id)
2730 if (dev >= SNDRV_CARDS)
2737 pci_read_config_word(pci, 0xe6, &val);
2738 #ifdef SUPPORT_JOYSTICK
2740 if (joystick[dev]) {
2741 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
2742 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
2745 ich_gameport_pci = pci;
2746 gameport_register_port(&ich_gameport);
2753 if (mpu_port[dev] > 0) {
2754 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2757 pci_read_config_byte(pci, 0xe2, &b);
2758 if (mpu_port[dev] == 0x300)
2762 pci_write_config_byte(pci, 0xe2, b);
2766 pci_write_config_word(pci, 0xe6, val);
2770 static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
2773 #ifdef SUPPORT_JOYSTICK
2774 if (ich_gameport_pci == pci) {
2775 gameport_unregister_port(&ich_gameport);
2776 release_region(ich_gameport.io, 8);
2777 ich_gameport_pci = NULL;
2780 /* disable joystick and MIDI */
2781 pci_read_config_word(pci, 0xe6, &val);
2783 pci_write_config_word(pci, 0xe6, val);
2786 static struct pci_device_id snd_intel8x0_joystick_ids[] = {
2787 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
2788 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
2789 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
2790 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
2791 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
2792 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
2793 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
2794 { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
2795 { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
2796 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
2800 static struct pci_driver joystick_driver = {
2801 .name = "Intel ICH Joystick",
2802 .id_table = snd_intel8x0_joystick_ids,
2803 .probe = snd_intel8x0_joystick_probe,
2804 .remove = __devexit_p(snd_intel8x0_joystick_remove),
2807 static int have_joystick;
2810 static int __init alsa_card_intel8x0_init(void)
2814 if ((err = pci_module_init(&driver)) < 0)
2817 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2818 if (pci_module_init(&joystick_driver) < 0) {
2819 snd_printdd(KERN_INFO "no joystick found\n");
2822 snd_printdd(KERN_INFO "joystick(s) found\n");
2830 static void __exit alsa_card_intel8x0_exit(void)
2832 pci_unregister_driver(&driver);
2833 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2835 pci_unregister_driver(&joystick_driver);
2839 module_init(alsa_card_intel8x0_init)
2840 module_exit(alsa_card_intel8x0_exit)