2 * ALSA driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
68 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
69 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
70 static int ac97_quirk[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = AC97_TUNE_DEFAULT};
71 static int buggy_irq[SNDRV_CARDS];
72 static int xbox[SNDRV_CARDS];
75 static int mpu_port[SNDRV_CARDS]; /* disabled */
78 module_param_array(index, int, NULL, 0444);
79 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
80 module_param_array(id, charp, NULL, 0444);
81 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
82 module_param_array(enable, bool, NULL, 0444);
83 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
84 module_param_array(ac97_clock, int, NULL, 0444);
85 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
86 module_param_array(ac97_quirk, int, NULL, 0444);
87 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
88 module_param_array(buggy_irq, bool, NULL, 0444);
89 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
90 module_param_array(xbox, bool, NULL, 0444);
91 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
97 #ifndef PCI_DEVICE_ID_INTEL_82801
98 #define PCI_DEVICE_ID_INTEL_82801 0x2415
100 #ifndef PCI_DEVICE_ID_INTEL_82901
101 #define PCI_DEVICE_ID_INTEL_82901 0x2425
103 #ifndef PCI_DEVICE_ID_INTEL_82801BA
104 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
106 #ifndef PCI_DEVICE_ID_INTEL_440MX
107 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
109 #ifndef PCI_DEVICE_ID_INTEL_ICH3
110 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
112 #ifndef PCI_DEVICE_ID_INTEL_ICH4
113 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
115 #ifndef PCI_DEVICE_ID_INTEL_ICH5
116 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
118 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
119 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
121 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
122 #define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e
124 #ifndef PCI_DEVICE_ID_INTEL_ICH7_20
125 #define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
127 #ifndef PCI_DEVICE_ID_SI_7012
128 #define PCI_DEVICE_ID_SI_7012 0x7012
130 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
131 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
133 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
134 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
136 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
137 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
139 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
140 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
142 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
143 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
145 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
146 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
149 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
151 #define ICHREG(x) ICH_REG_##x
153 #define DEFINE_REGSET(name,base) \
155 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
156 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
157 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
158 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
159 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
160 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
161 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
164 /* busmaster blocks */
165 DEFINE_REGSET(OFF, 0); /* offset */
166 DEFINE_REGSET(PI, 0x00); /* PCM in */
167 DEFINE_REGSET(PO, 0x10); /* PCM out */
168 DEFINE_REGSET(MC, 0x20); /* Mic in */
170 /* ICH4 busmaster blocks */
171 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
172 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
173 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
175 /* values for each busmaster block */
178 #define ICH_REG_LVI_MASK 0x1f
181 #define ICH_FIFOE 0x10 /* FIFO error */
182 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
183 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
184 #define ICH_CELV 0x02 /* current equals last valid */
185 #define ICH_DCH 0x01 /* DMA controller halted */
188 #define ICH_REG_PIV_MASK 0x1f /* mask */
191 #define ICH_IOCE 0x10 /* interrupt on completion enable */
192 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
193 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
194 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
195 #define ICH_STARTBM 0x01 /* start busmaster operation */
199 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
200 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
201 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
202 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
203 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
204 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
205 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
206 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
207 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
208 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
209 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
210 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
211 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
212 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
213 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
214 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
215 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
216 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
217 #define ICH_ACLINK 0x00000008 /* AClink shut off */
218 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
219 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
220 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
221 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
222 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
223 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
224 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
225 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
226 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
227 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
228 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
229 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
230 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
231 #define ICH_MD3 0x00020000 /* modem power down semaphore */
232 #define ICH_AD3 0x00010000 /* audio power down semaphore */
233 #define ICH_RCS 0x00008000 /* read completion status */
234 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
235 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
236 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
237 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
238 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
239 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
240 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
241 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
242 #define ICH_POINT 0x00000040 /* playback interrupt */
243 #define ICH_PIINT 0x00000020 /* capture interrupt */
244 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
245 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
246 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
247 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
248 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
249 #define ICH_CAS 0x01 /* codec access semaphore */
250 #define ICH_REG_SDM 0x80
251 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
252 #define ICH_DI2L_SHIFT 6
253 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
254 #define ICH_DI1L_SHIFT 4
255 #define ICH_SE 0x00000008 /* steer enable */
256 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
258 #define ICH_MAX_FRAGS 32 /* max hw frags */
262 * registers for Ali5455
265 /* ALi 5455 busmaster blocks */
266 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
267 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
268 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
269 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
270 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
271 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
272 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
273 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
274 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
275 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
276 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
279 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
280 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
281 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
282 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
283 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
284 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
285 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
286 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
287 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
288 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
289 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
290 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
291 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
292 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
293 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
294 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
295 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
296 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
297 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
298 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
299 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
302 #define ALI_CAS_SEM_BUSY 0x80000000
303 #define ALI_CPR_ADDR_SECONDARY 0x100
304 #define ALI_CPR_ADDR_READ 0x80
305 #define ALI_CSPSR_CODEC_READY 0x08
306 #define ALI_CSPSR_READ_OK 0x02
307 #define ALI_CSPSR_WRITE_OK 0x01
309 /* interrupts for the whole chip by interrupt status register finish */
311 #define ALI_INT_MICIN2 (1<<26)
312 #define ALI_INT_PCMIN2 (1<<25)
313 #define ALI_INT_I2SIN (1<<24)
314 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
315 #define ALI_INT_SPDIFIN (1<<22)
316 #define ALI_INT_LFEOUT (1<<21)
317 #define ALI_INT_CENTEROUT (1<<20)
318 #define ALI_INT_CODECSPDIFOUT (1<<19)
319 #define ALI_INT_MICIN (1<<18)
320 #define ALI_INT_PCMOUT (1<<17)
321 #define ALI_INT_PCMIN (1<<16)
322 #define ALI_INT_CPRAIS (1<<7) /* command port available */
323 #define ALI_INT_SPRAIS (1<<5) /* status port available */
324 #define ALI_INT_GPIO (1<<1)
325 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
327 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
328 #define ICH_ALI_SC_AC97_DBL (1<<30)
329 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
330 #define ICH_ALI_SC_IN_BITS (3<<18)
331 #define ICH_ALI_SC_OUT_BITS (3<<16)
332 #define ICH_ALI_SC_6CH_CFG (3<<14)
333 #define ICH_ALI_SC_PCM_4 (1<<8)
334 #define ICH_ALI_SC_PCM_6 (2<<8)
335 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
337 #define ICH_ALI_SS_SEC_ID (3<<5)
338 #define ICH_ALI_SS_PRI_ID (3<<3)
340 #define ICH_ALI_IF_AC97SP (1<<21)
341 #define ICH_ALI_IF_MC (1<<20)
342 #define ICH_ALI_IF_PI (1<<19)
343 #define ICH_ALI_IF_MC2 (1<<18)
344 #define ICH_ALI_IF_PI2 (1<<17)
345 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
346 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
347 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
348 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
349 #define ICH_ALI_IF_PO_SPDF (1<<3)
350 #define ICH_ALI_IF_PO (1<<1)
356 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
357 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
358 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
360 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
363 unsigned int ichd; /* ich device number */
364 unsigned long reg_offset; /* offset to bmaddr */
365 u32 *bdbar; /* CPU address (32bit) */
366 unsigned int bdbar_addr; /* PCI bus address (32bit) */
367 snd_pcm_substream_t *substream;
368 unsigned int physbuf; /* physical address (32bit) */
370 unsigned int fragsize;
371 unsigned int fragsize1;
372 unsigned int position;
373 unsigned int pos_shift;
380 unsigned int ack_bit;
381 unsigned int roff_sr;
382 unsigned int roff_picb;
383 unsigned int int_sta_mask; /* interrupt status mask */
384 unsigned int ali_slot; /* ALI DMA slot */
385 struct ac97_pcm *pcm;
387 unsigned int page_attr_changed: 1;
390 typedef struct _snd_intel8x0 intel8x0_t;
392 struct _snd_intel8x0 {
393 unsigned int device_type;
399 void __iomem *remap_addr;
400 unsigned int bm_mmio;
401 unsigned long bmaddr;
402 void __iomem *remap_bmaddr;
415 unsigned in_ac97_init: 1,
417 unsigned in_measurement: 1; /* during ac97 clock measurement */
418 unsigned fix_nocache: 1; /* workaround for 440MX */
419 unsigned buggy_irq: 1; /* workaround for buggy mobos */
420 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
422 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
424 ac97_bus_t *ac97_bus;
426 unsigned int ac97_sdin[3];
429 spinlock_t ac97_lock;
432 struct snd_dma_buffer bdbars;
433 u32 int_sta_reg; /* interrupt status register */
434 u32 int_sta_mask; /* interrupt status mask */
437 static struct pci_device_id snd_intel8x0_ids[] = {
438 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
439 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
440 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
441 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
442 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
443 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
444 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
445 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
446 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
447 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
448 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
449 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
450 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
451 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
452 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
453 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
454 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
455 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
456 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
457 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
458 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
462 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
465 * Lowlevel I/O - busmaster
468 static u8 igetbyte(intel8x0_t *chip, u32 offset)
471 return readb(chip->remap_bmaddr + offset);
473 return inb(chip->bmaddr + offset);
476 static u16 igetword(intel8x0_t *chip, u32 offset)
479 return readw(chip->remap_bmaddr + offset);
481 return inw(chip->bmaddr + offset);
484 static u32 igetdword(intel8x0_t *chip, u32 offset)
487 return readl(chip->remap_bmaddr + offset);
489 return inl(chip->bmaddr + offset);
492 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
495 writeb(val, chip->remap_bmaddr + offset);
497 outb(val, chip->bmaddr + offset);
500 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
503 writew(val, chip->remap_bmaddr + offset);
505 outw(val, chip->bmaddr + offset);
508 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
511 writel(val, chip->remap_bmaddr + offset);
513 outl(val, chip->bmaddr + offset);
517 * Lowlevel I/O - AC'97 registers
520 static u16 iagetword(intel8x0_t *chip, u32 offset)
523 return readw(chip->remap_addr + offset);
525 return inw(chip->addr + offset);
528 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
531 writew(val, chip->remap_addr + offset);
533 outw(val, chip->addr + offset);
541 * access to AC97 codec via normal i/o (for ICH and SIS7012)
544 /* return the GLOB_STA bit for the corresponding codec */
545 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
547 static unsigned int codec_bit[3] = {
548 ICH_PCR, ICH_SCR, ICH_TCR
550 snd_assert(codec < 3, return ICH_PCR);
551 if (chip->device_type == DEVICE_INTEL_ICH4)
552 codec = chip->ac97_sdin[codec];
553 return codec_bit[codec];
556 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
562 if (chip->in_sdin_init) {
563 /* we don't know the ready bit assignment at the moment */
564 /* so we check any */
565 codec = ICH_PCR | ICH_SCR | ICH_TCR;
567 codec = get_ich_codec_bit(chip, codec);
571 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
574 /* Anyone holding a semaphore for 1 msec should be shot... */
577 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
582 /* access to some forbidden (non existant) ac97 registers will not
583 * reset the semaphore. So even if you don't get the semaphore, still
584 * continue the access. We don't need the semaphore anyway. */
585 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
586 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
587 iagetword(chip, 0); /* clear semaphore flag */
588 /* I don't care about the semaphore */
592 static void snd_intel8x0_codec_write(ac97_t *ac97,
596 intel8x0_t *chip = ac97->private_data;
598 spin_lock(&chip->ac97_lock);
599 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
600 if (! chip->in_ac97_init)
601 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
603 iaputword(chip, reg + ac97->num * 0x80, val);
604 spin_unlock(&chip->ac97_lock);
607 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
610 intel8x0_t *chip = ac97->private_data;
614 spin_lock(&chip->ac97_lock);
615 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
616 if (! chip->in_ac97_init)
617 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
620 res = iagetword(chip, reg + ac97->num * 0x80);
621 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
622 /* reset RCS and preserve other R/WC bits */
623 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
624 if (! chip->in_ac97_init)
625 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
629 spin_unlock(&chip->ac97_lock);
633 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
637 spin_lock(&chip->ac97_lock);
638 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
639 iagetword(chip, codec * 0x80);
640 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
641 /* reset RCS and preserve other R/WC bits */
642 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
645 spin_unlock(&chip->ac97_lock);
649 * access to AC97 for Ali5455
651 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
654 for (count = 0; count < 0x7f; count++) {
655 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
659 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
663 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
666 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
669 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
670 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
673 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
675 intel8x0_t *chip = ac97->private_data;
676 unsigned short data = 0xffff;
678 spin_lock(&chip->ac97_lock);
679 if (snd_intel8x0_ali_codec_semaphore(chip))
681 reg |= ALI_CPR_ADDR_READ;
683 reg |= ALI_CPR_ADDR_SECONDARY;
684 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
685 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
687 data = igetword(chip, ICHREG(ALI_SPR));
689 spin_unlock(&chip->ac97_lock);
693 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
695 intel8x0_t *chip = ac97->private_data;
697 spin_lock(&chip->ac97_lock);
698 if (snd_intel8x0_ali_codec_semaphore(chip)) {
699 spin_unlock(&chip->ac97_lock);
702 iputword(chip, ICHREG(ALI_CPR), val);
704 reg |= ALI_CPR_ADDR_SECONDARY;
705 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
706 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
707 spin_unlock(&chip->ac97_lock);
714 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
717 u32 *bdbar = ichdev->bdbar;
718 unsigned long port = ichdev->reg_offset;
720 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
721 if (ichdev->size == ichdev->fragsize) {
722 ichdev->ack_reload = ichdev->ack = 2;
723 ichdev->fragsize1 = ichdev->fragsize >> 1;
724 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
725 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
726 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
727 ichdev->fragsize1 >> ichdev->pos_shift);
728 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
729 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
730 ichdev->fragsize1 >> ichdev->pos_shift);
734 ichdev->ack_reload = ichdev->ack = 1;
735 ichdev->fragsize1 = ichdev->fragsize;
736 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
737 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
738 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
739 ichdev->fragsize >> ichdev->pos_shift);
740 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
742 ichdev->frags = ichdev->size / ichdev->fragsize;
744 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
746 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
747 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
748 ichdev->position = 0;
750 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
751 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
753 /* clear interrupts */
754 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
759 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
760 * which aborts PCI busmaster for audio transfer. A workaround is to set
761 * the pages as non-cached. For details, see the errata in
762 * http://www.intel.com/design/chipsets/specupdt/245051.htm
764 static void fill_nocache(void *buf, int size, int nocache)
766 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
767 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
771 #define fill_nocache(buf,size,nocache)
778 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
780 unsigned long port = ichdev->reg_offset;
781 int status, civ, i, step;
784 spin_lock(&chip->reg_lock);
785 status = igetbyte(chip, port + ichdev->roff_sr);
786 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
787 if (!(status & ICH_BCIS)) {
789 } else if (civ == ichdev->civ) {
790 // snd_printd("civ same %d\n", civ);
793 ichdev->civ &= ICH_REG_LVI_MASK;
795 step = civ - ichdev->civ;
797 step += ICH_REG_LVI_MASK + 1;
799 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
803 ichdev->position += step * ichdev->fragsize1;
804 if (! chip->in_measurement)
805 ichdev->position %= ichdev->size;
807 ichdev->lvi &= ICH_REG_LVI_MASK;
808 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
809 for (i = 0; i < step; i++) {
811 ichdev->lvi_frag %= ichdev->frags;
812 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
813 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
814 if (--ichdev->ack == 0) {
815 ichdev->ack = ichdev->ack_reload;
819 spin_unlock(&chip->reg_lock);
820 if (ack && ichdev->substream) {
821 snd_pcm_period_elapsed(ichdev->substream);
823 iputbyte(chip, port + ichdev->roff_sr,
824 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
827 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
829 intel8x0_t *chip = dev_id;
834 status = igetdword(chip, chip->int_sta_reg);
835 if (status == 0xffffffff) /* we are not yet resumed */
838 if ((status & chip->int_sta_mask) == 0) {
841 iputdword(chip, chip->int_sta_reg, status);
842 if (! chip->buggy_irq)
845 return IRQ_RETVAL(status);
848 for (i = 0; i < chip->bdbars_count; i++) {
849 ichdev = &chip->ichd[i];
850 if (status & ichdev->int_sta_mask)
851 snd_intel8x0_update(chip, ichdev);
855 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
864 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
866 intel8x0_t *chip = snd_pcm_substream_chip(substream);
867 ichdev_t *ichdev = get_ichdev(substream);
868 unsigned char val = 0;
869 unsigned long port = ichdev->reg_offset;
872 case SNDRV_PCM_TRIGGER_START:
873 case SNDRV_PCM_TRIGGER_RESUME:
874 val = ICH_IOCE | ICH_STARTBM;
876 case SNDRV_PCM_TRIGGER_STOP:
877 case SNDRV_PCM_TRIGGER_SUSPEND:
880 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
883 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
884 val = ICH_IOCE | ICH_STARTBM;
889 iputbyte(chip, port + ICH_REG_OFF_CR, val);
890 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
891 /* wait until DMA stopped */
892 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
893 /* reset whole DMA things */
894 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
899 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
901 intel8x0_t *chip = snd_pcm_substream_chip(substream);
902 ichdev_t *ichdev = get_ichdev(substream);
903 unsigned long port = ichdev->reg_offset;
904 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
905 unsigned int val, fifo;
907 val = igetdword(chip, ICHREG(ALI_DMACR));
909 case SNDRV_PCM_TRIGGER_START:
910 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
911 case SNDRV_PCM_TRIGGER_RESUME:
912 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
913 /* clear FIFO for synchronization of channels */
914 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
915 fifo &= ~(0xff << (ichdev->ali_slot % 4));
916 fifo |= 0x83 << (ichdev->ali_slot % 4);
917 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
919 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
920 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
921 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
923 case SNDRV_PCM_TRIGGER_STOP:
924 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
925 case SNDRV_PCM_TRIGGER_SUSPEND:
926 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
927 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
928 while (igetbyte(chip, port + ICH_REG_OFF_CR))
930 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
932 /* reset whole DMA things */
933 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
934 /* clear interrupts */
935 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
936 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
937 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
945 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
946 snd_pcm_hw_params_t * hw_params)
948 intel8x0_t *chip = snd_pcm_substream_chip(substream);
949 ichdev_t *ichdev = get_ichdev(substream);
950 snd_pcm_runtime_t *runtime = substream->runtime;
951 size_t size = params_buffer_bytes(hw_params);
952 int dbl = params_rate(hw_params) > 48000;
955 if (chip->fix_nocache && ichdev->page_attr_changed) {
956 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
957 ichdev->page_attr_changed = 0;
959 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
962 if (chip->fix_nocache) {
963 if (runtime->dma_area && ! ichdev->page_attr_changed) {
964 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
965 ichdev->page_attr_changed = 1;
968 if (ichdev->pcm_open_flag) {
969 snd_ac97_pcm_close(ichdev->pcm);
970 ichdev->pcm_open_flag = 0;
972 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
973 params_channels(hw_params),
974 ichdev->pcm->r[dbl].slots);
976 ichdev->pcm_open_flag = 1;
977 /* Force SPDIF setting */
978 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
979 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
984 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
986 intel8x0_t *chip = snd_pcm_substream_chip(substream);
987 ichdev_t *ichdev = get_ichdev(substream);
989 if (ichdev->pcm_open_flag) {
990 snd_ac97_pcm_close(ichdev->pcm);
991 ichdev->pcm_open_flag = 0;
993 if (chip->fix_nocache && ichdev->page_attr_changed) {
994 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
995 ichdev->page_attr_changed = 0;
997 return snd_pcm_lib_free_pages(substream);
1000 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
1001 snd_pcm_runtime_t *runtime)
1004 int dbl = runtime->rate > 48000;
1005 switch (chip->device_type) {
1007 cnt = igetdword(chip, ICHREG(ALI_SCR));
1008 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1009 if (runtime->channels == 4 || dbl)
1010 cnt |= ICH_ALI_SC_PCM_4;
1011 else if (runtime->channels == 6)
1012 cnt |= ICH_ALI_SC_PCM_6;
1013 iputdword(chip, ICHREG(ALI_SCR), cnt);
1016 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1017 cnt &= ~ICH_SIS_PCM_246_MASK;
1018 if (runtime->channels == 4 || dbl)
1019 cnt |= ICH_SIS_PCM_4;
1020 else if (runtime->channels == 6)
1021 cnt |= ICH_SIS_PCM_6;
1022 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1025 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1026 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1027 if (runtime->channels == 4 || dbl)
1029 else if (runtime->channels == 6)
1031 if (chip->device_type == DEVICE_NFORCE) {
1032 /* reset to 2ch once to keep the 6 channel data in alignment,
1033 * to start from Front Left always
1035 if (cnt & ICH_PCM_246_MASK) {
1036 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1037 spin_unlock_irq(&chip->reg_lock);
1038 msleep(50); /* grrr... */
1039 spin_lock_irq(&chip->reg_lock);
1041 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1042 if (runtime->sample_bits > 16)
1043 cnt |= ICH_PCM_20BIT;
1045 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1050 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1052 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1053 snd_pcm_runtime_t *runtime = substream->runtime;
1054 ichdev_t *ichdev = get_ichdev(substream);
1056 ichdev->physbuf = runtime->dma_addr;
1057 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1058 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1059 spin_lock_irq(&chip->reg_lock);
1060 if (ichdev->ichd == ICHD_PCMOUT) {
1061 snd_intel8x0_setup_pcm_out(chip, runtime);
1062 if (chip->device_type == DEVICE_INTEL_ICH4) {
1063 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1066 snd_intel8x0_setup_periods(chip, ichdev);
1067 spin_unlock_irq(&chip->reg_lock);
1071 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1073 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1074 ichdev_t *ichdev = get_ichdev(substream);
1076 int civ, timeout = 10;
1077 unsigned int position;
1079 spin_lock(&chip->reg_lock);
1081 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1082 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1083 position = ichdev->position;
1086 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1087 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1089 } while (timeout--);
1090 ptr1 <<= ichdev->pos_shift;
1091 ptr = ichdev->fragsize1 - ptr1;
1093 spin_unlock(&chip->reg_lock);
1094 if (ptr >= ichdev->size)
1096 return bytes_to_frames(substream->runtime, ptr);
1099 static snd_pcm_hardware_t snd_intel8x0_stream =
1101 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1102 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1103 SNDRV_PCM_INFO_MMAP_VALID |
1104 SNDRV_PCM_INFO_PAUSE |
1105 SNDRV_PCM_INFO_RESUME),
1106 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1107 .rates = SNDRV_PCM_RATE_48000,
1112 .buffer_bytes_max = 128 * 1024,
1113 .period_bytes_min = 32,
1114 .period_bytes_max = 128 * 1024,
1116 .periods_max = 1024,
1120 static unsigned int channels4[] = {
1124 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1125 .count = ARRAY_SIZE(channels4),
1130 static unsigned int channels6[] = {
1134 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1135 .count = ARRAY_SIZE(channels6),
1140 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1142 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1143 snd_pcm_runtime_t *runtime = substream->runtime;
1146 ichdev->substream = substream;
1147 runtime->hw = snd_intel8x0_stream;
1148 runtime->hw.rates = ichdev->pcm->rates;
1149 snd_pcm_limit_hw_rates(runtime);
1150 if (chip->device_type == DEVICE_SIS) {
1151 runtime->hw.buffer_bytes_max = 64*1024;
1152 runtime->hw.period_bytes_max = 64*1024;
1154 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1156 runtime->private_data = ichdev;
1160 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1162 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1163 snd_pcm_runtime_t *runtime = substream->runtime;
1166 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1171 runtime->hw.channels_max = 6;
1172 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1173 } else if (chip->multi4) {
1174 runtime->hw.channels_max = 4;
1175 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1178 snd_ac97_pcm_double_rate_rules(runtime);
1180 if (chip->smp20bit) {
1181 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1182 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1187 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1189 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1191 chip->ichd[ICHD_PCMOUT].substream = NULL;
1195 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1197 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1199 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1202 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1204 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1206 chip->ichd[ICHD_PCMIN].substream = NULL;
1210 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1212 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1217 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1219 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1221 chip->ichd[ICHD_MIC].substream = NULL;
1225 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1227 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1229 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1232 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1234 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1236 chip->ichd[ICHD_MIC2].substream = NULL;
1240 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1242 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1244 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1247 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1249 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1251 chip->ichd[ICHD_PCM2IN].substream = NULL;
1255 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1257 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1258 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1260 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1263 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1265 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1266 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1268 chip->ichd[idx].substream = NULL;
1272 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1274 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1277 spin_lock_irq(&chip->reg_lock);
1278 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1279 val |= ICH_ALI_IF_AC97SP;
1280 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1281 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1282 spin_unlock_irq(&chip->reg_lock);
1284 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1287 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1289 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1292 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1293 spin_lock_irq(&chip->reg_lock);
1294 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1295 val &= ~ICH_ALI_IF_AC97SP;
1296 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1297 spin_unlock_irq(&chip->reg_lock);
1302 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1304 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1306 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1309 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1311 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1313 chip->ichd[ALID_SPDIFIN].substream = NULL;
1318 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1320 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1322 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1325 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1327 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1329 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1334 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1335 .open = snd_intel8x0_playback_open,
1336 .close = snd_intel8x0_playback_close,
1337 .ioctl = snd_pcm_lib_ioctl,
1338 .hw_params = snd_intel8x0_hw_params,
1339 .hw_free = snd_intel8x0_hw_free,
1340 .prepare = snd_intel8x0_pcm_prepare,
1341 .trigger = snd_intel8x0_pcm_trigger,
1342 .pointer = snd_intel8x0_pcm_pointer,
1345 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1346 .open = snd_intel8x0_capture_open,
1347 .close = snd_intel8x0_capture_close,
1348 .ioctl = snd_pcm_lib_ioctl,
1349 .hw_params = snd_intel8x0_hw_params,
1350 .hw_free = snd_intel8x0_hw_free,
1351 .prepare = snd_intel8x0_pcm_prepare,
1352 .trigger = snd_intel8x0_pcm_trigger,
1353 .pointer = snd_intel8x0_pcm_pointer,
1356 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1357 .open = snd_intel8x0_mic_open,
1358 .close = snd_intel8x0_mic_close,
1359 .ioctl = snd_pcm_lib_ioctl,
1360 .hw_params = snd_intel8x0_hw_params,
1361 .hw_free = snd_intel8x0_hw_free,
1362 .prepare = snd_intel8x0_pcm_prepare,
1363 .trigger = snd_intel8x0_pcm_trigger,
1364 .pointer = snd_intel8x0_pcm_pointer,
1367 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1368 .open = snd_intel8x0_mic2_open,
1369 .close = snd_intel8x0_mic2_close,
1370 .ioctl = snd_pcm_lib_ioctl,
1371 .hw_params = snd_intel8x0_hw_params,
1372 .hw_free = snd_intel8x0_hw_free,
1373 .prepare = snd_intel8x0_pcm_prepare,
1374 .trigger = snd_intel8x0_pcm_trigger,
1375 .pointer = snd_intel8x0_pcm_pointer,
1378 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1379 .open = snd_intel8x0_capture2_open,
1380 .close = snd_intel8x0_capture2_close,
1381 .ioctl = snd_pcm_lib_ioctl,
1382 .hw_params = snd_intel8x0_hw_params,
1383 .hw_free = snd_intel8x0_hw_free,
1384 .prepare = snd_intel8x0_pcm_prepare,
1385 .trigger = snd_intel8x0_pcm_trigger,
1386 .pointer = snd_intel8x0_pcm_pointer,
1389 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1390 .open = snd_intel8x0_spdif_open,
1391 .close = snd_intel8x0_spdif_close,
1392 .ioctl = snd_pcm_lib_ioctl,
1393 .hw_params = snd_intel8x0_hw_params,
1394 .hw_free = snd_intel8x0_hw_free,
1395 .prepare = snd_intel8x0_pcm_prepare,
1396 .trigger = snd_intel8x0_pcm_trigger,
1397 .pointer = snd_intel8x0_pcm_pointer,
1400 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1401 .open = snd_intel8x0_playback_open,
1402 .close = snd_intel8x0_playback_close,
1403 .ioctl = snd_pcm_lib_ioctl,
1404 .hw_params = snd_intel8x0_hw_params,
1405 .hw_free = snd_intel8x0_hw_free,
1406 .prepare = snd_intel8x0_pcm_prepare,
1407 .trigger = snd_intel8x0_ali_trigger,
1408 .pointer = snd_intel8x0_pcm_pointer,
1411 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1412 .open = snd_intel8x0_capture_open,
1413 .close = snd_intel8x0_capture_close,
1414 .ioctl = snd_pcm_lib_ioctl,
1415 .hw_params = snd_intel8x0_hw_params,
1416 .hw_free = snd_intel8x0_hw_free,
1417 .prepare = snd_intel8x0_pcm_prepare,
1418 .trigger = snd_intel8x0_ali_trigger,
1419 .pointer = snd_intel8x0_pcm_pointer,
1422 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1423 .open = snd_intel8x0_mic_open,
1424 .close = snd_intel8x0_mic_close,
1425 .ioctl = snd_pcm_lib_ioctl,
1426 .hw_params = snd_intel8x0_hw_params,
1427 .hw_free = snd_intel8x0_hw_free,
1428 .prepare = snd_intel8x0_pcm_prepare,
1429 .trigger = snd_intel8x0_ali_trigger,
1430 .pointer = snd_intel8x0_pcm_pointer,
1433 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1434 .open = snd_intel8x0_ali_ac97spdifout_open,
1435 .close = snd_intel8x0_ali_ac97spdifout_close,
1436 .ioctl = snd_pcm_lib_ioctl,
1437 .hw_params = snd_intel8x0_hw_params,
1438 .hw_free = snd_intel8x0_hw_free,
1439 .prepare = snd_intel8x0_pcm_prepare,
1440 .trigger = snd_intel8x0_ali_trigger,
1441 .pointer = snd_intel8x0_pcm_pointer,
1444 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1445 .open = snd_intel8x0_ali_spdifin_open,
1446 .close = snd_intel8x0_ali_spdifin_close,
1447 .ioctl = snd_pcm_lib_ioctl,
1448 .hw_params = snd_intel8x0_hw_params,
1449 .hw_free = snd_intel8x0_hw_free,
1450 .prepare = snd_intel8x0_pcm_prepare,
1451 .trigger = snd_intel8x0_pcm_trigger,
1452 .pointer = snd_intel8x0_pcm_pointer,
1456 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1457 .open = snd_intel8x0_ali_spdifout_open,
1458 .close = snd_intel8x0_ali_spdifout_close,
1459 .ioctl = snd_pcm_lib_ioctl,
1460 .hw_params = snd_intel8x0_hw_params,
1461 .hw_free = snd_intel8x0_hw_free,
1462 .prepare = snd_intel8x0_pcm_prepare,
1463 .trigger = snd_intel8x0_pcm_trigger,
1464 .pointer = snd_intel8x0_pcm_pointer,
1468 struct ich_pcm_table {
1470 snd_pcm_ops_t *playback_ops;
1471 snd_pcm_ops_t *capture_ops;
1472 size_t prealloc_size;
1473 size_t prealloc_max_size;
1477 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1484 sprintf(name, "Intel ICH - %s", rec->suffix);
1486 strcpy(name, "Intel ICH");
1487 err = snd_pcm_new(chip->card, name, device,
1488 rec->playback_ops ? 1 : 0,
1489 rec->capture_ops ? 1 : 0, &pcm);
1493 if (rec->playback_ops)
1494 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1495 if (rec->capture_ops)
1496 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1498 pcm->private_data = chip;
1499 pcm->info_flags = 0;
1501 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1503 strcpy(pcm->name, chip->card->shortname);
1504 chip->pcm[device] = pcm;
1506 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1507 rec->prealloc_size, rec->prealloc_max_size);
1512 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1514 .playback_ops = &snd_intel8x0_playback_ops,
1515 .capture_ops = &snd_intel8x0_capture_ops,
1516 .prealloc_size = 64 * 1024,
1517 .prealloc_max_size = 128 * 1024,
1520 .suffix = "MIC ADC",
1521 .capture_ops = &snd_intel8x0_capture_mic_ops,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = ICHD_MIC,
1527 .suffix = "MIC2 ADC",
1528 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1530 .prealloc_max_size = 128 * 1024,
1531 .ac97_idx = ICHD_MIC2,
1535 .capture_ops = &snd_intel8x0_capture2_ops,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ICHD_PCM2IN,
1542 .playback_ops = &snd_intel8x0_spdif_ops,
1543 .prealloc_size = 64 * 1024,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = ICHD_SPBAR,
1549 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1551 .playback_ops = &snd_intel8x0_playback_ops,
1552 .capture_ops = &snd_intel8x0_capture_ops,
1553 .prealloc_size = 64 * 1024,
1554 .prealloc_max_size = 128 * 1024,
1557 .suffix = "MIC ADC",
1558 .capture_ops = &snd_intel8x0_capture_mic_ops,
1560 .prealloc_max_size = 128 * 1024,
1561 .ac97_idx = NVD_MIC,
1565 .playback_ops = &snd_intel8x0_spdif_ops,
1566 .prealloc_size = 64 * 1024,
1567 .prealloc_max_size = 128 * 1024,
1568 .ac97_idx = NVD_SPBAR,
1572 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1574 .playback_ops = &snd_intel8x0_ali_playback_ops,
1575 .capture_ops = &snd_intel8x0_ali_capture_ops,
1576 .prealloc_size = 64 * 1024,
1577 .prealloc_max_size = 128 * 1024,
1580 .suffix = "MIC ADC",
1581 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1583 .prealloc_max_size = 128 * 1024,
1584 .ac97_idx = ALID_MIC,
1588 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1589 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1590 .prealloc_size = 64 * 1024,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = ALID_AC97SPDIFOUT,
1596 .suffix = "HW IEC958",
1597 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1598 .prealloc_size = 64 * 1024,
1599 .prealloc_max_size = 128 * 1024,
1604 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1606 int i, tblsize, device, err;
1607 struct ich_pcm_table *tbl, *rec;
1609 switch (chip->device_type) {
1610 case DEVICE_INTEL_ICH4:
1612 tblsize = ARRAY_SIZE(intel_pcms);
1616 tblsize = ARRAY_SIZE(nforce_pcms);
1620 tblsize = ARRAY_SIZE(ali_pcms);
1629 for (i = 0; i < tblsize; i++) {
1631 if (i > 0 && rec->ac97_idx) {
1632 /* activate PCM only when associated AC'97 codec */
1633 if (! chip->ichd[rec->ac97_idx].pcm)
1636 err = snd_intel8x0_pcm1(chip, device, rec);
1642 chip->pcm_devs = device;
1651 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1653 intel8x0_t *chip = bus->private_data;
1654 chip->ac97_bus = NULL;
1657 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1659 intel8x0_t *chip = ac97->private_data;
1660 chip->ac97[ac97->num] = NULL;
1663 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1668 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1669 (1 << AC97_SLOT_PCM_RIGHT) |
1670 (1 << AC97_SLOT_PCM_CENTER) |
1671 (1 << AC97_SLOT_PCM_SLEFT) |
1672 (1 << AC97_SLOT_PCM_SRIGHT) |
1673 (1 << AC97_SLOT_LFE)
1676 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1677 (1 << AC97_SLOT_PCM_RIGHT) |
1678 (1 << AC97_SLOT_PCM_LEFT_0) |
1679 (1 << AC97_SLOT_PCM_RIGHT_0)
1688 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1689 (1 << AC97_SLOT_PCM_RIGHT)
1698 .slots = (1 << AC97_SLOT_MIC)
1707 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1708 (1 << AC97_SLOT_SPDIF_RIGHT2)
1717 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1718 (1 << AC97_SLOT_PCM_RIGHT)
1727 .slots = (1 << AC97_SLOT_MIC)
1733 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1737 .name = "Compaq Evo W4000", /* AD1885 */
1738 .type = AC97_TUNE_HP_ONLY
1743 .name = "Compaq Evo D510C",
1744 .type = AC97_TUNE_HP_ONLY
1750 .type = AC97_TUNE_ALC_JACK
1755 .name = "Dell Precision 530", /* AD1885 */
1756 .type = AC97_TUNE_HP_ONLY
1761 .name = "Dell", /* which model? AD1885 */
1762 .type = AC97_TUNE_HP_ONLY
1767 .name = "Dell Optiplex GX260", /* AD1981A */
1768 .type = AC97_TUNE_HP_ONLY
1773 .name = "Dell Precision 450", /* AD1981B*/
1774 .type = AC97_TUNE_HP_ONLY
1779 .name = "Dell", /* which model? AD1981B*/
1780 .type = AC97_TUNE_HP_ONLY
1782 { /* FIXME: which codec? */
1785 .name = "Hewlett-Packard onboard",
1786 .type = AC97_TUNE_HP_ONLY
1791 .name = "HP xw8200", /* AD1981B*/
1792 .type = AC97_TUNE_HP_ONLY
1797 .name = "HP xw4200", /* AD1981B*/
1798 .type = AC97_TUNE_HP_ONLY
1803 .name = "Sony S1XP",
1804 .type = AC97_TUNE_INV_EAPD
1809 .name = "ASUS ICH5/AD1985",
1810 .type = AC97_TUNE_AD_SHARING
1815 .name = "Fujitsu-Siemens E4010",
1816 .type = AC97_TUNE_HP_ONLY
1821 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1822 .type = AC97_TUNE_HP_ONLY
1827 .name = "AMD64 Mobo", /* ALC650 */
1828 .type = AC97_TUNE_HP_ONLY
1833 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1834 .type = AC97_TUNE_HP_ONLY
1839 .name = "ADI AD1985 (discrete)",
1840 .type = AC97_TUNE_HP_ONLY
1845 .name = "MSI P4 ATX 645 Ultra",
1846 .type = AC97_TUNE_HP_ONLY
1851 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1852 .type = AC97_TUNE_HP_ONLY
1858 .name = "Intel ICH5/AD1985",
1859 .type = AC97_TUNE_AD_SHARING
1865 .name = "Intel ICH5/AD1985",
1866 .type = AC97_TUNE_AD_SHARING
1871 .name = "Intel D845WN (82801BA)",
1872 .type = AC97_TUNE_SWAP_HP
1877 .name = "Intel D850EMV2", /* AD1885 */
1878 .type = AC97_TUNE_HP_ONLY
1883 .name = "Intel ICH/AD1885",
1884 .type = AC97_TUNE_HP_ONLY
1890 .name = "Intel ICH5/AD1985",
1891 .type = AC97_TUNE_AD_SHARING
1897 .name = "Intel ICH5/AD1985",
1898 .type = AC97_TUNE_AD_SHARING
1900 #if 0 /* FIXME: this seems wrong on most boards */
1905 .name = "Intel ICH5/AD1985",
1906 .type = AC97_TUNE_HP_ONLY
1912 .name = "Dell Precision 450", /* AD1981B*/
1913 .type = AC97_TUNE_HP_ONLY
1918 .name = "HP xw4200", /* AD1981B*/
1919 .type = AC97_TUNE_HP_ONLY
1924 .name = "HP xw8200", /* AD1981B*/
1925 .type = AC97_TUNE_HP_ONLY
1927 { } /* terminator */
1930 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, int ac97_quirk)
1933 ac97_template_t ac97;
1935 unsigned int i, codecs;
1936 unsigned int glob_sta = 0;
1937 ac97_bus_ops_t *ops;
1938 static ac97_bus_ops_t standard_bus_ops = {
1939 .write = snd_intel8x0_codec_write,
1940 .read = snd_intel8x0_codec_read,
1942 static ac97_bus_ops_t ali_bus_ops = {
1943 .write = snd_intel8x0_ali_codec_write,
1944 .read = snd_intel8x0_ali_codec_read,
1947 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1948 switch (chip->device_type) {
1950 chip->spdif_idx = NVD_SPBAR;
1953 chip->spdif_idx = ALID_AC97SPDIFOUT;
1955 case DEVICE_INTEL_ICH4:
1956 chip->spdif_idx = ICHD_SPBAR;
1960 chip->in_ac97_init = 1;
1962 memset(&ac97, 0, sizeof(ac97));
1963 ac97.private_data = chip;
1964 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1965 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1967 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1968 if (chip->device_type != DEVICE_ALI) {
1969 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1970 ops = &standard_bus_ops;
1971 if (chip->device_type == DEVICE_INTEL_ICH4) {
1973 if (glob_sta & ICH_PCR)
1975 if (glob_sta & ICH_SCR)
1977 if (glob_sta & ICH_TCR)
1979 chip->in_sdin_init = 1;
1980 for (i = 0; i < codecs; i++) {
1981 snd_intel8x0_codec_read_test(chip, i);
1982 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1984 chip->in_sdin_init = 0;
1986 codecs = glob_sta & ICH_SCR ? 2 : 1;
1991 /* detect the secondary codec */
1992 for (i = 0; i < 100; i++) {
1993 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1998 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2002 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2004 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2005 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2006 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2007 pbus->clock = ac97_clock;
2008 /* FIXME: my test board doesn't work well with VRA... */
2009 if (chip->device_type == DEVICE_ALI)
2012 chip->ac97_bus = pbus;
2014 ac97.pci = chip->pci;
2015 for (i = 0; i < codecs; i++) {
2017 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2019 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2025 /* tune up the primary codec */
2026 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, ac97_quirk);
2027 /* enable separate SDINs for ICH4 */
2028 if (chip->device_type == DEVICE_INTEL_ICH4)
2030 /* find the available PCM streams */
2031 i = ARRAY_SIZE(ac97_pcm_defs);
2032 if (chip->device_type != DEVICE_INTEL_ICH4)
2033 i -= 2; /* do not allocate PCM2IN and MIC2 */
2034 if (chip->spdif_idx < 0)
2035 i--; /* do not allocate S/PDIF */
2036 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2039 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2040 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2041 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2042 if (chip->spdif_idx >= 0)
2043 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2044 if (chip->device_type == DEVICE_INTEL_ICH4) {
2045 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2046 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2048 /* enable separate SDINs for ICH4 */
2049 if (chip->device_type == DEVICE_INTEL_ICH4) {
2050 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2051 u8 tmp = igetbyte(chip, ICHREG(SDM));
2052 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2054 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2055 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2056 for (i = 1; i < 4; i++) {
2057 if (pcm->r[0].codec[i]) {
2058 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2063 tmp &= ~ICH_SE; /* steer disable */
2065 iputbyte(chip, ICHREG(SDM), tmp);
2067 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2069 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2072 if (pbus->pcms[0].r[1].rslots[0]) {
2075 if (chip->device_type == DEVICE_INTEL_ICH4) {
2076 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2079 if (chip->device_type == DEVICE_NFORCE) {
2081 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2083 if (chip->device_type == DEVICE_INTEL_ICH4) {
2084 /* use slot 10/11 for SPDIF */
2086 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2087 val |= ICH_PCM_SPDIF_1011;
2088 iputdword(chip, ICHREG(GLOB_CNT), val);
2089 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2091 chip->in_ac97_init = 0;
2095 /* clear the cold-reset bit for the next chance */
2096 if (chip->device_type != DEVICE_ALI)
2097 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2106 static void do_ali_reset(intel8x0_t *chip)
2108 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2109 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2110 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2111 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2112 iputdword(chip, ICHREG(ALI_INTERFACECR),
2113 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2114 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2115 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2118 #define do_delay(chip) do {\
2119 set_current_state(TASK_UNINTERRUPTIBLE);\
2120 schedule_timeout(1);\
2123 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2125 unsigned long end_time;
2126 unsigned int cnt, status, nstatus;
2128 /* put logic to right state */
2129 /* first clear status bits */
2130 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2131 if (chip->device_type == DEVICE_NFORCE)
2132 status |= ICH_NVSPINT;
2133 cnt = igetdword(chip, ICHREG(GLOB_STA));
2134 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2136 /* ACLink on, 2 channels */
2137 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2138 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2139 /* finish cold or do warm reset */
2140 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2141 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2142 end_time = (jiffies + (HZ / 4)) + 1;
2144 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2147 } while (time_after_eq(end_time, jiffies));
2148 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2153 /* wait for any codec ready status.
2154 * Once it becomes ready it should remain ready
2155 * as long as we do not disable the ac97 link.
2157 end_time = jiffies + HZ;
2159 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2163 } while (time_after_eq(end_time, jiffies));
2165 /* no codec is found */
2166 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2170 if (chip->device_type == DEVICE_INTEL_ICH4)
2171 /* ICH4 can have three codecs */
2172 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2174 /* others up to two codecs */
2175 nstatus = ICH_PCR | ICH_SCR;
2177 /* wait for other codecs ready status. */
2178 end_time = jiffies + HZ / 4;
2179 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2181 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2188 for (i = 0; i < 3; i++)
2190 status |= get_ich_codec_bit(chip, i);
2191 /* wait until all the probed codecs are ready */
2192 end_time = jiffies + HZ;
2194 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2195 if (status == nstatus)
2198 } while (time_after_eq(end_time, jiffies));
2201 if (chip->device_type == DEVICE_SIS) {
2202 /* unmute the output on SIS7012 */
2203 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2205 if (chip->device_type == DEVICE_NFORCE) {
2206 /* enable SPDIF interrupt */
2208 pci_read_config_dword(chip->pci, 0x4c, &val);
2210 pci_write_config_dword(chip->pci, 0x4c, val);
2215 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2220 reg = igetdword(chip, ICHREG(ALI_SCR));
2221 if ((reg & 2) == 0) /* Cold required */
2224 reg |= 1; /* Warm */
2225 reg &= ~0x80000000; /* ACLink on */
2226 iputdword(chip, ICHREG(ALI_SCR), reg);
2228 for (i = 0; i < HZ / 2; i++) {
2229 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2233 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2238 for (i = 0; i < HZ / 2; i++) {
2239 reg = igetdword(chip, ICHREG(ALI_RTSR));
2240 if (reg & 0x80) /* primary codec */
2242 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2250 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2255 if (chip->device_type != DEVICE_ALI) {
2256 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2258 iagetword(chip, 0); /* clear semaphore flag */
2260 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2264 /* disable interrupts */
2265 for (i = 0; i < chip->bdbars_count; i++)
2266 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2267 /* reset channels */
2268 for (i = 0; i < chip->bdbars_count; i++)
2269 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2270 /* initialize Buffer Descriptor Lists */
2271 for (i = 0; i < chip->bdbars_count; i++)
2272 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2276 static int snd_intel8x0_free(intel8x0_t *chip)
2282 /* disable interrupts */
2283 for (i = 0; i < chip->bdbars_count; i++)
2284 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2285 /* reset channels */
2286 for (i = 0; i < chip->bdbars_count; i++)
2287 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2288 if (chip->device_type == DEVICE_NFORCE) {
2289 /* stop the spdif interrupt */
2291 pci_read_config_dword(chip->pci, 0x4c, &val);
2293 pci_write_config_dword(chip->pci, 0x4c, val);
2296 synchronize_irq(chip->irq);
2299 free_irq(chip->irq, (void *)chip);
2300 if (chip->bdbars.area) {
2301 if (chip->fix_nocache)
2302 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2303 snd_dma_free_pages(&chip->bdbars);
2305 if (chip->remap_addr)
2306 iounmap(chip->remap_addr);
2307 if (chip->remap_bmaddr)
2308 iounmap(chip->remap_bmaddr);
2309 pci_release_regions(chip->pci);
2310 pci_disable_device(chip->pci);
2319 static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2321 intel8x0_t *chip = card->pm_private_data;
2324 for (i = 0; i < chip->pcm_devs; i++)
2325 snd_pcm_suspend_all(chip->pcm[i]);
2327 if (chip->fix_nocache) {
2328 for (i = 0; i < chip->bdbars_count; i++) {
2329 ichdev_t *ichdev = &chip->ichd[i];
2330 if (ichdev->substream && ichdev->page_attr_changed) {
2331 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2332 if (runtime->dma_area)
2333 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2337 for (i = 0; i < 3; i++)
2339 snd_ac97_suspend(chip->ac97[i]);
2340 pci_disable_device(chip->pci);
2341 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2345 static int intel8x0_resume(snd_card_t *card, unsigned int state)
2347 intel8x0_t *chip = card->pm_private_data;
2350 pci_enable_device(chip->pci);
2351 pci_set_master(chip->pci);
2352 snd_intel8x0_chip_init(chip, 0);
2354 /* refill nocache */
2355 if (chip->fix_nocache)
2356 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2358 for (i = 0; i < 3; i++)
2360 snd_ac97_resume(chip->ac97[i]);
2362 /* refill nocache */
2363 if (chip->fix_nocache) {
2364 for (i = 0; i < chip->bdbars_count; i++) {
2365 ichdev_t *ichdev = &chip->ichd[i];
2366 if (ichdev->substream && ichdev->page_attr_changed) {
2367 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2368 if (runtime->dma_area)
2369 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2374 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2377 #endif /* CONFIG_PM */
2379 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2381 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2383 snd_pcm_substream_t *subs;
2386 unsigned long pos, t;
2387 struct timeval start_time, stop_time;
2389 if (chip->ac97_bus->clock != 48000)
2390 return; /* specified in module option */
2392 subs = chip->pcm[0]->streams[0].substream;
2393 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2394 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2397 ichdev = &chip->ichd[ICHD_PCMOUT];
2398 ichdev->physbuf = subs->dma_buffer.addr;
2399 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2400 ichdev->substream = NULL; /* don't process interrupts */
2403 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2404 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2407 snd_intel8x0_setup_periods(chip, ichdev);
2408 port = ichdev->reg_offset;
2409 spin_lock_irq(&chip->reg_lock);
2410 chip->in_measurement = 1;
2412 if (chip->device_type != DEVICE_ALI)
2413 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2415 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2416 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2418 do_gettimeofday(&start_time);
2419 spin_unlock_irq(&chip->reg_lock);
2420 set_current_state(TASK_UNINTERRUPTIBLE);
2421 schedule_timeout(HZ / 20);
2422 spin_lock_irq(&chip->reg_lock);
2423 /* check the position */
2424 pos = ichdev->fragsize1;
2425 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2426 pos += ichdev->position;
2427 chip->in_measurement = 0;
2428 do_gettimeofday(&stop_time);
2430 if (chip->device_type == DEVICE_ALI) {
2431 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2432 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2433 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2436 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2437 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2440 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2441 spin_unlock_irq(&chip->reg_lock);
2443 t = stop_time.tv_sec - start_time.tv_sec;
2445 t += stop_time.tv_usec - start_time.tv_usec;
2446 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2448 snd_printk(KERN_ERR "?? calculation error..\n");
2451 pos = (pos / 4) * 1000;
2452 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2453 if (pos < 40000 || pos >= 60000)
2454 /* abnormal value. hw problem? */
2455 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2456 else if (pos < 47500 || pos > 48500)
2457 /* not 48000Hz, tuning the clock.. */
2458 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2459 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2462 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2463 snd_info_buffer_t * buffer)
2465 intel8x0_t *chip = entry->private_data;
2468 snd_iprintf(buffer, "Intel8x0\n\n");
2469 if (chip->device_type == DEVICE_ALI)
2471 tmp = igetdword(chip, ICHREG(GLOB_STA));
2472 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2473 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2474 if (chip->device_type == DEVICE_INTEL_ICH4)
2475 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2476 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2477 tmp & ICH_PCR ? " primary" : "",
2478 tmp & ICH_SCR ? " secondary" : "",
2479 tmp & ICH_TCR ? " tertiary" : "",
2480 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2481 if (chip->device_type == DEVICE_INTEL_ICH4)
2482 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2485 chip->ac97_sdin[2]);
2488 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2490 snd_info_entry_t *entry;
2492 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2493 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2496 static int snd_intel8x0_dev_free(snd_device_t *device)
2498 intel8x0_t *chip = device->device_data;
2499 return snd_intel8x0_free(chip);
2502 struct ich_reg_info {
2503 unsigned int int_sta_mask;
2504 unsigned int offset;
2507 static int __devinit snd_intel8x0_create(snd_card_t * card,
2508 struct pci_dev *pci,
2509 unsigned long device_type,
2510 intel8x0_t ** r_intel8x0)
2515 unsigned int int_sta_masks;
2517 static snd_device_ops_t ops = {
2518 .dev_free = snd_intel8x0_dev_free,
2521 static unsigned int bdbars[] = {
2522 3, /* DEVICE_INTEL */
2523 6, /* DEVICE_INTEL_ICH4 */
2526 4, /* DEVICE_NFORCE */
2528 static struct ich_reg_info intel_regs[6] = {
2530 { ICH_POINT, 0x10 },
2531 { ICH_MCINT, 0x20 },
2532 { ICH_M2INT, 0x40 },
2533 { ICH_P2INT, 0x50 },
2534 { ICH_SPINT, 0x60 },
2536 static struct ich_reg_info nforce_regs[4] = {
2538 { ICH_POINT, 0x10 },
2539 { ICH_MCINT, 0x20 },
2540 { ICH_NVSPINT, 0x70 },
2542 static struct ich_reg_info ali_regs[6] = {
2543 { ALI_INT_PCMIN, 0x40 },
2544 { ALI_INT_PCMOUT, 0x50 },
2545 { ALI_INT_MICIN, 0x60 },
2546 { ALI_INT_CODECSPDIFOUT, 0x70 },
2547 { ALI_INT_SPDIFIN, 0xa0 },
2548 { ALI_INT_SPDIFOUT, 0xb0 },
2550 struct ich_reg_info *tbl;
2554 if ((err = pci_enable_device(pci)) < 0)
2557 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2559 pci_disable_device(pci);
2562 spin_lock_init(&chip->reg_lock);
2563 spin_lock_init(&chip->ac97_lock);
2564 chip->device_type = device_type;
2569 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2570 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2571 chip->fix_nocache = 1; /* enable workaround */
2573 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2574 * Needs to return IRQ_HANDLED for unknown irqs.
2576 if (device_type == DEVICE_NFORCE)
2577 chip->buggy_irq = 1;
2579 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2581 pci_disable_device(pci);
2585 if (device_type == DEVICE_ALI) {
2586 /* ALI5455 has no ac97 region */
2587 chip->bmaddr = pci_resource_start(pci, 0);
2591 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2593 chip->addr = pci_resource_start(pci, 2);
2594 chip->remap_addr = ioremap_nocache(chip->addr,
2595 pci_resource_len(pci, 2));
2596 if (chip->remap_addr == NULL) {
2597 snd_printk("AC'97 space ioremap problem\n");
2598 snd_intel8x0_free(chip);
2602 chip->addr = pci_resource_start(pci, 0);
2604 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2606 chip->bmaddr = pci_resource_start(pci, 3);
2607 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2608 pci_resource_len(pci, 3));
2609 if (chip->remap_bmaddr == NULL) {
2610 snd_printk("Controller space ioremap problem\n");
2611 snd_intel8x0_free(chip);
2615 chip->bmaddr = pci_resource_start(pci, 1);
2619 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2620 snd_printk("unable to grab IRQ %d\n", pci->irq);
2621 snd_intel8x0_free(chip);
2624 chip->irq = pci->irq;
2625 pci_set_master(pci);
2626 synchronize_irq(chip->irq);
2628 chip->bdbars_count = bdbars[device_type];
2630 /* initialize offsets */
2631 switch (device_type) {
2642 for (i = 0; i < chip->bdbars_count; i++) {
2643 ichdev = &chip->ichd[i];
2645 ichdev->reg_offset = tbl[i].offset;
2646 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2647 if (device_type == DEVICE_SIS) {
2648 /* SiS 7012 swaps the registers */
2649 ichdev->roff_sr = ICH_REG_OFF_PICB;
2650 ichdev->roff_picb = ICH_REG_OFF_SR;
2652 ichdev->roff_sr = ICH_REG_OFF_SR;
2653 ichdev->roff_picb = ICH_REG_OFF_PICB;
2655 if (device_type == DEVICE_ALI)
2656 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2657 /* SIS7012 handles the pcm data in bytes, others are in samples */
2658 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2661 /* allocate buffer descriptor lists */
2662 /* the start of each lists must be aligned to 8 bytes */
2663 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2664 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2665 &chip->bdbars) < 0) {
2666 snd_intel8x0_free(chip);
2667 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2670 /* tables must be aligned to 8 bytes here, but the kernel pages
2671 are much bigger, so we don't care (on i386) */
2672 /* workaround for 440MX */
2673 if (chip->fix_nocache)
2674 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2676 for (i = 0; i < chip->bdbars_count; i++) {
2677 ichdev = &chip->ichd[i];
2678 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2679 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2680 int_sta_masks |= ichdev->int_sta_mask;
2682 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2683 chip->int_sta_mask = int_sta_masks;
2685 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2686 snd_intel8x0_free(chip);
2690 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2692 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2693 snd_intel8x0_free(chip);
2697 snd_card_set_dev(card, &pci->dev);
2703 static struct shortname_table {
2706 } shortnames[] __devinitdata = {
2707 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2708 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2709 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2710 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2711 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2712 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2713 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2714 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2715 { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2716 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2717 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2718 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2719 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2720 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2721 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2722 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2723 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2724 { 0x003a, "NVidia MCP04" },
2725 { 0x746d, "AMD AMD8111" },
2726 { 0x7445, "AMD AMD768" },
2727 { 0x5455, "ALi M5455" },
2731 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2732 const struct pci_device_id *pci_id)
2738 struct shortname_table *name;
2740 if (dev >= SNDRV_CARDS)
2747 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2751 switch (pci_id->driver_data) {
2753 strcpy(card->driver, "NFORCE");
2755 case DEVICE_INTEL_ICH4:
2756 strcpy(card->driver, "ICH4");
2759 strcpy(card->driver, "ICH");
2763 strcpy(card->shortname, "Intel ICH");
2764 for (name = shortnames; name->id; name++) {
2765 if (pci->device == name->id) {
2766 strcpy(card->shortname, name->s);
2771 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2772 snd_card_free(card);
2776 chip->buggy_irq = 1;
2780 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2781 snd_card_free(card);
2784 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2785 snd_card_free(card);
2789 snd_intel8x0_proc_init(chip);
2791 snprintf(card->longname, sizeof(card->longname),
2792 "%s with %s at %#lx, irq %i", card->shortname,
2793 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2795 if (! ac97_clock[dev])
2796 intel8x0_measure_ac97_clock(chip);
2798 if ((err = snd_card_register(card)) < 0) {
2799 snd_card_free(card);
2802 pci_set_drvdata(pci, card);
2807 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2809 snd_card_free(pci_get_drvdata(pci));
2810 pci_set_drvdata(pci, NULL);
2813 static struct pci_driver driver = {
2814 .name = "Intel ICH",
2815 .id_table = snd_intel8x0_ids,
2816 .probe = snd_intel8x0_probe,
2817 .remove = __devexit_p(snd_intel8x0_remove),
2818 SND_PCI_PM_CALLBACKS
2822 static int __init alsa_card_intel8x0_init(void)
2826 if ((err = pci_module_init(&driver)) < 0)
2831 static void __exit alsa_card_intel8x0_exit(void)
2833 pci_unregister_driver(&driver);
2836 module_init(alsa_card_intel8x0_init)
2837 module_exit(alsa_card_intel8x0_exit)