sound/pci/intel8x0m.c

   1 /*
   2  *   ALSA modem driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *   This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
   7  *   of ALSA ICH sound driver intel8x0.c .
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <asm/io.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/slab.h>
  33 #include <linux/moduleparam.h>
  34 #include <sound/core.h>
  35 #include <sound/pcm.h>
  36 #include <sound/ac97_codec.h>
  37 #include <sound/info.h>
  38 #include <sound/initval.h>
  39
  40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  41 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
  42 MODULE_LICENSE("GPL");
  43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  44                 "{Intel,82901AB-ICH0},"
  45                 "{Intel,82801BA-ICH2},"
  46                 "{Intel,82801CA-ICH3},"
  47                 "{Intel,82801DB-ICH4},"
  48                 "{Intel,ICH5},"
  49                 "{Intel,MX440},"
  50                 "{SiS,7013},"
  51                 "{NVidia,NForce Modem},"
  52                 "{NVidia,NForce2 Modem},"
  53                 "{NVidia,NForce2s Modem},"
  54                 "{NVidia,NForce3 Modem},"
  55                 "{AMD,AMD768}}");
  56
  57 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  58 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  59 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  60 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  61
  62 module_param_array(index, int, NULL, 0444);
  63 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
  64 module_param_array(id, charp, NULL, 0444);
  65 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
  66 module_param_array(enable, bool, NULL, 0444);
  67 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
  68 module_param_array(ac97_clock, int, NULL, 0444);
  69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  70
  71 /*
  72  *  Direct registers
  73  */
  74
  75 #ifndef PCI_DEVICE_ID_INTEL_82801_6
  76 #define PCI_DEVICE_ID_INTEL_82801_6     0x2416
  77 #endif
  78 #ifndef PCI_DEVICE_ID_INTEL_82901_6
  79 #define PCI_DEVICE_ID_INTEL_82901_6     0x2426
  80 #endif
  81 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6
  82 #define PCI_DEVICE_ID_INTEL_82801BA_6   0x2446
  83 #endif
  84 #ifndef PCI_DEVICE_ID_INTEL_440MX_6
  85 #define PCI_DEVICE_ID_INTEL_440MX_6     0x7196
  86 #endif
  87 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6
  88 #define PCI_DEVICE_ID_INTEL_ICH3_6      0x2486
  89 #endif
  90 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6
  91 #define PCI_DEVICE_ID_INTEL_ICH4_6      0x24c6
  92 #endif
  93 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6
  94 #define PCI_DEVICE_ID_INTEL_ICH5_6      0x24d6
  95 #endif
  96 #ifndef PCI_DEVICE_ID_SI_7013
  97 #define PCI_DEVICE_ID_SI_7013           0x7013
  98 #endif
  99 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_MODEM
 100 #define PCI_DEVICE_ID_NVIDIA_MCP_MODEM  0x01c1
 101 #endif
 102 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
 103 #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069
 104 #endif
 105 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
 106 #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089
 107 #endif
 108 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
 109 #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9
 110 #endif
 111
 112
 113 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 114
 115 #define ICHREG(x) ICH_REG_##x
 116
 117 #define DEFINE_REGSET(name,base) \
 118 enum { \
 119         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 120         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 121         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 122         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 123         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 124         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 125         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 126 };
 127
 128 /* busmaster blocks */
 129 DEFINE_REGSET(OFF, 0);          /* offset */
 130
 131 /* values for each busmaster block */
 132
 133 /* LVI */
 134 #define ICH_REG_LVI_MASK                0x1f
 135
 136 /* SR */
 137 #define ICH_FIFOE                       0x10    /* FIFO error */
 138 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 139 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 140 #define ICH_CELV                        0x02    /* current equals last valid */
 141 #define ICH_DCH                         0x01    /* DMA controller halted */
 142
 143 /* PIV */
 144 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 145
 146 /* CR */
 147 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 148 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 149 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 150 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 151 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 152
 153
 154 /* global block */
 155 #define ICH_REG_GLOB_CNT                0x3c    /* dword - global control */
 156 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 157 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 158 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 159 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 160 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 161 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 162 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 163 #define ICH_REG_GLOB_STA                0x40    /* dword - global status */
 164 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 165 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 166 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 167 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 168 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 169 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 170 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 171 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 172 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 173 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 174 #define   ICH_RCS               0x00008000      /* read completion status */
 175 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 176 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 177 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 178 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 179 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 180 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 181 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 182 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 183 #define   ICH_POINT             0x00000040      /* playback interrupt */
 184 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 185 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 186 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 187 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 188 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 189 #define ICH_REG_ACC_SEMA                0x44    /* byte - codec write semaphore */
 190 #define   ICH_CAS               0x01            /* codec access semaphore */
 191
 192 #define ICH_MAX_FRAGS           32              /* max hw frags */
 193
 194
 195 /*
 196  *
 197  */
 198
 199 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
 200 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
 201
 202 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 203
 204 typedef struct {
 205         unsigned int ichd;                      /* ich device number */
 206         unsigned long reg_offset;               /* offset to bmaddr */
 207         u32 *bdbar;                             /* CPU address (32bit) */
 208         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 209         snd_pcm_substream_t *substream;
 210         unsigned int physbuf;                   /* physical address (32bit) */
 211         unsigned int size;
 212         unsigned int fragsize;
 213         unsigned int fragsize1;
 214         unsigned int position;
 215         int frags;
 216         int lvi;
 217         int lvi_frag;
 218         int civ;
 219         int ack;
 220         int ack_reload;
 221         unsigned int ack_bit;
 222         unsigned int roff_sr;
 223         unsigned int roff_picb;
 224         unsigned int int_sta_mask;              /* interrupt status mask */
 225         unsigned int ali_slot;                  /* ALI DMA slot */
 226         ac97_t *ac97;
 227 } ichdev_t;
 228
 229 typedef struct _snd_intel8x0m intel8x0_t;
 230
 231 struct _snd_intel8x0m {
 232         unsigned int device_type;
 233
 234         int irq;
 235
 236         unsigned int mmio;
 237         unsigned long addr;
 238         void __iomem *remap_addr;
 239         unsigned int bm_mmio;
 240         unsigned long bmaddr;
 241         void __iomem *remap_bmaddr;
 242
 243         struct pci_dev *pci;
 244         snd_card_t *card;
 245
 246         int pcm_devs;
 247         snd_pcm_t *pcm[2];
 248         ichdev_t ichd[2];
 249
 250         int in_ac97_init: 1;
 251
 252         ac97_bus_t *ac97_bus;
 253         ac97_t *ac97;
 254
 255         spinlock_t reg_lock;
 256         spinlock_t ac97_lock;
 257
 258         struct snd_dma_buffer bdbars;
 259         u32 bdbars_count;
 260         u32 int_sta_reg;                /* interrupt status register */
 261         u32 int_sta_mask;               /* interrupt status mask */
 262         unsigned int pcm_pos_shift;
 263 };
 264
 265 static struct pci_device_id snd_intel8x0m_ids[] = {
 266         { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 267         { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 268         { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 269         { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 270         { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
 271         { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
 272         { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 273         { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 274         { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7013 */
 275         { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
 276         { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
 277         { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
 278         { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
 279 #if 0
 280         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 281         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 282 #endif
 283         { 0, }
 284 };
 285
 286 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
 287
 288 /*
 289  *  Lowlevel I/O - busmaster
 290  */
 291
 292 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 293 {
 294         if (chip->bm_mmio)
 295                 return readb(chip->remap_bmaddr + offset);
 296         else
 297                 return inb(chip->bmaddr + offset);
 298 }
 299
 300 static u16 igetword(intel8x0_t *chip, u32 offset)
 301 {
 302         if (chip->bm_mmio)
 303                 return readw(chip->remap_bmaddr + offset);
 304         else
 305                 return inw(chip->bmaddr + offset);
 306 }
 307
 308 static u32 igetdword(intel8x0_t *chip, u32 offset)
 309 {
 310         if (chip->bm_mmio)
 311                 return readl(chip->remap_bmaddr + offset);
 312         else
 313                 return inl(chip->bmaddr + offset);
 314 }
 315
 316 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 317 {
 318         if (chip->bm_mmio)
 319                 writeb(val, chip->remap_bmaddr + offset);
 320         else
 321                 outb(val, chip->bmaddr + offset);
 322 }
 323
 324 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 325 {
 326         if (chip->bm_mmio)
 327                 writew(val, chip->remap_bmaddr + offset);
 328         else
 329                 outw(val, chip->bmaddr + offset);
 330 }
 331
 332 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 333 {
 334         if (chip->bm_mmio)
 335                 writel(val, chip->remap_bmaddr + offset);
 336         else
 337                 outl(val, chip->bmaddr + offset);
 338 }
 339
 340 /*
 341  *  Lowlevel I/O - AC'97 registers
 342  */
 343
 344 static u16 iagetword(intel8x0_t *chip, u32 offset)
 345 {
 346         if (chip->mmio)
 347                 return readw(chip->remap_addr + offset);
 348         else
 349                 return inw(chip->addr + offset);
 350 }
 351
 352 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 353 {
 354         if (chip->mmio)
 355                 writew(val, chip->remap_addr + offset);
 356         else
 357                 outw(val, chip->addr + offset);
 358 }
 359
 360 /*
 361  *  Basic I/O
 362  */
 363
 364 /*
 365  * access to AC97 codec via normal i/o (for ICH and SIS7013)
 366  */
 367
 368 /* return the GLOB_STA bit for the corresponding codec */
 369 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 370 {
 371         static unsigned int codec_bit[3] = {
 372                 ICH_PCR, ICH_SCR, ICH_TCR
 373         };
 374         snd_assert(codec < 3, return ICH_PCR);
 375         return codec_bit[codec];
 376 }
 377
 378 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 379 {
 380         int time;
 381
 382         if (codec > 1)
 383                 return -EIO;
 384         codec = get_ich_codec_bit(chip, codec);
 385
 386         /* codec ready ? */
 387         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 388                 return -EIO;
 389
 390         /* Anyone holding a semaphore for 1 msec should be shot... */
 391         time = 100;
 392         do {
 393                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 394                         return 0;
 395                 udelay(10);
 396         } while (time--);
 397
 398         /* access to some forbidden (non existant) ac97 registers will not
 399          * reset the semaphore. So even if you don't get the semaphore, still
 400          * continue the access. We don't need the semaphore anyway. */
 401         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 402                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 403         iagetword(chip, 0);     /* clear semaphore flag */
 404         /* I don't care about the semaphore */
 405         return -EBUSY;
 406 }
 407
 408 static void snd_intel8x0_codec_write(ac97_t *ac97,
 409                                      unsigned short reg,
 410                                      unsigned short val)
 411 {
 412         intel8x0_t *chip = ac97->private_data;
 413
 414         spin_lock(&chip->ac97_lock);
 415         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 416                 if (! chip->in_ac97_init)
 417                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 418         }
 419         iaputword(chip, reg + ac97->num * 0x80, val);
 420         spin_unlock(&chip->ac97_lock);
 421 }
 422
 423 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 424                                               unsigned short reg)
 425 {
 426         intel8x0_t *chip = ac97->private_data;
 427         unsigned short res;
 428         unsigned int tmp;
 429
 430         spin_lock(&chip->ac97_lock);
 431         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 432                 if (! chip->in_ac97_init)
 433                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 434                 res = 0xffff;
 435         } else {
 436                 res = iagetword(chip, reg + ac97->num * 0x80);
 437                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 438                         /* reset RCS and preserve other R/WC bits */
 439                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 440                         if (! chip->in_ac97_init)
 441                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 442                         res = 0xffff;
 443                 }
 444         }
 445         spin_unlock(&chip->ac97_lock);
 446         return res;
 447 }
 448
 449
 450 /*
 451  * DMA I/O
 452  */
 453 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 454 {
 455         int idx;
 456         u32 *bdbar = ichdev->bdbar;
 457         unsigned long port = ichdev->reg_offset;
 458
 459         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 460         if (ichdev->size == ichdev->fragsize) {
 461                 ichdev->ack_reload = ichdev->ack = 2;
 462                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 463                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 464                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 465                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 466                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 467                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 468                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 469                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 470                 }
 471                 ichdev->frags = 2;
 472         } else {
 473                 ichdev->ack_reload = ichdev->ack = 1;
 474                 ichdev->fragsize1 = ichdev->fragsize;
 475                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 476                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 477                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 478                                                      ichdev->fragsize >> chip->pcm_pos_shift);
 479                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 480                 }
 481                 ichdev->frags = ichdev->size / ichdev->fragsize;
 482         }
 483         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 484         ichdev->civ = 0;
 485         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 486         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 487         ichdev->position = 0;
 488 #if 0
 489         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 490                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 491 #endif
 492         /* clear interrupts */
 493         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 494 }
 495
 496 /*
 497  *  Interrupt handler
 498  */
 499
 500 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 501 {
 502         unsigned long port = ichdev->reg_offset;
 503         int civ, i, step;
 504         int ack = 0;
 505
 506         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 507         if (civ == ichdev->civ) {
 508                 // snd_printd("civ same %d\n", civ);
 509                 step = 1;
 510                 ichdev->civ++;
 511                 ichdev->civ &= ICH_REG_LVI_MASK;
 512         } else {
 513                 step = civ - ichdev->civ;
 514                 if (step < 0)
 515                         step += ICH_REG_LVI_MASK + 1;
 516                 // if (step != 1)
 517                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 518                 ichdev->civ = civ;
 519         }
 520
 521         ichdev->position += step * ichdev->fragsize1;
 522         ichdev->position %= ichdev->size;
 523         ichdev->lvi += step;
 524         ichdev->lvi &= ICH_REG_LVI_MASK;
 525         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 526         for (i = 0; i < step; i++) {
 527                 ichdev->lvi_frag++;
 528                 ichdev->lvi_frag %= ichdev->frags;
 529                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 530         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 531                 if (--ichdev->ack == 0) {
 532                         ichdev->ack = ichdev->ack_reload;
 533                         ack = 1;
 534                 }
 535         }
 536         if (ack && ichdev->substream) {
 537                 spin_unlock(&chip->reg_lock);
 538                 snd_pcm_period_elapsed(ichdev->substream);
 539                 spin_lock(&chip->reg_lock);
 540         }
 541         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 542 }
 543
 544 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 545 {
 546         intel8x0_t *chip = dev_id;
 547         ichdev_t *ichdev;
 548         unsigned int status;
 549         unsigned int i;
 550
 551         spin_lock(&chip->reg_lock);
 552         status = igetdword(chip, chip->int_sta_reg);
 553         if (status == 0xffffffff) { /* we are not yet resumed */
 554                 spin_unlock(&chip->reg_lock);
 555                 return IRQ_NONE;
 556         }
 557         if ((status & chip->int_sta_mask) == 0) {
 558                 if (status)
 559                         iputdword(chip, chip->int_sta_reg, status);
 560                 spin_unlock(&chip->reg_lock);
 561                 return IRQ_NONE;
 562         }
 563
 564         for (i = 0; i < chip->bdbars_count; i++) {
 565                 ichdev = &chip->ichd[i];
 566                 if (status & ichdev->int_sta_mask)
 567                         snd_intel8x0_update(chip, ichdev);
 568         }
 569
 570         /* ack them */
 571         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 572         spin_unlock(&chip->reg_lock);
 573
 574         return IRQ_HANDLED;
 575 }
 576
 577 /*
 578  *  PCM part
 579  */
 580
 581 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 582 {
 583         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 584         ichdev_t *ichdev = get_ichdev(substream);
 585         unsigned char val = 0;
 586         unsigned long port = ichdev->reg_offset;
 587
 588         switch (cmd) {
 589         case SNDRV_PCM_TRIGGER_START:
 590         case SNDRV_PCM_TRIGGER_RESUME:
 591                 val = ICH_IOCE | ICH_STARTBM;
 592                 break;
 593         case SNDRV_PCM_TRIGGER_STOP:
 594         case SNDRV_PCM_TRIGGER_SUSPEND:
 595                 val = 0;
 596                 break;
 597         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 598                 val = ICH_IOCE;
 599                 break;
 600         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 601                 val = ICH_IOCE | ICH_STARTBM;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 607         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 608                 /* wait until DMA stopped */
 609                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 610                 /* reset whole DMA things */
 611                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 612         }
 613         return 0;
 614 }
 615
 616 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 617                                   snd_pcm_hw_params_t * hw_params)
 618 {
 619         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 620 }
 621
 622 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 623 {
 624         return snd_pcm_lib_free_pages(substream);
 625 }
 626
 627 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
 628 {
 629         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 630         ichdev_t *ichdev = get_ichdev(substream);
 631         size_t ptr1, ptr;
 632
 633         ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
 634         if (ptr1 != 0)
 635                 ptr = ichdev->fragsize1 - ptr1;
 636         else
 637                 ptr = 0;
 638         ptr += ichdev->position;
 639         if (ptr >= ichdev->size)
 640                 return 0;
 641         return bytes_to_frames(substream->runtime, ptr);
 642 }
 643
 644 static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 645 {
 646         ichdev_t *ichdev = get_ichdev(substream);
 647         /* hook off/on on start/stop */
 648         /* TODO: move it to ac97 controls */
 649         switch (cmd) {
 650         case SNDRV_PCM_TRIGGER_START:
 651                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 652                                      AC97_GPIO_LINE1_OH, AC97_GPIO_LINE1_OH);
 653                 break;
 654         case SNDRV_PCM_TRIGGER_STOP:
 655                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 656                                      AC97_GPIO_LINE1_OH, ~AC97_GPIO_LINE1_OH);
 657                 break;
 658         default:
 659                 return -EINVAL;
 660         }
 661         return snd_intel8x0_pcm_trigger(substream,cmd);
 662 }
 663
 664 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
 665 {
 666         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 667         snd_pcm_runtime_t *runtime = substream->runtime;
 668         ichdev_t *ichdev = get_ichdev(substream);
 669
 670         ichdev->physbuf = runtime->dma_addr;
 671         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 672         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 673         snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
 674         snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
 675         snd_intel8x0_setup_periods(chip, ichdev);
 676         return 0;
 677 }
 678
 679 static snd_pcm_hardware_t snd_intel8x0m_stream =
 680 {
 681         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 682                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 683                                  SNDRV_PCM_INFO_MMAP_VALID |
 684                                  SNDRV_PCM_INFO_PAUSE |
 685                                  SNDRV_PCM_INFO_RESUME),
 686         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 687         .rates =                SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
 688         .rate_min =             8000,
 689         .rate_max =             16000,
 690         .channels_min =         1,
 691         .channels_max =         1,
 692         .buffer_bytes_max =     64 * 1024,
 693         .period_bytes_min =     32,
 694         .period_bytes_max =     64 * 1024,
 695         .periods_min =          1,
 696         .periods_max =          1024,
 697         .fifo_size =            0,
 698 };
 699
 700
 701 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
 702 {
 703         static unsigned int rates[] = { 8000,  9600, 12000, 16000 };
 704         static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
 705                 .count = ARRAY_SIZE(rates),
 706                 .list = rates,
 707                 .mask = 0,
 708         };
 709         snd_pcm_runtime_t *runtime = substream->runtime;
 710         int err;
 711
 712         ichdev->substream = substream;
 713         runtime->hw = snd_intel8x0m_stream;
 714         err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
 715         if ( err < 0 )
 716                 return err;
 717         runtime->private_data = ichdev;
 718         return 0;
 719 }
 720
 721 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
 722 {
 723         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 724
 725         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
 726 }
 727
 728 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
 729 {
 730         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 731
 732         chip->ichd[ICHD_MDMOUT].substream = NULL;
 733         return 0;
 734 }
 735
 736 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
 737 {
 738         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 739
 740         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
 741 }
 742
 743 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
 744 {
 745         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 746
 747         chip->ichd[ICHD_MDMIN].substream = NULL;
 748         return 0;
 749 }
 750
 751
 752 static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
 753         .open =         snd_intel8x0m_playback_open,
 754         .close =        snd_intel8x0m_playback_close,
 755         .ioctl =        snd_pcm_lib_ioctl,
 756         .hw_params =    snd_intel8x0_hw_params,
 757         .hw_free =      snd_intel8x0_hw_free,
 758         .prepare =      snd_intel8x0m_pcm_prepare,
 759         .trigger =      snd_intel8x0m_pcm_trigger,
 760         .pointer =      snd_intel8x0_pcm_pointer,
 761 };
 762
 763 static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
 764         .open =         snd_intel8x0m_capture_open,
 765         .close =        snd_intel8x0m_capture_close,
 766         .ioctl =        snd_pcm_lib_ioctl,
 767         .hw_params =    snd_intel8x0_hw_params,
 768         .hw_free =      snd_intel8x0_hw_free,
 769         .prepare =      snd_intel8x0m_pcm_prepare,
 770         .trigger =      snd_intel8x0m_pcm_trigger,
 771         .pointer =      snd_intel8x0_pcm_pointer,
 772 };
 773
 774
 775 struct ich_pcm_table {
 776         char *suffix;
 777         snd_pcm_ops_t *playback_ops;
 778         snd_pcm_ops_t *capture_ops;
 779         size_t prealloc_size;
 780         size_t prealloc_max_size;
 781         int ac97_idx;
 782 };
 783
 784 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
 785 {
 786         snd_pcm_t *pcm;
 787         int err;
 788         char name[32];
 789
 790         if (rec->suffix)
 791                 sprintf(name, "Intel ICH - %s", rec->suffix);
 792         else
 793                 strcpy(name, "Intel ICH");
 794         err = snd_pcm_new(chip->card, name, device,
 795                           rec->playback_ops ? 1 : 0,
 796                           rec->capture_ops ? 1 : 0, &pcm);
 797         if (err < 0)
 798                 return err;
 799
 800         if (rec->playback_ops)
 801                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
 802         if (rec->capture_ops)
 803                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
 804
 805         pcm->private_data = chip;
 806         pcm->info_flags = 0;
 807         if (rec->suffix)
 808                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
 809         else
 810                 strcpy(pcm->name, chip->card->shortname);
 811         chip->pcm[device] = pcm;
 812
 813         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 814                                               snd_dma_pci_data(chip->pci),
 815                                               rec->prealloc_size,
 816                                               rec->prealloc_max_size);
 817
 818         return 0;
 819 }
 820
 821 static struct ich_pcm_table intel_pcms[] __devinitdata = {
 822         {
 823                 .suffix = "Modem",
 824                 .playback_ops = &snd_intel8x0m_playback_ops,
 825                 .capture_ops = &snd_intel8x0m_capture_ops,
 826                 .prealloc_size = 32 * 1024,
 827                 .prealloc_max_size = 64 * 1024,
 828         },
 829 };
 830
 831 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
 832 {
 833         int i, tblsize, device, err;
 834         struct ich_pcm_table *tbl, *rec;
 835
 836 #if 1
 837         tbl = intel_pcms;
 838         tblsize = 1;
 839 #else
 840         switch (chip->device_type) {
 841         case DEVICE_NFORCE:
 842                 tbl = nforce_pcms;
 843                 tblsize = ARRAY_SIZE(nforce_pcms);
 844                 break;
 845         case DEVICE_ALI:
 846                 tbl = ali_pcms;
 847                 tblsize = ARRAY_SIZE(ali_pcms);
 848                 break;
 849         default:
 850                 tbl = intel_pcms;
 851                 tblsize = 2;
 852                 break;
 853         }
 854 #endif
 855         device = 0;
 856         for (i = 0; i < tblsize; i++) {
 857                 rec = tbl + i;
 858                 if (i > 0 && rec->ac97_idx) {
 859                         /* activate PCM only when associated AC'97 codec */
 860                         if (! chip->ichd[rec->ac97_idx].ac97)
 861                                 continue;
 862                 }
 863                 err = snd_intel8x0_pcm1(chip, device, rec);
 864                 if (err < 0)
 865                         return err;
 866                 device++;
 867         }
 868
 869         chip->pcm_devs = device;
 870         return 0;
 871 }
 872
 873
 874 /*
 875  *  Mixer part
 876  */
 877
 878 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
 879 {
 880         intel8x0_t *chip = bus->private_data;
 881         chip->ac97_bus = NULL;
 882 }
 883
 884 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
 885 {
 886         intel8x0_t *chip = ac97->private_data;
 887         chip->ac97 = NULL;
 888 }
 889
 890
 891 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
 892 {
 893         ac97_bus_t *pbus;
 894         ac97_template_t ac97;
 895         ac97_t *x97;
 896         int err;
 897         unsigned int glob_sta = 0;
 898         static ac97_bus_ops_t ops = {
 899                 .write = snd_intel8x0_codec_write,
 900                 .read = snd_intel8x0_codec_read,
 901         };
 902
 903         chip->in_ac97_init = 1;
 904
 905         memset(&ac97, 0, sizeof(ac97));
 906         ac97.private_data = chip;
 907         ac97.private_free = snd_intel8x0_mixer_free_ac97;
 908         ac97.scaps = AC97_SCAP_SKIP_AUDIO;
 909
 910         glob_sta = igetdword(chip, ICHREG(GLOB_STA));
 911
 912         if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
 913                 goto __err;
 914         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
 915         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with audio driver */
 916         if (ac97_clock >= 8000 && ac97_clock <= 48000)
 917                 pbus->clock = ac97_clock;
 918         chip->ac97_bus = pbus;
 919
 920         ac97.pci = chip->pci;
 921         ac97.num = glob_sta & ICH_SCR ? 1 : 0;
 922         if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
 923                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
 924                 if (ac97.num == 0)
 925                         goto __err;
 926                 return err;
 927         }
 928         chip->ac97 = x97;
 929         if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97 ) {
 930                 chip->ichd[ICHD_MDMIN].ac97 = x97;
 931                 chip->ichd[ICHD_MDMOUT].ac97 = x97;
 932         }
 933
 934         chip->in_ac97_init = 0;
 935         return 0;
 936
 937  __err:
 938         /* clear the cold-reset bit for the next chance */
 939         if (chip->device_type != DEVICE_ALI)
 940                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
 941         return err;
 942 }
 943
 944
 945 /*
 946  *
 947  */
 948
 949 #define do_delay(chip) do {\
 950         set_current_state(TASK_UNINTERRUPTIBLE);\
 951         schedule_timeout(1);\
 952 } while (0)
 953
 954 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
 955 {
 956         unsigned long end_time;
 957         unsigned int cnt, status, nstatus;
 958
 959         /* put logic to right state */
 960         /* first clear status bits */
 961         status = ICH_RCS | ICH_MIINT | ICH_MOINT;
 962         cnt = igetdword(chip, ICHREG(GLOB_STA));
 963         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
 964
 965         /* ACLink on, 2 channels */
 966         cnt = igetdword(chip, ICHREG(GLOB_CNT));
 967         cnt &= ~(ICH_ACLINK);
 968         /* finish cold or do warm reset */
 969         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
 970         iputdword(chip, ICHREG(GLOB_CNT), cnt);
 971         end_time = (jiffies + (HZ / 4)) + 1;
 972         do {
 973                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
 974                         goto __ok;
 975                 do_delay(chip);
 976         } while (time_after_eq(end_time, jiffies));
 977         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
 978         return -EIO;
 979
 980       __ok:
 981         if (probing) {
 982                 /* wait for any codec ready status.
 983                  * Once it becomes ready it should remain ready
 984                  * as long as we do not disable the ac97 link.
 985                  */
 986                 end_time = jiffies + HZ;
 987                 do {
 988                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
 989                         if (status)
 990                                 break;
 991                         do_delay(chip);
 992                 } while (time_after_eq(end_time, jiffies));
 993                 if (! status) {
 994                         /* no codec is found */
 995                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
 996                         return -EIO;
 997                 }
 998
 999                 /* up to two codecs (modem cannot be tertiary with ICH4) */
1000                 nstatus = ICH_PCR | ICH_SCR;
1001
1002                 /* wait for other codecs ready status. */
1003                 end_time = jiffies + HZ / 4;
1004                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1005                         do_delay(chip);
1006                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1007                 }
1008
1009         } else {
1010                 /* resume phase */
1011                 status = 0;
1012                 if (chip->ac97)
1013                         status |= get_ich_codec_bit(chip, chip->ac97->num);
1014                 /* wait until all the probed codecs are ready */
1015                 end_time = jiffies + HZ;
1016                 do {
1017                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1018                         if (status == nstatus)
1019                                 break;
1020                         do_delay(chip);
1021                 } while (time_after_eq(end_time, jiffies));
1022         }
1023
1024         if (chip->device_type == DEVICE_SIS) {
1025                 /* unmute the output on SIS7012 */
1026                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1033 {
1034         unsigned int i;
1035         int err;
1036
1037         if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1038                 return err;
1039         iagetword(chip, 0);     /* clear semaphore flag */
1040
1041         /* disable interrupts */
1042         for (i = 0; i < chip->bdbars_count; i++)
1043                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1044         /* reset channels */
1045         for (i = 0; i < chip->bdbars_count; i++)
1046                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1047         /* initialize Buffer Descriptor Lists */
1048         for (i = 0; i < chip->bdbars_count; i++)
1049                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1050         return 0;
1051 }
1052
1053 static int snd_intel8x0_free(intel8x0_t *chip)
1054 {
1055         unsigned int i;
1056
1057         if (chip->irq < 0)
1058                 goto __hw_end;
1059         /* disable interrupts */
1060         for (i = 0; i < chip->bdbars_count; i++)
1061                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1062         /* reset channels */
1063         for (i = 0; i < chip->bdbars_count; i++)
1064                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1065         /* --- */
1066         synchronize_irq(chip->irq);
1067       __hw_end:
1068         if (chip->bdbars.area)
1069                 snd_dma_free_pages(&chip->bdbars);
1070         if (chip->remap_addr)
1071                 iounmap(chip->remap_addr);
1072         if (chip->remap_bmaddr)
1073                 iounmap(chip->remap_bmaddr);
1074         if (chip->irq >= 0)
1075                 free_irq(chip->irq, (void *)chip);
1076         pci_release_regions(chip->pci);
1077         pci_disable_device(chip->pci);
1078         kfree(chip);
1079         return 0;
1080 }
1081
1082 #ifdef CONFIG_PM
1083 /*
1084  * power management
1085  */
1086 static int intel8x0m_suspend(snd_card_t *card, unsigned int state)
1087 {
1088         intel8x0_t *chip = card->pm_private_data;
1089         int i;
1090
1091         for (i = 0; i < chip->pcm_devs; i++)
1092                 snd_pcm_suspend_all(chip->pcm[i]);
1093         if (chip->ac97)
1094                 snd_ac97_suspend(chip->ac97);
1095         pci_disable_device(chip->pci);
1096         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1097         return 0;
1098 }
1099
1100 static int intel8x0m_resume(snd_card_t *card, unsigned int state)
1101 {
1102         intel8x0_t *chip = card->pm_private_data;
1103         pci_enable_device(chip->pci);
1104         pci_set_master(chip->pci);
1105         snd_intel8x0_chip_init(chip, 0);
1106         if (chip->ac97)
1107                 snd_ac97_resume(chip->ac97);
1108
1109         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1110         return 0;
1111 }
1112 #endif /* CONFIG_PM */
1113
1114 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1115                                    snd_info_buffer_t * buffer)
1116 {
1117         intel8x0_t *chip = entry->private_data;
1118         unsigned int tmp;
1119
1120         snd_iprintf(buffer, "Intel8x0m\n\n");
1121         if (chip->device_type == DEVICE_ALI)
1122                 return;
1123         tmp = igetdword(chip, ICHREG(GLOB_STA));
1124         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1125         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1126         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1127                         tmp & ICH_PCR ? " primary" : "",
1128                         tmp & ICH_SCR ? " secondary" : "",
1129                         tmp & ICH_TCR ? " tertiary" : "",
1130                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1131 }
1132
1133 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1134 {
1135         snd_info_entry_t *entry;
1136
1137         if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1138                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1139 }
1140
1141 static int snd_intel8x0_dev_free(snd_device_t *device)
1142 {
1143         intel8x0_t *chip = device->device_data;
1144         return snd_intel8x0_free(chip);
1145 }
1146
1147 struct ich_reg_info {
1148         unsigned int int_sta_mask;
1149         unsigned int offset;
1150 };
1151
1152 static int __devinit snd_intel8x0m_create(snd_card_t * card,
1153                                          struct pci_dev *pci,
1154                                          unsigned long device_type,
1155                                          intel8x0_t ** r_intel8x0)
1156 {
1157         intel8x0_t *chip;
1158         int err;
1159         unsigned int i;
1160         unsigned int int_sta_masks;
1161         ichdev_t *ichdev;
1162         static snd_device_ops_t ops = {
1163                 .dev_free =     snd_intel8x0_dev_free,
1164         };
1165         static struct ich_reg_info intel_regs[2] = {
1166                 { ICH_MIINT, 0 },
1167                 { ICH_MOINT, 0x10 },
1168         };
1169         struct ich_reg_info *tbl;
1170
1171         *r_intel8x0 = NULL;
1172
1173         if ((err = pci_enable_device(pci)) < 0)
1174                 return err;
1175
1176         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1177         if (chip == NULL) {
1178                 pci_disable_device(pci);
1179                 return -ENOMEM;
1180         }
1181         spin_lock_init(&chip->reg_lock);
1182         spin_lock_init(&chip->ac97_lock);
1183         chip->device_type = device_type;
1184         chip->card = card;
1185         chip->pci = pci;
1186         chip->irq = -1;
1187
1188         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1189                 kfree(chip);
1190                 pci_disable_device(pci);
1191                 return err;
1192         }
1193
1194         if (device_type == DEVICE_ALI) {
1195                 /* ALI5455 has no ac97 region */
1196                 chip->bmaddr = pci_resource_start(pci, 0);
1197                 goto port_inited;
1198         }
1199
1200         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
1201                 chip->mmio = 1;
1202                 chip->addr = pci_resource_start(pci, 2);
1203                 chip->remap_addr = ioremap_nocache(chip->addr,
1204                                                    pci_resource_len(pci, 2));
1205                 if (chip->remap_addr == NULL) {
1206                         snd_printk("AC'97 space ioremap problem\n");
1207                         snd_intel8x0_free(chip);
1208                         return -EIO;
1209                 }
1210         } else {
1211                 chip->addr = pci_resource_start(pci, 0);
1212         }
1213         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
1214                 chip->bm_mmio = 1;
1215                 chip->bmaddr = pci_resource_start(pci, 3);
1216                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
1217                                                      pci_resource_len(pci, 3));
1218                 if (chip->remap_bmaddr == NULL) {
1219                         snd_printk("Controller space ioremap problem\n");
1220                         snd_intel8x0_free(chip);
1221                         return -EIO;
1222                 }
1223         } else {
1224                 chip->bmaddr = pci_resource_start(pci, 1);
1225         }
1226
1227  port_inited:
1228         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1229                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1230                 snd_intel8x0_free(chip);
1231                 return -EBUSY;
1232         }
1233         chip->irq = pci->irq;
1234         pci_set_master(pci);
1235         synchronize_irq(chip->irq);
1236
1237         /* initialize offsets */
1238         chip->bdbars_count = 2;
1239         tbl = intel_regs;
1240
1241         for (i = 0; i < chip->bdbars_count; i++) {
1242                 ichdev = &chip->ichd[i];
1243                 ichdev->ichd = i;
1244                 ichdev->reg_offset = tbl[i].offset;
1245                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1246                 if (device_type == DEVICE_SIS) {
1247                         /* SiS 7013 swaps the registers */
1248                         ichdev->roff_sr = ICH_REG_OFF_PICB;
1249                         ichdev->roff_picb = ICH_REG_OFF_SR;
1250                 } else {
1251                         ichdev->roff_sr = ICH_REG_OFF_SR;
1252                         ichdev->roff_picb = ICH_REG_OFF_PICB;
1253                 }
1254                 if (device_type == DEVICE_ALI)
1255                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1256         }
1257         /* SIS7013 handles the pcm data in bytes, others are in words */
1258         chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1259
1260         /* allocate buffer descriptor lists */
1261         /* the start of each lists must be aligned to 8 bytes */
1262         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1263                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1264                                 &chip->bdbars) < 0) {
1265                 snd_intel8x0_free(chip);
1266                 return -ENOMEM;
1267         }
1268         /* tables must be aligned to 8 bytes here, but the kernel pages
1269            are much bigger, so we don't care (on i386) */
1270         int_sta_masks = 0;
1271         for (i = 0; i < chip->bdbars_count; i++) {
1272                 ichdev = &chip->ichd[i];
1273                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1274                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1275                 int_sta_masks |= ichdev->int_sta_mask;
1276         }
1277         chip->int_sta_reg = ICH_REG_GLOB_STA;
1278         chip->int_sta_mask = int_sta_masks;
1279
1280         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1281                 snd_intel8x0_free(chip);
1282                 return err;
1283         }
1284
1285         snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1286
1287         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1288                 snd_intel8x0_free(chip);
1289                 return err;
1290         }
1291
1292         snd_card_set_dev(card, &pci->dev);
1293
1294         *r_intel8x0 = chip;
1295         return 0;
1296 }
1297
1298 static struct shortname_table {
1299         unsigned int id;
1300         const char *s;
1301 } shortnames[] __devinitdata = {
1302         { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1303         { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1304         { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1305         { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1306         { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1307         { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1308         { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1309         { 0x7446, "AMD AMD768" },
1310         { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1311         { PCI_DEVICE_ID_NVIDIA_MCP_MODEM, "NVidia nForce" },
1312         { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1313         { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1314         { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1315 #if 0
1316         { 0x5455, "ALi M5455" },
1317         { 0x746d, "AMD AMD8111" },
1318 #endif
1319         { 0 },
1320 };
1321
1322 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1323                                         const struct pci_device_id *pci_id)
1324 {
1325         static int dev;
1326         snd_card_t *card;
1327         intel8x0_t *chip;
1328         int err;
1329         struct shortname_table *name;
1330
1331         if (dev >= SNDRV_CARDS)
1332                 return -ENODEV;
1333         if (!enable[dev]) {
1334                 dev++;
1335                 return -ENOENT;
1336         }
1337
1338         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1339         if (card == NULL)
1340                 return -ENOMEM;
1341
1342         strcpy(card->driver, "ICH-MODEM");
1343         strcpy(card->shortname, "Intel ICH");
1344         for (name = shortnames; name->id; name++) {
1345                 if (pci->device == name->id) {
1346                         strcpy(card->shortname, name->s);
1347                         break;
1348                 }
1349         }
1350         strcat(card->shortname," Modem");
1351
1352         if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1353                 snd_card_free(card);
1354                 return err;
1355         }
1356
1357         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1358                 snd_card_free(card);
1359                 return err;
1360         }
1361         if ((err = snd_intel8x0_pcm(chip)) < 0) {
1362                 snd_card_free(card);
1363                 return err;
1364         }
1365
1366         snd_intel8x0m_proc_init(chip);
1367
1368         sprintf(card->longname, "%s at 0x%lx, irq %i",
1369                 card->shortname, chip->addr, chip->irq);
1370
1371         if ((err = snd_card_register(card)) < 0) {
1372                 snd_card_free(card);
1373                 return err;
1374         }
1375         pci_set_drvdata(pci, card);
1376         dev++;
1377         return 0;
1378 }
1379
1380 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1381 {
1382         snd_card_free(pci_get_drvdata(pci));
1383         pci_set_drvdata(pci, NULL);
1384 }
1385
1386 static struct pci_driver driver = {
1387         .name = "Intel ICH Modem",
1388         .id_table = snd_intel8x0m_ids,
1389         .probe = snd_intel8x0m_probe,
1390         .remove = __devexit_p(snd_intel8x0m_remove),
1391         SND_PCI_PM_CALLBACKS
1392 };
1393
1394
1395 static int __init alsa_card_intel8x0m_init(void)
1396 {
1397         return pci_module_init(&driver);
1398 }
1399
1400 static void __exit alsa_card_intel8x0m_exit(void)
1401 {
1402         pci_unregister_driver(&driver);
1403 }
1404
1405 module_init(alsa_card_intel8x0m_init)
1406 module_exit(alsa_card_intel8x0m_exit)