sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/moduleparam.h>
  43 #include <sound/core.h>
  44 #include <sound/info.h>
  45 #include <sound/control.h>
  46 #include <sound/pcm.h>
  47 #include <sound/mpu401.h>
  48 #include <sound/ac97_codec.h>
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  68 module_param_array(id, charp, NULL, 0444);
  69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  70 module_param_array(enable, bool, NULL, 0444);
  71 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  72 module_param_array(external_amp, bool, NULL, 0444);
  73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  74 module_param_array(amp_gpio, int, NULL, 0444);
  75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  76
  77 #define MAX_PLAYBACKS   2
  78 #define MAX_CAPTURES    1
  79 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  80
  81
  82 /*
  83  * maestro3 registers
  84  */
  85
  86 /* Allegro PCI configuration registers */
  87 #define PCI_LEGACY_AUDIO_CTRL   0x40
  88 #define SOUND_BLASTER_ENABLE    0x00000001
  89 #define FM_SYNTHESIS_ENABLE     0x00000002
  90 #define GAME_PORT_ENABLE        0x00000004
  91 #define MPU401_IO_ENABLE        0x00000008
  92 #define MPU401_IRQ_ENABLE       0x00000010
  93 #define ALIAS_10BIT_IO          0x00000020
  94 #define SB_DMA_MASK             0x000000C0
  95 #define SB_DMA_0                0x00000040
  96 #define SB_DMA_1                0x00000040
  97 #define SB_DMA_R                0x00000080
  98 #define SB_DMA_3                0x000000C0
  99 #define SB_IRQ_MASK             0x00000700
 100 #define SB_IRQ_5                0x00000000
 101 #define SB_IRQ_7                0x00000100
 102 #define SB_IRQ_9                0x00000200
 103 #define SB_IRQ_10               0x00000300
 104 #define MIDI_IRQ_MASK           0x00003800
 105 #define SERIAL_IRQ_ENABLE       0x00004000
 106 #define DISABLE_LEGACY          0x00008000
 107
 108 #define PCI_ALLEGRO_CONFIG      0x50
 109 #define SB_ADDR_240             0x00000004
 110 #define MPU_ADDR_MASK           0x00000018
 111 #define MPU_ADDR_330            0x00000000
 112 #define MPU_ADDR_300            0x00000008
 113 #define MPU_ADDR_320            0x00000010
 114 #define MPU_ADDR_340            0x00000018
 115 #define USE_PCI_TIMING          0x00000040
 116 #define POSTED_WRITE_ENABLE     0x00000080
 117 #define DMA_POLICY_MASK         0x00000700
 118 #define DMA_DDMA                0x00000000
 119 #define DMA_TDMA                0x00000100
 120 #define DMA_PCPCI               0x00000200
 121 #define DMA_WBDMA16             0x00000400
 122 #define DMA_WBDMA4              0x00000500
 123 #define DMA_WBDMA2              0x00000600
 124 #define DMA_WBDMA1              0x00000700
 125 #define DMA_SAFE_GUARD          0x00000800
 126 #define HI_PERF_GP_ENABLE       0x00001000
 127 #define PIC_SNOOP_MODE_0        0x00002000
 128 #define PIC_SNOOP_MODE_1        0x00004000
 129 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 130 #define RING_IN_ENABLE          0x00010000
 131 #define SPDIF_TEST_MODE         0x00020000
 132 #define CLK_MULT_MODE_SELECT_2  0x00040000
 133 #define EEPROM_WRITE_ENABLE     0x00080000
 134 #define CODEC_DIR_IN            0x00100000
 135 #define HV_BUTTON_FROM_GD       0x00200000
 136 #define REDUCED_DEBOUNCE        0x00400000
 137 #define HV_CTRL_ENABLE          0x00800000
 138 #define SPDIF_ENABLE            0x01000000
 139 #define CLK_DIV_SELECT          0x06000000
 140 #define CLK_DIV_BY_48           0x00000000
 141 #define CLK_DIV_BY_49           0x02000000
 142 #define CLK_DIV_BY_50           0x04000000
 143 #define CLK_DIV_RESERVED        0x06000000
 144 #define PM_CTRL_ENABLE          0x08000000
 145 #define CLK_MULT_MODE_SELECT    0x30000000
 146 #define CLK_MULT_MODE_SHIFT     28
 147 #define CLK_MULT_MODE_0         0x00000000
 148 #define CLK_MULT_MODE_1         0x10000000
 149 #define CLK_MULT_MODE_2         0x20000000
 150 #define CLK_MULT_MODE_3         0x30000000
 151 #define INT_CLK_SELECT          0x40000000
 152 #define INT_CLK_MULT_RESET      0x80000000
 153
 154 /* M3 */
 155 #define INT_CLK_SRC_NOT_PCI     0x00100000
 156 #define INT_CLK_MULT_ENABLE     0x80000000
 157
 158 #define PCI_ACPI_CONTROL        0x54
 159 #define PCI_ACPI_D0             0x00000000
 160 #define PCI_ACPI_D1             0xB4F70000
 161 #define PCI_ACPI_D2             0xB4F7B4F7
 162
 163 #define PCI_USER_CONFIG         0x58
 164 #define EXT_PCI_MASTER_ENABLE   0x00000001
 165 #define SPDIF_OUT_SELECT        0x00000002
 166 #define TEST_PIN_DIR_CTRL       0x00000004
 167 #define AC97_CODEC_TEST         0x00000020
 168 #define TRI_STATE_BUFFER        0x00000080
 169 #define IN_CLK_12MHZ_SELECT     0x00000100
 170 #define MULTI_FUNC_DISABLE      0x00000200
 171 #define EXT_MASTER_PAIR_SEL     0x00000400
 172 #define PCI_MASTER_SUPPORT      0x00000800
 173 #define STOP_CLOCK_ENABLE       0x00001000
 174 #define EAPD_DRIVE_ENABLE       0x00002000
 175 #define REQ_TRI_STATE_ENABLE    0x00004000
 176 #define REQ_LOW_ENABLE          0x00008000
 177 #define MIDI_1_ENABLE           0x00010000
 178 #define MIDI_2_ENABLE           0x00020000
 179 #define SB_AUDIO_SYNC           0x00040000
 180 #define HV_CTRL_TEST            0x00100000
 181 #define SOUNDBLASTER_TEST       0x00400000
 182
 183 #define PCI_USER_CONFIG_C       0x5C
 184
 185 #define PCI_DDMA_CTRL           0x60
 186 #define DDMA_ENABLE             0x00000001
 187
 188
 189 /* Allegro registers */
 190 #define HOST_INT_CTRL           0x18
 191 #define SB_INT_ENABLE           0x0001
 192 #define MPU401_INT_ENABLE       0x0002
 193 #define ASSP_INT_ENABLE         0x0010
 194 #define RING_INT_ENABLE         0x0020
 195 #define HV_INT_ENABLE           0x0040
 196 #define CLKRUN_GEN_ENABLE       0x0100
 197 #define HV_CTRL_TO_PME          0x0400
 198 #define SOFTWARE_RESET_ENABLE   0x8000
 199
 200 /*
 201  * should be using the above defines, probably.
 202  */
 203 #define REGB_ENABLE_RESET               0x01
 204 #define REGB_STOP_CLOCK                 0x10
 205
 206 #define HOST_INT_STATUS         0x1A
 207 #define SB_INT_PENDING          0x01
 208 #define MPU401_INT_PENDING      0x02
 209 #define ASSP_INT_PENDING        0x10
 210 #define RING_INT_PENDING        0x20
 211 #define HV_INT_PENDING          0x40
 212
 213 #define HARDWARE_VOL_CTRL       0x1B
 214 #define SHADOW_MIX_REG_VOICE    0x1C
 215 #define HW_VOL_COUNTER_VOICE    0x1D
 216 #define SHADOW_MIX_REG_MASTER   0x1E
 217 #define HW_VOL_COUNTER_MASTER   0x1F
 218
 219 #define CODEC_COMMAND           0x30
 220 #define CODEC_READ_B            0x80
 221
 222 #define CODEC_STATUS            0x30
 223 #define CODEC_BUSY_B            0x01
 224
 225 #define CODEC_DATA              0x32
 226
 227 #define RING_BUS_CTRL_A         0x36
 228 #define RAC_PME_ENABLE          0x0100
 229 #define RAC_SDFS_ENABLE         0x0200
 230 #define LAC_PME_ENABLE          0x0400
 231 #define LAC_SDFS_ENABLE         0x0800
 232 #define SERIAL_AC_LINK_ENABLE   0x1000
 233 #define IO_SRAM_ENABLE          0x2000
 234 #define IIS_INPUT_ENABLE        0x8000
 235
 236 #define RING_BUS_CTRL_B         0x38
 237 #define SECOND_CODEC_ID_MASK    0x0003
 238 #define SPDIF_FUNC_ENABLE       0x0010
 239 #define SECOND_AC_ENABLE        0x0020
 240 #define SB_MODULE_INTF_ENABLE   0x0040
 241 #define SSPE_ENABLE             0x0040
 242 #define M3I_DOCK_ENABLE         0x0080
 243
 244 #define SDO_OUT_DEST_CTRL       0x3A
 245 #define COMMAND_ADDR_OUT        0x0003
 246 #define PCM_LR_OUT_LOCAL        0x0000
 247 #define PCM_LR_OUT_REMOTE       0x0004
 248 #define PCM_LR_OUT_MUTE         0x0008
 249 #define PCM_LR_OUT_BOTH         0x000C
 250 #define LINE1_DAC_OUT_LOCAL     0x0000
 251 #define LINE1_DAC_OUT_REMOTE    0x0010
 252 #define LINE1_DAC_OUT_MUTE      0x0020
 253 #define LINE1_DAC_OUT_BOTH      0x0030
 254 #define PCM_CLS_OUT_LOCAL       0x0000
 255 #define PCM_CLS_OUT_REMOTE      0x0040
 256 #define PCM_CLS_OUT_MUTE        0x0080
 257 #define PCM_CLS_OUT_BOTH        0x00C0
 258 #define PCM_RLF_OUT_LOCAL       0x0000
 259 #define PCM_RLF_OUT_REMOTE      0x0100
 260 #define PCM_RLF_OUT_MUTE        0x0200
 261 #define PCM_RLF_OUT_BOTH        0x0300
 262 #define LINE2_DAC_OUT_LOCAL     0x0000
 263 #define LINE2_DAC_OUT_REMOTE    0x0400
 264 #define LINE2_DAC_OUT_MUTE      0x0800
 265 #define LINE2_DAC_OUT_BOTH      0x0C00
 266 #define HANDSET_OUT_LOCAL       0x0000
 267 #define HANDSET_OUT_REMOTE      0x1000
 268 #define HANDSET_OUT_MUTE        0x2000
 269 #define HANDSET_OUT_BOTH        0x3000
 270 #define IO_CTRL_OUT_LOCAL       0x0000
 271 #define IO_CTRL_OUT_REMOTE      0x4000
 272 #define IO_CTRL_OUT_MUTE        0x8000
 273 #define IO_CTRL_OUT_BOTH        0xC000
 274
 275 #define SDO_IN_DEST_CTRL        0x3C
 276 #define STATUS_ADDR_IN          0x0003
 277 #define PCM_LR_IN_LOCAL         0x0000
 278 #define PCM_LR_IN_REMOTE        0x0004
 279 #define PCM_LR_RESERVED         0x0008
 280 #define PCM_LR_IN_BOTH          0x000C
 281 #define LINE1_ADC_IN_LOCAL      0x0000
 282 #define LINE1_ADC_IN_REMOTE     0x0010
 283 #define LINE1_ADC_IN_MUTE       0x0020
 284 #define MIC_ADC_IN_LOCAL        0x0000
 285 #define MIC_ADC_IN_REMOTE       0x0040
 286 #define MIC_ADC_IN_MUTE         0x0080
 287 #define LINE2_DAC_IN_LOCAL      0x0000
 288 #define LINE2_DAC_IN_REMOTE     0x0400
 289 #define LINE2_DAC_IN_MUTE       0x0800
 290 #define HANDSET_IN_LOCAL        0x0000
 291 #define HANDSET_IN_REMOTE       0x1000
 292 #define HANDSET_IN_MUTE         0x2000
 293 #define IO_STATUS_IN_LOCAL      0x0000
 294 #define IO_STATUS_IN_REMOTE     0x4000
 295
 296 #define SPDIF_IN_CTRL           0x3E
 297 #define SPDIF_IN_ENABLE         0x0001
 298
 299 #define GPIO_DATA               0x60
 300 #define GPIO_DATA_MASK          0x0FFF
 301 #define GPIO_HV_STATUS          0x3000
 302 #define GPIO_PME_STATUS         0x4000
 303
 304 #define GPIO_MASK               0x64
 305 #define GPIO_DIRECTION          0x68
 306 #define GPO_PRIMARY_AC97        0x0001
 307 #define GPI_LINEOUT_SENSE       0x0004
 308 #define GPO_SECONDARY_AC97      0x0008
 309 #define GPI_VOL_DOWN            0x0010
 310 #define GPI_VOL_UP              0x0020
 311 #define GPI_IIS_CLK             0x0040
 312 #define GPI_IIS_LRCLK           0x0080
 313 #define GPI_IIS_DATA            0x0100
 314 #define GPI_DOCKING_STATUS      0x0100
 315 #define GPI_HEADPHONE_SENSE     0x0200
 316 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 317
 318 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 319 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 320
 321 /* M3 */
 322 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 323
 324 #define ASSP_INDEX_PORT         0x80
 325 #define ASSP_MEMORY_PORT        0x82
 326 #define ASSP_DATA_PORT          0x84
 327
 328 #define MPU401_DATA_PORT        0x98
 329 #define MPU401_STATUS_PORT      0x99
 330
 331 #define CLK_MULT_DATA_PORT      0x9C
 332
 333 #define ASSP_CONTROL_A          0xA2
 334 #define ASSP_0_WS_ENABLE        0x01
 335 #define ASSP_CTRL_A_RESERVED1   0x02
 336 #define ASSP_CTRL_A_RESERVED2   0x04
 337 #define ASSP_CLK_49MHZ_SELECT   0x08
 338 #define FAST_PLU_ENABLE         0x10
 339 #define ASSP_CTRL_A_RESERVED3   0x20
 340 #define DSP_CLK_36MHZ_SELECT    0x40
 341
 342 #define ASSP_CONTROL_B          0xA4
 343 #define RESET_ASSP              0x00
 344 #define RUN_ASSP                0x01
 345 #define ENABLE_ASSP_CLOCK       0x00
 346 #define STOP_ASSP_CLOCK         0x10
 347 #define RESET_TOGGLE            0x40
 348
 349 #define ASSP_CONTROL_C          0xA6
 350 #define ASSP_HOST_INT_ENABLE    0x01
 351 #define FM_ADDR_REMAP_DISABLE   0x02
 352 #define HOST_WRITE_PORT_ENABLE  0x08
 353
 354 #define ASSP_HOST_INT_STATUS    0xAC
 355 #define DSP2HOST_REQ_PIORECORD  0x01
 356 #define DSP2HOST_REQ_I2SRATE    0x02
 357 #define DSP2HOST_REQ_TIMER      0x04
 358
 359 /* AC97 registers */
 360 /* XXX fix this crap up */
 361 /*#define AC97_RESET              0x00*/
 362
 363 #define AC97_VOL_MUTE_B         0x8000
 364 #define AC97_VOL_M              0x1F
 365 #define AC97_LEFT_VOL_S         8
 366
 367 #define AC97_MASTER_VOL         0x02
 368 #define AC97_LINE_LEVEL_VOL     0x04
 369 #define AC97_MASTER_MONO_VOL    0x06
 370 #define AC97_PC_BEEP_VOL        0x0A
 371 #define AC97_PC_BEEP_VOL_M      0x0F
 372 #define AC97_SROUND_MASTER_VOL  0x38
 373 #define AC97_PC_BEEP_VOL_S      1
 374
 375 /*#define AC97_PHONE_VOL          0x0C
 376 #define AC97_MIC_VOL            0x0E*/
 377 #define AC97_MIC_20DB_ENABLE    0x40
 378
 379 /*#define AC97_LINEIN_VOL         0x10
 380 #define AC97_CD_VOL             0x12
 381 #define AC97_VIDEO_VOL          0x14
 382 #define AC97_AUX_VOL            0x16*/
 383 #define AC97_PCM_OUT_VOL        0x18
 384 /*#define AC97_RECORD_SELECT      0x1A*/
 385 #define AC97_RECORD_MIC         0x00
 386 #define AC97_RECORD_CD          0x01
 387 #define AC97_RECORD_VIDEO       0x02
 388 #define AC97_RECORD_AUX         0x03
 389 #define AC97_RECORD_MONO_MUX    0x02
 390 #define AC97_RECORD_DIGITAL     0x03
 391 #define AC97_RECORD_LINE        0x04
 392 #define AC97_RECORD_STEREO      0x05
 393 #define AC97_RECORD_MONO        0x06
 394 #define AC97_RECORD_PHONE       0x07
 395
 396 /*#define AC97_RECORD_GAIN        0x1C*/
 397 #define AC97_RECORD_VOL_M       0x0F
 398
 399 /*#define AC97_GENERAL_PURPOSE    0x20*/
 400 #define AC97_POWER_DOWN_CTRL    0x26
 401 #define AC97_ADC_READY          0x0001
 402 #define AC97_DAC_READY          0x0002
 403 #define AC97_ANALOG_READY       0x0004
 404 #define AC97_VREF_ON            0x0008
 405 #define AC97_PR0                0x0100
 406 #define AC97_PR1                0x0200
 407 #define AC97_PR2                0x0400
 408 #define AC97_PR3                0x0800
 409 #define AC97_PR4                0x1000
 410
 411 #define AC97_RESERVED1          0x28
 412
 413 #define AC97_VENDOR_TEST        0x5A
 414
 415 #define AC97_CLOCK_DELAY        0x5C
 416 #define AC97_LINEOUT_MUX_SEL    0x0001
 417 #define AC97_MONO_MUX_SEL       0x0002
 418 #define AC97_CLOCK_DELAY_SEL    0x1F
 419 #define AC97_DAC_CDS_SHIFT      6
 420 #define AC97_ADC_CDS_SHIFT      11
 421
 422 #define AC97_MULTI_CHANNEL_SEL  0x74
 423
 424 /*#define AC97_VENDOR_ID1         0x7C
 425 #define AC97_VENDOR_ID2         0x7E*/
 426
 427 /*
 428  * ASSP control regs
 429  */
 430 #define DSP_PORT_TIMER_COUNT    0x06
 431
 432 #define DSP_PORT_MEMORY_INDEX   0x80
 433
 434 #define DSP_PORT_MEMORY_TYPE    0x82
 435 #define MEMTYPE_INTERNAL_CODE   0x0002
 436 #define MEMTYPE_INTERNAL_DATA   0x0003
 437 #define MEMTYPE_MASK            0x0003
 438
 439 #define DSP_PORT_MEMORY_DATA    0x84
 440
 441 #define DSP_PORT_CONTROL_REG_A  0xA2
 442 #define DSP_PORT_CONTROL_REG_B  0xA4
 443 #define DSP_PORT_CONTROL_REG_C  0xA6
 444
 445 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 446 #define REV_A_CODE_MEMORY_END           0x0FFF
 447 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 448 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 449
 450 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 451 #define REV_B_CODE_MEMORY_END           0x0BFF
 452 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 453 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 454
 455 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 456 #define REV_A_DATA_MEMORY_END           0x2FFF
 457 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 458 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 459
 460 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 461 #define REV_B_DATA_MEMORY_END           0x2BFF
 462 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 463 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 464
 465
 466 #define NUM_UNITS_KERNEL_CODE          16
 467 #define NUM_UNITS_KERNEL_DATA           2
 468
 469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 471
 472 /*
 473  * Kernel data layout
 474  */
 475
 476 #define DP_SHIFT_COUNT                  7
 477
 478 #define KDATA_BASE_ADDR                 0x1000
 479 #define KDATA_BASE_ADDR2                0x1080
 480
 481 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 482 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 483 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 484 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 485 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 486 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 487 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 488 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 489 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 490
 491 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 492 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 493
 494 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 495 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 496 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 497 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 498 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 499 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 500 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 501 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 502 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 503 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 504
 505 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 507
 508 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 509 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 510
 511 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 512 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 513
 514 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 515 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 516 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 517
 518 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 519 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 520 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 521 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 522 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 523
 524 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 525 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 527
 528 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 529 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 530 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 531
 532 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 533 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 534 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 535 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 536 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 537 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 538 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 539 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 540 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 541 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 542
 543 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 544 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 545 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 546
 547 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 548 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 549
 550 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 551 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 552 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 553
 554 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 555 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 556 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 557 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 558 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 559 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 560
 561 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 562 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 563 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 564 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 565 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 566 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 567
 568 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 569 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 570 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 571 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 572 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 573 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 574
 575 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 576 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 577 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 578 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 579
 580 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 581 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 582
 583 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 584 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 585
 586 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 587 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 588 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 589 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 590 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 591
 592 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 593 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 594
 595 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 596 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 597 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 598
 599 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 600 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 601
 602 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 603
 604 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 605 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 606 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 607 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 608 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 609 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 610 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 611 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 612 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 613 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 614 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 615 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 616
 617 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 618 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 619 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 620 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 621
 622 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 623 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 624
 625 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 626 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 627 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 628 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 629
 630 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 631 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 632 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 633 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 634 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 635
 636 /*
 637  * second 'segment' (?) reserved for mixer
 638  * buffers..
 639  */
 640
 641 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 642 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 643 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 644 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 645 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 646 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 647 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 648 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 649 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 650 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 651 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 652 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 653 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 654 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 655 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 656 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 657
 658 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 659 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 660 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 661 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 662 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 663 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 664 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 665 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 666 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 667 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 668 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 669
 670 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 671 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 672 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 673 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 674 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 675 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 676
 677 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 678 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 679 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 680 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 681
 682 /*
 683  * client data area offsets
 684  */
 685 #define CDATA_INSTANCE_READY            0x00
 686
 687 #define CDATA_HOST_SRC_ADDRL            0x01
 688 #define CDATA_HOST_SRC_ADDRH            0x02
 689 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 690 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 691 #define CDATA_HOST_SRC_CURRENTL         0x05
 692 #define CDATA_HOST_SRC_CURRENTH         0x06
 693
 694 #define CDATA_IN_BUF_CONNECT            0x07
 695 #define CDATA_OUT_BUF_CONNECT           0x08
 696
 697 #define CDATA_IN_BUF_BEGIN              0x09
 698 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 699 #define CDATA_IN_BUF_HEAD               0x0B
 700 #define CDATA_IN_BUF_TAIL               0x0C
 701 #define CDATA_OUT_BUF_BEGIN             0x0D
 702 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 703 #define CDATA_OUT_BUF_HEAD              0x0F
 704 #define CDATA_OUT_BUF_TAIL              0x10
 705
 706 #define CDATA_DMA_CONTROL               0x11
 707 #define CDATA_RESERVED                  0x12
 708
 709 #define CDATA_FREQUENCY                 0x13
 710 #define CDATA_LEFT_VOLUME               0x14
 711 #define CDATA_RIGHT_VOLUME              0x15
 712 #define CDATA_LEFT_SUR_VOL              0x16
 713 #define CDATA_RIGHT_SUR_VOL             0x17
 714
 715 #define CDATA_HEADER_LEN                0x18
 716
 717 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 718 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 719 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 720 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 721 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 722 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 723 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 725
 726 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 727 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 730 #define MINISRC_BIQUAD_STAGE    2
 731 #define MINISRC_COEF_LOC          0x175
 732
 733 #define DMACONTROL_BLOCK_MASK           0x000F
 734 #define  DMAC_BLOCK0_SELECTOR           0x0000
 735 #define  DMAC_BLOCK1_SELECTOR           0x0001
 736 #define  DMAC_BLOCK2_SELECTOR           0x0002
 737 #define  DMAC_BLOCK3_SELECTOR           0x0003
 738 #define  DMAC_BLOCK4_SELECTOR           0x0004
 739 #define  DMAC_BLOCK5_SELECTOR           0x0005
 740 #define  DMAC_BLOCK6_SELECTOR           0x0006
 741 #define  DMAC_BLOCK7_SELECTOR           0x0007
 742 #define  DMAC_BLOCK8_SELECTOR           0x0008
 743 #define  DMAC_BLOCK9_SELECTOR           0x0009
 744 #define  DMAC_BLOCKA_SELECTOR           0x000A
 745 #define  DMAC_BLOCKB_SELECTOR           0x000B
 746 #define  DMAC_BLOCKC_SELECTOR           0x000C
 747 #define  DMAC_BLOCKD_SELECTOR           0x000D
 748 #define  DMAC_BLOCKE_SELECTOR           0x000E
 749 #define  DMAC_BLOCKF_SELECTOR           0x000F
 750 #define DMACONTROL_PAGE_MASK            0x00F0
 751 #define  DMAC_PAGE0_SELECTOR            0x0030
 752 #define  DMAC_PAGE1_SELECTOR            0x0020
 753 #define  DMAC_PAGE2_SELECTOR            0x0010
 754 #define  DMAC_PAGE3_SELECTOR            0x0000
 755 #define DMACONTROL_AUTOREPEAT           0x1000
 756 #define DMACONTROL_STOPPED              0x2000
 757 #define DMACONTROL_DIRECTION            0x0100
 758
 759 /*
 760  * an arbitrary volume we set the internal
 761  * volume settings to so that the ac97 volume
 762  * range is a little less insane.  0x7fff is
 763  * max.
 764  */
 765 #define ARB_VOLUME ( 0x6800 )
 766
 767 /*
 768  */
 769
 770 typedef struct snd_m3_dma m3_dma_t;
 771 typedef struct snd_m3 m3_t;
 772
 773 /* quirk lists */
 774 struct m3_quirk {
 775         const char *name;       /* device name */
 776         u16 vendor, device;     /* subsystem ids */
 777         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 778         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 779                                    (e.g. for IrDA on Dell Inspirons) */
 780 };
 781
 782 struct m3_list {
 783         int curlen;
 784         int mem_addr;
 785         int max;
 786 };
 787
 788 struct snd_m3_dma {
 789
 790         int number;
 791         m3_t *chip;
 792         snd_pcm_substream_t *substream;
 793
 794         struct assp_instance {
 795                 unsigned short code, data;
 796         } inst;
 797
 798         int running;
 799         int opened;
 800
 801         unsigned long buffer_addr;
 802         int dma_size;
 803         int period_size;
 804         unsigned int hwptr;
 805         int count;
 806
 807         int index[3];
 808         struct m3_list *index_list[3];
 809
 810         int in_lists;
 811
 812         struct list_head list;
 813
 814 };
 815
 816 struct snd_m3 {
 817
 818         snd_card_t *card;
 819
 820         unsigned long iobase;
 821
 822         int irq;
 823         int allegro_flag : 1;
 824
 825         ac97_t *ac97;
 826
 827         snd_pcm_t *pcm;
 828
 829         struct pci_dev *pci;
 830         struct m3_quirk *quirk;
 831
 832         int dacs_active;
 833         int timer_users;
 834
 835         struct m3_list  msrc_list;
 836         struct m3_list  mixer_list;
 837         struct m3_list  adc1_list;
 838         struct m3_list  dma_list;
 839
 840         /* for storing reset state..*/
 841         u8 reset_state;
 842
 843         int external_amp;
 844         int amp_gpio;
 845
 846         /* midi */
 847         snd_rawmidi_t *rmidi;
 848
 849         /* pcm streams */
 850         int num_substreams;
 851         m3_dma_t *substreams;
 852
 853         spinlock_t reg_lock;
 854
 855 #ifdef CONFIG_PM
 856         u16 *suspend_mem;
 857 #endif
 858 };
 859
 860 /*
 861  * pci ids
 862  */
 863
 864 #ifndef PCI_VENDOR_ID_ESS
 865 #define PCI_VENDOR_ID_ESS         0x125D
 866 #endif
 867 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 868 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 869 #endif
 870 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 871 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 872 #endif
 873 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 874 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 875 #endif
 876 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 877 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 878 #endif
 879 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 880 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 881 #endif
 882 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 883 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 884 #endif
 885 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 886 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 887 #endif
 888 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 889 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 890 #endif
 891
 892 static struct pci_device_id snd_m3_ids[] = {
 893         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 894          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 895         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 896          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 897         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 898          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 899         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 900          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 901         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 902          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 903         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 904          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 905         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 906          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 907         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 908          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 909         {0,},
 910 };
 911
 912 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 913
 914 static struct m3_quirk m3_quirk_list[] = {
 915         /* panasonic CF-28 "toughbook" */
 916         {
 917                 .name = "Panasonic CF-28",
 918                 .vendor = 0x10f7,
 919                 .device = 0x833e,
 920                 .amp_gpio = 0x0d,
 921         },
 922         /* panasonic CF-72 "toughbook" */
 923         {
 924                 .name = "Panasonic CF-72",
 925                 .vendor = 0x10f7,
 926                 .device = 0x833d,
 927                 .amp_gpio = 0x0d,
 928         },
 929         /* Dell Inspiron 4000 */
 930         {
 931                 .name = "Dell Inspiron 4000",
 932                 .vendor = 0x1028,
 933                 .device = 0x00b0,
 934                 .amp_gpio = -1,
 935                 .irda_workaround = 1,
 936         },
 937         /* Dell Inspiron 8000 */
 938         {
 939                 .name = "Dell Inspiron 8000",
 940                 .vendor = 0x1028,
 941                 .device = 0x00a4,
 942                 .amp_gpio = -1,
 943                 .irda_workaround = 1,
 944         },
 945         /* Dell Inspiron 8100 */
 946         {
 947                 .name = "Dell Inspiron 8100",
 948                 .vendor = 0x1028,
 949                 .device = 0x00e6,
 950                 .amp_gpio = -1,
 951                 .irda_workaround = 1,
 952         },
 953         /* NEC LM800J/7 */
 954         {
 955                 .name = "NEC LM800J/7",
 956                 .vendor = 0x1033,
 957                 .device = 0x80f1,
 958                 .amp_gpio = 0x03,
 959         },
 960         /* END */
 961         { NULL }
 962 };
 963
 964
 965 /*
 966  * lowlevel functions
 967  */
 968
 969 #define big_mdelay(msec) do {\
 970         set_current_state(TASK_UNINTERRUPTIBLE);\
 971         schedule_timeout(((msec) * HZ) / 1000);\
 972 } while (0)
 973
 974 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 975 {
 976         outw(value, chip->iobase + reg);
 977 }
 978
 979 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 980 {
 981         return inw(chip->iobase + reg);
 982 }
 983
 984 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 985 {
 986         outb(value, chip->iobase + reg);
 987 }
 988
 989 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
 990 {
 991         return inb(chip->iobase + reg);
 992 }
 993
 994 /*
 995  * access 16bit words to the code or data regions of the dsp's memory.
 996  * index addresses 16bit words.
 997  */
 998 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
 999 {
1000         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1001         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1002         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1003 }
1004
1005 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1006 {
1007         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1008         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1009         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1010 }
1011
1012 static void snd_m3_assp_halt(m3_t *chip)
1013 {
1014         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1015         big_mdelay(10);
1016         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1017 }
1018
1019 static void snd_m3_assp_continue(m3_t *chip)
1020 {
1021         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1022 }
1023
1024
1025 /*
1026  * This makes me sad. the maestro3 has lists
1027  * internally that must be packed.. 0 terminates,
1028  * apparently, or maybe all unused entries have
1029  * to be 0, the lists have static lengths set
1030  * by the binary code images.
1031  */
1032
1033 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1034 {
1035         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1036                           list->mem_addr + list->curlen,
1037                           val);
1038         return list->curlen++;
1039 }
1040
1041 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1042 {
1043         u16  val;
1044         int lastindex = list->curlen - 1;
1045
1046         if (index != lastindex) {
1047                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1048                                        list->mem_addr + lastindex);
1049                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1050                                   list->mem_addr + index,
1051                                   val);
1052         }
1053
1054         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055                           list->mem_addr + lastindex,
1056                           0);
1057
1058         list->curlen--;
1059 }
1060
1061 static void snd_m3_inc_timer_users(m3_t *chip)
1062 {
1063         chip->timer_users++;
1064         if (chip->timer_users != 1)
1065                 return;
1066
1067         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068                           KDATA_TIMER_COUNT_RELOAD,
1069                           240);
1070
1071         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1072                           KDATA_TIMER_COUNT_CURRENT,
1073                           240);
1074
1075         snd_m3_outw(chip,
1076                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1077                     HOST_INT_CTRL);
1078 }
1079
1080 static void snd_m3_dec_timer_users(m3_t *chip)
1081 {
1082         chip->timer_users--;
1083         if (chip->timer_users > 0)
1084                 return;
1085
1086         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1087                           KDATA_TIMER_COUNT_RELOAD,
1088                           0);
1089
1090         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1091                           KDATA_TIMER_COUNT_CURRENT,
1092                           0);
1093
1094         snd_m3_outw(chip,
1095                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1096                     HOST_INT_CTRL);
1097 }
1098
1099 /*
1100  * start/stop
1101  */
1102
1103 /* spinlock held! */
1104 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1105 {
1106         if (! s || ! subs)
1107                 return -EINVAL;
1108
1109         snd_m3_inc_timer_users(chip);
1110         switch (subs->stream) {
1111         case SNDRV_PCM_STREAM_PLAYBACK:
1112                 chip->dacs_active++;
1113                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1114                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1115                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116                                   KDATA_MIXER_TASK_NUMBER,
1117                                   chip->dacs_active);
1118                 break;
1119         case SNDRV_PCM_STREAM_CAPTURE:
1120                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1121                                   KDATA_ADC1_REQUEST, 1);
1122                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1123                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1124                 break;
1125         }
1126         return 0;
1127 }
1128
1129 /* spinlock held! */
1130 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1131 {
1132         if (! s || ! subs)
1133                 return -EINVAL;
1134
1135         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1136                           s->inst.data + CDATA_INSTANCE_READY, 0);
1137         snd_m3_dec_timer_users(chip);
1138         switch (subs->stream) {
1139         case SNDRV_PCM_STREAM_PLAYBACK:
1140                 chip->dacs_active--;
1141                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142                                   KDATA_MIXER_TASK_NUMBER,
1143                                   chip->dacs_active);
1144                 break;
1145         case SNDRV_PCM_STREAM_CAPTURE:
1146                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1147                                   KDATA_ADC1_REQUEST, 0);
1148                 break;
1149         }
1150         return 0;
1151 }
1152
1153 static int
1154 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1155 {
1156         m3_t *chip = snd_pcm_substream_chip(subs);
1157         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1158         int err = -EINVAL;
1159
1160         snd_assert(s != NULL, return -ENXIO);
1161
1162         spin_lock(&chip->reg_lock);
1163         switch (cmd) {
1164         case SNDRV_PCM_TRIGGER_START:
1165         case SNDRV_PCM_TRIGGER_RESUME:
1166                 if (s->running)
1167                         err = -EBUSY;
1168                 else {
1169                         s->running = 1;
1170                         err = snd_m3_pcm_start(chip, s, subs);
1171                 }
1172                 break;
1173         case SNDRV_PCM_TRIGGER_STOP:
1174         case SNDRV_PCM_TRIGGER_SUSPEND:
1175                 if (! s->running)
1176                         err = 0; /* should return error? */
1177                 else {
1178                         s->running = 0;
1179                         err = snd_m3_pcm_stop(chip, s, subs);
1180                 }
1181                 break;
1182         }
1183         spin_unlock(&chip->reg_lock);
1184         return err;
1185 }
1186
1187 /*
1188  * setup
1189  */
1190 static void
1191 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1192 {
1193         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1194         snd_pcm_runtime_t *runtime = subs->runtime;
1195
1196         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1197                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1198                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1199         } else {
1200                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1201                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1202         }
1203         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1204         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1205
1206         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1207         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1208         s->hwptr = 0;
1209         s->count = 0;
1210
1211 #define LO(x) ((x) & 0xffff)
1212 #define HI(x) LO((x) >> 16)
1213
1214         /* host dma buffer pointers */
1215         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1216                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1217                           LO(s->buffer_addr));
1218
1219         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1220                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1221                           HI(s->buffer_addr));
1222
1223         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1224                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1225                           LO(s->buffer_addr + s->dma_size));
1226
1227         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1228                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1229                           HI(s->buffer_addr + s->dma_size));
1230
1231         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1232                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1233                           LO(s->buffer_addr));
1234
1235         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1236                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1237                           HI(s->buffer_addr));
1238 #undef LO
1239 #undef HI
1240
1241         /* dsp buffers */
1242
1243         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244                           s->inst.data + CDATA_IN_BUF_BEGIN,
1245                           dsp_in_buffer);
1246
1247         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1249                           dsp_in_buffer + (dsp_in_size / 2));
1250
1251         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252                           s->inst.data + CDATA_IN_BUF_HEAD,
1253                           dsp_in_buffer);
1254
1255         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256                           s->inst.data + CDATA_IN_BUF_TAIL,
1257                           dsp_in_buffer);
1258
1259         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1261                           dsp_out_buffer);
1262
1263         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1265                           dsp_out_buffer + (dsp_out_size / 2));
1266
1267         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268                           s->inst.data + CDATA_OUT_BUF_HEAD,
1269                           dsp_out_buffer);
1270
1271         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1272                           s->inst.data + CDATA_OUT_BUF_TAIL,
1273                           dsp_out_buffer);
1274 }
1275
1276 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1277 {
1278         u32 freq;
1279
1280         /*
1281          * put us in the lists if we're not already there
1282          */
1283         if (! s->in_lists) {
1284                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1285                                               s->inst.data >> DP_SHIFT_COUNT);
1286                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1287                                               s->inst.data >> DP_SHIFT_COUNT);
1288                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1289                                               s->inst.data >> DP_SHIFT_COUNT);
1290                 s->in_lists = 1;
1291         }
1292
1293         /* write to 'mono' word */
1294         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1296                           runtime->channels == 2 ? 0 : 1);
1297         /* write to '8bit' word */
1298         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1299                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1300                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1301
1302         /* set up dac/adc rate */
1303         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1304         if (freq)
1305                 freq--;
1306
1307         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1308                           s->inst.data + CDATA_FREQUENCY,
1309                           freq);
1310 }
1311
1312
1313 static struct play_vals {
1314         u16 addr, val;
1315 } pv[] = {
1316         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1317         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1318         {SRC3_DIRECTION_OFFSET, 0} ,
1319         /* +1, +2 are stereo/16 bit */
1320         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1321         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1322         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1323         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1324         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1325         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1326         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1327         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1328         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1329         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1330         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1331         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1332         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1333         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1334         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1335         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1336         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1337 };
1338
1339
1340 /* the mode passed should be already shifted and masked */
1341 static void
1342 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1343 {
1344         unsigned int i;
1345
1346         /*
1347          * some per client initializers
1348          */
1349
1350         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1351                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1352                           s->inst.data + 40 + 8);
1353
1354         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1355                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1356                           s->inst.code + MINISRC_COEF_LOC);
1357
1358         /* enable or disable low pass filter? */
1359         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1360                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1361                           subs->runtime->rate > 45000 ? 0xff : 0);
1362
1363         /* tell it which way dma is going? */
1364         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1365                           s->inst.data + CDATA_DMA_CONTROL,
1366                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1367
1368         /*
1369          * set an armload of static initializers
1370          */
1371         for (i = 0; i < ARRAY_SIZE(pv); i++)
1372                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1373                                   s->inst.data + pv[i].addr, pv[i].val);
1374 }
1375
1376 /*
1377  *    Native record driver
1378  */
1379 static struct rec_vals {
1380         u16 addr, val;
1381 } rv[] = {
1382         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1383         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1384         {SRC3_DIRECTION_OFFSET, 1} ,
1385         /* +1, +2 are stereo/16 bit */
1386         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1387         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1388         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1389         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1390         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1391         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1392         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1393         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1394         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1395         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1396         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1397         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1398         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1399         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1400         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1401         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1402         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1403         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1404         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1405 };
1406
1407 static void
1408 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1409 {
1410         unsigned int i;
1411
1412         /*
1413          * some per client initializers
1414          */
1415
1416         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1417                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1418                           s->inst.data + 40 + 8);
1419
1420         /* tell it which way dma is going? */
1421         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1422                           s->inst.data + CDATA_DMA_CONTROL,
1423                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1424                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1425
1426         /*
1427          * set an armload of static initializers
1428          */
1429         for (i = 0; i < ARRAY_SIZE(rv); i++)
1430                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1431                                   s->inst.data + rv[i].addr, rv[i].val);
1432 }
1433
1434 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1435                                 snd_pcm_hw_params_t * hw_params)
1436 {
1437         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1438         int err;
1439
1440         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1441                 return err;
1442         /* set buffer address */
1443         s->buffer_addr = substream->runtime->dma_addr;
1444         if (s->buffer_addr & 0x3) {
1445                 snd_printk("oh my, not aligned\n");
1446                 s->buffer_addr = s->buffer_addr & ~0x3;
1447         }
1448         return 0;
1449 }
1450
1451 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1452 {
1453         m3_dma_t *s;
1454
1455         if (substream->runtime->private_data == NULL)
1456                 return 0;
1457         s = (m3_dma_t*) substream->runtime->private_data;
1458         snd_pcm_lib_free_pages(substream);
1459         s->buffer_addr = 0;
1460         return 0;
1461 }
1462
1463 static int
1464 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1465 {
1466         m3_t *chip = snd_pcm_substream_chip(subs);
1467         snd_pcm_runtime_t *runtime = subs->runtime;
1468         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1469
1470         snd_assert(s != NULL, return -ENXIO);
1471
1472         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1473             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1474                 return -EINVAL;
1475         if (runtime->rate > 48000 ||
1476             runtime->rate < 8000)
1477                 return -EINVAL;
1478
1479         spin_lock_irq(&chip->reg_lock);
1480
1481         snd_m3_pcm_setup1(chip, s, subs);
1482
1483         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1484                 snd_m3_playback_setup(chip, s, subs);
1485         else
1486                 snd_m3_capture_setup(chip, s, subs);
1487
1488         snd_m3_pcm_setup2(chip, s, runtime);
1489
1490         spin_unlock_irq(&chip->reg_lock);
1491
1492         return 0;
1493 }
1494
1495 /*
1496  * get current pointer
1497  */
1498 static unsigned int
1499 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1500 {
1501         u16 hi = 0, lo = 0;
1502         int retry = 10;
1503         u32 addr;
1504
1505         /*
1506          * try and get a valid answer
1507          */
1508         while (retry--) {
1509                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1510                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1511
1512                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1513                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1514
1515                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1516                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1517                         break;
1518         }
1519         addr = lo | ((u32)hi<<16);
1520         return (unsigned int)(addr - s->buffer_addr);
1521 }
1522
1523 static snd_pcm_uframes_t
1524 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1525 {
1526         m3_t *chip = snd_pcm_substream_chip(subs);
1527         unsigned int ptr;
1528         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1529         snd_assert(s != NULL, return 0);
1530
1531         spin_lock(&chip->reg_lock);
1532         ptr = snd_m3_get_pointer(chip, s, subs);
1533         spin_unlock(&chip->reg_lock);
1534         return bytes_to_frames(subs->runtime, ptr);
1535 }
1536
1537
1538 /* update pointer */
1539 /* spinlock held! */
1540 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1541 {
1542         snd_pcm_substream_t *subs = s->substream;
1543         unsigned int hwptr;
1544         int diff;
1545
1546         if (! s->running)
1547                 return;
1548
1549         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1550         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1551         s->hwptr = hwptr;
1552         s->count += diff;
1553         if (s->count >= (signed)s->period_size) {
1554                 s->count %= s->period_size;
1555                 spin_unlock(&chip->reg_lock);
1556                 snd_pcm_period_elapsed(subs);
1557                 spin_lock(&chip->reg_lock);
1558         }
1559 }
1560
1561 static irqreturn_t
1562 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1563 {
1564         m3_t *chip = dev_id;
1565         u8 status;
1566         int i;
1567
1568         status = inb(chip->iobase + HOST_INT_STATUS);
1569
1570         if (status == 0xff)
1571                 return IRQ_NONE;
1572
1573         /*
1574          * ack an assp int if its running
1575          * and has an int pending
1576          */
1577         if (status & ASSP_INT_PENDING) {
1578                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1579                 if (!(ctl & STOP_ASSP_CLOCK)) {
1580                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1581                         if (ctl & DSP2HOST_REQ_TIMER) {
1582                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1583                                 /* update adc/dac info if it was a timer int */
1584                                 spin_lock(&chip->reg_lock);
1585                                 for (i = 0; i < chip->num_substreams; i++) {
1586                                         m3_dma_t *s = &chip->substreams[i];
1587                                         if (s->running)
1588                                                 snd_m3_update_ptr(chip, s);
1589                                 }
1590                                 spin_unlock(&chip->reg_lock);
1591                         }
1592                 }
1593         }
1594
1595 #if 0 /* TODO: not supported yet */
1596         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1597                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1598 #endif
1599
1600         /* ack ints */
1601         snd_m3_outw(chip, HOST_INT_STATUS, status);
1602
1603         return IRQ_HANDLED;
1604 }
1605
1606
1607 /*
1608  */
1609
1610 static snd_pcm_hardware_t snd_m3_playback =
1611 {
1612         .info =                 (SNDRV_PCM_INFO_MMAP |
1613                                  SNDRV_PCM_INFO_INTERLEAVED |
1614                                  SNDRV_PCM_INFO_MMAP_VALID |
1615                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1616                                  /*SNDRV_PCM_INFO_PAUSE |*/
1617                                  SNDRV_PCM_INFO_RESUME),
1618         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1619         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1620         .rate_min =             8000,
1621         .rate_max =             48000,
1622         .channels_min =         1,
1623         .channels_max =         2,
1624         .buffer_bytes_max =     (512*1024),
1625         .period_bytes_min =     64,
1626         .period_bytes_max =     (512*1024),
1627         .periods_min =          1,
1628         .periods_max =          1024,
1629 };
1630
1631 static snd_pcm_hardware_t snd_m3_capture =
1632 {
1633         .info =                 (SNDRV_PCM_INFO_MMAP |
1634                                  SNDRV_PCM_INFO_INTERLEAVED |
1635                                  SNDRV_PCM_INFO_MMAP_VALID |
1636                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1637                                  /*SNDRV_PCM_INFO_PAUSE |*/
1638                                  SNDRV_PCM_INFO_RESUME),
1639         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1640         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1641         .rate_min =             8000,
1642         .rate_max =             48000,
1643         .channels_min =         1,
1644         .channels_max =         2,
1645         .buffer_bytes_max =     (512*1024),
1646         .period_bytes_min =     64,
1647         .period_bytes_max =     (512*1024),
1648         .periods_min =          1,
1649         .periods_max =          1024,
1650 };
1651
1652
1653 /*
1654  */
1655
1656 static int
1657 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1658 {
1659         int i;
1660         m3_dma_t *s;
1661
1662         spin_lock_irq(&chip->reg_lock);
1663         for (i = 0; i < chip->num_substreams; i++) {
1664                 s = &chip->substreams[i];
1665                 if (! s->opened)
1666                         goto __found;
1667         }
1668         spin_unlock_irq(&chip->reg_lock);
1669         return -ENOMEM;
1670 __found:
1671         s->opened = 1;
1672         s->running = 0;
1673         spin_unlock_irq(&chip->reg_lock);
1674
1675         subs->runtime->private_data = s;
1676         s->substream = subs;
1677
1678         /* set list owners */
1679         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1680                 s->index_list[0] = &chip->mixer_list;
1681         } else
1682                 s->index_list[0] = &chip->adc1_list;
1683         s->index_list[1] = &chip->msrc_list;
1684         s->index_list[2] = &chip->dma_list;
1685
1686         return 0;
1687 }
1688
1689 static void
1690 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1691 {
1692         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1693
1694         if (s == NULL)
1695                 return; /* not opened properly */
1696
1697         spin_lock_irq(&chip->reg_lock);
1698         if (s->substream && s->running)
1699                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1700         if (s->in_lists) {
1701                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1702                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1703                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1704                 s->in_lists = 0;
1705         }
1706         s->running = 0;
1707         s->opened = 0;
1708         spin_unlock_irq(&chip->reg_lock);
1709 }
1710
1711 static int
1712 snd_m3_playback_open(snd_pcm_substream_t *subs)
1713 {
1714         m3_t *chip = snd_pcm_substream_chip(subs);
1715         snd_pcm_runtime_t *runtime = subs->runtime;
1716         int err;
1717
1718         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1719                 return err;
1720
1721         runtime->hw = snd_m3_playback;
1722         snd_pcm_set_sync(subs);
1723
1724         return 0;
1725 }
1726
1727 static int
1728 snd_m3_playback_close(snd_pcm_substream_t *subs)
1729 {
1730         m3_t *chip = snd_pcm_substream_chip(subs);
1731
1732         snd_m3_substream_close(chip, subs);
1733         return 0;
1734 }
1735
1736 static int
1737 snd_m3_capture_open(snd_pcm_substream_t *subs)
1738 {
1739         m3_t *chip = snd_pcm_substream_chip(subs);
1740         snd_pcm_runtime_t *runtime = subs->runtime;
1741         int err;
1742
1743         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1744                 return err;
1745
1746         runtime->hw = snd_m3_capture;
1747         snd_pcm_set_sync(subs);
1748
1749         return 0;
1750 }
1751
1752 static int
1753 snd_m3_capture_close(snd_pcm_substream_t *subs)
1754 {
1755         m3_t *chip = snd_pcm_substream_chip(subs);
1756
1757         snd_m3_substream_close(chip, subs);
1758         return 0;
1759 }
1760
1761 /*
1762  * create pcm instance
1763  */
1764
1765 static snd_pcm_ops_t snd_m3_playback_ops = {
1766         .open =         snd_m3_playback_open,
1767         .close =        snd_m3_playback_close,
1768         .ioctl =        snd_pcm_lib_ioctl,
1769         .hw_params =    snd_m3_pcm_hw_params,
1770         .hw_free =      snd_m3_pcm_hw_free,
1771         .prepare =      snd_m3_pcm_prepare,
1772         .trigger =      snd_m3_pcm_trigger,
1773         .pointer =      snd_m3_pcm_pointer,
1774 };
1775
1776 static snd_pcm_ops_t snd_m3_capture_ops = {
1777         .open =         snd_m3_capture_open,
1778         .close =        snd_m3_capture_close,
1779         .ioctl =        snd_pcm_lib_ioctl,
1780         .hw_params =    snd_m3_pcm_hw_params,
1781         .hw_free =      snd_m3_pcm_hw_free,
1782         .prepare =      snd_m3_pcm_prepare,
1783         .trigger =      snd_m3_pcm_trigger,
1784         .pointer =      snd_m3_pcm_pointer,
1785 };
1786
1787 static int __devinit
1788 snd_m3_pcm(m3_t * chip, int device)
1789 {
1790         snd_pcm_t *pcm;
1791         int err;
1792
1793         err = snd_pcm_new(chip->card, chip->card->driver, device,
1794                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1795         if (err < 0)
1796                 return err;
1797
1798         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1799         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1800
1801         pcm->private_data = chip;
1802         pcm->info_flags = 0;
1803         strcpy(pcm->name, chip->card->driver);
1804         chip->pcm = pcm;
1805
1806         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1807                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1808
1809         return 0;
1810 }
1811
1812
1813 /*
1814  * ac97 interface
1815  */
1816
1817 /*
1818  * Wait for the ac97 serial bus to be free.
1819  * return nonzero if the bus is still busy.
1820  */
1821 static int snd_m3_ac97_wait(m3_t *chip)
1822 {
1823         int i = 10000;
1824
1825         do {
1826                 if (! (snd_m3_inb(chip, 0x30) & 1))
1827                         return 0;
1828         } while (i-- > 0);
1829
1830         snd_printk("ac97 serial bus busy\n");
1831         return 1;
1832 }
1833
1834 static unsigned short
1835 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1836 {
1837         m3_t *chip = ac97->private_data;
1838         unsigned short ret = 0;
1839         unsigned long flags;
1840
1841         spin_lock_irqsave(&chip->reg_lock, flags);
1842         if (snd_m3_ac97_wait(chip))
1843                 goto __error;
1844         snd_m3_outb(chip, 0x80 | (reg & 0x7f), 0x30);
1845         if (snd_m3_ac97_wait(chip))
1846                 goto __error;
1847         ret = snd_m3_inw(chip, 0x32);
1848 __error:
1849         spin_unlock_irqrestore(&chip->reg_lock, flags);
1850         return ret;
1851 }
1852
1853 static void
1854 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1855 {
1856         m3_t *chip = ac97->private_data;
1857         unsigned long flags;
1858
1859         spin_lock_irqsave(&chip->reg_lock, flags);
1860         if (snd_m3_ac97_wait(chip))
1861                 goto __error;
1862         snd_m3_outw(chip, val, 0x32);
1863         snd_m3_outb(chip, reg & 0x7f, 0x30);
1864 __error:
1865         spin_unlock_irqrestore(&chip->reg_lock, flags);
1866 }
1867
1868
1869 static void snd_m3_remote_codec_config(int io, int isremote)
1870 {
1871         isremote = isremote ? 1 : 0;
1872
1873         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1874              io + RING_BUS_CTRL_B);
1875         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1876              io + SDO_OUT_DEST_CTRL);
1877         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1878              io + SDO_IN_DEST_CTRL);
1879 }
1880
1881 /*
1882  * hack, returns non zero on err
1883  */
1884 static int snd_m3_try_read_vendor(m3_t *chip)
1885 {
1886         u16 ret;
1887
1888         if (snd_m3_ac97_wait(chip))
1889                 return 1;
1890
1891         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1892
1893         if (snd_m3_ac97_wait(chip))
1894                 return 1;
1895
1896         ret = snd_m3_inw(chip, 0x32);
1897
1898         return (ret == 0) || (ret == 0xffff);
1899 }
1900
1901 static void snd_m3_ac97_reset(m3_t *chip)
1902 {
1903         u16 dir;
1904         int delay1 = 0, delay2 = 0, i;
1905         int io = chip->iobase;
1906
1907         if (chip->allegro_flag) {
1908                 /*
1909                  * the onboard codec on the allegro seems
1910                  * to want to wait a very long time before
1911                  * coming back to life
1912                  */
1913                 delay1 = 50;
1914                 delay2 = 800;
1915         } else {
1916                 /* maestro3 */
1917                 delay1 = 20;
1918                 delay2 = 500;
1919         }
1920
1921         for (i = 0; i < 5; i++) {
1922                 dir = inw(io + GPIO_DIRECTION);
1923                 if (! chip->quirk || ! chip->quirk->irda_workaround)
1924                         dir |= 0x10; /* assuming pci bus master? */
1925
1926                 snd_m3_remote_codec_config(io, 0);
1927
1928                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1929                 udelay(20);
1930
1931                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1932                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1933                 outw(0, io + GPIO_DATA);
1934                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1935
1936                 set_current_state(TASK_UNINTERRUPTIBLE);
1937                 schedule_timeout((delay1 * HZ) / 1000);
1938
1939                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1940                 udelay(5);
1941                 /* ok, bring back the ac-link */
1942                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1943                 outw(~0, io + GPIO_MASK);
1944
1945                 set_current_state(TASK_UNINTERRUPTIBLE);
1946                 schedule_timeout((delay2 * HZ) / 1000);
1947
1948                 if (! snd_m3_try_read_vendor(chip))
1949                         break;
1950
1951                 delay1 += 10;
1952                 delay2 += 100;
1953
1954                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1955                            delay1, delay2);
1956         }
1957
1958 #if 0
1959         /* more gung-ho reset that doesn't
1960          * seem to work anywhere :)
1961          */
1962         tmp = inw(io + RING_BUS_CTRL_A);
1963         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1964         big_mdelay(20);
1965         outw(tmp, io + RING_BUS_CTRL_A);
1966         big_mdelay(50);
1967 #endif
1968 }
1969
1970 static int __devinit snd_m3_mixer(m3_t *chip)
1971 {
1972         ac97_bus_t *pbus;
1973         ac97_template_t ac97;
1974         int err;
1975         static ac97_bus_ops_t ops = {
1976                 .write = snd_m3_ac97_write,
1977                 .read = snd_m3_ac97_read,
1978         };
1979
1980         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1981                 return err;
1982
1983         memset(&ac97, 0, sizeof(ac97));
1984         ac97.private_data = chip;
1985         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1986                 return err;
1987
1988         /* seems ac97 PCM needs initialization.. hack hack.. */
1989         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
1990         set_current_state(TASK_UNINTERRUPTIBLE);
1991         schedule_timeout(HZ / 10);
1992         snd_ac97_write(chip->ac97, AC97_PCM, 0);
1993
1994         return 0;
1995 }
1996
1997
1998 /*
1999  * DSP Code images
2000  */
2001
2002 static u16 assp_kernel_image[] __devinitdata = {
2003     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2004     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2005     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2006     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2007     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2008     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2009     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2010     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2011     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2012     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2013     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2014     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2015     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2016     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2017     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2018     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2019     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2020     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2021     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2022     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2023     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2024     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2025     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2026     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2027     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2028     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2029     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2030     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2031     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2032     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2033     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2034     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2035     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2036     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2037     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2038     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2039     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2040     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2041     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2042     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2043     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2044     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2045     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2046     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2047     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2048     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2049     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2050     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2051     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2052     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2053     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2054     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2055     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2056     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2057     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2058     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2059     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2060     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2061     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2062     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2063     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2064     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2065     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2066     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2067     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2068     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2069     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2070     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2071     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2072     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2073     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2074     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2075     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2076     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2077     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2078     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2079     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2080     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2081     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2082     0xBE3A,
2083 };
2084
2085 /*
2086  * Mini sample rate converter code image
2087  * that is to be loaded at 0x400 on the DSP.
2088  */
2089 static u16 assp_minisrc_image[] __devinitdata = {
2090
2091     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2092     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2093     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2094     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2095     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2096     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2097     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2098     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2099     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2100     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2101     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2102     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2103     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2104     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2105     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2106     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2107     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2108     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2109     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2110     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2111     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2112     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2113     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2114     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2115     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2116     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2117     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2118     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2119     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2120     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2121     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2122     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2123     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2124 };
2125
2126
2127 /*
2128  * initialize ASSP
2129  */
2130
2131 #define MINISRC_LPF_LEN 10
2132 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2133         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2134         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2135 };
2136
2137 static void __devinit snd_m3_assp_init(m3_t *chip)
2138 {
2139         unsigned int i;
2140
2141         /* zero kernel data */
2142         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2143                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2144                                   KDATA_BASE_ADDR + i, 0);
2145
2146         /* zero mixer data? */
2147         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2148                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2149                                   KDATA_BASE_ADDR2 + i, 0);
2150
2151         /* init dma pointer */
2152         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2153                           KDATA_CURRENT_DMA,
2154                           KDATA_DMA_XFER0);
2155
2156         /* write kernel into code memory.. */
2157         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2158                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2159                                   REV_B_CODE_MEMORY_BEGIN + i,
2160                                   assp_kernel_image[i]);
2161         }
2162
2163         /*
2164          * We only have this one client and we know that 0x400
2165          * is free in our kernel's mem map, so lets just
2166          * drop it there.  It seems that the minisrc doesn't
2167          * need vectors, so we won't bother with them..
2168          */
2169         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2170                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2171                                   0x400 + i,
2172                                   assp_minisrc_image[i]);
2173         }
2174
2175         /*
2176          * write the coefficients for the low pass filter?
2177          */
2178         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2179                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2180                                   0x400 + MINISRC_COEF_LOC + i,
2181                                   minisrc_lpf[i]);
2182         }
2183
2184         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2185                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2186                           0x8000);
2187
2188         /*
2189          * the minisrc is the only thing on
2190          * our task list..
2191          */
2192         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2193                           KDATA_TASK0,
2194                           0x400);
2195
2196         /*
2197          * init the mixer number..
2198          */
2199
2200         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2201                           KDATA_MIXER_TASK_NUMBER,0);
2202
2203         /*
2204          * EXTREME KERNEL MASTER VOLUME
2205          */
2206         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2207                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2208         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2209                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2210
2211         chip->mixer_list.curlen = 0;
2212         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2213         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2214         chip->adc1_list.curlen = 0;
2215         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2216         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2217         chip->dma_list.curlen = 0;
2218         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2219         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2220         chip->msrc_list.curlen = 0;
2221         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2222         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2223 }
2224
2225
2226 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2227 {
2228         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2229                                MINISRC_IN_BUFFER_SIZE / 2 +
2230                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2231         int address, i;
2232
2233         /*
2234          * the revb memory map has 0x1100 through 0x1c00
2235          * free.
2236          */
2237
2238         /*
2239          * align instance address to 256 bytes so that it's
2240          * shifted list address is aligned.
2241          * list address = (mem address >> 1) >> 7;
2242          */
2243         data_bytes = (data_bytes + 255) & ~255;
2244         address = 0x1100 + ((data_bytes/2) * index);
2245
2246         if ((address + (data_bytes/2)) >= 0x1c00) {
2247                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2248                            data_bytes, index, address);
2249                 return -ENOMEM;
2250         }
2251
2252         s->number = index;
2253         s->inst.code = 0x400;
2254         s->inst.data = address;
2255
2256         for (i = data_bytes / 2; i > 0; address++, i--) {
2257                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2258                                   address, 0);
2259         }
2260
2261         return 0;
2262 }
2263
2264
2265 /*
2266  * this works for the reference board, have to find
2267  * out about others
2268  *
2269  * this needs more magic for 4 speaker, but..
2270  */
2271 static void
2272 snd_m3_amp_enable(m3_t *chip, int enable)
2273 {
2274         int io = chip->iobase;
2275         u16 gpo, polarity;
2276
2277         if (! chip->external_amp)
2278                 return;
2279
2280         polarity = enable ? 0 : 1;
2281         polarity = polarity << chip->amp_gpio;
2282         gpo = 1 << chip->amp_gpio;
2283
2284         outw(~gpo, io + GPIO_MASK);
2285
2286         outw(inw(io + GPIO_DIRECTION) | gpo,
2287              io + GPIO_DIRECTION);
2288
2289         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2290              io + GPIO_DATA);
2291
2292         outw(0xffff, io + GPIO_MASK);
2293 }
2294
2295 static int
2296 snd_m3_chip_init(m3_t *chip)
2297 {
2298         struct pci_dev *pcidev = chip->pci;
2299         u32 n;
2300         u16 w;
2301         u8 t; /* makes as much sense as 'n', no? */
2302
2303         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2304         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2305                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2306                DISABLE_LEGACY);
2307         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2308
2309         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2310         n &= REDUCED_DEBOUNCE;
2311         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2312         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2313
2314         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2315         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2316         n &= ~INT_CLK_SELECT;
2317         if (!chip->allegro_flag) {
2318                 n &= ~INT_CLK_MULT_ENABLE;
2319                 n |= INT_CLK_SRC_NOT_PCI;
2320         }
2321         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2322         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2323
2324         if (chip->allegro_flag) {
2325                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2326                 n |= IN_CLK_12MHZ_SELECT;
2327                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2328         }
2329
2330         t = inb(chip->iobase + ASSP_CONTROL_A);
2331         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2332         t |= ASSP_CLK_49MHZ_SELECT;
2333         t |= ASSP_0_WS_ENABLE;
2334         outb(t, chip->iobase + ASSP_CONTROL_A);
2335
2336         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2337
2338         return 0;
2339 }
2340
2341 static void
2342 snd_m3_enable_ints(m3_t *chip)
2343 {
2344         unsigned long io = chip->iobase;
2345
2346         /* TODO: MPU401 not supported yet */
2347         outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2348         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2349              io + ASSP_CONTROL_C);
2350 }
2351
2352
2353 /*
2354  */
2355
2356 static int snd_m3_free(m3_t *chip)
2357 {
2358         m3_dma_t *s;
2359         int i;
2360
2361         if (chip->substreams) {
2362                 spin_lock_irq(&chip->reg_lock);
2363                 for (i = 0; i < chip->num_substreams; i++) {
2364                         s = &chip->substreams[i];
2365                         /* check surviving pcms; this should not happen though.. */
2366                         if (s->substream && s->running)
2367                                 snd_m3_pcm_stop(chip, s, s->substream);
2368                 }
2369                 spin_unlock_irq(&chip->reg_lock);
2370                 kfree(chip->substreams);
2371         }
2372         if (chip->iobase) {
2373                 snd_m3_outw(chip, HOST_INT_CTRL, 0); /* disable ints */
2374         }
2375
2376 #ifdef CONFIG_PM
2377         if (chip->suspend_mem)
2378                 vfree(chip->suspend_mem);
2379 #endif
2380
2381         if (chip->irq >= 0) {
2382                 synchronize_irq(chip->irq);
2383                 free_irq(chip->irq, (void *)chip);
2384         }
2385
2386         if (chip->iobase)
2387                 pci_release_regions(chip->pci);
2388
2389         pci_disable_device(chip->pci);
2390         kfree(chip);
2391         return 0;
2392 }
2393
2394
2395 /*
2396  * APM support
2397  */
2398 #ifdef CONFIG_PM
2399 static int m3_suspend(snd_card_t *card, unsigned int state)
2400 {
2401         m3_t *chip = card->pm_private_data;
2402         int i, index;
2403
2404         if (chip->suspend_mem == NULL)
2405                 return 0;
2406
2407         snd_pcm_suspend_all(chip->pcm);
2408         snd_ac97_suspend(chip->ac97);
2409
2410         big_mdelay(10); /* give the assp a chance to idle.. */
2411
2412         snd_m3_assp_halt(chip);
2413
2414         /* save dsp image */
2415         index = 0;
2416         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2417                 chip->suspend_mem[index++] =
2418                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2419         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2420                 chip->suspend_mem[index++] =
2421                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2422
2423         /* power down apci registers */
2424         snd_m3_outw(chip, 0xffff, 0x54);
2425         snd_m3_outw(chip, 0xffff, 0x56);
2426
2427         pci_disable_device(chip->pci);
2428         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2429         return 0;
2430 }
2431
2432 static int m3_resume(snd_card_t *card, unsigned int state)
2433 {
2434         m3_t *chip = card->pm_private_data;
2435         int i, index;
2436
2437         if (chip->suspend_mem == NULL)
2438                 return 0;
2439
2440         pci_enable_device(chip->pci);
2441         pci_set_master(chip->pci);
2442
2443         /* first lets just bring everything back. .*/
2444         snd_m3_outw(chip, 0, 0x54);
2445         snd_m3_outw(chip, 0, 0x56);
2446
2447         snd_m3_chip_init(chip);
2448         snd_m3_assp_halt(chip);
2449         snd_m3_ac97_reset(chip);
2450
2451         /* restore dsp image */
2452         index = 0;
2453         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2454                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2455                                   chip->suspend_mem[index++]);
2456         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2457                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2458                                   chip->suspend_mem[index++]);
2459
2460         /* tell the dma engine to restart itself */
2461         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2462                           KDATA_DMA_ACTIVE, 0);
2463
2464         /* restore ac97 registers */
2465         snd_ac97_resume(chip->ac97);
2466
2467         snd_m3_assp_continue(chip);
2468         snd_m3_enable_ints(chip);
2469         snd_m3_amp_enable(chip, 1);
2470
2471         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2472         return 0;
2473 }
2474 #endif /* CONFIG_PM */
2475
2476
2477 /*
2478  */
2479
2480 static int snd_m3_dev_free(snd_device_t *device)
2481 {
2482         m3_t *chip = device->device_data;
2483         return snd_m3_free(chip);
2484 }
2485
2486 static int __devinit
2487 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2488               int enable_amp,
2489               int amp_gpio,
2490               m3_t **chip_ret)
2491 {
2492         m3_t *chip;
2493         int i, err;
2494         struct m3_quirk *quirk;
2495         u16 subsystem_vendor, subsystem_device;
2496         static snd_device_ops_t ops = {
2497                 .dev_free =     snd_m3_dev_free,
2498         };
2499
2500         *chip_ret = NULL;
2501
2502         if (pci_enable_device(pci))
2503                 return -EIO;
2504
2505         /* check, if we can restrict PCI DMA transfers to 28 bits */
2506         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2507             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2508                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2509                 pci_disable_device(pci);
2510                 return -ENXIO;
2511         }
2512
2513         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2514         if (chip == NULL) {
2515                 pci_disable_device(pci);
2516                 return -ENOMEM;
2517         }
2518
2519         spin_lock_init(&chip->reg_lock);
2520         switch (pci->device) {
2521         case PCI_DEVICE_ID_ESS_ALLEGRO:
2522         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2523         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2524         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2525                 chip->allegro_flag = 1;
2526                 break;
2527         }
2528
2529         chip->card = card;
2530         chip->pci = pci;
2531         chip->irq = -1;
2532
2533         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2534         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2535
2536         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2537                 if (subsystem_vendor == quirk->vendor &&
2538                     subsystem_device == quirk->device) {
2539                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2540                         chip->quirk = quirk;
2541                         break;
2542                 }
2543         }
2544
2545         chip->external_amp = enable_amp;
2546         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2547                 chip->amp_gpio = amp_gpio;
2548         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2549                 chip->amp_gpio = chip->quirk->amp_gpio;
2550         else if (chip->allegro_flag)
2551                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2552         else /* presumably this is for all 'maestro3's.. */
2553                 chip->amp_gpio = GPO_EXT_AMP_M3;
2554
2555         chip->num_substreams = NR_DSPS;
2556         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2557         if (chip->substreams == NULL) {
2558                 kfree(chip);
2559                 pci_disable_device(pci);
2560                 return -ENOMEM;
2561         }
2562         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2563
2564         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2565                 snd_m3_free(chip);
2566                 return err;
2567         }
2568         chip->iobase = pci_resource_start(pci, 0);
2569
2570         /* just to be sure */
2571         pci_set_master(pci);
2572
2573         snd_m3_chip_init(chip);
2574         snd_m3_assp_halt(chip);
2575
2576         snd_m3_ac97_reset(chip);
2577
2578         snd_m3_assp_init(chip);
2579         snd_m3_amp_enable(chip, 1);
2580
2581         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2582                         card->driver, (void *)chip)) {
2583                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2584                 snd_m3_free(chip);
2585                 return -ENOMEM;
2586         }
2587         chip->irq = pci->irq;
2588
2589 #ifdef CONFIG_PM
2590         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2591         if (chip->suspend_mem == NULL)
2592                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2593         else
2594                 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2595 #endif
2596
2597         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2598                 snd_m3_free(chip);
2599                 return err;
2600         }
2601
2602         if ((err = snd_m3_mixer(chip)) < 0)
2603                 return err;
2604
2605         for (i = 0; i < chip->num_substreams; i++) {
2606                 m3_dma_t *s = &chip->substreams[i];
2607                 s->chip = chip;
2608                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2609                         return err;
2610         }
2611
2612         if ((err = snd_m3_pcm(chip, 0)) < 0)
2613                 return err;
2614
2615         snd_m3_enable_ints(chip);
2616         snd_m3_assp_continue(chip);
2617
2618         snd_card_set_dev(card, &pci->dev);
2619
2620         *chip_ret = chip;
2621
2622         return 0;
2623 }
2624
2625 /*
2626  */
2627 static int __devinit
2628 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2629 {
2630         static int dev;
2631         snd_card_t *card;
2632         m3_t *chip;
2633         int err;
2634
2635         /* don't pick up modems */
2636         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2637                 return -ENODEV;
2638
2639         if (dev >= SNDRV_CARDS)
2640                 return -ENODEV;
2641         if (!enable[dev]) {
2642                 dev++;
2643                 return -ENOENT;
2644         }
2645
2646         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2647         if (card == NULL)
2648                 return -ENOMEM;
2649
2650         switch (pci->device) {
2651         case PCI_DEVICE_ID_ESS_ALLEGRO:
2652         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2653                 strcpy(card->driver, "Allegro");
2654                 break;
2655         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2656         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2657                 strcpy(card->driver, "Canyon3D-2");
2658                 break;
2659         default:
2660                 strcpy(card->driver, "Maestro3");
2661                 break;
2662         }
2663
2664         if ((err = snd_m3_create(card, pci,
2665                                  external_amp[dev],
2666                                  amp_gpio[dev],
2667                                  &chip)) < 0) {
2668                 snd_card_free(card);
2669                 return err;
2670         }
2671
2672         sprintf(card->shortname, "ESS %s PCI", card->driver);
2673         sprintf(card->longname, "%s at 0x%lx, irq %d",
2674                 card->shortname, chip->iobase, chip->irq);
2675
2676         if ((err = snd_card_register(card)) < 0) {
2677                 snd_card_free(card);
2678                 return err;
2679         }
2680
2681 #if 0 /* TODO: not supported yet */
2682         /* TODO enable midi irq and i/o */
2683         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2684                                   chip->iobase + MPU401_DATA_PORT, 1,
2685                                   chip->irq, 0, &chip->rmidi);
2686         if (err < 0)
2687                 printk(KERN_WARNING "maestro3: no midi support.\n");
2688 #endif
2689
2690         pci_set_drvdata(pci, card);
2691         dev++;
2692         return 0;
2693 }
2694
2695 static void __devexit snd_m3_remove(struct pci_dev *pci)
2696 {
2697         snd_card_free(pci_get_drvdata(pci));
2698         pci_set_drvdata(pci, NULL);
2699 }
2700
2701 static struct pci_driver driver = {
2702         .name = "Maestro3",
2703         .id_table = snd_m3_ids,
2704         .probe = snd_m3_probe,
2705         .remove = __devexit_p(snd_m3_remove),
2706         SND_PCI_PM_CALLBACKS
2707 };
2708
2709 static int __init alsa_card_m3_init(void)
2710 {
2711         return pci_module_init(&driver);
2712 }
2713
2714 static void __exit alsa_card_m3_exit(void)
2715 {
2716         pci_unregister_driver(&driver);
2717 }
2718
2719 module_init(alsa_card_m3_init)
2720 module_exit(alsa_card_m3_exit)