2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
34 #include <sound/driver.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <sound/core.h>
44 #include <sound/info.h>
45 #include <sound/control.h>
46 #include <sound/pcm.h>
47 #include <sound/mpu401.h>
48 #include <sound/ac97_codec.h>
49 #include <sound/initval.h>
51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
53 MODULE_LICENSE("GPL");
54 MODULE_CLASSES("{sound}");
55 MODULE_DEVICES("{{ESS,Maestro3 PCI},"
58 "{ESS,Allegro-1 PCI},"
59 "{ESS,Canyon3D-2/LE PCI}}");
61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
63 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
64 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
65 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
68 module_param_array(index, int, boot_devs, 0444);
69 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
70 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
71 module_param_array(id, charp, boot_devs, 0444);
72 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
73 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
74 module_param_array(enable, bool, boot_devs, 0444);
75 MODULE_PARM_DESC(enable, "Enable this soundcard.");
76 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
77 module_param_array(external_amp, bool, boot_devs, 0444);
78 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
79 MODULE_PARM_SYNTAX(external_amp, SNDRV_ENABLED "," SNDRV_BOOLEAN_TRUE_DESC);
80 module_param_array(amp_gpio, int, boot_devs, 0444);
81 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
82 MODULE_PARM_SYNTAX(amp_gpio, SNDRV_ENABLED);
84 #define MAX_PLAYBACKS 2
85 #define MAX_CAPTURES 1
86 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
93 /* Allegro PCI configuration registers */
94 #define PCI_LEGACY_AUDIO_CTRL 0x40
95 #define SOUND_BLASTER_ENABLE 0x00000001
96 #define FM_SYNTHESIS_ENABLE 0x00000002
97 #define GAME_PORT_ENABLE 0x00000004
98 #define MPU401_IO_ENABLE 0x00000008
99 #define MPU401_IRQ_ENABLE 0x00000010
100 #define ALIAS_10BIT_IO 0x00000020
101 #define SB_DMA_MASK 0x000000C0
102 #define SB_DMA_0 0x00000040
103 #define SB_DMA_1 0x00000040
104 #define SB_DMA_R 0x00000080
105 #define SB_DMA_3 0x000000C0
106 #define SB_IRQ_MASK 0x00000700
107 #define SB_IRQ_5 0x00000000
108 #define SB_IRQ_7 0x00000100
109 #define SB_IRQ_9 0x00000200
110 #define SB_IRQ_10 0x00000300
111 #define MIDI_IRQ_MASK 0x00003800
112 #define SERIAL_IRQ_ENABLE 0x00004000
113 #define DISABLE_LEGACY 0x00008000
115 #define PCI_ALLEGRO_CONFIG 0x50
116 #define SB_ADDR_240 0x00000004
117 #define MPU_ADDR_MASK 0x00000018
118 #define MPU_ADDR_330 0x00000000
119 #define MPU_ADDR_300 0x00000008
120 #define MPU_ADDR_320 0x00000010
121 #define MPU_ADDR_340 0x00000018
122 #define USE_PCI_TIMING 0x00000040
123 #define POSTED_WRITE_ENABLE 0x00000080
124 #define DMA_POLICY_MASK 0x00000700
125 #define DMA_DDMA 0x00000000
126 #define DMA_TDMA 0x00000100
127 #define DMA_PCPCI 0x00000200
128 #define DMA_WBDMA16 0x00000400
129 #define DMA_WBDMA4 0x00000500
130 #define DMA_WBDMA2 0x00000600
131 #define DMA_WBDMA1 0x00000700
132 #define DMA_SAFE_GUARD 0x00000800
133 #define HI_PERF_GP_ENABLE 0x00001000
134 #define PIC_SNOOP_MODE_0 0x00002000
135 #define PIC_SNOOP_MODE_1 0x00004000
136 #define SOUNDBLASTER_IRQ_MASK 0x00008000
137 #define RING_IN_ENABLE 0x00010000
138 #define SPDIF_TEST_MODE 0x00020000
139 #define CLK_MULT_MODE_SELECT_2 0x00040000
140 #define EEPROM_WRITE_ENABLE 0x00080000
141 #define CODEC_DIR_IN 0x00100000
142 #define HV_BUTTON_FROM_GD 0x00200000
143 #define REDUCED_DEBOUNCE 0x00400000
144 #define HV_CTRL_ENABLE 0x00800000
145 #define SPDIF_ENABLE 0x01000000
146 #define CLK_DIV_SELECT 0x06000000
147 #define CLK_DIV_BY_48 0x00000000
148 #define CLK_DIV_BY_49 0x02000000
149 #define CLK_DIV_BY_50 0x04000000
150 #define CLK_DIV_RESERVED 0x06000000
151 #define PM_CTRL_ENABLE 0x08000000
152 #define CLK_MULT_MODE_SELECT 0x30000000
153 #define CLK_MULT_MODE_SHIFT 28
154 #define CLK_MULT_MODE_0 0x00000000
155 #define CLK_MULT_MODE_1 0x10000000
156 #define CLK_MULT_MODE_2 0x20000000
157 #define CLK_MULT_MODE_3 0x30000000
158 #define INT_CLK_SELECT 0x40000000
159 #define INT_CLK_MULT_RESET 0x80000000
162 #define INT_CLK_SRC_NOT_PCI 0x00100000
163 #define INT_CLK_MULT_ENABLE 0x80000000
165 #define PCI_ACPI_CONTROL 0x54
166 #define PCI_ACPI_D0 0x00000000
167 #define PCI_ACPI_D1 0xB4F70000
168 #define PCI_ACPI_D2 0xB4F7B4F7
170 #define PCI_USER_CONFIG 0x58
171 #define EXT_PCI_MASTER_ENABLE 0x00000001
172 #define SPDIF_OUT_SELECT 0x00000002
173 #define TEST_PIN_DIR_CTRL 0x00000004
174 #define AC97_CODEC_TEST 0x00000020
175 #define TRI_STATE_BUFFER 0x00000080
176 #define IN_CLK_12MHZ_SELECT 0x00000100
177 #define MULTI_FUNC_DISABLE 0x00000200
178 #define EXT_MASTER_PAIR_SEL 0x00000400
179 #define PCI_MASTER_SUPPORT 0x00000800
180 #define STOP_CLOCK_ENABLE 0x00001000
181 #define EAPD_DRIVE_ENABLE 0x00002000
182 #define REQ_TRI_STATE_ENABLE 0x00004000
183 #define REQ_LOW_ENABLE 0x00008000
184 #define MIDI_1_ENABLE 0x00010000
185 #define MIDI_2_ENABLE 0x00020000
186 #define SB_AUDIO_SYNC 0x00040000
187 #define HV_CTRL_TEST 0x00100000
188 #define SOUNDBLASTER_TEST 0x00400000
190 #define PCI_USER_CONFIG_C 0x5C
192 #define PCI_DDMA_CTRL 0x60
193 #define DDMA_ENABLE 0x00000001
196 /* Allegro registers */
197 #define HOST_INT_CTRL 0x18
198 #define SB_INT_ENABLE 0x0001
199 #define MPU401_INT_ENABLE 0x0002
200 #define ASSP_INT_ENABLE 0x0010
201 #define RING_INT_ENABLE 0x0020
202 #define HV_INT_ENABLE 0x0040
203 #define CLKRUN_GEN_ENABLE 0x0100
204 #define HV_CTRL_TO_PME 0x0400
205 #define SOFTWARE_RESET_ENABLE 0x8000
208 * should be using the above defines, probably.
210 #define REGB_ENABLE_RESET 0x01
211 #define REGB_STOP_CLOCK 0x10
213 #define HOST_INT_STATUS 0x1A
214 #define SB_INT_PENDING 0x01
215 #define MPU401_INT_PENDING 0x02
216 #define ASSP_INT_PENDING 0x10
217 #define RING_INT_PENDING 0x20
218 #define HV_INT_PENDING 0x40
220 #define HARDWARE_VOL_CTRL 0x1B
221 #define SHADOW_MIX_REG_VOICE 0x1C
222 #define HW_VOL_COUNTER_VOICE 0x1D
223 #define SHADOW_MIX_REG_MASTER 0x1E
224 #define HW_VOL_COUNTER_MASTER 0x1F
226 #define CODEC_COMMAND 0x30
227 #define CODEC_READ_B 0x80
229 #define CODEC_STATUS 0x30
230 #define CODEC_BUSY_B 0x01
232 #define CODEC_DATA 0x32
234 #define RING_BUS_CTRL_A 0x36
235 #define RAC_PME_ENABLE 0x0100
236 #define RAC_SDFS_ENABLE 0x0200
237 #define LAC_PME_ENABLE 0x0400
238 #define LAC_SDFS_ENABLE 0x0800
239 #define SERIAL_AC_LINK_ENABLE 0x1000
240 #define IO_SRAM_ENABLE 0x2000
241 #define IIS_INPUT_ENABLE 0x8000
243 #define RING_BUS_CTRL_B 0x38
244 #define SECOND_CODEC_ID_MASK 0x0003
245 #define SPDIF_FUNC_ENABLE 0x0010
246 #define SECOND_AC_ENABLE 0x0020
247 #define SB_MODULE_INTF_ENABLE 0x0040
248 #define SSPE_ENABLE 0x0040
249 #define M3I_DOCK_ENABLE 0x0080
251 #define SDO_OUT_DEST_CTRL 0x3A
252 #define COMMAND_ADDR_OUT 0x0003
253 #define PCM_LR_OUT_LOCAL 0x0000
254 #define PCM_LR_OUT_REMOTE 0x0004
255 #define PCM_LR_OUT_MUTE 0x0008
256 #define PCM_LR_OUT_BOTH 0x000C
257 #define LINE1_DAC_OUT_LOCAL 0x0000
258 #define LINE1_DAC_OUT_REMOTE 0x0010
259 #define LINE1_DAC_OUT_MUTE 0x0020
260 #define LINE1_DAC_OUT_BOTH 0x0030
261 #define PCM_CLS_OUT_LOCAL 0x0000
262 #define PCM_CLS_OUT_REMOTE 0x0040
263 #define PCM_CLS_OUT_MUTE 0x0080
264 #define PCM_CLS_OUT_BOTH 0x00C0
265 #define PCM_RLF_OUT_LOCAL 0x0000
266 #define PCM_RLF_OUT_REMOTE 0x0100
267 #define PCM_RLF_OUT_MUTE 0x0200
268 #define PCM_RLF_OUT_BOTH 0x0300
269 #define LINE2_DAC_OUT_LOCAL 0x0000
270 #define LINE2_DAC_OUT_REMOTE 0x0400
271 #define LINE2_DAC_OUT_MUTE 0x0800
272 #define LINE2_DAC_OUT_BOTH 0x0C00
273 #define HANDSET_OUT_LOCAL 0x0000
274 #define HANDSET_OUT_REMOTE 0x1000
275 #define HANDSET_OUT_MUTE 0x2000
276 #define HANDSET_OUT_BOTH 0x3000
277 #define IO_CTRL_OUT_LOCAL 0x0000
278 #define IO_CTRL_OUT_REMOTE 0x4000
279 #define IO_CTRL_OUT_MUTE 0x8000
280 #define IO_CTRL_OUT_BOTH 0xC000
282 #define SDO_IN_DEST_CTRL 0x3C
283 #define STATUS_ADDR_IN 0x0003
284 #define PCM_LR_IN_LOCAL 0x0000
285 #define PCM_LR_IN_REMOTE 0x0004
286 #define PCM_LR_RESERVED 0x0008
287 #define PCM_LR_IN_BOTH 0x000C
288 #define LINE1_ADC_IN_LOCAL 0x0000
289 #define LINE1_ADC_IN_REMOTE 0x0010
290 #define LINE1_ADC_IN_MUTE 0x0020
291 #define MIC_ADC_IN_LOCAL 0x0000
292 #define MIC_ADC_IN_REMOTE 0x0040
293 #define MIC_ADC_IN_MUTE 0x0080
294 #define LINE2_DAC_IN_LOCAL 0x0000
295 #define LINE2_DAC_IN_REMOTE 0x0400
296 #define LINE2_DAC_IN_MUTE 0x0800
297 #define HANDSET_IN_LOCAL 0x0000
298 #define HANDSET_IN_REMOTE 0x1000
299 #define HANDSET_IN_MUTE 0x2000
300 #define IO_STATUS_IN_LOCAL 0x0000
301 #define IO_STATUS_IN_REMOTE 0x4000
303 #define SPDIF_IN_CTRL 0x3E
304 #define SPDIF_IN_ENABLE 0x0001
306 #define GPIO_DATA 0x60
307 #define GPIO_DATA_MASK 0x0FFF
308 #define GPIO_HV_STATUS 0x3000
309 #define GPIO_PME_STATUS 0x4000
311 #define GPIO_MASK 0x64
312 #define GPIO_DIRECTION 0x68
313 #define GPO_PRIMARY_AC97 0x0001
314 #define GPI_LINEOUT_SENSE 0x0004
315 #define GPO_SECONDARY_AC97 0x0008
316 #define GPI_VOL_DOWN 0x0010
317 #define GPI_VOL_UP 0x0020
318 #define GPI_IIS_CLK 0x0040
319 #define GPI_IIS_LRCLK 0x0080
320 #define GPI_IIS_DATA 0x0100
321 #define GPI_DOCKING_STATUS 0x0100
322 #define GPI_HEADPHONE_SENSE 0x0200
323 #define GPO_EXT_AMP_SHUTDOWN 0x1000
325 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
326 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
329 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
331 #define ASSP_INDEX_PORT 0x80
332 #define ASSP_MEMORY_PORT 0x82
333 #define ASSP_DATA_PORT 0x84
335 #define MPU401_DATA_PORT 0x98
336 #define MPU401_STATUS_PORT 0x99
338 #define CLK_MULT_DATA_PORT 0x9C
340 #define ASSP_CONTROL_A 0xA2
341 #define ASSP_0_WS_ENABLE 0x01
342 #define ASSP_CTRL_A_RESERVED1 0x02
343 #define ASSP_CTRL_A_RESERVED2 0x04
344 #define ASSP_CLK_49MHZ_SELECT 0x08
345 #define FAST_PLU_ENABLE 0x10
346 #define ASSP_CTRL_A_RESERVED3 0x20
347 #define DSP_CLK_36MHZ_SELECT 0x40
349 #define ASSP_CONTROL_B 0xA4
350 #define RESET_ASSP 0x00
351 #define RUN_ASSP 0x01
352 #define ENABLE_ASSP_CLOCK 0x00
353 #define STOP_ASSP_CLOCK 0x10
354 #define RESET_TOGGLE 0x40
356 #define ASSP_CONTROL_C 0xA6
357 #define ASSP_HOST_INT_ENABLE 0x01
358 #define FM_ADDR_REMAP_DISABLE 0x02
359 #define HOST_WRITE_PORT_ENABLE 0x08
361 #define ASSP_HOST_INT_STATUS 0xAC
362 #define DSP2HOST_REQ_PIORECORD 0x01
363 #define DSP2HOST_REQ_I2SRATE 0x02
364 #define DSP2HOST_REQ_TIMER 0x04
367 /* XXX fix this crap up */
368 /*#define AC97_RESET 0x00*/
370 #define AC97_VOL_MUTE_B 0x8000
371 #define AC97_VOL_M 0x1F
372 #define AC97_LEFT_VOL_S 8
374 #define AC97_MASTER_VOL 0x02
375 #define AC97_LINE_LEVEL_VOL 0x04
376 #define AC97_MASTER_MONO_VOL 0x06
377 #define AC97_PC_BEEP_VOL 0x0A
378 #define AC97_PC_BEEP_VOL_M 0x0F
379 #define AC97_SROUND_MASTER_VOL 0x38
380 #define AC97_PC_BEEP_VOL_S 1
382 /*#define AC97_PHONE_VOL 0x0C
383 #define AC97_MIC_VOL 0x0E*/
384 #define AC97_MIC_20DB_ENABLE 0x40
386 /*#define AC97_LINEIN_VOL 0x10
387 #define AC97_CD_VOL 0x12
388 #define AC97_VIDEO_VOL 0x14
389 #define AC97_AUX_VOL 0x16*/
390 #define AC97_PCM_OUT_VOL 0x18
391 /*#define AC97_RECORD_SELECT 0x1A*/
392 #define AC97_RECORD_MIC 0x00
393 #define AC97_RECORD_CD 0x01
394 #define AC97_RECORD_VIDEO 0x02
395 #define AC97_RECORD_AUX 0x03
396 #define AC97_RECORD_MONO_MUX 0x02
397 #define AC97_RECORD_DIGITAL 0x03
398 #define AC97_RECORD_LINE 0x04
399 #define AC97_RECORD_STEREO 0x05
400 #define AC97_RECORD_MONO 0x06
401 #define AC97_RECORD_PHONE 0x07
403 /*#define AC97_RECORD_GAIN 0x1C*/
404 #define AC97_RECORD_VOL_M 0x0F
406 /*#define AC97_GENERAL_PURPOSE 0x20*/
407 #define AC97_POWER_DOWN_CTRL 0x26
408 #define AC97_ADC_READY 0x0001
409 #define AC97_DAC_READY 0x0002
410 #define AC97_ANALOG_READY 0x0004
411 #define AC97_VREF_ON 0x0008
412 #define AC97_PR0 0x0100
413 #define AC97_PR1 0x0200
414 #define AC97_PR2 0x0400
415 #define AC97_PR3 0x0800
416 #define AC97_PR4 0x1000
418 #define AC97_RESERVED1 0x28
420 #define AC97_VENDOR_TEST 0x5A
422 #define AC97_CLOCK_DELAY 0x5C
423 #define AC97_LINEOUT_MUX_SEL 0x0001
424 #define AC97_MONO_MUX_SEL 0x0002
425 #define AC97_CLOCK_DELAY_SEL 0x1F
426 #define AC97_DAC_CDS_SHIFT 6
427 #define AC97_ADC_CDS_SHIFT 11
429 #define AC97_MULTI_CHANNEL_SEL 0x74
431 /*#define AC97_VENDOR_ID1 0x7C
432 #define AC97_VENDOR_ID2 0x7E*/
437 #define DSP_PORT_TIMER_COUNT 0x06
439 #define DSP_PORT_MEMORY_INDEX 0x80
441 #define DSP_PORT_MEMORY_TYPE 0x82
442 #define MEMTYPE_INTERNAL_CODE 0x0002
443 #define MEMTYPE_INTERNAL_DATA 0x0003
444 #define MEMTYPE_MASK 0x0003
446 #define DSP_PORT_MEMORY_DATA 0x84
448 #define DSP_PORT_CONTROL_REG_A 0xA2
449 #define DSP_PORT_CONTROL_REG_B 0xA4
450 #define DSP_PORT_CONTROL_REG_C 0xA6
452 #define REV_A_CODE_MEMORY_BEGIN 0x0000
453 #define REV_A_CODE_MEMORY_END 0x0FFF
454 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
455 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
457 #define REV_B_CODE_MEMORY_BEGIN 0x0000
458 #define REV_B_CODE_MEMORY_END 0x0BFF
459 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
460 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
462 #define REV_A_DATA_MEMORY_BEGIN 0x1000
463 #define REV_A_DATA_MEMORY_END 0x2FFF
464 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
465 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
467 #define REV_B_DATA_MEMORY_BEGIN 0x1000
468 #define REV_B_DATA_MEMORY_END 0x2BFF
469 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
470 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
473 #define NUM_UNITS_KERNEL_CODE 16
474 #define NUM_UNITS_KERNEL_DATA 2
476 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
477 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
483 #define DP_SHIFT_COUNT 7
485 #define KDATA_BASE_ADDR 0x1000
486 #define KDATA_BASE_ADDR2 0x1080
488 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
489 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
490 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
491 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
492 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
493 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
494 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
495 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
496 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
498 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
499 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
501 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
502 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
503 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
504 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
505 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
506 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
507 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
508 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
509 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
510 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
512 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
513 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
515 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
516 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
518 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
519 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
521 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
522 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
523 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
525 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
526 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
527 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
528 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
529 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
531 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
532 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
533 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
535 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
536 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
537 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
539 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
540 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
541 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
542 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
543 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
544 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
545 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
546 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
547 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
548 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
550 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
551 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
552 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
554 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
555 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
557 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
558 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
559 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
561 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
562 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
563 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
564 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
565 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
566 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
568 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
569 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
570 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
571 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
572 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
573 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
575 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
576 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
577 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
578 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
579 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
580 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
582 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
583 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
584 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
585 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
587 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
588 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
590 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
591 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
593 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
594 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
595 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
596 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
597 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
599 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
600 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
602 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
603 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
604 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
606 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
607 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
609 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
611 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
612 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
613 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
614 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
615 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
616 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
617 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
618 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
619 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
620 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
621 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
622 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
624 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
625 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
626 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
627 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
629 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
630 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
632 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
633 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
634 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
635 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
637 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
638 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
639 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
640 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
641 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
644 * second 'segment' (?) reserved for mixer
648 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
649 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
650 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
651 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
652 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
653 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
654 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
655 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
656 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
657 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
658 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
659 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
660 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
661 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
662 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
663 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
665 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
666 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
667 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
668 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
669 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
670 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
671 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
672 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
673 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
674 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
675 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
677 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
678 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
679 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
680 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
681 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
682 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
684 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
685 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
686 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
687 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
690 * client data area offsets
692 #define CDATA_INSTANCE_READY 0x00
694 #define CDATA_HOST_SRC_ADDRL 0x01
695 #define CDATA_HOST_SRC_ADDRH 0x02
696 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
697 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
698 #define CDATA_HOST_SRC_CURRENTL 0x05
699 #define CDATA_HOST_SRC_CURRENTH 0x06
701 #define CDATA_IN_BUF_CONNECT 0x07
702 #define CDATA_OUT_BUF_CONNECT 0x08
704 #define CDATA_IN_BUF_BEGIN 0x09
705 #define CDATA_IN_BUF_END_PLUS_1 0x0A
706 #define CDATA_IN_BUF_HEAD 0x0B
707 #define CDATA_IN_BUF_TAIL 0x0C
708 #define CDATA_OUT_BUF_BEGIN 0x0D
709 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
710 #define CDATA_OUT_BUF_HEAD 0x0F
711 #define CDATA_OUT_BUF_TAIL 0x10
713 #define CDATA_DMA_CONTROL 0x11
714 #define CDATA_RESERVED 0x12
716 #define CDATA_FREQUENCY 0x13
717 #define CDATA_LEFT_VOLUME 0x14
718 #define CDATA_RIGHT_VOLUME 0x15
719 #define CDATA_LEFT_SUR_VOL 0x16
720 #define CDATA_RIGHT_SUR_VOL 0x17
722 #define CDATA_HEADER_LEN 0x18
724 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
725 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
726 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
727 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
728 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
729 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
730 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
731 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
733 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
734 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
735 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
736 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
737 #define MINISRC_BIQUAD_STAGE 2
738 #define MINISRC_COEF_LOC 0x175
740 #define DMACONTROL_BLOCK_MASK 0x000F
741 #define DMAC_BLOCK0_SELECTOR 0x0000
742 #define DMAC_BLOCK1_SELECTOR 0x0001
743 #define DMAC_BLOCK2_SELECTOR 0x0002
744 #define DMAC_BLOCK3_SELECTOR 0x0003
745 #define DMAC_BLOCK4_SELECTOR 0x0004
746 #define DMAC_BLOCK5_SELECTOR 0x0005
747 #define DMAC_BLOCK6_SELECTOR 0x0006
748 #define DMAC_BLOCK7_SELECTOR 0x0007
749 #define DMAC_BLOCK8_SELECTOR 0x0008
750 #define DMAC_BLOCK9_SELECTOR 0x0009
751 #define DMAC_BLOCKA_SELECTOR 0x000A
752 #define DMAC_BLOCKB_SELECTOR 0x000B
753 #define DMAC_BLOCKC_SELECTOR 0x000C
754 #define DMAC_BLOCKD_SELECTOR 0x000D
755 #define DMAC_BLOCKE_SELECTOR 0x000E
756 #define DMAC_BLOCKF_SELECTOR 0x000F
757 #define DMACONTROL_PAGE_MASK 0x00F0
758 #define DMAC_PAGE0_SELECTOR 0x0030
759 #define DMAC_PAGE1_SELECTOR 0x0020
760 #define DMAC_PAGE2_SELECTOR 0x0010
761 #define DMAC_PAGE3_SELECTOR 0x0000
762 #define DMACONTROL_AUTOREPEAT 0x1000
763 #define DMACONTROL_STOPPED 0x2000
764 #define DMACONTROL_DIRECTION 0x0100
767 * an arbitrary volume we set the internal
768 * volume settings to so that the ac97 volume
769 * range is a little less insane. 0x7fff is
772 #define ARB_VOLUME ( 0x6800 )
777 typedef struct snd_m3_dma m3_dma_t;
778 typedef struct snd_m3 m3_t;
784 const char *name; /* device name */
785 u16 vendor, device; /* subsystem ids */
786 int amp_gpio; /* gpio pin # for external amp, -1 = default */
787 int irda_workaround; /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
788 (e.g. for IrDA on Dell Inspirons) */
801 snd_pcm_substream_t *substream;
803 struct assp_instance {
804 unsigned short code, data;
810 unsigned long buffer_addr;
817 struct m3_list *index_list[3];
821 struct list_head list;
829 unsigned long iobase;
830 struct resource *iobase_res;
833 int allegro_flag : 1;
840 struct m3_quirk *quirk;
845 struct m3_list msrc_list;
846 struct m3_list mixer_list;
847 struct m3_list adc1_list;
848 struct m3_list dma_list;
850 /* for storing reset state..*/
857 snd_rawmidi_t *rmidi;
861 m3_dma_t *substreams;
874 #ifndef PCI_VENDOR_ID_ESS
875 #define PCI_VENDOR_ID_ESS 0x125D
877 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
878 #define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988
880 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
881 #define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989
883 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
884 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990
886 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
887 #define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992
889 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
890 #define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998
892 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
893 #define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999
895 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
896 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a
898 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
899 #define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b
902 static struct pci_device_id snd_m3_ids[] = {
903 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
904 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
905 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
906 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
907 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
908 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
909 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
910 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
911 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
912 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
913 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
914 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
915 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
916 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
917 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
918 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
922 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
924 static struct m3_quirk m3_quirk_list[] = {
925 /* panasonic CF-28 "toughbook" */
927 .name = "Panasonic CF-28",
932 /* panasonic CF-72 "toughbook" */
934 .name = "Panasonic CF-72",
939 /* Dell Inspiron 4000 */
941 .name = "Dell Inspiron 4000",
945 .irda_workaround = 1,
947 /* Dell Inspiron 8000 */
949 .name = "Dell Inspiron 8000",
953 .irda_workaround = 1,
955 /* Dell Inspiron 8100 */
957 .name = "Dell Inspiron 8100",
961 .irda_workaround = 1,
965 .name = "NEC LM800J/7",
979 #define big_mdelay(msec) do {\
980 set_current_state(TASK_UNINTERRUPTIBLE);\
981 schedule_timeout(((msec) * HZ) / 1000);\
984 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
986 outw(value, chip->iobase + reg);
989 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
991 return inw(chip->iobase + reg);
994 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
996 outb(value, chip->iobase + reg);
999 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
1001 return inb(chip->iobase + reg);
1005 * access 16bit words to the code or data regions of the dsp's memory.
1006 * index addresses 16bit words.
1008 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1010 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1011 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1012 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1015 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1017 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1018 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1019 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1022 static void snd_m3_assp_halt(m3_t *chip)
1024 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1026 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1029 static void snd_m3_assp_continue(m3_t *chip)
1031 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1036 * This makes me sad. the maestro3 has lists
1037 * internally that must be packed.. 0 terminates,
1038 * apparently, or maybe all unused entries have
1039 * to be 0, the lists have static lengths set
1040 * by the binary code images.
1043 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1045 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1046 list->mem_addr + list->curlen,
1048 return list->curlen++;
1051 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1054 int lastindex = list->curlen - 1;
1056 if (index != lastindex) {
1057 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1058 list->mem_addr + lastindex);
1059 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1060 list->mem_addr + index,
1064 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1065 list->mem_addr + lastindex,
1071 static void snd_m3_inc_timer_users(m3_t *chip)
1073 chip->timer_users++;
1074 if (chip->timer_users != 1)
1077 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1078 KDATA_TIMER_COUNT_RELOAD,
1081 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1082 KDATA_TIMER_COUNT_CURRENT,
1086 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1090 static void snd_m3_dec_timer_users(m3_t *chip)
1092 chip->timer_users--;
1093 if (chip->timer_users > 0)
1096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1097 KDATA_TIMER_COUNT_RELOAD,
1100 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1101 KDATA_TIMER_COUNT_CURRENT,
1105 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1113 /* spinlock held! */
1114 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1119 snd_m3_inc_timer_users(chip);
1120 switch (subs->stream) {
1121 case SNDRV_PCM_STREAM_PLAYBACK:
1122 chip->dacs_active++;
1123 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1124 s->inst.data + CDATA_INSTANCE_READY, 1);
1125 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1126 KDATA_MIXER_TASK_NUMBER,
1129 case SNDRV_PCM_STREAM_CAPTURE:
1130 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1131 KDATA_ADC1_REQUEST, 1);
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 s->inst.data + CDATA_INSTANCE_READY, 1);
1139 /* spinlock held! */
1140 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1145 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1146 s->inst.data + CDATA_INSTANCE_READY, 0);
1147 snd_m3_dec_timer_users(chip);
1148 switch (subs->stream) {
1149 case SNDRV_PCM_STREAM_PLAYBACK:
1150 chip->dacs_active--;
1151 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1152 KDATA_MIXER_TASK_NUMBER,
1155 case SNDRV_PCM_STREAM_CAPTURE:
1156 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1157 KDATA_ADC1_REQUEST, 0);
1164 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1166 m3_t *chip = snd_pcm_substream_chip(subs);
1167 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1168 unsigned long flags;
1171 snd_assert(s != NULL, return -ENXIO);
1173 spin_lock_irqsave(&chip->reg_lock, flags);
1175 case SNDRV_PCM_TRIGGER_START:
1176 case SNDRV_PCM_TRIGGER_RESUME:
1181 err = snd_m3_pcm_start(chip, s, subs);
1184 case SNDRV_PCM_TRIGGER_STOP:
1185 case SNDRV_PCM_TRIGGER_SUSPEND:
1187 err = 0; /* should return error? */
1190 err = snd_m3_pcm_stop(chip, s, subs);
1194 spin_unlock_irqrestore(&chip->reg_lock, flags);
1202 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1204 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1205 snd_pcm_runtime_t *runtime = subs->runtime;
1207 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1208 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1209 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1211 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1212 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1214 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1215 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1217 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1218 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1222 #define LO(x) ((x) & 0xffff)
1223 #define HI(x) LO((x) >> 16)
1225 /* host dma buffer pointers */
1226 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1227 s->inst.data + CDATA_HOST_SRC_ADDRL,
1228 LO(s->buffer_addr));
1230 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1231 s->inst.data + CDATA_HOST_SRC_ADDRH,
1232 HI(s->buffer_addr));
1234 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1235 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1236 LO(s->buffer_addr + s->dma_size));
1238 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1239 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1240 HI(s->buffer_addr + s->dma_size));
1242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1243 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1244 LO(s->buffer_addr));
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1248 HI(s->buffer_addr));
1254 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1255 s->inst.data + CDATA_IN_BUF_BEGIN,
1258 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1259 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1260 dsp_in_buffer + (dsp_in_size / 2));
1262 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1263 s->inst.data + CDATA_IN_BUF_HEAD,
1266 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1267 s->inst.data + CDATA_IN_BUF_TAIL,
1270 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1271 s->inst.data + CDATA_OUT_BUF_BEGIN,
1274 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1275 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1276 dsp_out_buffer + (dsp_out_size / 2));
1278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1279 s->inst.data + CDATA_OUT_BUF_HEAD,
1282 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1283 s->inst.data + CDATA_OUT_BUF_TAIL,
1287 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1292 * put us in the lists if we're not already there
1294 if (! s->in_lists) {
1295 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1296 s->inst.data >> DP_SHIFT_COUNT);
1297 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1298 s->inst.data >> DP_SHIFT_COUNT);
1299 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1300 s->inst.data >> DP_SHIFT_COUNT);
1304 /* write to 'mono' word */
1305 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1306 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1307 runtime->channels == 2 ? 0 : 1);
1308 /* write to '8bit' word */
1309 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1310 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1311 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1313 /* set up dac/adc rate */
1314 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1318 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1319 s->inst.data + CDATA_FREQUENCY,
1324 static struct play_vals {
1327 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1328 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1329 {SRC3_DIRECTION_OFFSET, 0} ,
1330 /* +1, +2 are stereo/16 bit */
1331 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1332 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1333 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1334 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1335 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1336 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1337 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1338 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1339 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1340 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1341 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1342 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1343 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1344 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1345 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1346 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1347 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1351 /* the mode passed should be already shifted and masked */
1353 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1358 * some per client initializers
1361 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1362 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1363 s->inst.data + 40 + 8);
1365 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1366 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1367 s->inst.code + MINISRC_COEF_LOC);
1369 /* enable or disable low pass filter? */
1370 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1371 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1372 subs->runtime->rate > 45000 ? 0xff : 0);
1374 /* tell it which way dma is going? */
1375 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1376 s->inst.data + CDATA_DMA_CONTROL,
1377 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1380 * set an armload of static initializers
1382 for (i = 0; i < ARRAY_SIZE(pv); i++)
1383 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1384 s->inst.data + pv[i].addr, pv[i].val);
1388 * Native record driver
1390 static struct rec_vals {
1393 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1394 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1395 {SRC3_DIRECTION_OFFSET, 1} ,
1396 /* +1, +2 are stereo/16 bit */
1397 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1398 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1399 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1400 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1401 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1402 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1403 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1404 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1405 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1406 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1407 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1408 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1409 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1410 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1411 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1412 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1413 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1414 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1415 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1419 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1424 * some per client initializers
1427 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1428 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1429 s->inst.data + 40 + 8);
1431 /* tell it which way dma is going? */
1432 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1433 s->inst.data + CDATA_DMA_CONTROL,
1434 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1435 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1438 * set an armload of static initializers
1440 for (i = 0; i < ARRAY_SIZE(rv); i++)
1441 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1442 s->inst.data + rv[i].addr, rv[i].val);
1445 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1446 snd_pcm_hw_params_t * hw_params)
1448 m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1451 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1453 /* set buffer address */
1454 s->buffer_addr = substream->runtime->dma_addr;
1455 if (s->buffer_addr & 0x3) {
1456 snd_printk("oh my, not aligned\n");
1457 s->buffer_addr = s->buffer_addr & ~0x3;
1462 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1466 if (substream->runtime->private_data == NULL)
1468 s = (m3_dma_t*) substream->runtime->private_data;
1469 snd_pcm_lib_free_pages(substream);
1475 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1477 m3_t *chip = snd_pcm_substream_chip(subs);
1478 snd_pcm_runtime_t *runtime = subs->runtime;
1479 m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1480 unsigned long flags;
1482 snd_assert(s != NULL, return -ENXIO);
1484 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1485 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1487 if (runtime->rate > 48000 ||
1488 runtime->rate < 8000)
1491 spin_lock_irqsave(&chip->reg_lock, flags);
1493 snd_m3_pcm_setup1(chip, s, subs);
1495 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1496 snd_m3_playback_setup(chip, s, subs);
1498 snd_m3_capture_setup(chip, s, subs);
1500 snd_m3_pcm_setup2(chip, s, runtime);
1502 spin_unlock_irqrestore(&chip->reg_lock, flags);
1508 * get current pointer
1511 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1518 * try and get a valid answer
1521 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1522 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1524 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1525 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1527 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1528 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1531 addr = lo | ((u32)hi<<16);
1532 return (unsigned int)(addr - s->buffer_addr);
1535 static snd_pcm_uframes_t
1536 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1538 m3_t *chip = snd_pcm_substream_chip(subs);
1540 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1541 snd_assert(s != NULL, return 0);
1543 spin_lock(&chip->reg_lock);
1544 ptr = snd_m3_get_pointer(chip, s, subs);
1545 spin_unlock(&chip->reg_lock);
1546 return bytes_to_frames(subs->runtime, ptr);
1550 /* update pointer */
1551 /* spinlock held! */
1552 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1554 snd_pcm_substream_t *subs = s->substream;
1561 hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1562 diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1565 if (s->count >= (signed)s->period_size) {
1566 s->count %= s->period_size;
1567 spin_unlock(&chip->reg_lock);
1568 snd_pcm_period_elapsed(subs);
1569 spin_lock(&chip->reg_lock);
1574 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1576 m3_t *chip = snd_magic_cast(m3_t, dev_id, );
1580 status = inb(chip->iobase + HOST_INT_STATUS);
1586 * ack an assp int if its running
1587 * and has an int pending
1589 if (status & ASSP_INT_PENDING) {
1590 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1591 if (!(ctl & STOP_ASSP_CLOCK)) {
1592 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1593 if (ctl & DSP2HOST_REQ_TIMER) {
1594 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1595 /* update adc/dac info if it was a timer int */
1596 spin_lock(&chip->reg_lock);
1597 for (i = 0; i < chip->num_substreams; i++) {
1598 m3_dma_t *s = &chip->substreams[i];
1600 snd_m3_update_ptr(chip, s);
1602 spin_unlock(&chip->reg_lock);
1607 #if 0 /* TODO: not supported yet */
1608 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1609 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1613 snd_m3_outw(chip, HOST_INT_STATUS, status);
1622 static snd_pcm_hardware_t snd_m3_playback =
1624 .info = (SNDRV_PCM_INFO_MMAP |
1625 SNDRV_PCM_INFO_INTERLEAVED |
1626 SNDRV_PCM_INFO_MMAP_VALID |
1627 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1628 /*SNDRV_PCM_INFO_PAUSE |*/
1629 SNDRV_PCM_INFO_RESUME),
1630 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1631 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1636 .buffer_bytes_max = (512*1024),
1637 .period_bytes_min = 64,
1638 .period_bytes_max = (512*1024),
1640 .periods_max = 1024,
1643 static snd_pcm_hardware_t snd_m3_capture =
1645 .info = (SNDRV_PCM_INFO_MMAP |
1646 SNDRV_PCM_INFO_INTERLEAVED |
1647 SNDRV_PCM_INFO_MMAP_VALID |
1648 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1649 /*SNDRV_PCM_INFO_PAUSE |*/
1650 SNDRV_PCM_INFO_RESUME),
1651 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1652 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1657 .buffer_bytes_max = (512*1024),
1658 .period_bytes_min = 64,
1659 .period_bytes_max = (512*1024),
1661 .periods_max = 1024,
1669 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1673 unsigned long flags;
1675 spin_lock_irqsave(&chip->reg_lock, flags);
1676 for (i = 0; i < chip->num_substreams; i++) {
1677 s = &chip->substreams[i];
1681 spin_unlock_irqrestore(&chip->reg_lock, flags);
1686 spin_unlock_irqrestore(&chip->reg_lock, flags);
1688 subs->runtime->private_data = s;
1689 s->substream = subs;
1691 /* set list owners */
1692 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1693 s->index_list[0] = &chip->mixer_list;
1695 s->index_list[0] = &chip->adc1_list;
1696 s->index_list[1] = &chip->msrc_list;
1697 s->index_list[2] = &chip->dma_list;
1703 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1705 m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1706 unsigned long flags;
1709 return; /* not opened properly */
1711 spin_lock_irqsave(&chip->reg_lock, flags);
1712 if (s->substream && s->running)
1713 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1715 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1716 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1717 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1722 spin_unlock_irqrestore(&chip->reg_lock, flags);
1726 snd_m3_playback_open(snd_pcm_substream_t *subs)
1728 m3_t *chip = snd_pcm_substream_chip(subs);
1729 snd_pcm_runtime_t *runtime = subs->runtime;
1732 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1735 runtime->hw = snd_m3_playback;
1736 snd_pcm_set_sync(subs);
1742 snd_m3_playback_close(snd_pcm_substream_t *subs)
1744 m3_t *chip = snd_pcm_substream_chip(subs);
1746 snd_m3_substream_close(chip, subs);
1751 snd_m3_capture_open(snd_pcm_substream_t *subs)
1753 m3_t *chip = snd_pcm_substream_chip(subs);
1754 snd_pcm_runtime_t *runtime = subs->runtime;
1757 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1760 runtime->hw = snd_m3_capture;
1761 snd_pcm_set_sync(subs);
1767 snd_m3_capture_close(snd_pcm_substream_t *subs)
1769 m3_t *chip = snd_pcm_substream_chip(subs);
1771 snd_m3_substream_close(chip, subs);
1776 * create pcm instance
1779 static snd_pcm_ops_t snd_m3_playback_ops = {
1780 .open = snd_m3_playback_open,
1781 .close = snd_m3_playback_close,
1782 .ioctl = snd_pcm_lib_ioctl,
1783 .hw_params = snd_m3_pcm_hw_params,
1784 .hw_free = snd_m3_pcm_hw_free,
1785 .prepare = snd_m3_pcm_prepare,
1786 .trigger = snd_m3_pcm_trigger,
1787 .pointer = snd_m3_pcm_pointer,
1790 static snd_pcm_ops_t snd_m3_capture_ops = {
1791 .open = snd_m3_capture_open,
1792 .close = snd_m3_capture_close,
1793 .ioctl = snd_pcm_lib_ioctl,
1794 .hw_params = snd_m3_pcm_hw_params,
1795 .hw_free = snd_m3_pcm_hw_free,
1796 .prepare = snd_m3_pcm_prepare,
1797 .trigger = snd_m3_pcm_trigger,
1798 .pointer = snd_m3_pcm_pointer,
1801 static int __devinit
1802 snd_m3_pcm(m3_t * chip, int device)
1807 err = snd_pcm_new(chip->card, chip->card->driver, device,
1808 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1812 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1813 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1815 pcm->private_data = chip;
1816 pcm->info_flags = 0;
1817 strcpy(pcm->name, chip->card->driver);
1820 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1821 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1832 * Wait for the ac97 serial bus to be free.
1833 * return nonzero if the bus is still busy.
1835 static int snd_m3_ac97_wait(m3_t *chip)
1840 if (! (snd_m3_inb(chip, 0x30) & 1))
1844 snd_printk("ac97 serial bus busy\n");
1848 static unsigned short
1849 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1851 m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return -ENXIO);
1852 unsigned short ret = 0;
1853 unsigned long flags;
1855 spin_lock_irqsave(&chip->reg_lock, flags);
1856 if (snd_m3_ac97_wait(chip))
1858 snd_m3_outb(chip, 0x80 | (reg & 0x7f), 0x30);
1859 if (snd_m3_ac97_wait(chip))
1861 ret = snd_m3_inw(chip, 0x32);
1863 spin_unlock_irqrestore(&chip->reg_lock, flags);
1868 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1870 m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return);
1871 unsigned long flags;
1873 spin_lock_irqsave(&chip->reg_lock, flags);
1874 if (snd_m3_ac97_wait(chip))
1876 snd_m3_outw(chip, val, 0x32);
1877 snd_m3_outb(chip, reg & 0x7f, 0x30);
1879 spin_unlock_irqrestore(&chip->reg_lock, flags);
1883 static void snd_m3_remote_codec_config(int io, int isremote)
1885 isremote = isremote ? 1 : 0;
1887 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1888 io + RING_BUS_CTRL_B);
1889 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1890 io + SDO_OUT_DEST_CTRL);
1891 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1892 io + SDO_IN_DEST_CTRL);
1896 * hack, returns non zero on err
1898 static int snd_m3_try_read_vendor(m3_t *chip)
1902 if (snd_m3_ac97_wait(chip))
1905 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1907 if (snd_m3_ac97_wait(chip))
1910 ret = snd_m3_inw(chip, 0x32);
1912 return (ret == 0) || (ret == 0xffff);
1915 static void snd_m3_ac97_reset(m3_t *chip)
1918 int delay1 = 0, delay2 = 0, i;
1919 int io = chip->iobase;
1921 if (chip->allegro_flag) {
1923 * the onboard codec on the allegro seems
1924 * to want to wait a very long time before
1925 * coming back to life
1935 for (i = 0; i < 5; i++) {
1936 dir = inw(io + GPIO_DIRECTION);
1937 if (! chip->quirk || ! chip->quirk->irda_workaround)
1938 dir |= 0x10; /* assuming pci bus master? */
1940 snd_m3_remote_codec_config(io, 0);
1942 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1945 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1946 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1947 outw(0, io + GPIO_DATA);
1948 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1950 set_current_state(TASK_UNINTERRUPTIBLE);
1951 schedule_timeout((delay1 * HZ) / 1000);
1953 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1955 /* ok, bring back the ac-link */
1956 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1957 outw(~0, io + GPIO_MASK);
1959 set_current_state(TASK_UNINTERRUPTIBLE);
1960 schedule_timeout((delay2 * HZ) / 1000);
1962 if (! snd_m3_try_read_vendor(chip))
1968 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1973 /* more gung-ho reset that doesn't
1974 * seem to work anywhere :)
1976 tmp = inw(io + RING_BUS_CTRL_A);
1977 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1979 outw(tmp, io + RING_BUS_CTRL_A);
1984 static int __devinit snd_m3_mixer(m3_t *chip)
1986 ac97_bus_t bus, *pbus;
1990 memset(&bus, 0, sizeof(bus));
1991 bus.write = snd_m3_ac97_write;
1992 bus.read = snd_m3_ac97_read;
1993 if ((err = snd_ac97_bus(chip->card, &bus, &pbus)) < 0)
1996 memset(&ac97, 0, sizeof(ac97));
1997 ac97.private_data = chip;
1998 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2001 /* seems ac97 PCM needs initialization.. hack hack.. */
2002 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2003 set_current_state(TASK_UNINTERRUPTIBLE);
2004 schedule_timeout(HZ / 10);
2005 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2015 static u16 assp_kernel_image[] __devinitdata = {
2016 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2017 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2018 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2019 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2020 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2021 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2022 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2023 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2024 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2025 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2026 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2027 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2028 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2029 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2030 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2031 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2032 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2033 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2034 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2035 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2036 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2037 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2038 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2039 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2040 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2041 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2042 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2043 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2044 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2045 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2046 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2047 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2048 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2049 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2050 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2051 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2052 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2053 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2054 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2055 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2056 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2057 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2058 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2059 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2060 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2061 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2062 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2063 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2064 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2065 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2066 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2067 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2068 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2069 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2070 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2071 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2072 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2073 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2074 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2075 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2076 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2077 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2078 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2079 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2080 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2081 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2082 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2083 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2084 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2085 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2086 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2087 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2088 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2089 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2090 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2091 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2092 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2093 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2094 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2099 * Mini sample rate converter code image
2100 * that is to be loaded at 0x400 on the DSP.
2102 static u16 assp_minisrc_image[] __devinitdata = {
2104 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2105 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2106 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2107 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2108 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2109 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2110 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2111 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2112 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2113 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2114 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2115 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2116 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2117 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2118 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2119 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2120 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2121 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2122 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2123 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2124 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2125 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2126 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2127 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2128 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2129 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2130 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2131 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2132 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2133 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2134 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2135 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2136 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2144 #define MINISRC_LPF_LEN 10
2145 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2146 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2147 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2150 static void __devinit snd_m3_assp_init(m3_t *chip)
2154 /* zero kernel data */
2155 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2156 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2157 KDATA_BASE_ADDR + i, 0);
2159 /* zero mixer data? */
2160 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2162 KDATA_BASE_ADDR2 + i, 0);
2164 /* init dma pointer */
2165 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2169 /* write kernel into code memory.. */
2170 for (i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2171 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2172 REV_B_CODE_MEMORY_BEGIN + i,
2173 assp_kernel_image[i]);
2177 * We only have this one client and we know that 0x400
2178 * is free in our kernel's mem map, so lets just
2179 * drop it there. It seems that the minisrc doesn't
2180 * need vectors, so we won't bother with them..
2182 for (i = 0; i < sizeof(assp_minisrc_image) / 2; i++) {
2183 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2185 assp_minisrc_image[i]);
2189 * write the coefficients for the low pass filter?
2191 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2192 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2193 0x400 + MINISRC_COEF_LOC + i,
2197 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2198 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2202 * the minisrc is the only thing on
2205 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2210 * init the mixer number..
2213 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2214 KDATA_MIXER_TASK_NUMBER,0);
2217 * EXTREME KERNEL MASTER VOLUME
2219 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2220 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2221 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2222 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2224 chip->mixer_list.curlen = 0;
2225 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2226 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2227 chip->adc1_list.curlen = 0;
2228 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2229 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2230 chip->dma_list.curlen = 0;
2231 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2232 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2233 chip->msrc_list.curlen = 0;
2234 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2235 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2239 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2241 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2242 MINISRC_IN_BUFFER_SIZE / 2 +
2243 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2247 * the revb memory map has 0x1100 through 0x1c00
2252 * align instance address to 256 bytes so that it's
2253 * shifted list address is aligned.
2254 * list address = (mem address >> 1) >> 7;
2256 data_bytes = (data_bytes + 255) & ~255;
2257 address = 0x1100 + ((data_bytes/2) * index);
2259 if ((address + (data_bytes/2)) >= 0x1c00) {
2260 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2261 data_bytes, index, address);
2266 s->inst.code = 0x400;
2267 s->inst.data = address;
2269 for (i = data_bytes / 2; i > 0; address++, i--) {
2270 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2279 * this works for the reference board, have to find
2282 * this needs more magic for 4 speaker, but..
2285 snd_m3_amp_enable(m3_t *chip, int enable)
2287 int io = chip->iobase;
2290 if (! chip->external_amp)
2293 polarity = enable ? 0 : 1;
2294 polarity = polarity << chip->amp_gpio;
2295 gpo = 1 << chip->amp_gpio;
2297 outw(~gpo, io + GPIO_MASK);
2299 outw(inw(io + GPIO_DIRECTION) | gpo,
2300 io + GPIO_DIRECTION);
2302 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2305 outw(0xffff, io + GPIO_MASK);
2309 snd_m3_chip_init(m3_t *chip)
2311 struct pci_dev *pcidev = chip->pci;
2314 u8 t; /* makes as much sense as 'n', no? */
2316 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2317 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2318 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2320 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2322 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2323 n &= REDUCED_DEBOUNCE;
2324 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2325 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2327 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2328 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2329 n &= ~INT_CLK_SELECT;
2330 if (!chip->allegro_flag) {
2331 n &= ~INT_CLK_MULT_ENABLE;
2332 n |= INT_CLK_SRC_NOT_PCI;
2334 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2335 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2337 if (chip->allegro_flag) {
2338 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2339 n |= IN_CLK_12MHZ_SELECT;
2340 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2343 t = inb(chip->iobase + ASSP_CONTROL_A);
2344 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2345 t |= ASSP_CLK_49MHZ_SELECT;
2346 t |= ASSP_0_WS_ENABLE;
2347 outb(t, chip->iobase + ASSP_CONTROL_A);
2349 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2355 snd_m3_enable_ints(m3_t *chip)
2357 unsigned long io = chip->iobase;
2359 /* TODO: MPU401 not supported yet */
2360 outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2361 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2362 io + ASSP_CONTROL_C);
2369 static int snd_m3_free(m3_t *chip)
2371 unsigned long flags;
2375 if (chip->substreams) {
2376 spin_lock_irqsave(&chip->reg_lock, flags);
2377 for (i = 0; i < chip->num_substreams; i++) {
2378 s = &chip->substreams[i];
2379 /* check surviving pcms; this should not happen though.. */
2380 if (s->substream && s->running)
2381 snd_m3_pcm_stop(chip, s, s->substream);
2383 spin_unlock_irqrestore(&chip->reg_lock, flags);
2384 kfree(chip->substreams);
2386 if (chip->iobase_res) {
2387 snd_m3_outw(chip, HOST_INT_CTRL, 0); /* disable ints */
2391 if (chip->suspend_mem)
2392 vfree(chip->suspend_mem);
2396 synchronize_irq(chip->irq);
2398 if (chip->iobase_res) {
2399 release_resource(chip->iobase_res);
2400 kfree_nocheck(chip->iobase_res);
2403 free_irq(chip->irq, (void *)chip);
2405 snd_magic_kfree(chip);
2414 static int m3_suspend(snd_card_t *card, unsigned int state)
2416 m3_t *chip = snd_magic_cast(m3_t, card->pm_private_data, return -EINVAL);
2419 if (chip->suspend_mem == NULL)
2422 snd_pcm_suspend_all(chip->pcm);
2423 snd_ac97_suspend(chip->ac97);
2425 big_mdelay(10); /* give the assp a chance to idle.. */
2427 snd_m3_assp_halt(chip);
2429 /* save dsp image */
2431 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2432 chip->suspend_mem[index++] =
2433 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2434 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2435 chip->suspend_mem[index++] =
2436 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2438 /* power down apci registers */
2439 snd_m3_outw(chip, 0xffff, 0x54);
2440 snd_m3_outw(chip, 0xffff, 0x56);
2441 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2445 static int m3_resume(snd_card_t *card, unsigned int state)
2447 m3_t *chip = snd_magic_cast(m3_t, card->pm_private_data, return -EINVAL);
2450 if (chip->suspend_mem == NULL)
2453 /* first lets just bring everything back. .*/
2454 snd_m3_outw(chip, 0, 0x54);
2455 snd_m3_outw(chip, 0, 0x56);
2457 snd_m3_chip_init(chip);
2458 snd_m3_assp_halt(chip);
2459 snd_m3_ac97_reset(chip);
2461 /* restore dsp image */
2463 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2464 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2465 chip->suspend_mem[index++]);
2466 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2467 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2468 chip->suspend_mem[index++]);
2470 /* tell the dma engine to restart itself */
2471 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2472 KDATA_DMA_ACTIVE, 0);
2474 /* restore ac97 registers */
2475 snd_ac97_resume(chip->ac97);
2477 snd_m3_assp_continue(chip);
2478 snd_m3_enable_ints(chip);
2479 snd_m3_amp_enable(chip, 1);
2481 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2484 #endif /* CONFIG_PM */
2490 static int snd_m3_dev_free(snd_device_t *device)
2492 m3_t *chip = snd_magic_cast(m3_t, device->device_data, return -ENXIO);
2493 return snd_m3_free(chip);
2496 static int __devinit
2497 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2504 struct m3_quirk *quirk;
2505 u16 subsystem_vendor, subsystem_device;
2506 static snd_device_ops_t ops = {
2507 .dev_free = snd_m3_dev_free,
2512 if (pci_enable_device(pci))
2515 /* check, if we can restrict PCI DMA transfers to 28 bits */
2516 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2517 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2518 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2522 chip = snd_magic_kcalloc(m3_t, 0, GFP_KERNEL);
2526 spin_lock_init(&chip->reg_lock);
2527 switch (pci->device) {
2528 case PCI_DEVICE_ID_ESS_ALLEGRO:
2529 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2530 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2531 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2532 chip->allegro_flag = 1;
2540 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2541 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2543 for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2544 if (subsystem_vendor == quirk->vendor &&
2545 subsystem_device == quirk->device) {
2546 printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2547 chip->quirk = quirk;
2552 chip->external_amp = enable_amp;
2553 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2554 chip->amp_gpio = amp_gpio;
2555 else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2556 chip->amp_gpio = chip->quirk->amp_gpio;
2557 else if (chip->allegro_flag)
2558 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2559 else /* presumably this is for all 'maestro3's.. */
2560 chip->amp_gpio = GPO_EXT_AMP_M3;
2562 chip->num_substreams = NR_DSPS;
2563 chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2564 if (chip->substreams == NULL) {
2565 snd_magic_kfree(chip);
2568 memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2570 chip->iobase = pci_resource_start(pci, 0);
2571 if ((chip->iobase_res = request_region(chip->iobase, 256,
2572 card->driver)) == NULL) {
2573 snd_printk("unable to grab i/o ports %ld\n", chip->iobase);
2578 /* just to be sure */
2579 pci_set_master(pci);
2581 snd_m3_chip_init(chip);
2582 snd_m3_assp_halt(chip);
2584 snd_m3_ac97_reset(chip);
2586 snd_m3_assp_init(chip);
2587 snd_m3_amp_enable(chip, 1);
2589 if ((err = snd_m3_mixer(chip)) < 0) {
2594 for (i = 0; i < chip->num_substreams; i++) {
2595 m3_dma_t *s = &chip->substreams[i];
2597 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) {
2603 if ((err = snd_m3_pcm(chip, 0)) < 0) {
2608 if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2609 card->driver, (void *)chip)) {
2610 snd_printk("unable to grab IRQ %d\n", pci->irq);
2614 chip->irq = pci->irq;
2617 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2618 if (chip->suspend_mem == NULL)
2619 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2621 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2624 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2629 snd_m3_enable_ints(chip);
2630 snd_m3_assp_continue(chip);
2632 snd_card_set_dev(card, &pci->dev);
2641 static int __devinit
2642 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2649 /* don't pick up modems */
2650 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2653 if (dev >= SNDRV_CARDS)
2660 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2664 switch (pci->device) {
2665 case PCI_DEVICE_ID_ESS_ALLEGRO:
2666 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2667 strcpy(card->driver, "Allegro");
2669 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2670 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2671 strcpy(card->driver, "Canyon3D-2");
2674 strcpy(card->driver, "Maestro3");
2678 if ((err = snd_m3_create(card, pci,
2682 snd_card_free(card);
2686 sprintf(card->shortname, "ESS %s PCI", card->driver);
2687 sprintf(card->longname, "%s at 0x%lx, irq %d",
2688 card->shortname, chip->iobase, chip->irq);
2690 if ((err = snd_card_register(card)) < 0) {
2691 snd_card_free(card);
2695 #if 0 /* TODO: not supported yet */
2696 /* TODO enable midi irq and i/o */
2697 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2698 chip->iobase + MPU401_DATA_PORT, 1,
2699 chip->irq, 0, &chip->rmidi);
2701 printk(KERN_WARNING "maestro3: no midi support.\n");
2704 pci_set_drvdata(pci, card);
2709 static void __devexit snd_m3_remove(struct pci_dev *pci)
2711 snd_card_free(pci_get_drvdata(pci));
2712 pci_set_drvdata(pci, NULL);
2715 static struct pci_driver driver = {
2717 .id_table = snd_m3_ids,
2718 .probe = snd_m3_probe,
2719 .remove = __devexit_p(snd_m3_remove),
2720 SND_PCI_PM_CALLBACKS
2723 static int __init alsa_card_m3_init(void)
2725 return pci_module_init(&driver);
2728 static void __exit alsa_card_m3_exit(void)
2730 pci_unregister_driver(&driver);
2733 module_init(alsa_card_m3_init)
2734 module_exit(alsa_card_m3_exit)