2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
44 /* note, two last pcis should be equal, it is not a bug */
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
49 MODULE_LICENSE("GPL");
50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
54 "{RME,Digi96/8 PAD}}");
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
61 module_param_array(index, int, boot_devs, 0444);
62 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
63 module_param_array(id, charp, boot_devs, 0444);
64 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
65 module_param_array(enable, bool, boot_devs, 0444);
66 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
69 * Defines for RME Digi96 series, from internal RME reference documents
73 #define RME96_SPDIF_NCHANNELS 2
75 /* Playback and capture buffer size */
76 #define RME96_BUFFER_SIZE 0x10000
79 #define RME96_IO_SIZE 0x60000
82 #define RME96_IO_PLAY_BUFFER 0x0
83 #define RME96_IO_REC_BUFFER 0x10000
84 #define RME96_IO_CONTROL_REGISTER 0x20000
85 #define RME96_IO_ADDITIONAL_REG 0x20004
86 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
87 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
88 #define RME96_IO_SET_PLAY_POS 0x40000
89 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
90 #define RME96_IO_SET_REC_POS 0x50000
91 #define RME96_IO_RESET_REC_POS 0x5FFFC
92 #define RME96_IO_GET_PLAY_POS 0x20000
93 #define RME96_IO_GET_REC_POS 0x30000
95 /* Write control register bits */
96 #define RME96_WCR_START (1 << 0)
97 #define RME96_WCR_START_2 (1 << 1)
98 #define RME96_WCR_GAIN_0 (1 << 2)
99 #define RME96_WCR_GAIN_1 (1 << 3)
100 #define RME96_WCR_MODE24 (1 << 4)
101 #define RME96_WCR_MODE24_2 (1 << 5)
102 #define RME96_WCR_BM (1 << 6)
103 #define RME96_WCR_BM_2 (1 << 7)
104 #define RME96_WCR_ADAT (1 << 8)
105 #define RME96_WCR_FREQ_0 (1 << 9)
106 #define RME96_WCR_FREQ_1 (1 << 10)
107 #define RME96_WCR_DS (1 << 11)
108 #define RME96_WCR_PRO (1 << 12)
109 #define RME96_WCR_EMP (1 << 13)
110 #define RME96_WCR_SEL (1 << 14)
111 #define RME96_WCR_MASTER (1 << 15)
112 #define RME96_WCR_PD (1 << 16)
113 #define RME96_WCR_INP_0 (1 << 17)
114 #define RME96_WCR_INP_1 (1 << 18)
115 #define RME96_WCR_THRU_0 (1 << 19)
116 #define RME96_WCR_THRU_1 (1 << 20)
117 #define RME96_WCR_THRU_2 (1 << 21)
118 #define RME96_WCR_THRU_3 (1 << 22)
119 #define RME96_WCR_THRU_4 (1 << 23)
120 #define RME96_WCR_THRU_5 (1 << 24)
121 #define RME96_WCR_THRU_6 (1 << 25)
122 #define RME96_WCR_THRU_7 (1 << 26)
123 #define RME96_WCR_DOLBY (1 << 27)
124 #define RME96_WCR_MONITOR_0 (1 << 28)
125 #define RME96_WCR_MONITOR_1 (1 << 29)
126 #define RME96_WCR_ISEL (1 << 30)
127 #define RME96_WCR_IDIS (1 << 31)
129 #define RME96_WCR_BITPOS_GAIN_0 2
130 #define RME96_WCR_BITPOS_GAIN_1 3
131 #define RME96_WCR_BITPOS_FREQ_0 9
132 #define RME96_WCR_BITPOS_FREQ_1 10
133 #define RME96_WCR_BITPOS_INP_0 17
134 #define RME96_WCR_BITPOS_INP_1 18
135 #define RME96_WCR_BITPOS_MONITOR_0 28
136 #define RME96_WCR_BITPOS_MONITOR_1 29
138 /* Read control register bits */
139 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
140 #define RME96_RCR_IRQ_2 (1 << 16)
141 #define RME96_RCR_T_OUT (1 << 17)
142 #define RME96_RCR_DEV_ID_0 (1 << 21)
143 #define RME96_RCR_DEV_ID_1 (1 << 22)
144 #define RME96_RCR_LOCK (1 << 23)
145 #define RME96_RCR_VERF (1 << 26)
146 #define RME96_RCR_F0 (1 << 27)
147 #define RME96_RCR_F1 (1 << 28)
148 #define RME96_RCR_F2 (1 << 29)
149 #define RME96_RCR_AUTOSYNC (1 << 30)
150 #define RME96_RCR_IRQ (1 << 31)
152 #define RME96_RCR_BITPOS_F0 27
153 #define RME96_RCR_BITPOS_F1 28
154 #define RME96_RCR_BITPOS_F2 29
156 /* Additonal register bits */
157 #define RME96_AR_WSEL (1 << 0)
158 #define RME96_AR_ANALOG (1 << 1)
159 #define RME96_AR_FREQPAD_0 (1 << 2)
160 #define RME96_AR_FREQPAD_1 (1 << 3)
161 #define RME96_AR_FREQPAD_2 (1 << 4)
162 #define RME96_AR_PD2 (1 << 5)
163 #define RME96_AR_DAC_EN (1 << 6)
164 #define RME96_AR_CLATCH (1 << 7)
165 #define RME96_AR_CCLK (1 << 8)
166 #define RME96_AR_CDATA (1 << 9)
168 #define RME96_AR_BITPOS_F0 2
169 #define RME96_AR_BITPOS_F1 3
170 #define RME96_AR_BITPOS_F2 4
173 #define RME96_MONITOR_TRACKS_1_2 0
174 #define RME96_MONITOR_TRACKS_3_4 1
175 #define RME96_MONITOR_TRACKS_5_6 2
176 #define RME96_MONITOR_TRACKS_7_8 3
179 #define RME96_ATTENUATION_0 0
180 #define RME96_ATTENUATION_6 1
181 #define RME96_ATTENUATION_12 2
182 #define RME96_ATTENUATION_18 3
185 #define RME96_INPUT_OPTICAL 0
186 #define RME96_INPUT_COAXIAL 1
187 #define RME96_INPUT_INTERNAL 2
188 #define RME96_INPUT_XLR 3
189 #define RME96_INPUT_ANALOG 4
192 #define RME96_CLOCKMODE_SLAVE 0
193 #define RME96_CLOCKMODE_MASTER 1
194 #define RME96_CLOCKMODE_WORDCLOCK 2
196 /* Block sizes in bytes */
197 #define RME96_SMALL_BLOCK_SIZE 2048
198 #define RME96_LARGE_BLOCK_SIZE 8192
201 #define RME96_AD1852_VOL_BITS 14
202 #define RME96_AD1855_VOL_BITS 10
205 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
206 * therefore #ifndef is used.
208 #ifndef PCI_VENDOR_ID_XILINX
209 #define PCI_VENDOR_ID_XILINX 0x10ee
211 #ifndef PCI_DEVICE_ID_DIGI96
212 #define PCI_DEVICE_ID_DIGI96 0x3fc0
214 #ifndef PCI_DEVICE_ID_DIGI96_8
215 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
217 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
218 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
220 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
221 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
224 typedef struct snd_rme96 {
228 unsigned long iobase;
230 u32 wcreg; /* cached write control register value */
231 u32 wcreg_spdif; /* S/PDIF setup */
232 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
233 u32 rcreg; /* cached read control register value */
234 u32 areg; /* cached additional register value */
235 u16 vol[2]; /* cached volume of analog output */
237 u8 rev; /* card revision number */
239 snd_pcm_substream_t *playback_substream;
240 snd_pcm_substream_t *capture_substream;
242 int playback_frlog; /* log2 of framesize */
245 size_t playback_periodsize; /* in bytes, zero if not used */
246 size_t capture_periodsize; /* in bytes, zero if not used */
249 snd_pcm_t *spdif_pcm;
252 snd_kcontrol_t *spdif_ctl;
255 static struct pci_device_id snd_rme96_ids[] = {
256 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
258 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
260 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
262 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
267 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
269 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
270 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
271 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
272 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
273 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
274 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
275 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
276 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
277 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
280 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
283 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
286 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
290 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
293 static snd_pcm_uframes_t
294 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
296 static snd_pcm_uframes_t
297 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
299 static void __devinit
300 snd_rme96_proc_init(rme96_t *rme96);
303 snd_rme96_create_switches(snd_card_t *card,
307 snd_rme96_getinputtype(rme96_t *rme96);
309 static inline unsigned int
310 snd_rme96_playback_ptr(rme96_t *rme96)
312 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
313 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
316 static inline unsigned int
317 snd_rme96_capture_ptr(rme96_t *rme96)
319 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
320 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
324 snd_rme96_ratecode(int rate)
327 case 32000: return SNDRV_PCM_RATE_32000;
328 case 44100: return SNDRV_PCM_RATE_44100;
329 case 48000: return SNDRV_PCM_RATE_48000;
330 case 64000: return SNDRV_PCM_RATE_64000;
331 case 88200: return SNDRV_PCM_RATE_88200;
332 case 96000: return SNDRV_PCM_RATE_96000;
338 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
339 int channel, /* not used (interleaved data) */
340 snd_pcm_uframes_t pos,
341 snd_pcm_uframes_t count)
343 rme96_t *rme96 = snd_pcm_substream_chip(substream);
344 count <<= rme96->playback_frlog;
345 pos <<= rme96->playback_frlog;
346 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
352 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
353 int channel, /* not used (interleaved data) */
354 snd_pcm_uframes_t pos,
356 snd_pcm_uframes_t count)
358 rme96_t *rme96 = snd_pcm_substream_chip(substream);
359 count <<= rme96->playback_frlog;
360 pos <<= rme96->playback_frlog;
361 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
367 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
368 int channel, /* not used (interleaved data) */
369 snd_pcm_uframes_t pos,
371 snd_pcm_uframes_t count)
373 rme96_t *rme96 = snd_pcm_substream_chip(substream);
374 count <<= rme96->capture_frlog;
375 pos <<= rme96->capture_frlog;
376 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
382 * Digital output capabilites (S/PDIF)
384 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
386 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
387 SNDRV_PCM_INFO_MMAP_VALID |
388 SNDRV_PCM_INFO_INTERLEAVED |
389 SNDRV_PCM_INFO_PAUSE),
390 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
391 SNDRV_PCM_FMTBIT_S32_LE),
392 .rates = (SNDRV_PCM_RATE_32000 |
393 SNDRV_PCM_RATE_44100 |
394 SNDRV_PCM_RATE_48000 |
395 SNDRV_PCM_RATE_64000 |
396 SNDRV_PCM_RATE_88200 |
397 SNDRV_PCM_RATE_96000),
402 .buffer_bytes_max = RME96_BUFFER_SIZE,
403 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
404 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
405 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
406 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
411 * Digital input capabilites (S/PDIF)
413 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
415 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
416 SNDRV_PCM_INFO_MMAP_VALID |
417 SNDRV_PCM_INFO_INTERLEAVED |
418 SNDRV_PCM_INFO_PAUSE),
419 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
420 SNDRV_PCM_FMTBIT_S32_LE),
421 .rates = (SNDRV_PCM_RATE_32000 |
422 SNDRV_PCM_RATE_44100 |
423 SNDRV_PCM_RATE_48000 |
424 SNDRV_PCM_RATE_64000 |
425 SNDRV_PCM_RATE_88200 |
426 SNDRV_PCM_RATE_96000),
431 .buffer_bytes_max = RME96_BUFFER_SIZE,
432 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
433 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
434 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
435 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
440 * Digital output capabilites (ADAT)
442 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
444 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
445 SNDRV_PCM_INFO_MMAP_VALID |
446 SNDRV_PCM_INFO_INTERLEAVED |
447 SNDRV_PCM_INFO_PAUSE),
448 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
449 SNDRV_PCM_FMTBIT_S32_LE),
450 .rates = (SNDRV_PCM_RATE_44100 |
451 SNDRV_PCM_RATE_48000),
456 .buffer_bytes_max = RME96_BUFFER_SIZE,
457 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
458 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
459 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
460 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
465 * Digital input capabilites (ADAT)
467 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
469 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
470 SNDRV_PCM_INFO_MMAP_VALID |
471 SNDRV_PCM_INFO_INTERLEAVED |
472 SNDRV_PCM_INFO_PAUSE),
473 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
474 SNDRV_PCM_FMTBIT_S32_LE),
475 .rates = (SNDRV_PCM_RATE_44100 |
476 SNDRV_PCM_RATE_48000),
481 .buffer_bytes_max = RME96_BUFFER_SIZE,
482 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
483 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
484 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
485 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
490 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
491 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
492 * on the falling edge of CCLK and be stable on the rising edge. The rising
493 * edge of CLATCH after the last data bit clocks in the whole data word.
494 * A fast processor could probably drive the SPI interface faster than the
495 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
496 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
498 * NOTE: increased delay from 1 to 10, since there where problems setting
502 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
506 for (i = 0; i < 16; i++) {
508 rme96->areg |= RME96_AR_CDATA;
510 rme96->areg &= ~RME96_AR_CDATA;
512 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
513 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
515 rme96->areg |= RME96_AR_CCLK;
516 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
520 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
521 rme96->areg |= RME96_AR_CLATCH;
522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
524 rme96->areg &= ~RME96_AR_CLATCH;
525 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
529 snd_rme96_apply_dac_volume(rme96_t *rme96)
531 if (RME96_DAC_IS_1852(rme96)) {
532 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
533 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
534 } else if (RME96_DAC_IS_1855(rme96)) {
535 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
536 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
541 snd_rme96_reset_dac(rme96_t *rme96)
543 writel(rme96->wcreg | RME96_WCR_PD,
544 rme96->iobase + RME96_IO_CONTROL_REGISTER);
545 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
549 snd_rme96_getmontracks(rme96_t *rme96)
551 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
552 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
556 snd_rme96_setmontracks(rme96_t *rme96,
560 rme96->wcreg |= RME96_WCR_MONITOR_0;
562 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
565 rme96->wcreg |= RME96_WCR_MONITOR_1;
567 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
569 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
574 snd_rme96_getattenuation(rme96_t *rme96)
576 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
577 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
581 snd_rme96_setattenuation(rme96_t *rme96,
584 switch (attenuation) {
586 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
590 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
594 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
598 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
604 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
609 snd_rme96_capture_getrate(rme96_t *rme96,
615 if (rme96->areg & RME96_AR_ANALOG) {
616 /* Analog input, overrides S/PDIF setting */
617 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
618 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
632 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
635 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
636 if (rme96->rcreg & RME96_RCR_LOCK) {
639 if (rme96->rcreg & RME96_RCR_T_OUT) {
645 if (rme96->rcreg & RME96_RCR_VERF) {
650 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
651 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
652 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
656 if (rme96->rcreg & RME96_RCR_T_OUT) {
660 case 3: return 96000;
661 case 4: return 88200;
662 case 5: return 48000;
663 case 6: return 44100;
664 case 7: return 32000;
672 snd_rme96_playback_getrate(rme96_t *rme96)
676 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
677 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
678 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
683 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
684 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
698 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
702 snd_rme96_playback_setrate(rme96_t *rme96,
707 ds = rme96->wcreg & RME96_WCR_DS;
710 rme96->wcreg &= ~RME96_WCR_DS;
711 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
715 rme96->wcreg &= ~RME96_WCR_DS;
716 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
720 rme96->wcreg &= ~RME96_WCR_DS;
721 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
725 rme96->wcreg |= RME96_WCR_DS;
726 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
730 rme96->wcreg |= RME96_WCR_DS;
731 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
735 rme96->wcreg |= RME96_WCR_DS;
736 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
742 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
743 (ds && !(rme96->wcreg & RME96_WCR_DS)))
745 /* change to/from double-speed: reset the DAC (if available) */
746 snd_rme96_reset_dac(rme96);
748 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
754 snd_rme96_capture_analog_setrate(rme96_t *rme96,
759 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
760 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
763 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
764 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
767 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
768 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
771 if (rme96->rev < 4) {
774 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
775 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
778 if (rme96->rev < 4) {
781 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
782 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
785 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
786 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
791 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
796 snd_rme96_setclockmode(rme96_t *rme96,
800 case RME96_CLOCKMODE_SLAVE:
802 rme96->wcreg &= ~RME96_WCR_MASTER;
803 rme96->areg &= ~RME96_AR_WSEL;
805 case RME96_CLOCKMODE_MASTER:
807 rme96->wcreg |= RME96_WCR_MASTER;
808 rme96->areg &= ~RME96_AR_WSEL;
810 case RME96_CLOCKMODE_WORDCLOCK:
811 /* Word clock is a master mode */
812 rme96->wcreg |= RME96_WCR_MASTER;
813 rme96->areg |= RME96_AR_WSEL;
818 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
819 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
824 snd_rme96_getclockmode(rme96_t *rme96)
826 if (rme96->areg & RME96_AR_WSEL) {
827 return RME96_CLOCKMODE_WORDCLOCK;
829 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
830 RME96_CLOCKMODE_SLAVE;
834 snd_rme96_setinputtype(rme96_t *rme96,
840 case RME96_INPUT_OPTICAL:
841 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
844 case RME96_INPUT_COAXIAL:
845 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
848 case RME96_INPUT_INTERNAL:
849 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
852 case RME96_INPUT_XLR:
853 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
854 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
855 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
858 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
861 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
864 case RME96_INPUT_ANALOG:
865 if (!RME96_HAS_ANALOG_IN(rme96)) {
868 rme96->areg |= RME96_AR_ANALOG;
869 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
870 if (rme96->rev < 4) {
872 * Revision less than 004 does not support 64 and
875 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
876 snd_rme96_capture_analog_setrate(rme96, 44100);
878 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
879 snd_rme96_capture_analog_setrate(rme96, 32000);
886 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
887 rme96->areg &= ~RME96_AR_ANALOG;
888 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
890 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
895 snd_rme96_getinputtype(rme96_t *rme96)
897 if (rme96->areg & RME96_AR_ANALOG) {
898 return RME96_INPUT_ANALOG;
900 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
901 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
905 snd_rme96_setframelog(rme96_t *rme96,
911 if (n_channels == 2) {
914 /* assume 8 channels */
918 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
919 rme96->playback_frlog = frlog;
921 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
922 rme96->capture_frlog = frlog;
927 snd_rme96_playback_setformat(rme96_t *rme96,
931 case SNDRV_PCM_FORMAT_S16_LE:
932 rme96->wcreg &= ~RME96_WCR_MODE24;
934 case SNDRV_PCM_FORMAT_S32_LE:
935 rme96->wcreg |= RME96_WCR_MODE24;
940 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
945 snd_rme96_capture_setformat(rme96_t *rme96,
949 case SNDRV_PCM_FORMAT_S16_LE:
950 rme96->wcreg &= ~RME96_WCR_MODE24_2;
952 case SNDRV_PCM_FORMAT_S32_LE:
953 rme96->wcreg |= RME96_WCR_MODE24_2;
958 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
963 snd_rme96_set_period_properties(rme96_t *rme96,
966 switch (period_bytes) {
967 case RME96_LARGE_BLOCK_SIZE:
968 rme96->wcreg &= ~RME96_WCR_ISEL;
970 case RME96_SMALL_BLOCK_SIZE:
971 rme96->wcreg |= RME96_WCR_ISEL;
977 rme96->wcreg &= ~RME96_WCR_IDIS;
978 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
982 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
983 snd_pcm_hw_params_t *params)
985 rme96_t *rme96 = snd_pcm_substream_chip(substream);
986 snd_pcm_runtime_t *runtime = substream->runtime;
987 int err, rate, dummy;
989 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_PLAY_BUFFER);
990 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
991 runtime->dma_bytes = RME96_BUFFER_SIZE;
993 spin_lock_irq(&rme96->lock);
994 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
995 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
996 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
999 if ((int)params_rate(params) != rate) {
1000 spin_unlock_irq(&rme96->lock);
1003 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1004 spin_unlock_irq(&rme96->lock);
1007 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1008 spin_unlock_irq(&rme96->lock);
1011 snd_rme96_setframelog(rme96, params_channels(params), 1);
1012 if (rme96->capture_periodsize != 0) {
1013 if (params_period_size(params) << rme96->playback_frlog !=
1014 rme96->capture_periodsize)
1016 spin_unlock_irq(&rme96->lock);
1020 rme96->playback_periodsize =
1021 params_period_size(params) << rme96->playback_frlog;
1022 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1024 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1028 spin_unlock_irq(&rme96->lock);
1034 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1035 snd_pcm_hw_params_t *params)
1037 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1038 snd_pcm_runtime_t *runtime = substream->runtime;
1039 int err, isadat, rate;
1041 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_REC_BUFFER);
1042 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1043 runtime->dma_bytes = RME96_BUFFER_SIZE;
1045 spin_lock_irq(&rme96->lock);
1046 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1047 spin_unlock_irq(&rme96->lock);
1050 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1051 if ((err = snd_rme96_capture_analog_setrate(rme96,
1052 params_rate(params))) < 0)
1054 spin_unlock_irq(&rme96->lock);
1057 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1058 if ((int)params_rate(params) != rate) {
1059 spin_unlock_irq(&rme96->lock);
1062 if ((isadat && runtime->hw.channels_min == 2) ||
1063 (!isadat && runtime->hw.channels_min == 8))
1065 spin_unlock_irq(&rme96->lock);
1069 snd_rme96_setframelog(rme96, params_channels(params), 0);
1070 if (rme96->playback_periodsize != 0) {
1071 if (params_period_size(params) << rme96->capture_frlog !=
1072 rme96->playback_periodsize)
1074 spin_unlock_irq(&rme96->lock);
1078 rme96->capture_periodsize =
1079 params_period_size(params) << rme96->capture_frlog;
1080 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1081 spin_unlock_irq(&rme96->lock);
1087 snd_rme96_playback_start(rme96_t *rme96,
1091 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1094 rme96->wcreg |= RME96_WCR_START;
1095 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1099 snd_rme96_capture_start(rme96_t *rme96,
1103 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1106 rme96->wcreg |= RME96_WCR_START_2;
1107 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1111 snd_rme96_playback_stop(rme96_t *rme96)
1114 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1115 * the hardware will not stop generating interrupts
1117 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1118 if (rme96->rcreg & RME96_RCR_IRQ) {
1119 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1121 rme96->wcreg &= ~RME96_WCR_START;
1122 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1126 snd_rme96_capture_stop(rme96_t *rme96)
1128 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1129 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1130 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1132 rme96->wcreg &= ~RME96_WCR_START_2;
1133 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1137 snd_rme96_interrupt(int irq,
1139 struct pt_regs *regs)
1141 rme96_t *rme96 = (rme96_t *)dev_id;
1143 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1144 /* fastpath out, to ease interrupt sharing */
1145 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1146 (rme96->rcreg & RME96_RCR_IRQ_2)))
1151 if (rme96->rcreg & RME96_RCR_IRQ) {
1153 snd_pcm_period_elapsed(rme96->playback_substream);
1154 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1156 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1158 snd_pcm_period_elapsed(rme96->capture_substream);
1159 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1164 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1166 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1167 .count = ARRAY_SIZE(period_bytes),
1168 .list = period_bytes,
1173 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1176 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1177 snd_pcm_runtime_t *runtime = substream->runtime;
1179 snd_pcm_set_sync(substream);
1181 spin_lock_irq(&rme96->lock);
1182 if (rme96->playback_substream != NULL) {
1183 spin_unlock_irq(&rme96->lock);
1186 rme96->wcreg &= ~RME96_WCR_ADAT;
1187 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1188 rme96->playback_substream = substream;
1189 spin_unlock_irq(&rme96->lock);
1191 runtime->hw = snd_rme96_playback_spdif_info;
1192 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1193 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1194 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1197 runtime->hw.rates = snd_rme96_ratecode(rate);
1198 runtime->hw.rate_min = rate;
1199 runtime->hw.rate_max = rate;
1201 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1202 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1204 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1205 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1206 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1207 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1212 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1215 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1216 snd_pcm_runtime_t *runtime = substream->runtime;
1218 snd_pcm_set_sync(substream);
1220 runtime->hw = snd_rme96_capture_spdif_info;
1221 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1222 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1227 runtime->hw.rates = snd_rme96_ratecode(rate);
1228 runtime->hw.rate_min = rate;
1229 runtime->hw.rate_max = rate;
1232 spin_lock_irq(&rme96->lock);
1233 if (rme96->capture_substream != NULL) {
1234 spin_unlock_irq(&rme96->lock);
1237 rme96->capture_substream = substream;
1238 spin_unlock_irq(&rme96->lock);
1240 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1241 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1247 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1250 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1251 snd_pcm_runtime_t *runtime = substream->runtime;
1253 snd_pcm_set_sync(substream);
1255 spin_lock_irq(&rme96->lock);
1256 if (rme96->playback_substream != NULL) {
1257 spin_unlock_irq(&rme96->lock);
1260 rme96->wcreg |= RME96_WCR_ADAT;
1261 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1262 rme96->playback_substream = substream;
1263 spin_unlock_irq(&rme96->lock);
1265 runtime->hw = snd_rme96_playback_adat_info;
1266 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1267 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1268 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1271 runtime->hw.rates = snd_rme96_ratecode(rate);
1272 runtime->hw.rate_min = rate;
1273 runtime->hw.rate_max = rate;
1275 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1276 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1281 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1284 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1285 snd_pcm_runtime_t *runtime = substream->runtime;
1287 snd_pcm_set_sync(substream);
1289 runtime->hw = snd_rme96_capture_adat_info;
1290 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1291 /* makes no sense to use analog input. Note that analog
1292 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1295 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1299 runtime->hw.rates = snd_rme96_ratecode(rate);
1300 runtime->hw.rate_min = rate;
1301 runtime->hw.rate_max = rate;
1304 spin_lock_irq(&rme96->lock);
1305 if (rme96->capture_substream != NULL) {
1306 spin_unlock_irq(&rme96->lock);
1309 rme96->capture_substream = substream;
1310 spin_unlock_irq(&rme96->lock);
1312 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1313 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1318 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1320 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1323 spin_lock_irq(&rme96->lock);
1324 if (RME96_ISPLAYING(rme96)) {
1325 snd_rme96_playback_stop(rme96);
1327 rme96->playback_substream = NULL;
1328 rme96->playback_periodsize = 0;
1329 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1330 spin_unlock_irq(&rme96->lock);
1332 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1333 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1334 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1340 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1342 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1344 spin_lock_irq(&rme96->lock);
1345 if (RME96_ISRECORDING(rme96)) {
1346 snd_rme96_capture_stop(rme96);
1348 rme96->capture_substream = NULL;
1349 rme96->capture_periodsize = 0;
1350 spin_unlock_irq(&rme96->lock);
1355 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1357 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1359 spin_lock_irq(&rme96->lock);
1360 if (RME96_ISPLAYING(rme96)) {
1361 snd_rme96_playback_stop(rme96);
1363 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1364 spin_unlock_irq(&rme96->lock);
1369 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1371 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1373 spin_lock_irq(&rme96->lock);
1374 if (RME96_ISRECORDING(rme96)) {
1375 snd_rme96_capture_stop(rme96);
1377 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1378 spin_unlock_irq(&rme96->lock);
1383 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1386 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1389 case SNDRV_PCM_TRIGGER_START:
1390 if (!RME96_ISPLAYING(rme96)) {
1391 if (substream != rme96->playback_substream) {
1394 snd_rme96_playback_start(rme96, 0);
1398 case SNDRV_PCM_TRIGGER_STOP:
1399 if (RME96_ISPLAYING(rme96)) {
1400 if (substream != rme96->playback_substream) {
1403 snd_rme96_playback_stop(rme96);
1407 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1408 if (RME96_ISPLAYING(rme96)) {
1409 snd_rme96_playback_stop(rme96);
1413 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1414 if (!RME96_ISPLAYING(rme96)) {
1415 snd_rme96_playback_start(rme96, 1);
1426 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1429 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1432 case SNDRV_PCM_TRIGGER_START:
1433 if (!RME96_ISRECORDING(rme96)) {
1434 if (substream != rme96->capture_substream) {
1437 snd_rme96_capture_start(rme96, 0);
1441 case SNDRV_PCM_TRIGGER_STOP:
1442 if (RME96_ISRECORDING(rme96)) {
1443 if (substream != rme96->capture_substream) {
1446 snd_rme96_capture_stop(rme96);
1450 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1451 if (RME96_ISRECORDING(rme96)) {
1452 snd_rme96_capture_stop(rme96);
1456 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1457 if (!RME96_ISRECORDING(rme96)) {
1458 snd_rme96_capture_start(rme96, 1);
1469 static snd_pcm_uframes_t
1470 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1472 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1473 return snd_rme96_playback_ptr(rme96);
1476 static snd_pcm_uframes_t
1477 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1479 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1480 return snd_rme96_capture_ptr(rme96);
1483 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1484 .open = snd_rme96_playback_spdif_open,
1485 .close = snd_rme96_playback_close,
1486 .ioctl = snd_pcm_lib_ioctl,
1487 .hw_params = snd_rme96_playback_hw_params,
1488 .prepare = snd_rme96_playback_prepare,
1489 .trigger = snd_rme96_playback_trigger,
1490 .pointer = snd_rme96_playback_pointer,
1491 .copy = snd_rme96_playback_copy,
1492 .silence = snd_rme96_playback_silence,
1493 .mmap = snd_pcm_lib_mmap_iomem,
1496 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1497 .open = snd_rme96_capture_spdif_open,
1498 .close = snd_rme96_capture_close,
1499 .ioctl = snd_pcm_lib_ioctl,
1500 .hw_params = snd_rme96_capture_hw_params,
1501 .prepare = snd_rme96_capture_prepare,
1502 .trigger = snd_rme96_capture_trigger,
1503 .pointer = snd_rme96_capture_pointer,
1504 .copy = snd_rme96_capture_copy,
1505 .mmap = snd_pcm_lib_mmap_iomem,
1508 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1509 .open = snd_rme96_playback_adat_open,
1510 .close = snd_rme96_playback_close,
1511 .ioctl = snd_pcm_lib_ioctl,
1512 .hw_params = snd_rme96_playback_hw_params,
1513 .prepare = snd_rme96_playback_prepare,
1514 .trigger = snd_rme96_playback_trigger,
1515 .pointer = snd_rme96_playback_pointer,
1516 .copy = snd_rme96_playback_copy,
1517 .silence = snd_rme96_playback_silence,
1518 .mmap = snd_pcm_lib_mmap_iomem,
1521 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1522 .open = snd_rme96_capture_adat_open,
1523 .close = snd_rme96_capture_close,
1524 .ioctl = snd_pcm_lib_ioctl,
1525 .hw_params = snd_rme96_capture_hw_params,
1526 .prepare = snd_rme96_capture_prepare,
1527 .trigger = snd_rme96_capture_trigger,
1528 .pointer = snd_rme96_capture_pointer,
1529 .copy = snd_rme96_capture_copy,
1530 .mmap = snd_pcm_lib_mmap_iomem,
1534 snd_rme96_free(void *private_data)
1536 rme96_t *rme96 = (rme96_t *)private_data;
1538 if (rme96 == NULL) {
1541 if (rme96->irq >= 0) {
1542 snd_rme96_playback_stop(rme96);
1543 snd_rme96_capture_stop(rme96);
1544 rme96->areg &= ~RME96_AR_DAC_EN;
1545 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1546 free_irq(rme96->irq, (void *)rme96);
1549 if (rme96->iobase) {
1550 iounmap((void *)rme96->iobase);
1554 pci_release_regions(rme96->pci);
1560 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1562 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1563 rme96->spdif_pcm = NULL;
1567 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1569 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1570 rme96->adat_pcm = NULL;
1573 static int __devinit
1574 snd_rme96_create(rme96_t *rme96)
1576 struct pci_dev *pci = rme96->pci;
1580 spin_lock_init(&rme96->lock);
1582 if ((err = pci_enable_device(pci)) < 0)
1585 if ((err = pci_request_regions(pci, "RME96")) < 0)
1587 rme96->port = pci_resource_start(rme96->pci, 0);
1589 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1590 snd_printk("unable to grab IRQ %d\n", pci->irq);
1593 rme96->irq = pci->irq;
1595 if ((rme96->iobase = (unsigned long) ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1596 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1600 /* read the card's revision number */
1601 pci_read_config_byte(pci, 8, &rme96->rev);
1603 /* set up ALSA pcm device for S/PDIF */
1604 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1605 1, 1, &rme96->spdif_pcm)) < 0)
1609 rme96->spdif_pcm->private_data = rme96;
1610 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1611 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1612 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1613 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1615 rme96->spdif_pcm->info_flags = 0;
1617 /* set up ALSA pcm device for ADAT */
1618 if (pci->device == PCI_DEVICE_ID_DIGI96) {
1619 /* ADAT is not available on the base model */
1620 rme96->adat_pcm = NULL;
1622 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1623 1, 1, &rme96->adat_pcm)) < 0)
1627 rme96->adat_pcm->private_data = rme96;
1628 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1629 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1630 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1631 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1633 rme96->adat_pcm->info_flags = 0;
1636 rme96->playback_periodsize = 0;
1637 rme96->capture_periodsize = 0;
1639 /* make sure playback/capture is stopped, if by some reason active */
1640 snd_rme96_playback_stop(rme96);
1641 snd_rme96_capture_stop(rme96);
1643 /* set default values in registers */
1645 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1646 RME96_WCR_SEL | /* normal playback */
1647 RME96_WCR_MASTER | /* set to master clock mode */
1648 RME96_WCR_INP_0; /* set coaxial input */
1650 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1652 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1653 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1656 writel(rme96->areg | RME96_AR_PD2,
1657 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1658 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1660 /* reset and enable the DAC (order is important). */
1661 snd_rme96_reset_dac(rme96);
1662 rme96->areg |= RME96_AR_DAC_EN;
1663 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1665 /* reset playback and record buffer pointers */
1666 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1667 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1670 rme96->vol[0] = rme96->vol[1] = 0;
1671 if (RME96_HAS_ANALOG_OUT(rme96)) {
1672 snd_rme96_apply_dac_volume(rme96);
1675 /* init switch interface */
1676 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1680 /* init proc interface */
1681 snd_rme96_proc_init(rme96);
1691 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1694 rme96_t *rme96 = (rme96_t *)entry->private_data;
1696 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1698 snd_iprintf(buffer, rme96->card->longname);
1699 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1701 snd_iprintf(buffer, "\nGeneral settings\n");
1702 if (rme96->wcreg & RME96_WCR_IDIS) {
1703 snd_iprintf(buffer, " period size: N/A (interrupts "
1705 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1706 snd_iprintf(buffer, " period size: 2048 bytes\n");
1708 snd_iprintf(buffer, " period size: 8192 bytes\n");
1710 snd_iprintf(buffer, "\nInput settings\n");
1711 switch (snd_rme96_getinputtype(rme96)) {
1712 case RME96_INPUT_OPTICAL:
1713 snd_iprintf(buffer, " input: optical");
1715 case RME96_INPUT_COAXIAL:
1716 snd_iprintf(buffer, " input: coaxial");
1718 case RME96_INPUT_INTERNAL:
1719 snd_iprintf(buffer, " input: internal");
1721 case RME96_INPUT_XLR:
1722 snd_iprintf(buffer, " input: XLR");
1724 case RME96_INPUT_ANALOG:
1725 snd_iprintf(buffer, " input: analog");
1728 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1729 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1732 snd_iprintf(buffer, " (8 channels)\n");
1734 snd_iprintf(buffer, " (2 channels)\n");
1736 snd_iprintf(buffer, " sample rate: %d Hz\n",
1737 snd_rme96_capture_getrate(rme96, &n));
1739 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1740 snd_iprintf(buffer, " sample format: 24 bit\n");
1742 snd_iprintf(buffer, " sample format: 16 bit\n");
1745 snd_iprintf(buffer, "\nOutput settings\n");
1746 if (rme96->wcreg & RME96_WCR_SEL) {
1747 snd_iprintf(buffer, " output signal: normal playback\n");
1749 snd_iprintf(buffer, " output signal: same as input\n");
1751 snd_iprintf(buffer, " sample rate: %d Hz\n",
1752 snd_rme96_playback_getrate(rme96));
1753 if (rme96->wcreg & RME96_WCR_MODE24) {
1754 snd_iprintf(buffer, " sample format: 24 bit\n");
1756 snd_iprintf(buffer, " sample format: 16 bit\n");
1758 if (rme96->areg & RME96_AR_WSEL) {
1759 snd_iprintf(buffer, " sample clock source: word clock\n");
1760 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1761 snd_iprintf(buffer, " sample clock source: internal\n");
1762 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1763 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1764 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1765 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1767 snd_iprintf(buffer, " sample clock source: autosync\n");
1769 if (rme96->wcreg & RME96_WCR_PRO) {
1770 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1772 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1774 if (rme96->wcreg & RME96_WCR_EMP) {
1775 snd_iprintf(buffer, " emphasis: on\n");
1777 snd_iprintf(buffer, " emphasis: off\n");
1779 if (rme96->wcreg & RME96_WCR_DOLBY) {
1780 snd_iprintf(buffer, " non-audio (dolby): on\n");
1782 snd_iprintf(buffer, " non-audio (dolby): off\n");
1784 if (RME96_HAS_ANALOG_IN(rme96)) {
1785 snd_iprintf(buffer, "\nAnalog output settings\n");
1786 switch (snd_rme96_getmontracks(rme96)) {
1787 case RME96_MONITOR_TRACKS_1_2:
1788 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1790 case RME96_MONITOR_TRACKS_3_4:
1791 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1793 case RME96_MONITOR_TRACKS_5_6:
1794 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1796 case RME96_MONITOR_TRACKS_7_8:
1797 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1800 switch (snd_rme96_getattenuation(rme96)) {
1801 case RME96_ATTENUATION_0:
1802 snd_iprintf(buffer, " attenuation: 0 dB\n");
1804 case RME96_ATTENUATION_6:
1805 snd_iprintf(buffer, " attenuation: -6 dB\n");
1807 case RME96_ATTENUATION_12:
1808 snd_iprintf(buffer, " attenuation: -12 dB\n");
1810 case RME96_ATTENUATION_18:
1811 snd_iprintf(buffer, " attenuation: -18 dB\n");
1814 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1815 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1819 static void __devinit
1820 snd_rme96_proc_init(rme96_t *rme96)
1822 snd_info_entry_t *entry;
1824 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1825 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1833 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1837 uinfo->value.integer.min = 0;
1838 uinfo->value.integer.max = 1;
1842 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1844 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1846 spin_lock_irq(&rme96->lock);
1847 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1848 spin_unlock_irq(&rme96->lock);
1852 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1854 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1858 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1859 spin_lock_irq(&rme96->lock);
1860 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1861 change = val != rme96->wcreg;
1862 writel(rme96->wcreg = val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1863 spin_unlock_irq(&rme96->lock);
1868 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1870 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1871 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1872 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1874 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1876 switch (rme96->pci->device) {
1877 case PCI_DEVICE_ID_DIGI96:
1878 case PCI_DEVICE_ID_DIGI96_8:
1879 uinfo->value.enumerated.items = 3;
1881 case PCI_DEVICE_ID_DIGI96_8_PRO:
1882 uinfo->value.enumerated.items = 4;
1884 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1885 if (rme96->rev > 4) {
1887 uinfo->value.enumerated.items = 4;
1888 texts[3] = _texts[4]; /* Analog instead of XLR */
1891 uinfo->value.enumerated.items = 5;
1898 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1899 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1901 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1905 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1907 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1908 unsigned int items = 3;
1910 spin_lock_irq(&rme96->lock);
1911 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1913 switch (rme96->pci->device) {
1914 case PCI_DEVICE_ID_DIGI96:
1915 case PCI_DEVICE_ID_DIGI96_8:
1918 case PCI_DEVICE_ID_DIGI96_8_PRO:
1921 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1922 if (rme96->rev > 4) {
1923 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1924 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1925 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1936 if (ucontrol->value.enumerated.item[0] >= items) {
1937 ucontrol->value.enumerated.item[0] = items - 1;
1940 spin_unlock_irq(&rme96->lock);
1944 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1946 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1948 int change, items = 3;
1950 switch (rme96->pci->device) {
1951 case PCI_DEVICE_ID_DIGI96:
1952 case PCI_DEVICE_ID_DIGI96_8:
1955 case PCI_DEVICE_ID_DIGI96_8_PRO:
1958 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1959 if (rme96->rev > 4) {
1969 val = ucontrol->value.enumerated.item[0] % items;
1971 /* special case for PST */
1972 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1973 if (val == RME96_INPUT_XLR) {
1974 val = RME96_INPUT_ANALOG;
1978 spin_lock_irq(&rme96->lock);
1979 change = (int)val != snd_rme96_getinputtype(rme96);
1980 snd_rme96_setinputtype(rme96, val);
1981 spin_unlock_irq(&rme96->lock);
1986 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1988 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1990 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1992 uinfo->value.enumerated.items = 3;
1993 if (uinfo->value.enumerated.item > 2) {
1994 uinfo->value.enumerated.item = 2;
1996 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2000 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2002 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2004 spin_lock_irq(&rme96->lock);
2005 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2006 spin_unlock_irq(&rme96->lock);
2010 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2012 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2016 val = ucontrol->value.enumerated.item[0] % 3;
2017 spin_lock_irq(&rme96->lock);
2018 change = (int)val != snd_rme96_getclockmode(rme96);
2019 snd_rme96_setclockmode(rme96, val);
2020 spin_unlock_irq(&rme96->lock);
2025 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2027 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2029 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2031 uinfo->value.enumerated.items = 4;
2032 if (uinfo->value.enumerated.item > 3) {
2033 uinfo->value.enumerated.item = 3;
2035 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2039 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2041 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2043 spin_lock_irq(&rme96->lock);
2044 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2045 spin_unlock_irq(&rme96->lock);
2049 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2051 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2055 val = ucontrol->value.enumerated.item[0] % 4;
2056 spin_lock_irq(&rme96->lock);
2058 change = (int)val != snd_rme96_getattenuation(rme96);
2059 snd_rme96_setattenuation(rme96, val);
2060 spin_unlock_irq(&rme96->lock);
2065 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2067 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2069 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2071 uinfo->value.enumerated.items = 4;
2072 if (uinfo->value.enumerated.item > 3) {
2073 uinfo->value.enumerated.item = 3;
2075 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2079 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2081 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2083 spin_lock_irq(&rme96->lock);
2084 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2085 spin_unlock_irq(&rme96->lock);
2089 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2091 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2095 val = ucontrol->value.enumerated.item[0] % 4;
2096 spin_lock_irq(&rme96->lock);
2097 change = (int)val != snd_rme96_getmontracks(rme96);
2098 snd_rme96_setmontracks(rme96, val);
2099 spin_unlock_irq(&rme96->lock);
2103 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2106 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2107 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2108 if (val & RME96_WCR_PRO)
2109 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2111 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2115 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2117 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2118 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2119 if (val & RME96_WCR_PRO)
2120 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2122 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2125 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2127 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2132 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2134 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2136 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2140 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2142 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2146 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2147 spin_lock_irq(&rme96->lock);
2148 change = val != rme96->wcreg_spdif;
2149 rme96->wcreg_spdif = val;
2150 spin_unlock_irq(&rme96->lock);
2154 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2156 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2161 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2163 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2165 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2169 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2171 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2175 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2176 spin_lock_irq(&rme96->lock);
2177 change = val != rme96->wcreg_spdif_stream;
2178 rme96->wcreg_spdif_stream = val;
2179 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2180 writel(rme96->wcreg |= val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2181 spin_unlock_irq(&rme96->lock);
2185 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2187 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2192 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2194 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2199 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2201 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2203 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2205 uinfo->value.integer.min = 0;
2206 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2211 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2213 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2215 spin_lock_irq(&rme96->lock);
2216 u->value.integer.value[0] = rme96->vol[0];
2217 u->value.integer.value[1] = rme96->vol[1];
2218 spin_unlock_irq(&rme96->lock);
2224 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2226 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2229 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2232 spin_lock_irq(&rme96->lock);
2233 if (u->value.integer.value[0] != rme96->vol[0]) {
2234 rme96->vol[0] = u->value.integer.value[0];
2237 if (u->value.integer.value[1] != rme96->vol[1]) {
2238 rme96->vol[1] = u->value.integer.value[1];
2242 snd_rme96_apply_dac_volume(rme96);
2244 spin_unlock_irq(&rme96->lock);
2249 static snd_kcontrol_new_t snd_rme96_controls[] = {
2251 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2252 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2253 .info = snd_rme96_control_spdif_info,
2254 .get = snd_rme96_control_spdif_get,
2255 .put = snd_rme96_control_spdif_put
2258 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2259 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2260 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2261 .info = snd_rme96_control_spdif_stream_info,
2262 .get = snd_rme96_control_spdif_stream_get,
2263 .put = snd_rme96_control_spdif_stream_put
2266 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2267 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2268 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2269 .info = snd_rme96_control_spdif_mask_info,
2270 .get = snd_rme96_control_spdif_mask_get,
2271 .private_value = IEC958_AES0_NONAUDIO |
2272 IEC958_AES0_PROFESSIONAL |
2273 IEC958_AES0_CON_EMPHASIS
2276 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2279 .info = snd_rme96_control_spdif_mask_info,
2280 .get = snd_rme96_control_spdif_mask_get,
2281 .private_value = IEC958_AES0_NONAUDIO |
2282 IEC958_AES0_PROFESSIONAL |
2283 IEC958_AES0_PRO_EMPHASIS
2286 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2287 .name = "Input Connector",
2288 .info = snd_rme96_info_inputtype_control,
2289 .get = snd_rme96_get_inputtype_control,
2290 .put = snd_rme96_put_inputtype_control
2293 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2294 .name = "Loopback Input",
2295 .info = snd_rme96_info_loopback_control,
2296 .get = snd_rme96_get_loopback_control,
2297 .put = snd_rme96_put_loopback_control
2300 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2301 .name = "Sample Clock Source",
2302 .info = snd_rme96_info_clockmode_control,
2303 .get = snd_rme96_get_clockmode_control,
2304 .put = snd_rme96_put_clockmode_control
2307 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2308 .name = "Monitor Tracks",
2309 .info = snd_rme96_info_montracks_control,
2310 .get = snd_rme96_get_montracks_control,
2311 .put = snd_rme96_put_montracks_control
2314 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2315 .name = "Attenuation",
2316 .info = snd_rme96_info_attenuation_control,
2317 .get = snd_rme96_get_attenuation_control,
2318 .put = snd_rme96_put_attenuation_control
2321 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2322 .name = "DAC Playback Volume",
2323 .info = snd_rme96_dac_volume_info,
2324 .get = snd_rme96_dac_volume_get,
2325 .put = snd_rme96_dac_volume_put
2330 snd_rme96_create_switches(snd_card_t *card,
2334 snd_kcontrol_t *kctl;
2336 for (idx = 0; idx < 7; idx++) {
2337 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2339 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2340 rme96->spdif_ctl = kctl;
2343 if (RME96_HAS_ANALOG_OUT(rme96)) {
2344 for (idx = 7; idx < 10; idx++)
2345 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2353 * Card initialisation
2356 static void snd_rme96_card_free(snd_card_t *card)
2358 snd_rme96_free(card->private_data);
2361 static int __devinit
2362 snd_rme96_probe(struct pci_dev *pci,
2363 const struct pci_device_id *pci_id)
2371 if (dev >= SNDRV_CARDS) {
2378 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2379 sizeof(rme96_t))) == NULL)
2381 card->private_free = snd_rme96_card_free;
2382 rme96 = (rme96_t *)card->private_data;
2385 snd_card_set_dev(card, &pci->dev);
2386 if ((err = snd_rme96_create(rme96)) < 0) {
2387 snd_card_free(card);
2391 strcpy(card->driver, "Digi96");
2392 switch (rme96->pci->device) {
2393 case PCI_DEVICE_ID_DIGI96:
2394 strcpy(card->shortname, "RME Digi96");
2396 case PCI_DEVICE_ID_DIGI96_8:
2397 strcpy(card->shortname, "RME Digi96/8");
2399 case PCI_DEVICE_ID_DIGI96_8_PRO:
2400 strcpy(card->shortname, "RME Digi96/8 PRO");
2402 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2403 pci_read_config_byte(rme96->pci, 8, &val);
2405 strcpy(card->shortname, "RME Digi96/8 PAD");
2407 strcpy(card->shortname, "RME Digi96/8 PST");
2411 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2412 rme96->port, rme96->irq);
2414 if ((err = snd_card_register(card)) < 0) {
2415 snd_card_free(card);
2418 pci_set_drvdata(pci, card);
2423 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2425 snd_card_free(pci_get_drvdata(pci));
2426 pci_set_drvdata(pci, NULL);
2429 static struct pci_driver driver = {
2430 .name = "RME Digi96",
2431 .id_table = snd_rme96_ids,
2432 .probe = snd_rme96_probe,
2433 .remove = __devexit_p(snd_rme96_remove),
2436 static int __init alsa_card_rme96_init(void)
2438 return pci_module_init(&driver);
2441 static void __exit alsa_card_rme96_exit(void)
2443 pci_unregister_driver(&driver);
2446 module_init(alsa_card_rme96_init)
2447 module_exit(alsa_card_rme96_exit)