sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <sound/driver.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/control.h>
  34 #include <sound/pcm.h>
  35 #include <sound/info.h>
  36 #include <sound/asoundef.h>
  37 #include <sound/rawmidi.h>
  38 #include <sound/hwdep.h>
  39 #include <sound/initval.h>
  40 #include <sound/hdsp.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/current.h>
  44 #include <asm/io.h>
  45
  46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  49 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
  50 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  58 module_param_array(precise_ptr, bool, NULL, 0444);
  59 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
  60 module_param_array(line_outs_monitor, bool, NULL, 0444);
  61 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
  62 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  63 MODULE_DESCRIPTION("RME Hammerfall DSP");
  64 MODULE_LICENSE("GPL");
  65 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  66                 "{RME HDSP-9652},"
  67                 "{RME HDSP-9632}}");
  68
  69 #define HDSP_MAX_CHANNELS        26
  70 #define HDSP_MAX_DS_CHANNELS     14
  71 #define HDSP_MAX_QS_CHANNELS     8
  72 #define DIGIFACE_SS_CHANNELS     26
  73 #define DIGIFACE_DS_CHANNELS     14
  74 #define MULTIFACE_SS_CHANNELS    18
  75 #define MULTIFACE_DS_CHANNELS    14
  76 #define H9652_SS_CHANNELS        26
  77 #define H9652_DS_CHANNELS        14
  78 /* This does not include possible Analog Extension Boards
  79    AEBs are detected at card initialization
  80 */
  81 #define H9632_SS_CHANNELS        12
  82 #define H9632_DS_CHANNELS        8
  83 #define H9632_QS_CHANNELS        4
  84
  85 /* Write registers. These are defined as byte-offsets from the iobase value.
  86  */
  87 #define HDSP_resetPointer               0
  88 #define HDSP_outputBufferAddress        32
  89 #define HDSP_inputBufferAddress         36
  90 #define HDSP_controlRegister            64
  91 #define HDSP_interruptConfirmation      96
  92 #define HDSP_outputEnable               128
  93 #define HDSP_control2Reg                256
  94 #define HDSP_midiDataOut0               352
  95 #define HDSP_midiDataOut1               356
  96 #define HDSP_fifoData                   368
  97 #define HDSP_inputEnable                384
  98
  99 /* Read registers. These are defined as byte-offsets from the iobase value
 100  */
 101
 102 #define HDSP_statusRegister    0
 103 #define HDSP_timecode        128
 104 #define HDSP_status2Register 192
 105 #define HDSP_midiDataOut0    352
 106 #define HDSP_midiDataOut1    356
 107 #define HDSP_midiDataIn0     360
 108 #define HDSP_midiDataIn1     364
 109 #define HDSP_midiStatusOut0  384
 110 #define HDSP_midiStatusOut1  388
 111 #define HDSP_midiStatusIn0   392
 112 #define HDSP_midiStatusIn1   396
 113 #define HDSP_fifoStatus      400
 114
 115 /* the meters are regular i/o-mapped registers, but offset
 116    considerably from the rest. the peak registers are reset
 117    when read; the least-significant 4 bits are full-scale counters;
 118    the actual peak value is in the most-significant 24 bits.
 119 */
 120
 121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 126
 127
 128 /* This is for H9652 cards
 129    Peak values are read downward from the base
 130    Rms values are read upward
 131    There are rms values for the outputs too
 132    26*3 values are read in ss mode
 133    14*3 in ds mode, with no gap between values
 134 */
 135 #define HDSP_9652_peakBase      7164
 136 #define HDSP_9652_rmsBase       4096
 137
 138 /* c.f. the hdsp_9632_meters_t struct */
 139 #define HDSP_9632_metersBase    4096
 140
 141 #define HDSP_IO_EXTENT     7168
 142
 143 /* control2 register bits */
 144
 145 #define HDSP_TMS                0x01
 146 #define HDSP_TCK                0x02
 147 #define HDSP_TDI                0x04
 148 #define HDSP_JTAG               0x08
 149 #define HDSP_PWDN               0x10
 150 #define HDSP_PROGRAM            0x020
 151 #define HDSP_CONFIG_MODE_0      0x040
 152 #define HDSP_CONFIG_MODE_1      0x080
 153 #define HDSP_VERSION_BIT        0x100
 154 #define HDSP_BIGENDIAN_MODE     0x200
 155 #define HDSP_RD_MULTIPLE        0x400
 156 #define HDSP_9652_ENABLE_MIXER  0x800
 157 #define HDSP_TDO                0x10000000
 158
 159 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 160 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 161
 162 /* Control Register bits */
 163
 164 #define HDSP_Start                (1<<0)  /* start engine */
 165 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 166 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 167 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 168 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 169 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 170 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 171 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 172 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 173 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 174 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 175 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 176 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 177 #define HDSP_SyncRef2             (1<<13)
 178 #define HDSP_SPDIFInputSelect0    (1<<14)
 179 #define HDSP_SPDIFInputSelect1    (1<<15)
 180 #define HDSP_SyncRef0             (1<<16)
 181 #define HDSP_SyncRef1             (1<<17)
 182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 183 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 184 #define HDSP_Midi0InterruptEnable (1<<22)
 185 #define HDSP_Midi1InterruptEnable (1<<23)
 186 #define HDSP_LineOut              (1<<24)
 187 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 188 #define HDSP_ADGain1              (1<<26)
 189 #define HDSP_DAGain0              (1<<27)
 190 #define HDSP_DAGain1              (1<<28)
 191 #define HDSP_PhoneGain0           (1<<29)
 192 #define HDSP_PhoneGain1           (1<<30)
 193 #define HDSP_QuadSpeed            (1<<31)
 194
 195 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 196 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 197 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 198 #define HDSP_ADGainLowGain     0
 199
 200 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 201 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 202 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 203 #define HDSP_DAGainMinus10dBV    0
 204
 205 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 206 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 207 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 208 #define HDSP_PhoneGainMinus12dB  0
 209
 210 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 211 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 212
 213 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 214 #define HDSP_SPDIFInputADAT1    0
 215 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 216 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 217 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 218
 219 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 220 #define HDSP_SyncRef_ADAT1       0
 221 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 222 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 223 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 224 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 225 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 226
 227 /* Sample Clock Sources */
 228
 229 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 230 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 231 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 232 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 233 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 234 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 235 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 236 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 239
 240 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 241
 242 #define HDSP_SYNC_FROM_WORD      0
 243 #define HDSP_SYNC_FROM_SPDIF     1
 244 #define HDSP_SYNC_FROM_ADAT1     2
 245 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 246 #define HDSP_SYNC_FROM_ADAT2     4
 247 #define HDSP_SYNC_FROM_ADAT3     5
 248
 249 /* SyncCheck status */
 250
 251 #define HDSP_SYNC_CHECK_NO_LOCK 0
 252 #define HDSP_SYNC_CHECK_LOCK    1
 253 #define HDSP_SYNC_CHECK_SYNC    2
 254
 255 /* AutoSync references - used by "autosync_ref" control switch */
 256
 257 #define HDSP_AUTOSYNC_FROM_WORD      0
 258 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 259 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 260 #define HDSP_AUTOSYNC_FROM_NONE      3
 261 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 262 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 263 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 264
 265 /* Possible sources of S/PDIF input */
 266
 267 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 268 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 269 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 270 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 271
 272 #define HDSP_Frequency32KHz    HDSP_Frequency0
 273 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 274 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 275 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 276 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 277 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 278 /* For H9632 cards */
 279 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 280 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 281 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 282
 283 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 284 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 285
 286 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 287 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 288
 289 /* Status Register bits */
 290
 291 #define HDSP_audioIRQPending    (1<<0)
 292 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 293 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 294 #define HDSP_Lock1              (1<<2)
 295 #define HDSP_Lock0              (1<<3)
 296 #define HDSP_SPDIFSync          (1<<4)
 297 #define HDSP_TimecodeLock       (1<<5)
 298 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 299 #define HDSP_Sync2              (1<<16)
 300 #define HDSP_Sync1              (1<<17)
 301 #define HDSP_Sync0              (1<<18)
 302 #define HDSP_DoubleSpeedStatus  (1<<19)
 303 #define HDSP_ConfigError        (1<<20)
 304 #define HDSP_DllError           (1<<21)
 305 #define HDSP_spdifFrequency0    (1<<22)
 306 #define HDSP_spdifFrequency1    (1<<23)
 307 #define HDSP_spdifFrequency2    (1<<24)
 308 #define HDSP_SPDIFErrorFlag     (1<<25)
 309 #define HDSP_BufferID           (1<<26)
 310 #define HDSP_TimecodeSync       (1<<27)
 311 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 312 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 313 #define HDSP_midi0IRQPending    (1<<30)
 314 #define HDSP_midi1IRQPending    (1<<31)
 315
 316 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 317
 318 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 319 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 320 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 321
 322 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 323 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 324 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 325
 326 /* This is for H9632 cards */
 327 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
 328 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 329 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 330
 331 /* Status2 Register bits */
 332
 333 #define HDSP_version0     (1<<0)
 334 #define HDSP_version1     (1<<1)
 335 #define HDSP_version2     (1<<2)
 336 #define HDSP_wc_lock      (1<<3)
 337 #define HDSP_wc_sync      (1<<4)
 338 #define HDSP_inp_freq0    (1<<5)
 339 #define HDSP_inp_freq1    (1<<6)
 340 #define HDSP_inp_freq2    (1<<7)
 341 #define HDSP_SelSyncRef0  (1<<8)
 342 #define HDSP_SelSyncRef1  (1<<9)
 343 #define HDSP_SelSyncRef2  (1<<10)
 344
 345 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 346
 347 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 348 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 349 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 350 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 351 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 352 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 353 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 354 /* FIXME : more values for 9632 cards ? */
 355
 356 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 357 #define HDSP_SelSyncRef_ADAT1      0
 358 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 359 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 360 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 361 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 362 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 363
 364 /* Card state flags */
 365
 366 #define HDSP_InitializationComplete  (1<<0)
 367 #define HDSP_FirmwareLoaded          (1<<1)
 368 #define HDSP_FirmwareCached          (1<<2)
 369
 370 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 371
 372 #define HDSP_LONG_WAIT   5000
 373 #define HDSP_SHORT_WAIT  30
 374
 375 #define UNITY_GAIN                       32768
 376 #define MINUS_INFINITY_GAIN              0
 377
 378 #ifndef PCI_VENDOR_ID_XILINX
 379 #define PCI_VENDOR_ID_XILINX            0x10ee
 380 #endif
 381 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
 382 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
 383 #endif
 384
 385 /* the size of a substream (1 mono data stream) */
 386
 387 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 388 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 389
 390 /* the size of the area we need to allocate for DMA transfers. the
 391    size is the same regardless of the number of channels - the
 392    Multiface still uses the same memory area.
 393
 394    Note that we allocate 1 more channel than is apparently needed
 395    because the h/w seems to write 1 byte beyond the end of the last
 396    page. Sigh.
 397 */
 398
 399 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 400 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 401
 402 typedef struct _hdsp             hdsp_t;
 403 typedef struct _hdsp_midi        hdsp_midi_t;
 404 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
 405
 406 struct _hdsp_9632_meters {
 407     u32 input_peak[16];
 408     u32 playback_peak[16];
 409     u32 output_peak[16];
 410     u32 xxx_peak[16];
 411     u32 padding[64];
 412     u32 input_rms_low[16];
 413     u32 playback_rms_low[16];
 414     u32 output_rms_low[16];
 415     u32 xxx_rms_low[16];
 416     u32 input_rms_high[16];
 417     u32 playback_rms_high[16];
 418     u32 output_rms_high[16];
 419     u32 xxx_rms_high[16];
 420 };
 421
 422 struct _hdsp_midi {
 423     hdsp_t                  *hdsp;
 424     int                      id;
 425     snd_rawmidi_t           *rmidi;
 426     snd_rawmidi_substream_t *input;
 427     snd_rawmidi_substream_t *output;
 428     char                     istimer; /* timer in use */
 429     struct timer_list        timer;
 430     spinlock_t               lock;
 431     int                      pending;
 432 };
 433
 434 struct _hdsp {
 435         spinlock_t            lock;
 436         snd_pcm_substream_t  *capture_substream;
 437         snd_pcm_substream_t  *playback_substream;
 438         hdsp_midi_t           midi[2];
 439         struct tasklet_struct midi_tasklet;
 440         int                   precise_ptr;
 441         u32                   control_register;      /* cached value */
 442         u32                   control2_register;     /* cached value */
 443         u32                   creg_spdif;
 444         u32                   creg_spdif_stream;
 445         char                 *card_name;             /* digiface/multiface */
 446         HDSP_IO_Type          io_type;               /* ditto, but for code use */
 447         unsigned short        firmware_rev;
 448         unsigned short        state;                 /* stores state bits */
 449         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
 450         size_t                period_bytes;          /* guess what this is */
 451         unsigned char         max_channels;
 452         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 453         unsigned char         ds_in_channels;
 454         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 455         unsigned char         qs_out_channels;
 456         unsigned char         ds_out_channels;
 457         unsigned char         ss_out_channels;
 458
 459         struct snd_dma_buffer capture_dma_buf;
 460         struct snd_dma_buffer playback_dma_buf;
 461         unsigned char        *capture_buffer;       /* suitably aligned address */
 462         unsigned char        *playback_buffer;      /* suitably aligned address */
 463
 464         pid_t                 capture_pid;
 465         pid_t                 playback_pid;
 466         int                   running;
 467         int                   passthru;              /* non-zero if doing pass-thru */
 468         int                   system_sample_rate;
 469         char                 *channel_map;
 470         int                   dev;
 471         int                   irq;
 472         unsigned long         port;
 473         void __iomem         *iobase;
 474         snd_card_t           *card;
 475         snd_pcm_t            *pcm;
 476         snd_hwdep_t          *hwdep;
 477         struct pci_dev       *pci;
 478         snd_kcontrol_t       *spdif_ctl;
 479         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 480 };
 481
 482 /* These tables map the ALSA channels 1..N to the channels that we
 483    need to use in order to find the relevant channel buffer. RME
 484    refer to this kind of mapping as between "the ADAT channel and
 485    the DMA channel." We index it using the logical audio channel,
 486    and the value is the DMA channel (i.e. channel buffer number)
 487    where the data for that channel can be read/written from/to.
 488 */
 489
 490 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 491         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 492         18, 19, 20, 21, 22, 23, 24, 25
 493 };
 494
 495 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 496         /* Analog */
 497         0, 1, 2, 3, 4, 5, 6, 7,
 498         /* ADAT 2 */
 499         16, 17, 18, 19, 20, 21, 22, 23,
 500         /* SPDIF */
 501         24, 25,
 502         -1, -1, -1, -1, -1, -1, -1, -1
 503 };
 504
 505 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 506         /* ADAT channels are remapped */
 507         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 508         /* channels 12 and 13 are S/PDIF */
 509         24, 25,
 510         /* others don't exist */
 511         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 512 };
 513
 514 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 515         /* ADAT channels */
 516         0, 1, 2, 3, 4, 5, 6, 7,
 517         /* SPDIF */
 518         8, 9,
 519         /* Analog */
 520         10, 11,
 521         /* AO4S-192 and AI4S-192 extension boards */
 522         12, 13, 14, 15,
 523         /* others don't exist */
 524         -1, -1, -1, -1, -1, -1, -1, -1,
 525         -1, -1
 526 };
 527
 528 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 529         /* ADAT */
 530         1, 3, 5, 7,
 531         /* SPDIF */
 532         8, 9,
 533         /* Analog */
 534         10, 11,
 535         /* AO4S-192 and AI4S-192 extension boards */
 536         12, 13, 14, 15,
 537         /* others don't exist */
 538         -1, -1, -1, -1, -1, -1, -1, -1,
 539         -1, -1, -1, -1, -1, -1
 540 };
 541
 542 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 543         /* ADAT is disabled in this mode */
 544         /* SPDIF */
 545         8, 9,
 546         /* Analog */
 547         10, 11,
 548         /* AO4S-192 and AI4S-192 extension boards */
 549         12, 13, 14, 15,
 550         /* others don't exist */
 551         -1, -1, -1, -1, -1, -1, -1, -1,
 552         -1, -1, -1, -1, -1, -1, -1, -1,
 553         -1, -1
 554 };
 555
 556 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 557 {
 558         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 559         dmab->dev.dev = snd_dma_pci_data(pci);
 560         if (! snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
 561                 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 562                                         size, dmab) < 0)
 563                         return -ENOMEM;
 564         }
 565         return 0;
 566 }
 567
 568 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 569 {
 570         if (dmab->area)
 571                 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
 572 }
 573
 574
 575 static struct pci_device_id snd_hdsp_ids[] = {
 576         {
 577                 .vendor = PCI_VENDOR_ID_XILINX,
 578                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 579                 .subvendor = PCI_ANY_ID,
 580                 .subdevice = PCI_ANY_ID,
 581         }, /* RME Hammerfall-DSP */
 582         { 0, },
 583 };
 584
 585 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 586
 587 /* prototypes */
 588 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
 589 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
 590 static int snd_hdsp_enable_io (hdsp_t *hdsp);
 591 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
 592 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
 593 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
 594 static int hdsp_autosync_ref(hdsp_t *hdsp);
 595 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
 596 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
 597
 598 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
 599 {
 600         switch (hdsp->firmware_rev) {
 601         case 0xa:
 602                 return (64 * out) + (32 + (in));
 603         case 0x96:
 604         case 0x97:
 605                 return (32 * out) + (16 + (in));
 606         default:
 607                 return (52 * out) + (26 + (in));
 608         }
 609 }
 610
 611 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
 612 {
 613         switch (hdsp->firmware_rev) {
 614         case 0xa:
 615                 return (64 * out) + in;
 616         case 0x96:
 617         case 0x97:
 618                 return (32 * out) + in;
 619         default:
 620                 return (52 * out) + in;
 621         }
 622 }
 623
 624 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
 625 {
 626         writel(val, hdsp->iobase + reg);
 627 }
 628
 629 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
 630 {
 631         return readl (hdsp->iobase + reg);
 632 }
 633
 634 static int hdsp_check_for_iobox (hdsp_t *hdsp)
 635 {
 636
 637         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 638         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
 639                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
 640                 hdsp->state &= ~HDSP_FirmwareLoaded;
 641                 return -EIO;
 642         }
 643         return 0;
 644
 645 }
 646
 647 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 648
 649         int i;
 650         unsigned long flags;
 651
 652         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 653
 654                 snd_printk ("loading firmware\n");
 655
 656                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 657                 hdsp_write (hdsp, HDSP_fifoData, 0);
 658
 659                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 660                         snd_printk ("timeout waiting for download preparation\n");
 661                         return -EIO;
 662                 }
 663
 664                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 665
 666                 for (i = 0; i < 24413; ++i) {
 667                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
 668                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 669                                 snd_printk ("timeout during firmware loading\n");
 670                                 return -EIO;
 671                         }
 672                 }
 673
 674                 if ((1000 / HZ) < 3000) {
 675                         set_current_state(TASK_UNINTERRUPTIBLE);
 676                         schedule_timeout((3000 * HZ + 999) / 1000);
 677                 } else {
 678                         mdelay(3000);
 679                 }
 680
 681                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 682                         snd_printk ("timeout at end of firmware loading\n");
 683                         return -EIO;
 684                 }
 685
 686 #ifdef SNDRV_BIG_ENDIAN
 687                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 688 #else
 689                 hdsp->control2_register = 0;
 690 #endif
 691                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 692                 snd_printk ("finished firmware loading\n");
 693
 694         }
 695         if (hdsp->state & HDSP_InitializationComplete) {
 696                 snd_printk("firmware loaded from cache, restoring defaults\n");
 697                 spin_lock_irqsave(&hdsp->lock, flags);
 698                 snd_hdsp_set_defaults(hdsp);
 699                 spin_unlock_irqrestore(&hdsp->lock, flags);
 700         }
 701
 702         hdsp->state |= HDSP_FirmwareLoaded;
 703
 704         return 0;
 705 }
 706
 707 static int hdsp_get_iobox_version (hdsp_t *hdsp)
 708 {
 709         int err;
 710
 711         if (hdsp_check_for_iobox (hdsp)) {
 712                 return -EIO;
 713         }
 714
 715         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
 716                 return err;
 717         }
 718
 719         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 720
 721                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
 722                 hdsp_write (hdsp, HDSP_fifoData, 0);
 723                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 724                         return -EIO;
 725                 }
 726
 727                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 728                 hdsp_write (hdsp, HDSP_fifoData, 0);
 729
 730                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
 731                         hdsp->io_type = Multiface;
 732                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
 733                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 734                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
 735                 } else {
 736                         hdsp->io_type = Digiface;
 737                 }
 738         } else {
 739                 /* firmware was already loaded, get iobox type */
 740                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
 741                         hdsp->io_type = Multiface;
 742                 } else {
 743                         hdsp->io_type = Digiface;
 744                 }
 745         }
 746         return 0;
 747 }
 748
 749
 750 static int hdsp_check_for_firmware (hdsp_t *hdsp)
 751 {
 752         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 753         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 754                 snd_printk("firmware not present.\n");
 755                 hdsp->state &= ~HDSP_FirmwareLoaded;
 756                 return -EIO;
 757         }
 758         return 0;
 759 }
 760
 761
 762 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
 763 {
 764         int i;
 765
 766         /* the fifoStatus registers reports on how many words
 767            are available in the command FIFO.
 768         */
 769
 770         for (i = 0; i < timeout; i++) {
 771
 772                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 773                         return 0;
 774
 775                 /* not very friendly, but we only do this during a firmware
 776                    load and changing the mixer, so we just put up with it.
 777                 */
 778
 779                 udelay (100);
 780         }
 781
 782         snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
 783                     count, timeout);
 784         return -1;
 785 }
 786
 787 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
 788 {
 789         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
 790                 return 0;
 791         }
 792         return hdsp->mixer_matrix[addr];
 793 }
 794
 795 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
 796 {
 797         unsigned int ad;
 798
 799         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 800                 return -1;
 801
 802         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 803
 804                 /* from martin björnsen:
 805
 806                    "You can only write dwords to the
 807                    mixer memory which contain two
 808                    mixer values in the low and high
 809                    word. So if you want to change
 810                    value 0 you have to read value 1
 811                    from the cache and write both to
 812                    the first dword in the mixer
 813                    memory."
 814                 */
 815
 816                 if (hdsp->io_type == H9632 && addr >= 512) {
 817                         return 0;
 818                 }
 819
 820                 if (hdsp->io_type == H9652 && addr >= 1352) {
 821                         return 0;
 822                 }
 823
 824                 hdsp->mixer_matrix[addr] = data;
 825
 826
 827                 /* `addr' addresses a 16-bit wide address, but
 828                    the address space accessed via hdsp_write
 829                    uses byte offsets. put another way, addr
 830                    varies from 0 to 1351, but to access the
 831                    corresponding memory location, we need
 832                    to access 0 to 2703 ...
 833                 */
 834                 ad = addr/2;
 835
 836                 hdsp_write (hdsp, 4096 + (ad*4),
 837                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 838                             hdsp->mixer_matrix[addr&0x7fe]);
 839
 840                 return 0;
 841
 842         } else {
 843
 844                 ad = (addr << 16) + data;
 845
 846                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
 847                         return -1;
 848                 }
 849
 850                 hdsp_write (hdsp, HDSP_fifoData, ad);
 851                 hdsp->mixer_matrix[addr] = data;
 852
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
 859 {
 860         unsigned long flags;
 861         int ret = 1;
 862
 863         spin_lock_irqsave(&hdsp->lock, flags);
 864         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 865             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
 866                 ret = 0;
 867         }
 868         spin_unlock_irqrestore(&hdsp->lock, flags);
 869         return ret;
 870 }
 871
 872 static int hdsp_external_sample_rate (hdsp_t *hdsp)
 873 {
 874         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 875         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 876
 877         switch (rate_bits) {
 878         case HDSP_systemFrequency32:   return 32000;
 879         case HDSP_systemFrequency44_1: return 44100;
 880         case HDSP_systemFrequency48:   return 48000;
 881         case HDSP_systemFrequency64:   return 64000;
 882         case HDSP_systemFrequency88_2: return 88200;
 883         case HDSP_systemFrequency96:   return 96000;
 884         default:
 885                 return 0;
 886         }
 887 }
 888
 889 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
 890 {
 891         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 892         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 893
 894         if (status & HDSP_SPDIFErrorFlag) {
 895                 return 0;
 896         }
 897
 898         switch (rate_bits) {
 899         case HDSP_spdifFrequency32KHz: return 32000;
 900         case HDSP_spdifFrequency44_1KHz: return 44100;
 901         case HDSP_spdifFrequency48KHz: return 48000;
 902         case HDSP_spdifFrequency64KHz: return 64000;
 903         case HDSP_spdifFrequency88_2KHz: return 88200;
 904         case HDSP_spdifFrequency96KHz: return 96000;
 905         case HDSP_spdifFrequency128KHz:
 906                 if (hdsp->io_type == H9632) return 128000;
 907                 break;
 908         case HDSP_spdifFrequency176_4KHz:
 909                 if (hdsp->io_type == H9632) return 176400;
 910                 break;
 911         case HDSP_spdifFrequency192KHz:
 912                 if (hdsp->io_type == H9632) return 192000;
 913                 break;
 914         default:
 915                 break;
 916         }
 917         snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
 918         return 0;
 919 }
 920
 921 static void hdsp_compute_period_size(hdsp_t *hdsp)
 922 {
 923         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
 924 }
 925
 926 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
 927 {
 928         int position;
 929
 930         position = hdsp_read(hdsp, HDSP_statusRegister);
 931
 932         if (!hdsp->precise_ptr) {
 933                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
 934         }
 935
 936         position &= HDSP_BufferPositionMask;
 937         position /= 4;
 938         position &= (hdsp->period_bytes/2) - 1;
 939         return position;
 940 }
 941
 942 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
 943 {
 944         hdsp_write (hdsp, HDSP_resetPointer, 0);
 945 }
 946
 947 static void hdsp_start_audio(hdsp_t *s)
 948 {
 949         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
 950         hdsp_write(s, HDSP_controlRegister, s->control_register);
 951 }
 952
 953 static void hdsp_stop_audio(hdsp_t *s)
 954 {
 955         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
 956         hdsp_write(s, HDSP_controlRegister, s->control_register);
 957 }
 958
 959 static void hdsp_silence_playback(hdsp_t *hdsp)
 960 {
 961         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
 962 }
 963
 964 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
 965 {
 966         int n;
 967
 968         spin_lock_irq(&s->lock);
 969
 970         frames >>= 7;
 971         n = 0;
 972         while (frames) {
 973                 n++;
 974                 frames >>= 1;
 975         }
 976
 977         s->control_register &= ~HDSP_LatencyMask;
 978         s->control_register |= hdsp_encode_latency(n);
 979
 980         hdsp_write(s, HDSP_controlRegister, s->control_register);
 981
 982         hdsp_compute_period_size(s);
 983
 984         spin_unlock_irq(&s->lock);
 985
 986         return 0;
 987 }
 988
 989 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
 990 {
 991         int reject_if_open = 0;
 992         int current_rate;
 993         int rate_bits;
 994
 995         /* ASSUMPTION: hdsp->lock is either held, or
 996            there is no need for it (e.g. during module
 997            initialization).
 998         */
 999
1000         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1001                 if (called_internally) {
1002                         /* request from ctl or card initialization */
1003                         snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1004                         return -1;
1005                 } else {
1006                         /* hw_param request while in AutoSync mode */
1007                         int external_freq = hdsp_external_sample_rate(hdsp);
1008                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1009
1010                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1011                                 snd_printk("Detected ADAT in double speed mode\n");
1012                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1013                                 snd_printk("Detected ADAT in quad speed mode\n");
1014                         } else if (rate != external_freq) {
1015                                 snd_printk("No AutoSync source for requested rate\n");
1016                                 return -1;
1017                         }
1018                 }
1019         }
1020
1021         current_rate = hdsp->system_sample_rate;
1022
1023         /* Changing from a "single speed" to a "double speed" rate is
1024            not allowed if any substreams are open. This is because
1025            such a change causes a shift in the location of
1026            the DMA buffers and a reduction in the number of available
1027            buffers.
1028
1029            Note that a similar but essentially insoluble problem
1030            exists for externally-driven rate changes. All we can do
1031            is to flag rate changes in the read/write routines.  */
1032
1033         if (rate > 96000 && hdsp->io_type != H9632) {
1034                 return -EINVAL;
1035         }
1036
1037         switch (rate) {
1038         case 32000:
1039                 if (current_rate > 48000) {
1040                         reject_if_open = 1;
1041                 }
1042                 rate_bits = HDSP_Frequency32KHz;
1043                 break;
1044         case 44100:
1045                 if (current_rate > 48000) {
1046                         reject_if_open = 1;
1047                 }
1048                 rate_bits = HDSP_Frequency44_1KHz;
1049                 break;
1050         case 48000:
1051                 if (current_rate > 48000) {
1052                         reject_if_open = 1;
1053                 }
1054                 rate_bits = HDSP_Frequency48KHz;
1055                 break;
1056         case 64000:
1057                 if (current_rate <= 48000 || current_rate > 96000) {
1058                         reject_if_open = 1;
1059                 }
1060                 rate_bits = HDSP_Frequency64KHz;
1061                 break;
1062         case 88200:
1063                 if (current_rate <= 48000 || current_rate > 96000) {
1064                         reject_if_open = 1;
1065                 }
1066                 rate_bits = HDSP_Frequency88_2KHz;
1067                 break;
1068         case 96000:
1069                 if (current_rate <= 48000 || current_rate > 96000) {
1070                         reject_if_open = 1;
1071                 }
1072                 rate_bits = HDSP_Frequency96KHz;
1073                 break;
1074         case 128000:
1075                 if (current_rate < 128000) {
1076                         reject_if_open = 1;
1077                 }
1078                 rate_bits = HDSP_Frequency128KHz;
1079                 break;
1080         case 176400:
1081                 if (current_rate < 128000) {
1082                         reject_if_open = 1;
1083                 }
1084                 rate_bits = HDSP_Frequency176_4KHz;
1085                 break;
1086         case 192000:
1087                 if (current_rate < 128000) {
1088                         reject_if_open = 1;
1089                 }
1090                 rate_bits = HDSP_Frequency192KHz;
1091                 break;
1092         default:
1093                 return -EINVAL;
1094         }
1095
1096         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1097                 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1098                             hdsp->capture_pid,
1099                             hdsp->playback_pid);
1100                 return -EBUSY;
1101         }
1102
1103         hdsp->control_register &= ~HDSP_FrequencyMask;
1104         hdsp->control_register |= rate_bits;
1105         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1106
1107         if (rate >= 128000) {
1108                 hdsp->channel_map = channel_map_H9632_qs;
1109         } else if (rate > 48000) {
1110                 if (hdsp->io_type == H9632) {
1111                         hdsp->channel_map = channel_map_H9632_ds;
1112                 } else {
1113                         hdsp->channel_map = channel_map_ds;
1114                 }
1115         } else {
1116                 switch (hdsp->io_type) {
1117                 case Multiface:
1118                         hdsp->channel_map = channel_map_mf_ss;
1119                         break;
1120                 case Digiface:
1121                 case H9652:
1122                         hdsp->channel_map = channel_map_df_ss;
1123                         break;
1124                 case H9632:
1125                         hdsp->channel_map = channel_map_H9632_ss;
1126                         break;
1127                 default:
1128                         /* should never happen */
1129                         break;
1130                 }
1131         }
1132
1133         hdsp->system_sample_rate = rate;
1134
1135         return 0;
1136 }
1137
1138 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1139 {
1140
1141         hdsp->passthru = 0;
1142
1143         if (channel < 0) {
1144
1145                 int i;
1146
1147                 /* set thru for all channels */
1148
1149                 if (enable) {
1150                         for (i = 0; i < hdsp->max_channels; i++) {
1151                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1152                         }
1153                 } else {
1154                         for (i = 0; i < hdsp->max_channels; i++) {
1155                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1156                         }
1157                 }
1158
1159         } else {
1160                 int mapped_channel;
1161
1162                 snd_assert(channel < hdsp->max_channels, return);
1163
1164                 mapped_channel = hdsp->channel_map[channel];
1165
1166                 snd_assert(mapped_channel > -1, return);
1167
1168                 if (enable) {
1169                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1170                 } else {
1171                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1172                 }
1173         }
1174 }
1175
1176 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1177 {
1178         if (onoff) {
1179                 hdsp_set_thru(hdsp, -1, 1);
1180                 hdsp_reset_hw_pointer(hdsp);
1181                 hdsp_silence_playback(hdsp);
1182
1183                 /* we don't want interrupts, so do a
1184                    custom version of hdsp_start_audio().
1185                 */
1186
1187                 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1188
1189                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1190                 hdsp->passthru = 1;
1191         } else {
1192                 hdsp_set_thru(hdsp, -1, 0);
1193                 hdsp_stop_audio(hdsp);
1194                 hdsp->passthru = 0;
1195         }
1196
1197         return 0;
1198 }
1199
1200 /*----------------------------------------------------------------------------
1201    MIDI
1202   ----------------------------------------------------------------------------*/
1203
1204 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1205 {
1206         /* the hardware already does the relevant bit-mask with 0xff */
1207         if (id) {
1208                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1209         } else {
1210                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1211         }
1212 }
1213
1214 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1215 {
1216         /* the hardware already does the relevant bit-mask with 0xff */
1217         if (id) {
1218                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1219         } else {
1220                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1221         }
1222 }
1223
1224 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1225 {
1226         if (id) {
1227                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1228         } else {
1229                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1230         }
1231 }
1232
1233 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1234 {
1235         int fifo_bytes_used;
1236
1237         if (id) {
1238                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1239         } else {
1240                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1241         }
1242
1243         if (fifo_bytes_used < 128) {
1244                 return  128 - fifo_bytes_used;
1245         } else {
1246                 return 0;
1247         }
1248 }
1249
1250 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1251 {
1252         while (snd_hdsp_midi_input_available (hdsp, id)) {
1253                 snd_hdsp_midi_read_byte (hdsp, id);
1254         }
1255 }
1256
1257 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1258 {
1259         unsigned long flags;
1260         int n_pending;
1261         int to_write;
1262         int i;
1263         unsigned char buf[128];
1264
1265         /* Output is not interrupt driven */
1266
1267         spin_lock_irqsave (&hmidi->lock, flags);
1268         if (hmidi->output) {
1269                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1270                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1271                                 if (n_pending > (int)sizeof (buf))
1272                                         n_pending = sizeof (buf);
1273
1274                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1275                                         for (i = 0; i < to_write; ++i)
1276                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1277                                 }
1278                         }
1279                 }
1280         }
1281         spin_unlock_irqrestore (&hmidi->lock, flags);
1282         return 0;
1283 }
1284
1285 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1286 {
1287         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1288         unsigned long flags;
1289         int n_pending;
1290         int i;
1291
1292         spin_lock_irqsave (&hmidi->lock, flags);
1293         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1294                 if (hmidi->input) {
1295                         if (n_pending > (int)sizeof (buf)) {
1296                                 n_pending = sizeof (buf);
1297                         }
1298                         for (i = 0; i < n_pending; ++i) {
1299                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1300                         }
1301                         if (n_pending) {
1302                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1303                         }
1304                 } else {
1305                         /* flush the MIDI input FIFO */
1306                         while (--n_pending) {
1307                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1308                         }
1309                 }
1310         }
1311         hmidi->pending = 0;
1312         if (hmidi->id) {
1313                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1314         } else {
1315                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1316         }
1317         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1318         spin_unlock_irqrestore (&hmidi->lock, flags);
1319         return snd_hdsp_midi_output_write (hmidi);
1320 }
1321
1322 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1323 {
1324         hdsp_t *hdsp;
1325         hdsp_midi_t *hmidi;
1326         unsigned long flags;
1327         u32 ie;
1328
1329         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1330         hdsp = hmidi->hdsp;
1331         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1332         spin_lock_irqsave (&hdsp->lock, flags);
1333         if (up) {
1334                 if (!(hdsp->control_register & ie)) {
1335                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1336                         hdsp->control_register |= ie;
1337                 }
1338         } else {
1339                 hdsp->control_register &= ~ie;
1340         }
1341
1342         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1343         spin_unlock_irqrestore (&hdsp->lock, flags);
1344 }
1345
1346 static void snd_hdsp_midi_output_timer(unsigned long data)
1347 {
1348         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1349         unsigned long flags;
1350
1351         snd_hdsp_midi_output_write(hmidi);
1352         spin_lock_irqsave (&hmidi->lock, flags);
1353
1354         /* this does not bump hmidi->istimer, because the
1355            kernel automatically removed the timer when it
1356            expired, and we are now adding it back, thus
1357            leaving istimer wherever it was set before.
1358         */
1359
1360         if (hmidi->istimer) {
1361                 hmidi->timer.expires = 1 + jiffies;
1362                 add_timer(&hmidi->timer);
1363         }
1364
1365         spin_unlock_irqrestore (&hmidi->lock, flags);
1366 }
1367
1368 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1369 {
1370         hdsp_midi_t *hmidi;
1371         unsigned long flags;
1372
1373         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1374         spin_lock_irqsave (&hmidi->lock, flags);
1375         if (up) {
1376                 if (!hmidi->istimer) {
1377                         init_timer(&hmidi->timer);
1378                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1379                         hmidi->timer.data = (unsigned long) hmidi;
1380                         hmidi->timer.expires = 1 + jiffies;
1381                         add_timer(&hmidi->timer);
1382                         hmidi->istimer++;
1383                 }
1384         } else {
1385                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1386                         del_timer (&hmidi->timer);
1387                 }
1388         }
1389         spin_unlock_irqrestore (&hmidi->lock, flags);
1390         if (up)
1391                 snd_hdsp_midi_output_write(hmidi);
1392 }
1393
1394 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1395 {
1396         hdsp_midi_t *hmidi;
1397
1398         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1399         spin_lock_irq (&hmidi->lock);
1400         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1401         hmidi->input = substream;
1402         spin_unlock_irq (&hmidi->lock);
1403
1404         return 0;
1405 }
1406
1407 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1408 {
1409         hdsp_midi_t *hmidi;
1410
1411         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1412         spin_lock_irq (&hmidi->lock);
1413         hmidi->output = substream;
1414         spin_unlock_irq (&hmidi->lock);
1415
1416         return 0;
1417 }
1418
1419 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1420 {
1421         hdsp_midi_t *hmidi;
1422
1423         snd_hdsp_midi_input_trigger (substream, 0);
1424
1425         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1426         spin_lock_irq (&hmidi->lock);
1427         hmidi->input = NULL;
1428         spin_unlock_irq (&hmidi->lock);
1429
1430         return 0;
1431 }
1432
1433 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1434 {
1435         hdsp_midi_t *hmidi;
1436
1437         snd_hdsp_midi_output_trigger (substream, 0);
1438
1439         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1440         spin_lock_irq (&hmidi->lock);
1441         hmidi->output = NULL;
1442         spin_unlock_irq (&hmidi->lock);
1443
1444         return 0;
1445 }
1446
1447 snd_rawmidi_ops_t snd_hdsp_midi_output =
1448 {
1449         .open =         snd_hdsp_midi_output_open,
1450         .close =        snd_hdsp_midi_output_close,
1451         .trigger =      snd_hdsp_midi_output_trigger,
1452 };
1453
1454 snd_rawmidi_ops_t snd_hdsp_midi_input =
1455 {
1456         .open =         snd_hdsp_midi_input_open,
1457         .close =        snd_hdsp_midi_input_close,
1458         .trigger =      snd_hdsp_midi_input_trigger,
1459 };
1460
1461 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1462 {
1463         char buf[32];
1464
1465         hdsp->midi[id].id = id;
1466         hdsp->midi[id].rmidi = NULL;
1467         hdsp->midi[id].input = NULL;
1468         hdsp->midi[id].output = NULL;
1469         hdsp->midi[id].hdsp = hdsp;
1470         hdsp->midi[id].istimer = 0;
1471         hdsp->midi[id].pending = 0;
1472         spin_lock_init (&hdsp->midi[id].lock);
1473
1474         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1475         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1476                 return -1;
1477         }
1478
1479         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1480         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1481
1482         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1483         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1484
1485         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1486                 SNDRV_RAWMIDI_INFO_INPUT |
1487                 SNDRV_RAWMIDI_INFO_DUPLEX;
1488
1489         return 0;
1490 }
1491
1492 /*-----------------------------------------------------------------------------
1493   Control Interface
1494   ----------------------------------------------------------------------------*/
1495
1496 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1497 {
1498         u32 val = 0;
1499         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1500         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1501         if (val & HDSP_SPDIFProfessional)
1502                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1503         else
1504                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1505         return val;
1506 }
1507
1508 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1509 {
1510         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1511                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1512         if (val & HDSP_SPDIFProfessional)
1513                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1514         else
1515                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1516 }
1517
1518 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1519 {
1520         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1521         uinfo->count = 1;
1522         return 0;
1523 }
1524
1525 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1526 {
1527         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1528
1529         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1530         return 0;
1531 }
1532
1533 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1534 {
1535         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1536         int change;
1537         u32 val;
1538
1539         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1540         spin_lock_irq(&hdsp->lock);
1541         change = val != hdsp->creg_spdif;
1542         hdsp->creg_spdif = val;
1543         spin_unlock_irq(&hdsp->lock);
1544         return change;
1545 }
1546
1547 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1548 {
1549         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1550         uinfo->count = 1;
1551         return 0;
1552 }
1553
1554 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1555 {
1556         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1557
1558         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1559         return 0;
1560 }
1561
1562 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1563 {
1564         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1565         int change;
1566         u32 val;
1567
1568         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1569         spin_lock_irq(&hdsp->lock);
1570         change = val != hdsp->creg_spdif_stream;
1571         hdsp->creg_spdif_stream = val;
1572         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1573         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1574         spin_unlock_irq(&hdsp->lock);
1575         return change;
1576 }
1577
1578 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1579 {
1580         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1581         uinfo->count = 1;
1582         return 0;
1583 }
1584
1585 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1586 {
1587         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1588         return 0;
1589 }
1590
1591 #define HDSP_SPDIF_IN(xname, xindex) \
1592 { .iface = SNDRV_CTL_ELEM_IFACE_PCM,  \
1593   .name = xname, \
1594   .index = xindex, \
1595   .info = snd_hdsp_info_spdif_in, \
1596   .get = snd_hdsp_get_spdif_in, \
1597   .put = snd_hdsp_put_spdif_in }
1598
1599 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1600 {
1601         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1602 }
1603
1604 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1605 {
1606         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1607         hdsp->control_register |= hdsp_encode_spdif_in(in);
1608         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1609         return 0;
1610 }
1611
1612 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1613 {
1614         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1615         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1616
1617         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1618         uinfo->count = 1;
1619         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1620         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1621                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1622         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1623         return 0;
1624 }
1625
1626 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1627 {
1628         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1629
1630         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1631         return 0;
1632 }
1633
1634 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1635 {
1636         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1637         int change;
1638         unsigned int val;
1639
1640         if (!snd_hdsp_use_is_exclusive(hdsp))
1641                 return -EBUSY;
1642         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1643         spin_lock_irq(&hdsp->lock);
1644         change = val != hdsp_spdif_in(hdsp);
1645         if (change)
1646                 hdsp_set_spdif_input(hdsp, val);
1647         spin_unlock_irq(&hdsp->lock);
1648         return change;
1649 }
1650
1651 #define HDSP_SPDIF_OUT(xname, xindex) \
1652 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1653   .info = snd_hdsp_info_spdif_bits, \
1654   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1655
1656 static int hdsp_spdif_out(hdsp_t *hdsp)
1657 {
1658         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1659 }
1660
1661 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1662 {
1663         if (out) {
1664                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1665         } else {
1666                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1667         }
1668         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1669         return 0;
1670 }
1671
1672 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1673 {
1674         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1675         uinfo->count = 1;
1676         uinfo->value.integer.min = 0;
1677         uinfo->value.integer.max = 1;
1678         return 0;
1679 }
1680
1681 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1682 {
1683         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1684
1685         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1686         return 0;
1687 }
1688
1689 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1690 {
1691         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1692         int change;
1693         unsigned int val;
1694
1695         if (!snd_hdsp_use_is_exclusive(hdsp))
1696                 return -EBUSY;
1697         val = ucontrol->value.integer.value[0] & 1;
1698         spin_lock_irq(&hdsp->lock);
1699         change = (int)val != hdsp_spdif_out(hdsp);
1700         hdsp_set_spdif_output(hdsp, val);
1701         spin_unlock_irq(&hdsp->lock);
1702         return change;
1703 }
1704
1705 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1706 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1707   .info = snd_hdsp_info_spdif_bits, \
1708   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1709
1710 static int hdsp_spdif_professional(hdsp_t *hdsp)
1711 {
1712         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1713 }
1714
1715 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1716 {
1717         if (val) {
1718                 hdsp->control_register |= HDSP_SPDIFProfessional;
1719         } else {
1720                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1721         }
1722         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1723         return 0;
1724 }
1725
1726 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1727 {
1728         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1729
1730         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1731         return 0;
1732 }
1733
1734 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1735 {
1736         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1737         int change;
1738         unsigned int val;
1739
1740         if (!snd_hdsp_use_is_exclusive(hdsp))
1741                 return -EBUSY;
1742         val = ucontrol->value.integer.value[0] & 1;
1743         spin_lock_irq(&hdsp->lock);
1744         change = (int)val != hdsp_spdif_professional(hdsp);
1745         hdsp_set_spdif_professional(hdsp, val);
1746         spin_unlock_irq(&hdsp->lock);
1747         return change;
1748 }
1749
1750 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1751 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1752   .info = snd_hdsp_info_spdif_bits, \
1753   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1754
1755 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1756 {
1757         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1758 }
1759
1760 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1761 {
1762         if (val) {
1763                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1764         } else {
1765                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1766         }
1767         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1768         return 0;
1769 }
1770
1771 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1772 {
1773         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1774
1775         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1776         return 0;
1777 }
1778
1779 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1780 {
1781         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1782         int change;
1783         unsigned int val;
1784
1785         if (!snd_hdsp_use_is_exclusive(hdsp))
1786                 return -EBUSY;
1787         val = ucontrol->value.integer.value[0] & 1;
1788         spin_lock_irq(&hdsp->lock);
1789         change = (int)val != hdsp_spdif_emphasis(hdsp);
1790         hdsp_set_spdif_emphasis(hdsp, val);
1791         spin_unlock_irq(&hdsp->lock);
1792         return change;
1793 }
1794
1795 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1796 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1797   .info = snd_hdsp_info_spdif_bits, \
1798   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1799
1800 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1801 {
1802         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1803 }
1804
1805 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1806 {
1807         if (val) {
1808                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1809         } else {
1810                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1811         }
1812         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1813         return 0;
1814 }
1815
1816 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1817 {
1818         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1819
1820         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1821         return 0;
1822 }
1823
1824 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1825 {
1826         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1827         int change;
1828         unsigned int val;
1829
1830         if (!snd_hdsp_use_is_exclusive(hdsp))
1831                 return -EBUSY;
1832         val = ucontrol->value.integer.value[0] & 1;
1833         spin_lock_irq(&hdsp->lock);
1834         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1835         hdsp_set_spdif_nonaudio(hdsp, val);
1836         spin_unlock_irq(&hdsp->lock);
1837         return change;
1838 }
1839
1840 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1841 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1842   .name = xname, \
1843   .index = xindex, \
1844   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1845   .info = snd_hdsp_info_spdif_sample_rate, \
1846   .get = snd_hdsp_get_spdif_sample_rate \
1847 }
1848
1849 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1850 {
1851         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1852         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1853
1854         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1855         uinfo->count = 1;
1856         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1857         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1858                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1859         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1860         return 0;
1861 }
1862
1863 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1864 {
1865         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1866
1867         switch (hdsp_spdif_sample_rate(hdsp)) {
1868         case 32000:
1869                 ucontrol->value.enumerated.item[0] = 0;
1870                 break;
1871         case 44100:
1872                 ucontrol->value.enumerated.item[0] = 1;
1873                 break;
1874         case 48000:
1875                 ucontrol->value.enumerated.item[0] = 2;
1876                 break;
1877         case 64000:
1878                 ucontrol->value.enumerated.item[0] = 3;
1879                 break;
1880         case 88200:
1881                 ucontrol->value.enumerated.item[0] = 4;
1882                 break;
1883         case 96000:
1884                 ucontrol->value.enumerated.item[0] = 5;
1885                 break;
1886         case 128000:
1887                 ucontrol->value.enumerated.item[0] = 7;
1888                 break;
1889         case 176400:
1890                 ucontrol->value.enumerated.item[0] = 8;
1891                 break;
1892         case 192000:
1893                 ucontrol->value.enumerated.item[0] = 9;
1894                 break;
1895         default:
1896                 ucontrol->value.enumerated.item[0] = 6;
1897         }
1898         return 0;
1899 }
1900
1901 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1902 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1903   .name = xname, \
1904   .index = xindex, \
1905   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1906   .info = snd_hdsp_info_system_sample_rate, \
1907   .get = snd_hdsp_get_system_sample_rate \
1908 }
1909
1910 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1911 {
1912         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1913         uinfo->count = 1;
1914         return 0;
1915 }
1916
1917 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1918 {
1919         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1920
1921         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1922         return 0;
1923 }
1924
1925 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1926 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1927   .name = xname, \
1928   .index = xindex, \
1929   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1930   .info = snd_hdsp_info_autosync_sample_rate, \
1931   .get = snd_hdsp_get_autosync_sample_rate \
1932 }
1933
1934 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1935 {
1936         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1937         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1938         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1939         uinfo->count = 1;
1940         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1941         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1942                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1943         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1944         return 0;
1945 }
1946
1947 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1948 {
1949         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1950
1951         switch (hdsp_external_sample_rate(hdsp)) {
1952         case 32000:
1953                 ucontrol->value.enumerated.item[0] = 0;
1954                 break;
1955         case 44100:
1956                 ucontrol->value.enumerated.item[0] = 1;
1957                 break;
1958         case 48000:
1959                 ucontrol->value.enumerated.item[0] = 2;
1960                 break;
1961         case 64000:
1962                 ucontrol->value.enumerated.item[0] = 3;
1963                 break;
1964         case 88200:
1965                 ucontrol->value.enumerated.item[0] = 4;
1966                 break;
1967         case 96000:
1968                 ucontrol->value.enumerated.item[0] = 5;
1969                 break;
1970         case 128000:
1971                 ucontrol->value.enumerated.item[0] = 7;
1972                 break;
1973         case 176400:
1974                 ucontrol->value.enumerated.item[0] = 8;
1975                 break;
1976         case 192000:
1977                 ucontrol->value.enumerated.item[0] = 9;
1978                 break;
1979         default:
1980                 ucontrol->value.enumerated.item[0] = 6;
1981         }
1982         return 0;
1983 }
1984
1985 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1986 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1987   .name = xname, \
1988   .index = xindex, \
1989   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1990   .info = snd_hdsp_info_system_clock_mode, \
1991   .get = snd_hdsp_get_system_clock_mode \
1992 }
1993
1994 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1995 {
1996         if (hdsp->control_register & HDSP_ClockModeMaster) {
1997                 return 0;
1998         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
1999                         return 0;
2000         }
2001         return 1;
2002 }
2003
2004 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2005 {
2006         static char *texts[] = {"Master", "Slave" };
2007
2008         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2009         uinfo->count = 1;
2010         uinfo->value.enumerated.items = 2;
2011         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2012                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2013         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2014         return 0;
2015 }
2016
2017 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2018 {
2019         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2020
2021         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2022         return 0;
2023 }
2024
2025 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2026 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2027   .name = xname, \
2028   .index = xindex, \
2029   .info = snd_hdsp_info_clock_source, \
2030   .get = snd_hdsp_get_clock_source, \
2031   .put = snd_hdsp_put_clock_source \
2032 }
2033
2034 static int hdsp_clock_source(hdsp_t *hdsp)
2035 {
2036         if (hdsp->control_register & HDSP_ClockModeMaster) {
2037                 switch (hdsp->system_sample_rate) {
2038                 case 32000:
2039                         return 1;
2040                 case 44100:
2041                         return 2;
2042                 case 48000:
2043                         return 3;
2044                 case 64000:
2045                         return 4;
2046                 case 88200:
2047                         return 5;
2048                 case 96000:
2049                         return 6;
2050                 case 128000:
2051                         return 7;
2052                 case 176400:
2053                         return 8;
2054                 case 192000:
2055                         return 9;
2056                 default:
2057                         return 3;
2058                 }
2059         } else {
2060                 return 0;
2061         }
2062 }
2063
2064 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2065 {
2066         int rate;
2067         switch (mode) {
2068         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2069                 if (hdsp_external_sample_rate(hdsp) != 0) {
2070                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2071                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2072                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2073                         return 0;
2074                     }
2075                 }
2076                 return -1;
2077         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2078                 rate = 32000;
2079                 break;
2080         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2081                 rate = 44100;
2082                 break;
2083         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2084                 rate = 48000;
2085                 break;
2086         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2087                 rate = 64000;
2088                 break;
2089         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2090                 rate = 88200;
2091                 break;
2092         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2093                 rate = 96000;
2094                 break;
2095         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2096                 rate = 128000;
2097                 break;
2098         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2099                 rate = 176400;
2100                 break;
2101         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2102                 rate = 192000;
2103                 break;
2104         default:
2105                 rate = 48000;
2106         }
2107         hdsp->control_register |= HDSP_ClockModeMaster;
2108         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2109         hdsp_set_rate(hdsp, rate, 1);
2110         return 0;
2111 }
2112
2113 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2114 {
2115         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2116         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2117
2118         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2119         uinfo->count = 1;
2120         if (hdsp->io_type == H9632)
2121             uinfo->value.enumerated.items = 10;
2122         else
2123             uinfo->value.enumerated.items = 7;
2124         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2125                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2126         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2127         return 0;
2128 }
2129
2130 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2131 {
2132         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2133
2134         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2135         return 0;
2136 }
2137
2138 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2139 {
2140         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2141         int change;
2142         int val;
2143
2144         if (!snd_hdsp_use_is_exclusive(hdsp))
2145                 return -EBUSY;
2146         val = ucontrol->value.enumerated.item[0];
2147         if (val < 0) val = 0;
2148         if (hdsp->io_type == H9632) {
2149             if (val > 9) val = 9;
2150         } else {
2151             if (val > 6) val = 6;
2152         }
2153         spin_lock_irq(&hdsp->lock);
2154         if (val != hdsp_clock_source(hdsp)) {
2155                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2156         } else {
2157                 change = 0;
2158         }
2159         spin_unlock_irq(&hdsp->lock);
2160         return change;
2161 }
2162
2163 #define HDSP_DA_GAIN(xname, xindex) \
2164 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2165   .name = xname, \
2166   .index = xindex, \
2167   .info = snd_hdsp_info_da_gain, \
2168   .get = snd_hdsp_get_da_gain, \
2169   .put = snd_hdsp_put_da_gain \
2170 }
2171
2172 static int hdsp_da_gain(hdsp_t *hdsp)
2173 {
2174         switch (hdsp->control_register & HDSP_DAGainMask) {
2175         case HDSP_DAGainHighGain:
2176                 return 0;
2177         case HDSP_DAGainPlus4dBu:
2178                 return 1;
2179         case HDSP_DAGainMinus10dBV:
2180                 return 2;
2181         default:
2182                 return 1;
2183         }
2184 }
2185
2186 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2187 {
2188         hdsp->control_register &= ~HDSP_DAGainMask;
2189         switch (mode) {
2190         case 0:
2191                 hdsp->control_register |= HDSP_DAGainHighGain;
2192                 break;
2193         case 1:
2194                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2195                 break;
2196         case 2:
2197                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2198                 break;
2199         default:
2200                 return -1;
2201
2202         }
2203         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2204         return 0;
2205 }
2206
2207 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2208 {
2209         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2210
2211         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2212         uinfo->count = 1;
2213         uinfo->value.enumerated.items = 3;
2214         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2215                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2216         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2217         return 0;
2218 }
2219
2220 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2221 {
2222         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2223
2224         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2225         return 0;
2226 }
2227
2228 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2229 {
2230         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2231         int change;
2232         int val;
2233
2234         if (!snd_hdsp_use_is_exclusive(hdsp))
2235                 return -EBUSY;
2236         val = ucontrol->value.enumerated.item[0];
2237         if (val < 0) val = 0;
2238         if (val > 2) val = 2;
2239         spin_lock_irq(&hdsp->lock);
2240         if (val != hdsp_da_gain(hdsp)) {
2241                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2242         } else {
2243                 change = 0;
2244         }
2245         spin_unlock_irq(&hdsp->lock);
2246         return change;
2247 }
2248
2249 #define HDSP_AD_GAIN(xname, xindex) \
2250 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2251   .name = xname, \
2252   .index = xindex, \
2253   .info = snd_hdsp_info_ad_gain, \
2254   .get = snd_hdsp_get_ad_gain, \
2255   .put = snd_hdsp_put_ad_gain \
2256 }
2257
2258 static int hdsp_ad_gain(hdsp_t *hdsp)
2259 {
2260         switch (hdsp->control_register & HDSP_ADGainMask) {
2261         case HDSP_ADGainMinus10dBV:
2262                 return 0;
2263         case HDSP_ADGainPlus4dBu:
2264                 return 1;
2265         case HDSP_ADGainLowGain:
2266                 return 2;
2267         default:
2268                 return 1;
2269         }
2270 }
2271
2272 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2273 {
2274         hdsp->control_register &= ~HDSP_ADGainMask;
2275         switch (mode) {
2276         case 0:
2277                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2278                 break;
2279         case 1:
2280                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2281                 break;
2282         case 2:
2283                 hdsp->control_register |= HDSP_ADGainLowGain;
2284                 break;
2285         default:
2286                 return -1;
2287
2288         }
2289         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2290         return 0;
2291 }
2292
2293 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2294 {
2295         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2296
2297         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2298         uinfo->count = 1;
2299         uinfo->value.enumerated.items = 3;
2300         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2301                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2302         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2303         return 0;
2304 }
2305
2306 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2307 {
2308         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2309
2310         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2311         return 0;
2312 }
2313
2314 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2315 {
2316         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2317         int change;
2318         int val;
2319
2320         if (!snd_hdsp_use_is_exclusive(hdsp))
2321                 return -EBUSY;
2322         val = ucontrol->value.enumerated.item[0];
2323         if (val < 0) val = 0;
2324         if (val > 2) val = 2;
2325         spin_lock_irq(&hdsp->lock);
2326         if (val != hdsp_ad_gain(hdsp)) {
2327                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2328         } else {
2329                 change = 0;
2330         }
2331         spin_unlock_irq(&hdsp->lock);
2332         return change;
2333 }
2334
2335 #define HDSP_PHONE_GAIN(xname, xindex) \
2336 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2337   .name = xname, \
2338   .index = xindex, \
2339   .info = snd_hdsp_info_phone_gain, \
2340   .get = snd_hdsp_get_phone_gain, \
2341   .put = snd_hdsp_put_phone_gain \
2342 }
2343
2344 static int hdsp_phone_gain(hdsp_t *hdsp)
2345 {
2346         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2347         case HDSP_PhoneGain0dB:
2348                 return 0;
2349         case HDSP_PhoneGainMinus6dB:
2350                 return 1;
2351         case HDSP_PhoneGainMinus12dB:
2352                 return 2;
2353         default:
2354                 return 0;
2355         }
2356 }
2357
2358 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2359 {
2360         hdsp->control_register &= ~HDSP_PhoneGainMask;
2361         switch (mode) {
2362         case 0:
2363                 hdsp->control_register |= HDSP_PhoneGain0dB;
2364                 break;
2365         case 1:
2366                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2367                 break;
2368         case 2:
2369                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2370                 break;
2371         default:
2372                 return -1;
2373
2374         }
2375         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2376         return 0;
2377 }
2378
2379 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2380 {
2381         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2382
2383         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2384         uinfo->count = 1;
2385         uinfo->value.enumerated.items = 3;
2386         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2387                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2388         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2389         return 0;
2390 }
2391
2392 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2393 {
2394         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2395
2396         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2397         return 0;
2398 }
2399
2400 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2401 {
2402         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2403         int change;
2404         int val;
2405
2406         if (!snd_hdsp_use_is_exclusive(hdsp))
2407                 return -EBUSY;
2408         val = ucontrol->value.enumerated.item[0];
2409         if (val < 0) val = 0;
2410         if (val > 2) val = 2;
2411         spin_lock_irq(&hdsp->lock);
2412         if (val != hdsp_phone_gain(hdsp)) {
2413                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2414         } else {
2415                 change = 0;
2416         }
2417         spin_unlock_irq(&hdsp->lock);
2418         return change;
2419 }
2420
2421 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2422 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2423   .name = xname, \
2424   .index = xindex, \
2425   .info = snd_hdsp_info_xlr_breakout_cable, \
2426   .get = snd_hdsp_get_xlr_breakout_cable, \
2427   .put = snd_hdsp_put_xlr_breakout_cable \
2428 }
2429
2430 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2431 {
2432         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2433                 return 1;
2434         }
2435         return 0;
2436 }
2437
2438 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2439 {
2440         if (mode) {
2441                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2442         } else {
2443                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2444         }
2445         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2446         return 0;
2447 }
2448
2449 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2450 {
2451         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2452         uinfo->count = 1;
2453         uinfo->value.integer.min = 0;
2454         uinfo->value.integer.max = 1;
2455         return 0;
2456 }
2457
2458 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2459 {
2460         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2461
2462         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2463         return 0;
2464 }
2465
2466 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2467 {
2468         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2469         int change;
2470         int val;
2471
2472         if (!snd_hdsp_use_is_exclusive(hdsp))
2473                 return -EBUSY;
2474         val = ucontrol->value.integer.value[0] & 1;
2475         spin_lock_irq(&hdsp->lock);
2476         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2477         hdsp_set_xlr_breakout_cable(hdsp, val);
2478         spin_unlock_irq(&hdsp->lock);
2479         return change;
2480 }
2481
2482 /* (De)activates old RME Analog Extension Board
2483    These are connected to the internal ADAT connector
2484    Switching this on desactivates external ADAT
2485 */
2486 #define HDSP_AEB(xname, xindex) \
2487 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2488   .name = xname, \
2489   .index = xindex, \
2490   .info = snd_hdsp_info_aeb, \
2491   .get = snd_hdsp_get_aeb, \
2492   .put = snd_hdsp_put_aeb \
2493 }
2494
2495 static int hdsp_aeb(hdsp_t *hdsp)
2496 {
2497         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2498                 return 1;
2499         }
2500         return 0;
2501 }
2502
2503 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2504 {
2505         if (mode) {
2506                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2507         } else {
2508                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2509         }
2510         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2511         return 0;
2512 }
2513
2514 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2515 {
2516         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2517         uinfo->count = 1;
2518         uinfo->value.integer.min = 0;
2519         uinfo->value.integer.max = 1;
2520         return 0;
2521 }
2522
2523 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2524 {
2525         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2526
2527         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2528         return 0;
2529 }
2530
2531 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2532 {
2533         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2534         int change;
2535         int val;
2536
2537         if (!snd_hdsp_use_is_exclusive(hdsp))
2538                 return -EBUSY;
2539         val = ucontrol->value.integer.value[0] & 1;
2540         spin_lock_irq(&hdsp->lock);
2541         change = (int)val != hdsp_aeb(hdsp);
2542         hdsp_set_aeb(hdsp, val);
2543         spin_unlock_irq(&hdsp->lock);
2544         return change;
2545 }
2546
2547 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2548 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2549   .name = xname, \
2550   .index = xindex, \
2551   .info = snd_hdsp_info_pref_sync_ref, \
2552   .get = snd_hdsp_get_pref_sync_ref, \
2553   .put = snd_hdsp_put_pref_sync_ref \
2554 }
2555
2556 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2557 {
2558         /* Notice that this looks at the requested sync source,
2559            not the one actually in use.
2560         */
2561
2562         switch (hdsp->control_register & HDSP_SyncRefMask) {
2563         case HDSP_SyncRef_ADAT1:
2564                 return HDSP_SYNC_FROM_ADAT1;
2565         case HDSP_SyncRef_ADAT2:
2566                 return HDSP_SYNC_FROM_ADAT2;
2567         case HDSP_SyncRef_ADAT3:
2568                 return HDSP_SYNC_FROM_ADAT3;
2569         case HDSP_SyncRef_SPDIF:
2570                 return HDSP_SYNC_FROM_SPDIF;
2571         case HDSP_SyncRef_WORD:
2572                 return HDSP_SYNC_FROM_WORD;
2573         case HDSP_SyncRef_ADAT_SYNC:
2574                 return HDSP_SYNC_FROM_ADAT_SYNC;
2575         default:
2576                 return HDSP_SYNC_FROM_WORD;
2577         }
2578         return 0;
2579 }
2580
2581 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2582 {
2583         hdsp->control_register &= ~HDSP_SyncRefMask;
2584         switch (pref) {
2585         case HDSP_SYNC_FROM_ADAT1:
2586                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2587                 break;
2588         case HDSP_SYNC_FROM_ADAT2:
2589                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2590                 break;
2591         case HDSP_SYNC_FROM_ADAT3:
2592                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2593                 break;
2594         case HDSP_SYNC_FROM_SPDIF:
2595                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2596                 break;
2597         case HDSP_SYNC_FROM_WORD:
2598                 hdsp->control_register |= HDSP_SyncRef_WORD;
2599                 break;
2600         case HDSP_SYNC_FROM_ADAT_SYNC:
2601                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2602                 break;
2603         default:
2604                 return -1;
2605         }
2606         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2607         return 0;
2608 }
2609
2610 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2611 {
2612         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2613         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2614
2615         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2616         uinfo->count = 1;
2617
2618         switch (hdsp->io_type) {
2619         case Digiface:
2620         case H9652:
2621                 uinfo->value.enumerated.items = 6;
2622                 break;
2623         case Multiface:
2624                 uinfo->value.enumerated.items = 4;
2625                 break;
2626         case H9632:
2627                 uinfo->value.enumerated.items = 3;
2628                 break;
2629         default:
2630                 uinfo->value.enumerated.items = 0;
2631                 break;
2632         }
2633
2634         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2635                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2636         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2637         return 0;
2638 }
2639
2640 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2641 {
2642         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2643
2644         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2645         return 0;
2646 }
2647
2648 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2649 {
2650         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2651         int change, max;
2652         unsigned int val;
2653
2654         if (!snd_hdsp_use_is_exclusive(hdsp))
2655                 return -EBUSY;
2656
2657         switch (hdsp->io_type) {
2658         case Digiface:
2659         case H9652:
2660                 max = 6;
2661                 break;
2662         case Multiface:
2663                 max = 4;
2664                 break;
2665         case H9632:
2666                 max = 3;
2667                 break;
2668         default:
2669                 return -EIO;
2670         }
2671
2672         val = ucontrol->value.enumerated.item[0] % max;
2673         spin_lock_irq(&hdsp->lock);
2674         change = (int)val != hdsp_pref_sync_ref(hdsp);
2675         hdsp_set_pref_sync_ref(hdsp, val);
2676         spin_unlock_irq(&hdsp->lock);
2677         return change;
2678 }
2679
2680 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2681 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2682   .name = xname, \
2683   .index = xindex, \
2684   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2685   .info = snd_hdsp_info_autosync_ref, \
2686   .get = snd_hdsp_get_autosync_ref, \
2687 }
2688
2689 static int hdsp_autosync_ref(hdsp_t *hdsp)
2690 {
2691         /* This looks at the autosync selected sync reference */
2692         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2693
2694         switch (status2 & HDSP_SelSyncRefMask) {
2695         case HDSP_SelSyncRef_WORD:
2696                 return HDSP_AUTOSYNC_FROM_WORD;
2697         case HDSP_SelSyncRef_ADAT_SYNC:
2698                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2699         case HDSP_SelSyncRef_SPDIF:
2700                 return HDSP_AUTOSYNC_FROM_SPDIF;
2701         case HDSP_SelSyncRefMask:
2702                 return HDSP_AUTOSYNC_FROM_NONE;
2703         case HDSP_SelSyncRef_ADAT1:
2704                 return HDSP_AUTOSYNC_FROM_ADAT1;
2705         case HDSP_SelSyncRef_ADAT2:
2706                 return HDSP_AUTOSYNC_FROM_ADAT2;
2707         case HDSP_SelSyncRef_ADAT3:
2708                 return HDSP_AUTOSYNC_FROM_ADAT3;
2709         default:
2710                 return HDSP_AUTOSYNC_FROM_WORD;
2711         }
2712         return 0;
2713 }
2714
2715 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2716 {
2717         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2718
2719         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2720         uinfo->count = 1;
2721         uinfo->value.enumerated.items = 7;
2722         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2723                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2724         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2725         return 0;
2726 }
2727
2728 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2729 {
2730         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2731
2732         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2733         return 0;
2734 }
2735
2736 #define HDSP_PASSTHRU(xname, xindex) \
2737 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2738   .name = xname, \
2739   .index = xindex, \
2740   .info = snd_hdsp_info_passthru, \
2741   .put = snd_hdsp_put_passthru, \
2742   .get = snd_hdsp_get_passthru \
2743 }
2744
2745 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2746 {
2747         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2748         uinfo->count = 1;
2749         uinfo->value.integer.min = 0;
2750         uinfo->value.integer.max = 1;
2751         return 0;
2752 }
2753
2754 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2755 {
2756         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2757
2758         spin_lock_irq(&hdsp->lock);
2759         ucontrol->value.integer.value[0] = hdsp->passthru;
2760         spin_unlock_irq(&hdsp->lock);
2761         return 0;
2762 }
2763
2764 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2765 {
2766         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2767         int change;
2768         unsigned int val;
2769         int err = 0;
2770
2771         if (!snd_hdsp_use_is_exclusive(hdsp))
2772                 return -EBUSY;
2773
2774         val = ucontrol->value.integer.value[0] & 1;
2775         spin_lock_irq(&hdsp->lock);
2776         change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2777         if (change)
2778                 err = hdsp_set_passthru(hdsp, val);
2779         spin_unlock_irq(&hdsp->lock);
2780         return err ? err : change;
2781 }
2782
2783 #define HDSP_LINE_OUT(xname, xindex) \
2784 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2785   .name = xname, \
2786   .index = xindex, \
2787   .info = snd_hdsp_info_line_out, \
2788   .get = snd_hdsp_get_line_out, \
2789   .put = snd_hdsp_put_line_out \
2790 }
2791
2792 static int hdsp_line_out(hdsp_t *hdsp)
2793 {
2794         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2795 }
2796
2797 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2798 {
2799         if (out) {
2800                 hdsp->control_register |= HDSP_LineOut;
2801         } else {
2802                 hdsp->control_register &= ~HDSP_LineOut;
2803         }
2804         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2805         return 0;
2806 }
2807
2808 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2809 {
2810         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2811         uinfo->count = 1;
2812         uinfo->value.integer.min = 0;
2813         uinfo->value.integer.max = 1;
2814         return 0;
2815 }
2816
2817 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2818 {
2819         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2820
2821         spin_lock_irq(&hdsp->lock);
2822         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2823         spin_unlock_irq(&hdsp->lock);
2824         return 0;
2825 }
2826
2827 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2828 {
2829         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2830         int change;
2831         unsigned int val;
2832
2833         if (!snd_hdsp_use_is_exclusive(hdsp))
2834                 return -EBUSY;
2835         val = ucontrol->value.integer.value[0] & 1;
2836         spin_lock_irq(&hdsp->lock);
2837         change = (int)val != hdsp_line_out(hdsp);
2838         hdsp_set_line_output(hdsp, val);
2839         spin_unlock_irq(&hdsp->lock);
2840         return change;
2841 }
2842
2843 #define HDSP_MIXER(xname, xindex) \
2844 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2845   .name = xname, \
2846   .index = xindex, \
2847   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2848                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2849   .info = snd_hdsp_info_mixer, \
2850   .get = snd_hdsp_get_mixer, \
2851   .put = snd_hdsp_put_mixer \
2852 }
2853
2854 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2855 {
2856         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2857         uinfo->count = 3;
2858         uinfo->value.integer.min = 0;
2859         uinfo->value.integer.max = 65536;
2860         uinfo->value.integer.step = 1;
2861         return 0;
2862 }
2863
2864 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2865 {
2866         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2867         int source;
2868         int destination;
2869         int addr;
2870
2871         source = ucontrol->value.integer.value[0];
2872         destination = ucontrol->value.integer.value[1];
2873
2874         if (source >= hdsp->max_channels) {
2875                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2876         } else {
2877                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2878         }
2879
2880         spin_lock_irq(&hdsp->lock);
2881         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2882         spin_unlock_irq(&hdsp->lock);
2883         return 0;
2884 }
2885
2886 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2887 {
2888         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2889         int change;
2890         int source;
2891         int destination;
2892         int gain;
2893         int addr;
2894
2895         if (!snd_hdsp_use_is_exclusive(hdsp))
2896                 return -EBUSY;
2897
2898         source = ucontrol->value.integer.value[0];
2899         destination = ucontrol->value.integer.value[1];
2900
2901         if (source >= hdsp->max_channels) {
2902                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2903         } else {
2904                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2905         }
2906
2907         gain = ucontrol->value.integer.value[2];
2908
2909         spin_lock_irq(&hdsp->lock);
2910         change = gain != hdsp_read_gain(hdsp, addr);
2911         if (change)
2912                 hdsp_write_gain(hdsp, addr, gain);
2913         spin_unlock_irq(&hdsp->lock);
2914         return change;
2915 }
2916
2917 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2918 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2919   .name = xname, \
2920   .index = xindex, \
2921   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2922   .info = snd_hdsp_info_sync_check, \
2923   .get = snd_hdsp_get_wc_sync_check \
2924 }
2925
2926 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2927 {
2928         static char *texts[] = {"No Lock", "Lock", "Sync" };
2929         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2930         uinfo->count = 1;
2931         uinfo->value.enumerated.items = 3;
2932         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2933                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2934         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2935         return 0;
2936 }
2937
2938 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2939 {
2940         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2941         if (status2 & HDSP_wc_lock) {
2942                 if (status2 & HDSP_wc_sync) {
2943                         return 2;
2944                 } else {
2945                          return 1;
2946                 }
2947         } else {
2948                 return 0;
2949         }
2950         return 0;
2951 }
2952
2953 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2954 {
2955         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2956
2957         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2958         return 0;
2959 }
2960
2961 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2962 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2963   .name = xname, \
2964   .index = xindex, \
2965   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2966   .info = snd_hdsp_info_sync_check, \
2967   .get = snd_hdsp_get_spdif_sync_check \
2968 }
2969
2970 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2971 {
2972         int status = hdsp_read(hdsp, HDSP_statusRegister);
2973         if (status & HDSP_SPDIFErrorFlag) {
2974                 return 0;
2975         } else {
2976                 if (status & HDSP_SPDIFSync) {
2977                         return 2;
2978                 } else {
2979                         return 1;
2980                 }
2981         }
2982         return 0;
2983 }
2984
2985 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2986 {
2987         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2988
2989         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2990         return 0;
2991 }
2992
2993 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2994 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2995   .name = xname, \
2996   .index = xindex, \
2997   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2998   .info = snd_hdsp_info_sync_check, \
2999   .get = snd_hdsp_get_adatsync_sync_check \
3000 }
3001
3002 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3003 {
3004         int status = hdsp_read(hdsp, HDSP_statusRegister);
3005         if (status & HDSP_TimecodeLock) {
3006                 if (status & HDSP_TimecodeSync) {
3007                         return 2;
3008                 } else {
3009                         return 1;
3010                 }
3011         } else {
3012                 return 0;
3013         }
3014 }
3015
3016 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3017 {
3018         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3019
3020         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3021         return 0;
3022 }
3023
3024 #define HDSP_ADAT_SYNC_CHECK \
3025 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3026   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3027   .info = snd_hdsp_info_sync_check, \
3028   .get = snd_hdsp_get_adat_sync_check \
3029 }
3030
3031 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3032 {
3033         int status = hdsp_read(hdsp, HDSP_statusRegister);
3034
3035         if (status & (HDSP_Lock0>>idx)) {
3036                 if (status & (HDSP_Sync0>>idx)) {
3037                         return 2;
3038                 } else {
3039                         return 1;
3040                 }
3041         } else {
3042                 return 0;
3043         }
3044 }
3045
3046 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3047 {
3048         int offset;
3049         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3050
3051         offset = ucontrol->id.index - 1;
3052         snd_assert(offset >= 0);
3053
3054         switch (hdsp->io_type) {
3055         case Digiface:
3056         case H9652:
3057                 if (offset >= 3)
3058                         return -EINVAL;
3059                 break;
3060         case Multiface:
3061         case H9632:
3062                 if (offset >= 1)
3063                         return -EINVAL;
3064                 break;
3065         default:
3066                 return -EIO;
3067         }
3068
3069         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3070         return 0;
3071 }
3072
3073 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3074 HDSP_DA_GAIN("DA Gain", 0),
3075 HDSP_AD_GAIN("AD Gain", 0),
3076 HDSP_PHONE_GAIN("Phones Gain", 0),
3077 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3078 };
3079
3080 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3081 {
3082         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3083         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3084         .info =         snd_hdsp_control_spdif_info,
3085         .get =          snd_hdsp_control_spdif_get,
3086         .put =          snd_hdsp_control_spdif_put,
3087 },
3088 {
3089         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3090         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3091         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3092         .info =         snd_hdsp_control_spdif_stream_info,
3093         .get =          snd_hdsp_control_spdif_stream_get,
3094         .put =          snd_hdsp_control_spdif_stream_put,
3095 },
3096 {
3097         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3098         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3099         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3100         .info =         snd_hdsp_control_spdif_mask_info,
3101         .get =          snd_hdsp_control_spdif_mask_get,
3102         .private_value = IEC958_AES0_NONAUDIO |
3103                          IEC958_AES0_PROFESSIONAL |
3104                          IEC958_AES0_CON_EMPHASIS,
3105 },
3106 {
3107         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3108         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3109         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3110         .info =         snd_hdsp_control_spdif_mask_info,
3111         .get =          snd_hdsp_control_spdif_mask_get,
3112         .private_value = IEC958_AES0_NONAUDIO |
3113                          IEC958_AES0_PROFESSIONAL |
3114                          IEC958_AES0_PRO_EMPHASIS,
3115 },
3116 HDSP_MIXER("Mixer", 0),
3117 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3118 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3119 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3120 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3121 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3122 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3123 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3124 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3125 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3126 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3127 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3128 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3129 /* 'External Rate' complies with the alsa control naming scheme */
3130 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3131 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3132 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3133 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3134 HDSP_PASSTHRU("Passthru", 0),
3135 HDSP_LINE_OUT("Line Out", 0),
3136 };
3137
3138 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3139 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3140
3141 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3142 {
3143         unsigned int idx;
3144         int err;
3145         snd_kcontrol_t *kctl;
3146
3147         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3148                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3149                         return err;
3150                 }
3151                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3152                         hdsp->spdif_ctl = kctl;
3153         }
3154
3155         /* ADAT SyncCheck status */
3156         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3157         snd_hdsp_adat_sync_check.index = 1;
3158         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3159                 return err;
3160         }
3161         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3162                 for (idx = 1; idx < 3; ++idx) {
3163                         snd_hdsp_adat_sync_check.index = idx+1;
3164                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3165                                 return err;
3166                         }
3167                 }
3168         }
3169
3170         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3171         if (hdsp->io_type == H9632) {
3172                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3173                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3174                                 return err;
3175                         }
3176                 }
3177         }
3178
3179         /* AEB control for H96xx card */
3180         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3181                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3182                                 return err;
3183                 }
3184         }
3185
3186         return 0;
3187 }
3188
3189 /*------------------------------------------------------------
3190    /proc interface
3191  ------------------------------------------------------------*/
3192
3193 static void
3194 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3195 {
3196         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3197         unsigned int status;
3198         unsigned int status2;
3199         char *pref_sync_ref;
3200         char *autosync_ref;
3201         char *system_clock_mode;
3202         char *clock_source;
3203         int x;
3204
3205         if (hdsp_check_for_iobox (hdsp)) {
3206                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3207                 return;
3208         }
3209
3210         if (hdsp_check_for_firmware(hdsp)) {
3211                 if (hdsp->state & HDSP_FirmwareCached) {
3212                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3213                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3214                                 return;
3215                         }
3216                 } else {
3217                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3218                         return;
3219                 }
3220         }
3221
3222         status = hdsp_read(hdsp, HDSP_statusRegister);
3223         status2 = hdsp_read(hdsp, HDSP_status2Register);
3224
3225         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3226         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3227                     hdsp->capture_buffer, hdsp->playback_buffer);
3228         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3229                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3230         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3231         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3232         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3233         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3234         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3235
3236         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3237         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3238         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3239         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3240
3241         snd_iprintf(buffer, "\n");
3242
3243         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3244
3245         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3246         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3247         snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3248         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3249
3250         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3251
3252         snd_iprintf(buffer, "\n");
3253
3254
3255         switch (hdsp_clock_source(hdsp)) {
3256         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3257                 clock_source = "AutoSync";
3258                 break;
3259         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3260                 clock_source = "Internal 32 kHz";
3261                 break;
3262         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3263                 clock_source = "Internal 44.1 kHz";
3264                 break;
3265         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3266                 clock_source = "Internal 48 kHz";
3267                 break;
3268         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3269                 clock_source = "Internal 64 kHz";
3270                 break;
3271         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3272                 clock_source = "Internal 88.2 kHz";
3273                 break;
3274         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3275                 clock_source = "Internal 96 kHz";
3276                 break;
3277         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3278                 clock_source = "Internal 128 kHz";
3279                 break;
3280         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3281                 clock_source = "Internal 176.4 kHz";
3282                 break;
3283                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3284                 clock_source = "Internal 192 kHz";
3285                 break;
3286         default:
3287                 clock_source = "Error";
3288         }
3289         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3290
3291         if (hdsp_system_clock_mode(hdsp)) {
3292                 system_clock_mode = "Slave";
3293         } else {
3294                 system_clock_mode = "Master";
3295         }
3296
3297         switch (hdsp_pref_sync_ref (hdsp)) {
3298         case HDSP_SYNC_FROM_WORD:
3299                 pref_sync_ref = "Word Clock";
3300                 break;
3301         case HDSP_SYNC_FROM_ADAT_SYNC:
3302                 pref_sync_ref = "ADAT Sync";
3303                 break;
3304         case HDSP_SYNC_FROM_SPDIF:
3305                 pref_sync_ref = "SPDIF";
3306                 break;
3307         case HDSP_SYNC_FROM_ADAT1:
3308                 pref_sync_ref = "ADAT1";
3309                 break;
3310         case HDSP_SYNC_FROM_ADAT2:
3311                 pref_sync_ref = "ADAT2";
3312                 break;
3313         case HDSP_SYNC_FROM_ADAT3:
3314                 pref_sync_ref = "ADAT3";
3315                 break;
3316         default:
3317                 pref_sync_ref = "Word Clock";
3318                 break;
3319         }
3320         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3321
3322         switch (hdsp_autosync_ref (hdsp)) {
3323         case HDSP_AUTOSYNC_FROM_WORD:
3324                 autosync_ref = "Word Clock";
3325                 break;
3326         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3327                 autosync_ref = "ADAT Sync";
3328                 break;
3329         case HDSP_AUTOSYNC_FROM_SPDIF:
3330                 autosync_ref = "SPDIF";
3331                 break;
3332         case HDSP_AUTOSYNC_FROM_NONE:
3333                 autosync_ref = "None";
3334                 break;
3335         case HDSP_AUTOSYNC_FROM_ADAT1:
3336                 autosync_ref = "ADAT1";
3337                 break;
3338         case HDSP_AUTOSYNC_FROM_ADAT2:
3339                 autosync_ref = "ADAT2";
3340                 break;
3341         case HDSP_AUTOSYNC_FROM_ADAT3:
3342                 autosync_ref = "ADAT3";
3343                 break;
3344         default:
3345                 autosync_ref = "---";
3346                 break;
3347         }
3348         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3349
3350         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3351
3352         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3353
3354         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3355
3356         snd_iprintf(buffer, "\n");
3357
3358         switch (hdsp_spdif_in(hdsp)) {
3359         case HDSP_SPDIFIN_OPTICAL:
3360                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3361                 break;
3362         case HDSP_SPDIFIN_COAXIAL:
3363                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3364                 break;
3365         case HDSP_SPDIFIN_INTERNAL:
3366                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3367                 break;
3368         case HDSP_SPDIFIN_AES:
3369                 snd_iprintf(buffer, "IEC958 input: AES\n");
3370                 break;
3371         default:
3372                 snd_iprintf(buffer, "IEC958 input: ???\n");
3373                 break;
3374         }
3375
3376         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3377                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3378         } else {
3379                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3380         }
3381
3382         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3383                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3384         } else {
3385                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3386         }
3387
3388         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3389                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3390         } else {
3391                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3392         }
3393
3394         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3395                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3396         } else {
3397                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3398         }
3399         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3400                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3401         } else {
3402                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3403         }
3404
3405         snd_iprintf(buffer, "\n");
3406
3407         /* Sync Check */
3408         x = status & HDSP_Sync0;
3409         if (status & HDSP_Lock0) {
3410                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3411         } else {
3412                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3413         }
3414
3415         switch (hdsp->io_type) {
3416         case Digiface:
3417         case H9652:
3418                 x = status & HDSP_Sync1;
3419                 if (status & HDSP_Lock1) {
3420                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3421                 } else {
3422                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3423                 }
3424                 x = status & HDSP_Sync2;
3425                 if (status & HDSP_Lock2) {
3426                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3427                 } else {
3428                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3429                 }
3430         default:
3431                 /* relax */
3432                 break;
3433         }
3434
3435         x = status & HDSP_SPDIFSync;
3436         if (status & HDSP_SPDIFErrorFlag) {
3437                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3438         } else {
3439                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3440         }
3441
3442         x = status2 & HDSP_wc_sync;
3443         if (status2 & HDSP_wc_lock) {
3444                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3445         } else {
3446                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3447         }
3448
3449         x = status & HDSP_TimecodeSync;
3450         if (status & HDSP_TimecodeLock) {
3451                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3452         } else {
3453                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3454         }
3455
3456         snd_iprintf(buffer, "\n");
3457
3458         /* Informations about H9632 specific controls */
3459         if (hdsp->io_type == H9632) {
3460                 char *tmp;
3461
3462                 switch (hdsp_ad_gain(hdsp)) {
3463                 case 0:
3464                         tmp = "-10 dBV";
3465                         break;
3466                 case 1:
3467                         tmp = "+4 dBu";
3468                         break;
3469                 default:
3470                         tmp = "Lo Gain";
3471                         break;
3472                 }
3473                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3474
3475                 switch (hdsp_da_gain(hdsp)) {
3476                 case 0:
3477                         tmp = "Hi Gain";
3478                         break;
3479                 case 1:
3480                         tmp = "+4 dBu";
3481                         break;
3482                 default:
3483                         tmp = "-10 dBV";
3484                         break;
3485                 }
3486                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3487
3488                 switch (hdsp_phone_gain(hdsp)) {
3489                 case 0:
3490                         tmp = "0 dB";
3491                         break;
3492                 case 1:
3493                         tmp = "-6 dB";
3494                         break;
3495                 default:
3496                         tmp = "-12 dB";
3497                         break;
3498                 }
3499                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3500
3501                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3502
3503                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3504                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3505                 } else {
3506                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3507                 }
3508                 snd_iprintf(buffer, "\n");
3509         }
3510
3511 }
3512
3513 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3514 {
3515         snd_info_entry_t *entry;
3516
3517         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3518                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3519 }
3520
3521 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3522 {
3523         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3524         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3525 }
3526
3527 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3528 {
3529         unsigned long pb_bus, cb_bus;
3530
3531         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3532             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3533                 if (hdsp->capture_dma_buf.area)
3534                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3535                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3536                 return -ENOMEM;
3537         }
3538
3539         /* Align to bus-space 64K boundary */
3540
3541         cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3542         pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3543
3544         /* Tell the card where it is */
3545
3546         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3547         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3548
3549         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3550         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3551
3552         return 0;
3553 }
3554
3555 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3556 {
3557         unsigned int i;
3558
3559         /* ASSUMPTION: hdsp->lock is either held, or
3560            there is no need to hold it (e.g. during module
3561            initalization).
3562          */
3563
3564         /* set defaults:
3565
3566            SPDIF Input via Coax
3567            Master clock mode
3568            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3569                             which implies 2 4096 sample, 32Kbyte periods).
3570            Enable line out.
3571          */
3572
3573         hdsp->control_register = HDSP_ClockModeMaster |
3574                                  HDSP_SPDIFInputCoaxial |
3575                                  hdsp_encode_latency(7) |
3576                                  HDSP_LineOut;
3577
3578
3579         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3580
3581 #ifdef SNDRV_BIG_ENDIAN
3582         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3583 #else
3584         hdsp->control2_register = 0;
3585 #endif
3586         if (hdsp->io_type == H9652) {
3587                 snd_hdsp_9652_enable_mixer (hdsp);
3588         } else {
3589             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3590         }
3591
3592         hdsp_reset_hw_pointer(hdsp);
3593         hdsp_compute_period_size(hdsp);
3594
3595         /* silence everything */
3596
3597         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3598                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3599         }
3600
3601         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3602                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3603                         return -EIO;
3604                 }
3605         }
3606
3607         if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3608
3609                 int lineouts_base;
3610
3611                 snd_printk ("sending all inputs and playback streams to line outs.\n");
3612
3613                 /* route all inputs to the line outs for easy monitoring. send
3614                    odd numbered channels to right, even to left.
3615                 */
3616                 if (hdsp->io_type == H9632) {
3617                         /* this is the phones/analog output */
3618                         lineouts_base = 10;
3619                 } else {
3620                         lineouts_base = 26;
3621                 }
3622
3623                 for (i = 0; i < hdsp->max_channels; i++) {
3624                         if (i & 1) {
3625                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3626                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3627                                     return -EIO;
3628                                 }
3629                         } else {
3630                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3631                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3632
3633                                     return -EIO;
3634                                 }
3635                         }
3636                 }
3637         }
3638
3639         hdsp->passthru = 0;
3640
3641         /* H9632 specific defaults */
3642         if (hdsp->io_type == H9632) {
3643                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3644                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3645         }
3646
3647         /* set a default rate so that the channel map is set up.
3648          */
3649
3650         hdsp_set_rate(hdsp, 48000, 1);
3651
3652         return 0;
3653 }
3654
3655 void hdsp_midi_tasklet(unsigned long arg)
3656 {
3657         hdsp_t *hdsp = (hdsp_t *)arg;
3658
3659         if (hdsp->midi[0].pending) {
3660                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3661         }
3662         if (hdsp->midi[1].pending) {
3663                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3664         }
3665 }
3666
3667 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3668 {
3669         hdsp_t *hdsp = (hdsp_t *) dev_id;
3670         unsigned int status;
3671         int audio;
3672         int midi0;
3673         int midi1;
3674         unsigned int midi0status;
3675         unsigned int midi1status;
3676         int schedule = 0;
3677
3678         status = hdsp_read(hdsp, HDSP_statusRegister);
3679
3680         audio = status & HDSP_audioIRQPending;
3681         midi0 = status & HDSP_midi0IRQPending;
3682         midi1 = status & HDSP_midi1IRQPending;
3683
3684         if (!audio && !midi0 && !midi1) {
3685                 return IRQ_NONE;
3686         }
3687
3688         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3689
3690         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3691         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3692
3693         if (audio) {
3694                 if (hdsp->capture_substream) {
3695                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3696                 }
3697
3698                 if (hdsp->playback_substream) {
3699                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3700                 }
3701         }
3702
3703         if (midi0 && midi0status) {
3704                 /* we disable interrupts for this input until processing is done */
3705                 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3706                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3707                 hdsp->midi[0].pending = 1;
3708                 schedule = 1;
3709         }
3710         if (midi1 && midi1status) {
3711                 /* we disable interrupts for this input until processing is done */
3712                 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3713                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3714                 hdsp->midi[1].pending = 1;
3715                 schedule = 1;
3716         }
3717         if (schedule)
3718             tasklet_hi_schedule(&hdsp->midi_tasklet);
3719         return IRQ_HANDLED;
3720 }
3721
3722 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3723 {
3724         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3725         return hdsp_hw_pointer(hdsp);
3726 }
3727
3728 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3729                                              int stream,
3730                                              int channel)
3731
3732 {
3733         int mapped_channel;
3734
3735         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3736
3737         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3738                 return NULL;
3739         }
3740
3741         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3742                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3743         } else {
3744                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3745         }
3746 }
3747
3748 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3749                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3750 {
3751         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3752         char *channel_buf;
3753
3754         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3755
3756         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3757         snd_assert(channel_buf != NULL, return -EIO);
3758         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3759                 return -EFAULT;
3760         return count;
3761 }
3762
3763 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3764                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3765 {
3766         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3767         char *channel_buf;
3768
3769         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3770
3771         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3772         snd_assert(channel_buf != NULL, return -EIO);
3773         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3774                 return -EFAULT;
3775         return count;
3776 }
3777
3778 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3779                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3780 {
3781         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3782         char *channel_buf;
3783
3784         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3785         snd_assert(channel_buf != NULL, return -EIO);
3786         memset(channel_buf + pos * 4, 0, count * 4);
3787         return count;
3788 }
3789
3790 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3791 {
3792         snd_pcm_runtime_t *runtime = substream->runtime;
3793         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3794         snd_pcm_substream_t *other;
3795         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3796                 other = hdsp->capture_substream;
3797         else
3798                 other = hdsp->playback_substream;
3799         if (hdsp->running)
3800                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3801         else
3802                 runtime->status->hw_ptr = 0;
3803         if (other) {
3804                 struct list_head *pos;
3805                 snd_pcm_substream_t *s;
3806                 snd_pcm_runtime_t *oruntime = other->runtime;
3807                 snd_pcm_group_for_each(pos, substream) {
3808                         s = snd_pcm_group_substream_entry(pos);
3809                         if (s == other) {
3810                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3811                                 break;
3812                         }
3813                 }
3814         }
3815         return 0;
3816 }
3817
3818 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3819                                  snd_pcm_hw_params_t *params)
3820 {
3821         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3822         int err;
3823         pid_t this_pid;
3824         pid_t other_pid;
3825
3826         if (hdsp_check_for_iobox (hdsp)) {
3827                 return -EIO;
3828         }
3829
3830         if (hdsp_check_for_firmware(hdsp)) {
3831                 if (hdsp->state & HDSP_FirmwareCached) {
3832                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3833                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3834                         }
3835                 } else {
3836                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3837                 }
3838                 return -EIO;
3839         }
3840
3841         spin_lock_irq(&hdsp->lock);
3842
3843         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3844                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3845                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3846                 this_pid = hdsp->playback_pid;
3847                 other_pid = hdsp->capture_pid;
3848         } else {
3849                 this_pid = hdsp->capture_pid;
3850                 other_pid = hdsp->playback_pid;
3851         }
3852
3853         if ((other_pid > 0) && (this_pid != other_pid)) {
3854
3855                 /* The other stream is open, and not by the same
3856                    task as this one. Make sure that the parameters
3857                    that matter are the same.
3858                  */
3859
3860                 if (params_rate(params) != hdsp->system_sample_rate) {
3861                         spin_unlock_irq(&hdsp->lock);
3862                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3863                         return -EBUSY;
3864                 }
3865
3866                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3867                         spin_unlock_irq(&hdsp->lock);
3868                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3869                         return -EBUSY;
3870                 }
3871
3872                 /* We're fine. */
3873
3874                 spin_unlock_irq(&hdsp->lock);
3875                 return 0;
3876
3877         } else {
3878                 spin_unlock_irq(&hdsp->lock);
3879         }
3880
3881         /* how to make sure that the rate matches an externally-set one ?
3882          */
3883
3884         spin_lock_irq(&hdsp->lock);
3885         if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3886                 spin_unlock_irq(&hdsp->lock);
3887                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3888                 return err;
3889         } else {
3890                 spin_unlock_irq(&hdsp->lock);
3891         }
3892
3893         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3894                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3895                 return err;
3896         }
3897
3898         return 0;
3899 }
3900
3901 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3902                                     snd_pcm_channel_info_t *info)
3903 {
3904         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3905         int mapped_channel;
3906
3907         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3908
3909         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3910                 return -EINVAL;
3911         }
3912
3913         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3914         info->first = 0;
3915         info->step = 32;
3916         return 0;
3917 }
3918
3919 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3920                              unsigned int cmd, void *arg)
3921 {
3922         switch (cmd) {
3923         case SNDRV_PCM_IOCTL1_RESET:
3924         {
3925                 return snd_hdsp_reset(substream);
3926         }
3927         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3928         {
3929                 snd_pcm_channel_info_t *info = arg;
3930                 return snd_hdsp_channel_info(substream, info);
3931         }
3932         default:
3933                 break;
3934         }
3935
3936         return snd_pcm_lib_ioctl(substream, cmd, arg);
3937 }
3938
3939 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3940 {
3941         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3942         snd_pcm_substream_t *other;
3943         int running;
3944
3945         if (hdsp_check_for_iobox (hdsp)) {
3946                 return -EIO;
3947         }
3948
3949         if (hdsp_check_for_firmware(hdsp)) {
3950                 if (hdsp->state & HDSP_FirmwareCached) {
3951                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3952                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3953                         }
3954                 } else {
3955                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3956                 }
3957                 return -EIO;
3958         }
3959
3960         spin_lock(&hdsp->lock);
3961         running = hdsp->running;
3962         switch (cmd) {
3963         case SNDRV_PCM_TRIGGER_START:
3964                 running |= 1 << substream->stream;
3965                 break;
3966         case SNDRV_PCM_TRIGGER_STOP:
3967                 running &= ~(1 << substream->stream);
3968                 break;
3969         default:
3970                 snd_BUG();
3971                 spin_unlock(&hdsp->lock);
3972                 return -EINVAL;
3973         }
3974         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3975                 other = hdsp->capture_substream;
3976         else
3977                 other = hdsp->playback_substream;
3978
3979         if (other) {
3980                 struct list_head *pos;
3981                 snd_pcm_substream_t *s;
3982                 snd_pcm_group_for_each(pos, substream) {
3983                         s = snd_pcm_group_substream_entry(pos);
3984                         if (s == other) {
3985                                 snd_pcm_trigger_done(s, substream);
3986                                 if (cmd == SNDRV_PCM_TRIGGER_START)
3987                                         running |= 1 << s->stream;
3988                                 else
3989                                         running &= ~(1 << s->stream);
3990                                 goto _ok;
3991                         }
3992                 }
3993                 if (cmd == SNDRV_PCM_TRIGGER_START) {
3994                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3995                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3996                                 hdsp_silence_playback(hdsp);
3997                 } else {
3998                         if (running &&
3999                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4000                                 hdsp_silence_playback(hdsp);
4001                 }
4002         } else {
4003                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4004                                 hdsp_silence_playback(hdsp);
4005         }
4006  _ok:
4007         snd_pcm_trigger_done(substream, substream);
4008         if (!hdsp->running && running)
4009                 hdsp_start_audio(hdsp);
4010         else if (hdsp->running && !running)
4011                 hdsp_stop_audio(hdsp);
4012         hdsp->running = running;
4013         spin_unlock(&hdsp->lock);
4014
4015         return 0;
4016 }
4017
4018 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4019 {
4020         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4021         int result = 0;
4022
4023         if (hdsp_check_for_iobox (hdsp)) {
4024                 return -EIO;
4025         }
4026
4027         if (hdsp_check_for_firmware(hdsp)) {
4028                 if (hdsp->state & HDSP_FirmwareCached) {
4029                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4030                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4031                         }
4032                 } else {
4033                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4034                 }
4035                 return -EIO;
4036         }
4037
4038         spin_lock_irq(&hdsp->lock);
4039         if (!hdsp->running)
4040                 hdsp_reset_hw_pointer(hdsp);
4041         spin_unlock_irq(&hdsp->lock);
4042         return result;
4043 }
4044
4045 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4046 {
4047         .info =                 (SNDRV_PCM_INFO_MMAP |
4048                                  SNDRV_PCM_INFO_MMAP_VALID |
4049                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4050                                  SNDRV_PCM_INFO_SYNC_START |
4051                                  SNDRV_PCM_INFO_DOUBLE),
4052         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4053         .rates =                (SNDRV_PCM_RATE_32000 |
4054                                  SNDRV_PCM_RATE_44100 |
4055                                  SNDRV_PCM_RATE_48000 |
4056                                  SNDRV_PCM_RATE_64000 |
4057                                  SNDRV_PCM_RATE_88200 |
4058                                  SNDRV_PCM_RATE_96000),
4059         .rate_min =             32000,
4060         .rate_max =             96000,
4061         .channels_min =         14,
4062         .channels_max =         HDSP_MAX_CHANNELS,
4063         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4064         .period_bytes_min =     (64 * 4) * 10,
4065         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4066         .periods_min =          2,
4067         .periods_max =          2,
4068         .fifo_size =            0
4069 };
4070
4071 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4072 {
4073         .info =                 (SNDRV_PCM_INFO_MMAP |
4074                                  SNDRV_PCM_INFO_MMAP_VALID |
4075                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4076                                  SNDRV_PCM_INFO_SYNC_START),
4077         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4078         .rates =                (SNDRV_PCM_RATE_32000 |
4079                                  SNDRV_PCM_RATE_44100 |
4080                                  SNDRV_PCM_RATE_48000 |
4081                                  SNDRV_PCM_RATE_64000 |
4082                                  SNDRV_PCM_RATE_88200 |
4083                                  SNDRV_PCM_RATE_96000),
4084         .rate_min =             32000,
4085         .rate_max =             96000,
4086         .channels_min =         14,
4087         .channels_max =         HDSP_MAX_CHANNELS,
4088         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4089         .period_bytes_min =     (64 * 4) * 10,
4090         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4091         .periods_min =          2,
4092         .periods_max =          2,
4093         .fifo_size =            0
4094 };
4095
4096 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4097
4098 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4099         .count = ARRAY_SIZE(hdsp_period_sizes),
4100         .list = hdsp_period_sizes,
4101         .mask = 0
4102 };
4103
4104 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4105
4106 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4107         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4108         .list = hdsp_9632_sample_rates,
4109         .mask = 0
4110 };
4111
4112 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4113                                         snd_pcm_hw_rule_t *rule)
4114 {
4115         hdsp_t *hdsp = rule->private;
4116         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4117         if (hdsp->io_type == H9632) {
4118                 unsigned int list[3];
4119                 list[0] = hdsp->qs_in_channels;
4120                 list[1] = hdsp->ds_in_channels;
4121                 list[2] = hdsp->ss_in_channels;
4122                 return snd_interval_list(c, 3, list, 0);
4123         } else {
4124                 unsigned int list[2];
4125                 list[0] = hdsp->ds_in_channels;
4126                 list[1] = hdsp->ss_in_channels;
4127                 return snd_interval_list(c, 2, list, 0);
4128         }
4129 }
4130
4131 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4132                                         snd_pcm_hw_rule_t *rule)
4133 {
4134         unsigned int list[3];
4135         hdsp_t *hdsp = rule->private;
4136         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4137         if (hdsp->io_type == H9632) {
4138                 list[0] = hdsp->qs_out_channels;
4139                 list[1] = hdsp->ds_out_channels;
4140                 list[2] = hdsp->ss_out_channels;
4141                 return snd_interval_list(c, 3, list, 0);
4142         } else {
4143                 list[0] = hdsp->ds_out_channels;
4144                 list[1] = hdsp->ss_out_channels;
4145         }
4146         return snd_interval_list(c, 2, list, 0);
4147 }
4148
4149 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4150                                              snd_pcm_hw_rule_t *rule)
4151 {
4152         hdsp_t *hdsp = rule->private;
4153         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4154         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4155         if (r->min > 96000 && hdsp->io_type == H9632) {
4156                 snd_interval_t t = {
4157                         .min = hdsp->qs_in_channels,
4158                         .max = hdsp->qs_in_channels,
4159                         .integer = 1,
4160                 };
4161                 return snd_interval_refine(c, &t);
4162         } else if (r->min > 48000 && r->max <= 96000) {
4163                 snd_interval_t t = {
4164                         .min = hdsp->ds_in_channels,
4165                         .max = hdsp->ds_in_channels,
4166                         .integer = 1,
4167                 };
4168                 return snd_interval_refine(c, &t);
4169         } else if (r->max < 64000) {
4170                 snd_interval_t t = {
4171                         .min = hdsp->ss_in_channels,
4172                         .max = hdsp->ss_in_channels,
4173                         .integer = 1,
4174                 };
4175                 return snd_interval_refine(c, &t);
4176         }
4177         return 0;
4178 }
4179
4180 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4181                                              snd_pcm_hw_rule_t *rule)
4182 {
4183         hdsp_t *hdsp = rule->private;
4184         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4185         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4186         if (r->min > 96000 && hdsp->io_type == H9632) {
4187                 snd_interval_t t = {
4188                         .min = hdsp->qs_out_channels,
4189                         .max = hdsp->qs_out_channels,
4190                         .integer = 1,
4191                 };
4192                 return snd_interval_refine(c, &t);
4193         } else if (r->min > 48000 && r->max <= 96000) {
4194                 snd_interval_t t = {
4195                         .min = hdsp->ds_out_channels,
4196                         .max = hdsp->ds_out_channels,
4197                         .integer = 1,
4198                 };
4199                 return snd_interval_refine(c, &t);
4200         } else if (r->max < 64000) {
4201                 snd_interval_t t = {
4202                         .min = hdsp->ss_out_channels,
4203                         .max = hdsp->ss_out_channels,
4204                         .integer = 1,
4205                 };
4206                 return snd_interval_refine(c, &t);
4207         }
4208         return 0;
4209 }
4210
4211 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4212                                              snd_pcm_hw_rule_t *rule)
4213 {
4214         hdsp_t *hdsp = rule->private;
4215         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4216         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4217         if (c->min >= hdsp->ss_out_channels) {
4218                 snd_interval_t t = {
4219                         .min = 32000,
4220                         .max = 48000,
4221                         .integer = 1,
4222                 };
4223                 return snd_interval_refine(r, &t);
4224         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4225                 snd_interval_t t = {
4226                         .min = 128000,
4227                         .max = 192000,
4228                         .integer = 1,
4229                 };
4230                 return snd_interval_refine(r, &t);
4231         } else if (c->max <= hdsp->ds_out_channels) {
4232                 snd_interval_t t = {
4233                         .min = 64000,
4234                         .max = 96000,
4235                         .integer = 1,
4236                 };
4237                 return snd_interval_refine(r, &t);
4238         }
4239         return 0;
4240 }
4241
4242 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4243                                              snd_pcm_hw_rule_t *rule)
4244 {
4245         hdsp_t *hdsp = rule->private;
4246         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4247         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4248         if (c->min >= hdsp->ss_in_channels) {
4249                 snd_interval_t t = {
4250                         .min = 32000,
4251                         .max = 48000,
4252                         .integer = 1,
4253                 };
4254                 return snd_interval_refine(r, &t);
4255         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4256                 snd_interval_t t = {
4257                         .min = 128000,
4258                         .max = 192000,
4259                         .integer = 1,
4260                 };
4261                 return snd_interval_refine(r, &t);
4262         } else if (c->max <= hdsp->ds_in_channels) {
4263                 snd_interval_t t = {
4264                         .min = 64000,
4265                         .max = 96000,
4266                         .integer = 1,
4267                 };
4268                 return snd_interval_refine(r, &t);
4269         }
4270         return 0;
4271 }
4272
4273 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4274 {
4275         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4276         snd_pcm_runtime_t *runtime = substream->runtime;
4277
4278         if (hdsp_check_for_iobox (hdsp)) {
4279                 return -EIO;
4280         }
4281
4282         if (hdsp_check_for_firmware(hdsp)) {
4283                 if (hdsp->state & HDSP_FirmwareCached) {
4284                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4285                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4286                         }
4287                 } else {
4288                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4289                 }
4290                 return -EIO;
4291         }
4292
4293         spin_lock_irq(&hdsp->lock);
4294
4295         snd_pcm_set_sync(substream);
4296
4297         runtime->hw = snd_hdsp_playback_subinfo;
4298         runtime->dma_area = hdsp->playback_buffer;
4299         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4300
4301         if (hdsp->capture_substream == NULL) {
4302                 hdsp_stop_audio(hdsp);
4303                 hdsp_set_thru(hdsp, -1, 0);
4304         }
4305
4306         hdsp->playback_pid = current->pid;
4307         hdsp->playback_substream = substream;
4308
4309         spin_unlock_irq(&hdsp->lock);
4310
4311         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4312         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4313         if (hdsp->io_type == H9632) {
4314                 runtime->hw.channels_min = hdsp->qs_out_channels;
4315                 runtime->hw.channels_max = hdsp->ss_out_channels;
4316                 runtime->hw.rate_max = 192000;
4317                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4318                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4319         }
4320
4321         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4322                              snd_hdsp_hw_rule_out_channels, hdsp,
4323                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4324         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4325                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4326                              SNDRV_PCM_HW_PARAM_RATE, -1);
4327         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4328                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4329                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4330
4331         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4332         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4333         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4334                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4335         return 0;
4336 }
4337
4338 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4339 {
4340         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4341
4342         spin_lock_irq(&hdsp->lock);
4343
4344         hdsp->playback_pid = -1;
4345         hdsp->playback_substream = NULL;
4346
4347         spin_unlock_irq(&hdsp->lock);
4348
4349         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4350         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4351                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4352         return 0;
4353 }
4354
4355
4356 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4357 {
4358         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4359         snd_pcm_runtime_t *runtime = substream->runtime;
4360
4361         if (hdsp_check_for_iobox (hdsp)) {
4362                 return -EIO;
4363         }
4364
4365         if (hdsp_check_for_firmware(hdsp)) {
4366                 if (hdsp->state & HDSP_FirmwareCached) {
4367                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4368                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4369                         }
4370                 } else {
4371                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4372                 }
4373                 return -EIO;
4374         }
4375
4376         spin_lock_irq(&hdsp->lock);
4377
4378         snd_pcm_set_sync(substream);
4379
4380         runtime->hw = snd_hdsp_capture_subinfo;
4381         runtime->dma_area = hdsp->capture_buffer;
4382         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4383
4384         if (hdsp->playback_substream == NULL) {
4385                 hdsp_stop_audio(hdsp);
4386                 hdsp_set_thru(hdsp, -1, 0);
4387         }
4388
4389         hdsp->capture_pid = current->pid;
4390         hdsp->capture_substream = substream;
4391
4392         spin_unlock_irq(&hdsp->lock);
4393
4394         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4395         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4396         if (hdsp->io_type == H9632) {
4397                 runtime->hw.channels_min = hdsp->qs_in_channels;
4398                 runtime->hw.channels_max = hdsp->ss_in_channels;
4399                 runtime->hw.rate_max = 192000;
4400                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4401                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4402         }
4403         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4404                              snd_hdsp_hw_rule_in_channels, hdsp,
4405                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4406         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4407                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4408                              SNDRV_PCM_HW_PARAM_RATE, -1);
4409         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4410                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4411                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4412         return 0;
4413 }
4414
4415 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4416 {
4417         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4418
4419         spin_lock_irq(&hdsp->lock);
4420
4421         hdsp->capture_pid = -1;
4422         hdsp->capture_substream = NULL;
4423
4424         spin_unlock_irq(&hdsp->lock);
4425         return 0;
4426 }
4427
4428 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4429 {
4430         /* we have nothing to initialize but the call is required */
4431         return 0;
4432 }
4433
4434
4435 /* helper functions for copying meter values */
4436 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4437 {
4438         u32 val = readl(src);
4439         return copy_to_user(dest, &val, 4);
4440 }
4441
4442 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4443 {
4444         u32 rms_low, rms_high;
4445         u64 rms;
4446         rms_low = readl(src_low);
4447         rms_high = readl(src_high);
4448         rms = ((u64)rms_high << 32) | rms_low;
4449         return copy_to_user(dest, &rms, 8);
4450 }
4451
4452 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4453 {
4454         u32 rms_low, rms_high;
4455         u64 rms;
4456         rms_low = readl(src_low) & 0xffffff00;
4457         rms_high = readl(src_high) & 0xffffff00;
4458         rms = ((u64)rms_high << 32) | rms_low;
4459         return copy_to_user(dest, &rms, 8);
4460 }
4461
4462 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4463 {
4464         int doublespeed = 0;
4465         int i, j, channels, ofs;
4466
4467         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4468                 doublespeed = 1;
4469         channels = doublespeed ? 14 : 26;
4470         for (i = 0, j = 0; i < 26; ++i) {
4471                 if (doublespeed && (i & 4))
4472                         continue;
4473                 ofs = HDSP_9652_peakBase - j * 4;
4474                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4475                         return -EFAULT;
4476                 ofs -= channels * 4;
4477                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4478                         return -EFAULT;
4479                 ofs -= channels * 4;
4480                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4481                         return -EFAULT;
4482                 ofs = HDSP_9652_rmsBase + j * 8;
4483                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4484                                 hdsp->iobase + ofs + 4))
4485                         return -EFAULT;
4486                 ofs += channels * 8;
4487                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4488                                 hdsp->iobase + ofs + 4))
4489                         return -EFAULT;
4490                 ofs += channels * 8;
4491                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4492                                 hdsp->iobase + ofs + 4))
4493                         return -EFAULT;
4494                 j++;
4495         }
4496         return 0;
4497 }
4498
4499 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4500 {
4501         int i, j;
4502         hdsp_9632_meters_t __iomem *m;
4503         int doublespeed = 0;
4504
4505         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4506                 doublespeed = 1;
4507         m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4508         for (i = 0, j = 0; i < 16; ++i, ++j) {
4509                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4510                         return -EFAULT;
4511                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4512                         return -EFAULT;
4513                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4514                         return -EFAULT;
4515                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4516                                 &m->input_rms_high[j]))
4517                         return -EFAULT;
4518                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4519                                 &m->playback_rms_high[j]))
4520                         return -EFAULT;
4521                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4522                                 &m->output_rms_high[j]))
4523                         return -EFAULT;
4524                 if (doublespeed && i == 3) i += 4;
4525         }
4526         return 0;
4527 }
4528
4529 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4530 {
4531         int i;
4532
4533         for (i = 0; i < 26; i++) {
4534                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4535                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4536                         return -EFAULT;
4537                 if (copy_u32_le(&peak_rms->input_peaks[i],
4538                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4539                         return -EFAULT;
4540         }
4541         for (i = 0; i < 28; i++) {
4542                 if (copy_u32_le(&peak_rms->output_peaks[i],
4543                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4544                         return -EFAULT;
4545         }
4546         for (i = 0; i < 26; ++i) {
4547                 if (copy_u64_le(&peak_rms->playback_rms[i],
4548                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8,
4549                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4))
4550                         return -EFAULT;
4551                 if (copy_u64_le(&peak_rms->input_rms[i],
4552                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8,
4553                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4))
4554                         return -EFAULT;
4555         }
4556         return 0;
4557 }
4558
4559 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4560 {
4561         hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4562         void __user *argp = (void __user *)arg;
4563
4564         switch (cmd) {
4565         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4566                 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4567
4568                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4569                         snd_printk(KERN_ERR "firmware needs to be uploaded to the card.\n");
4570                         return -EINVAL;
4571                 }
4572
4573                 switch (hdsp->io_type) {
4574                 case H9652:
4575                         return hdsp_9652_get_peak(hdsp, peak_rms);
4576                 case H9632:
4577                         return hdsp_9632_get_peak(hdsp, peak_rms);
4578                 default:
4579                         return hdsp_get_peak(hdsp, peak_rms);
4580                 }
4581         }
4582         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4583                 hdsp_config_info_t info;
4584                 unsigned long flags;
4585                 int i;
4586
4587                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4588                         snd_printk("Firmware needs to be uploaded to the card.\n");
4589                         return -EINVAL;
4590                 }
4591                 spin_lock_irqsave(&hdsp->lock, flags);
4592                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4593                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4594                 if (hdsp->io_type != H9632) {
4595                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4596                 }
4597                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4598                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4599                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4600                 }
4601                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4602                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4603                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4604                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4605                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4606                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4607                 info.system_sample_rate = hdsp->system_sample_rate;
4608                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4609                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4610                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4611                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4612                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4613                 info.passthru = (unsigned char)hdsp->passthru;
4614                 if (hdsp->io_type == H9632) {
4615                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4616                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4617                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4618                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4619
4620                 }
4621                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4622                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4623                 }
4624                 spin_unlock_irqrestore(&hdsp->lock, flags);
4625                 if (copy_to_user(argp, &info, sizeof(info)))
4626                         return -EFAULT;
4627                 break;
4628         }
4629         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4630                 hdsp_9632_aeb_t h9632_aeb;
4631
4632                 if (hdsp->io_type != H9632) return -EINVAL;
4633                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4634                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4635                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4636                         return -EFAULT;
4637                 break;
4638         }
4639         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4640                 hdsp_version_t hdsp_version;
4641                 int err;
4642
4643                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4644                 if (hdsp->io_type == Undefined) {
4645                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4646                                 return err;
4647                         }
4648                 }
4649                 hdsp_version.io_type = hdsp->io_type;
4650                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4651                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4652                         return -EFAULT;
4653                 }
4654                 break;
4655         }
4656         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4657                 hdsp_firmware_t __user *firmware;
4658                 u32 __user *firmware_data;
4659                 int err;
4660
4661                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4662                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4663                 if (hdsp->io_type == Undefined) return -EINVAL;
4664
4665                 snd_printk("initializing firmware upload\n");
4666                 firmware = (hdsp_firmware_t __user *)argp;
4667
4668                 if (get_user(firmware_data, &firmware->firmware_data)) {
4669                         return -EFAULT;
4670                 }
4671
4672                 if (hdsp_check_for_iobox (hdsp)) {
4673                         return -EIO;
4674                 }
4675
4676                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4677                         return -EFAULT;
4678                 }
4679
4680                 hdsp->state |= HDSP_FirmwareCached;
4681
4682                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4683                         return err;
4684                 }
4685
4686                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4687                         snd_hdsp_initialize_channels(hdsp);
4688
4689                         snd_hdsp_initialize_midi_flush(hdsp);
4690
4691                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4692                                 snd_printk("error creating alsa devices\n");
4693                             return err;
4694                         }
4695                 }
4696                 break;
4697         }
4698         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4699                 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4700                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4701                         return -EFAULT;
4702                 break;
4703         }
4704         default:
4705                 return -EINVAL;
4706         }
4707         return 0;
4708 }
4709
4710 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4711         .open =         snd_hdsp_playback_open,
4712         .close =        snd_hdsp_playback_release,
4713         .ioctl =        snd_hdsp_ioctl,
4714         .hw_params =    snd_hdsp_hw_params,
4715         .prepare =      snd_hdsp_prepare,
4716         .trigger =      snd_hdsp_trigger,
4717         .pointer =      snd_hdsp_hw_pointer,
4718         .copy =         snd_hdsp_playback_copy,
4719         .silence =      snd_hdsp_hw_silence,
4720 };
4721
4722 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4723         .open =         snd_hdsp_capture_open,
4724         .close =        snd_hdsp_capture_release,
4725         .ioctl =        snd_hdsp_ioctl,
4726         .hw_params =    snd_hdsp_hw_params,
4727         .prepare =      snd_hdsp_prepare,
4728         .trigger =      snd_hdsp_trigger,
4729         .pointer =      snd_hdsp_hw_pointer,
4730         .copy =         snd_hdsp_capture_copy,
4731 };
4732
4733 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4734                                            hdsp_t *hdsp)
4735 {
4736         snd_hwdep_t *hw;
4737         int err;
4738
4739         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4740                 return err;
4741
4742         hdsp->hwdep = hw;
4743         hw->private_data = hdsp;
4744         strcpy(hw->name, "HDSP hwdep interface");
4745
4746         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4747         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4748         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4749
4750         return 0;
4751 }
4752
4753 static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
4754                                          hdsp_t *hdsp)
4755 {
4756         snd_pcm_t *pcm;
4757         int err;
4758
4759         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4760                 return err;
4761
4762         hdsp->pcm = pcm;
4763         pcm->private_data = hdsp;
4764         strcpy(pcm->name, hdsp->card_name);
4765
4766         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4767         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4768
4769         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4770
4771         return 0;
4772 }
4773
4774 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4775 {
4776         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4777         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4778 }
4779
4780 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4781 {
4782         int i;
4783
4784         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4785                 return -EIO;
4786         }
4787
4788         for (i = 0; i < hdsp->max_channels; ++i) {
4789                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4790                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4791         }
4792
4793         return 0;
4794 }
4795
4796 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4797 {
4798         int status, aebi_channels, aebo_channels;
4799
4800         switch (hdsp->io_type) {
4801         case Digiface:
4802                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4803                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4804                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4805                 break;
4806
4807         case H9652:
4808                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4809                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4810                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4811                 break;
4812
4813         case H9632:
4814                 status = hdsp_read(hdsp, HDSP_statusRegister);
4815                 /* HDSP_AEBx bits are low when AEB are connected */
4816                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4817                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4818                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4819                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4820                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4821                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4822                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4823                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4824                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4825                 break;
4826
4827         case Multiface:
4828                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4829                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4830                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4831                 break;
4832
4833         default:
4834                 /* should never get here */
4835                 break;
4836         }
4837 }
4838
4839 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4840 {
4841         snd_hdsp_flush_midi_input (hdsp, 0);
4842         snd_hdsp_flush_midi_input (hdsp, 1);
4843 }
4844
4845 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4846 {
4847         int err;
4848
4849         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4850                 snd_printk("Error creating pcm interface\n");
4851                 return err;
4852         }
4853
4854
4855         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4856                 snd_printk("Error creating first midi interface\n");
4857                 return err;
4858         }
4859
4860
4861         if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4862                 snd_printk("Error creating second midi interface\n");
4863                 return err;
4864         }
4865
4866         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4867                 snd_printk("Error creating ctl interface\n");
4868                 return err;
4869         }
4870
4871         snd_hdsp_proc_init(hdsp);
4872
4873         hdsp->system_sample_rate = -1;
4874         hdsp->playback_pid = -1;
4875         hdsp->capture_pid = -1;
4876         hdsp->capture_substream = NULL;
4877         hdsp->playback_substream = NULL;
4878
4879         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4880                 snd_printk("Error setting default values\n");
4881                 return err;
4882         }
4883
4884         if (!(hdsp->state & HDSP_InitializationComplete)) {
4885                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4886                         hdsp->port, hdsp->irq);
4887
4888                 if ((err = snd_card_register(card)) < 0) {
4889                         snd_printk("error registering card\n");
4890                         return err;
4891                 }
4892                 hdsp->state |= HDSP_InitializationComplete;
4893         }
4894
4895         return 0;
4896 }
4897
4898 static int __devinit snd_hdsp_create(snd_card_t *card,
4899                                      hdsp_t *hdsp,
4900                                      int precise_ptr)
4901 {
4902         struct pci_dev *pci = hdsp->pci;
4903         int err;
4904         int is_9652 = 0;
4905         int is_9632 = 0;
4906
4907         hdsp->irq = -1;
4908         hdsp->state = 0;
4909         hdsp->midi[0].rmidi = NULL;
4910         hdsp->midi[1].rmidi = NULL;
4911         hdsp->midi[0].input = NULL;
4912         hdsp->midi[1].input = NULL;
4913         hdsp->midi[0].output = NULL;
4914         hdsp->midi[1].output = NULL;
4915         spin_lock_init(&hdsp->midi[0].lock);
4916         spin_lock_init(&hdsp->midi[1].lock);
4917         hdsp->iobase = NULL;
4918         hdsp->control_register = 0;
4919         hdsp->control2_register = 0;
4920         hdsp->io_type = Undefined;
4921         hdsp->max_channels = 26;
4922
4923         hdsp->card = card;
4924
4925         spin_lock_init(&hdsp->lock);
4926
4927         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4928
4929         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4930
4931         /* From Martin Bjoernsen :
4932             "It is important that the card's latency timer register in
4933             the PCI configuration space is set to a value much larger
4934             than 0 by the computer's BIOS or the driver.
4935             The windows driver always sets this 8 bit register [...]
4936             to its maximum 255 to avoid problems with some computers."
4937         */
4938         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4939
4940         strcpy(card->driver, "H-DSP");
4941         strcpy(card->mixername, "Xilinx FPGA");
4942
4943         switch (hdsp->firmware_rev & 0xff) {
4944         case 0xa:
4945         case 0xb:
4946         case 0x32:
4947                 hdsp->card_name = "RME Hammerfall DSP";
4948                 break;
4949
4950         case 0x64:
4951         case 0x65:
4952         case 0x68:
4953                 hdsp->card_name = "RME HDSP 9652";
4954                 is_9652 = 1;
4955                 break;
4956         case 0x96:
4957         case 0x97:
4958                 hdsp->card_name = "RME HDSP 9632";
4959                 hdsp->max_channels = 16;
4960                 is_9632 = 1;
4961                 break;
4962         default:
4963                 return -ENODEV;
4964         }
4965
4966         if ((err = pci_enable_device(pci)) < 0) {
4967                 return err;
4968         }
4969
4970         pci_set_master(hdsp->pci);
4971
4972         if ((err = pci_request_regions(pci, "hdsp")) < 0)
4973                 return err;
4974         hdsp->port = pci_resource_start(pci, 0);
4975         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
4976                 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
4977                 return -EBUSY;
4978         }
4979
4980         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
4981                 snd_printk("unable to use IRQ %d\n", pci->irq);
4982                 return -EBUSY;
4983         }
4984
4985         hdsp->irq = pci->irq;
4986         hdsp->precise_ptr = precise_ptr;
4987
4988         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
4989                 return err;
4990         }
4991
4992         if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
4993                 /* no iobox connected, we defer initialization */
4994                 snd_printk("card initialization pending : waiting for firmware\n");
4995                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
4996                         return err;
4997                 }
4998                 return 0;
4999         }
5000
5001         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5002                 return err;
5003         }
5004
5005         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5006                 snd_printk("card initialization pending : waiting for firmware\n");
5007                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5008                         return err;
5009                 }
5010                 return 0;
5011         }
5012
5013         snd_printk("Firmware already loaded, initializing card.\n");
5014
5015         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5016                 hdsp->io_type = Multiface;
5017         } else {
5018                 hdsp->io_type = Digiface;
5019         }
5020
5021         if (is_9652) {
5022                 hdsp->io_type = H9652;
5023         }
5024
5025         if (is_9632) {
5026                 hdsp->io_type = H9632;
5027         }
5028
5029         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5030                 return err;
5031         }
5032
5033         snd_hdsp_initialize_channels(hdsp);
5034         snd_hdsp_initialize_midi_flush(hdsp);
5035
5036         hdsp->state |= HDSP_FirmwareLoaded;
5037
5038         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5039                 return err;
5040         }
5041
5042         return 0;
5043 }
5044
5045 static int snd_hdsp_free(hdsp_t *hdsp)
5046 {
5047         if (hdsp->port) {
5048                 /* stop the audio, and cancel all interrupts */
5049                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5050                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5051         }
5052
5053         if (hdsp->irq >= 0)
5054                 free_irq(hdsp->irq, (void *)hdsp);
5055
5056         snd_hdsp_free_buffers(hdsp);
5057
5058         if (hdsp->iobase)
5059                 iounmap(hdsp->iobase);
5060
5061         if (hdsp->port)
5062                 pci_release_regions(hdsp->pci);
5063
5064         pci_disable_device(hdsp->pci);
5065         return 0;
5066 }
5067
5068 static void snd_hdsp_card_free(snd_card_t *card)
5069 {
5070         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5071
5072         if (hdsp)
5073                 snd_hdsp_free(hdsp);
5074 }
5075
5076 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5077                                     const struct pci_device_id *pci_id)
5078 {
5079         static int dev;
5080         hdsp_t *hdsp;
5081         snd_card_t *card;
5082         int err;
5083
5084         if (dev >= SNDRV_CARDS)
5085                 return -ENODEV;
5086         if (!enable[dev]) {
5087                 dev++;
5088                 return -ENOENT;
5089         }
5090
5091         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5092                 return -ENOMEM;
5093
5094         hdsp = (hdsp_t *) card->private_data;
5095         card->private_free = snd_hdsp_card_free;
5096         hdsp->dev = dev;
5097         hdsp->pci = pci;
5098         snd_card_set_dev(card, &pci->dev);
5099
5100         if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5101                 snd_card_free(card);
5102                 return err;
5103         }
5104
5105         strcpy(card->shortname, "Hammerfall DSP");
5106         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5107                 hdsp->port, hdsp->irq);
5108
5109         if ((err = snd_card_register(card)) < 0) {
5110                 snd_card_free(card);
5111                 return err;
5112         }
5113         pci_set_drvdata(pci, card);
5114         dev++;
5115         return 0;
5116 }
5117
5118 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5119 {
5120         snd_card_free(pci_get_drvdata(pci));
5121         pci_set_drvdata(pci, NULL);
5122 }
5123
5124 static struct pci_driver driver = {
5125         .name =     "RME Hammerfall DSP",
5126         .id_table = snd_hdsp_ids,
5127         .probe =    snd_hdsp_probe,
5128         .remove = __devexit_p(snd_hdsp_remove),
5129 };
5130
5131 static int __init alsa_card_hdsp_init(void)
5132 {
5133         return pci_module_init(&driver);
5134 }
5135
5136 static void __exit alsa_card_hdsp_exit(void)
5137 {
5138         pci_unregister_driver(&driver);
5139 }
5140
5141 module_init(alsa_card_hdsp_init)
5142 module_exit(alsa_card_hdsp_exit)