+The bit ordering for the alarm "realtime status register" and the
+"beep enable registers" are different.
+
+in0 (VCORE) : alarms: 0x000001 beep_enable: 0x000001
+in1 (VINR0) : alarms: 0x000002 beep_enable: 0x002000 <== mismatch
+in2 (+3.3VIN): alarms: 0x000004 beep_enable: 0x000004
+in3 (5VDD) : alarms: 0x000008 beep_enable: 0x000008
+in4 (+12VIN) : alarms: 0x000100 beep_enable: 0x000100
+in5 (-12VIN) : alarms: 0x000200 beep_enable: 0x000200
+in6 (-5VIN) : alarms: 0x000400 beep_enable: 0x000400
+in7 (VSB) : alarms: 0x080000 beep_enable: 0x010000 <== mismatch
+in8 (VBAT) : alarms: 0x100000 beep_enable: 0x020000 <== mismatch
+in9 (VINR1) : alarms: 0x004000 beep_enable: 0x004000
+temp1 : alarms: 0x000010 beep_enable: 0x000010
+temp2 : alarms: 0x000020 beep_enable: 0x000020
+temp3 : alarms: 0x002000 beep_enable: 0x000002 <== mismatch
+fan1 : alarms: 0x000040 beep_enable: 0x000040
+fan2 : alarms: 0x000080 beep_enable: 0x000080
+fan3 : alarms: 0x000800 beep_enable: 0x000800
+fan4 : alarms: 0x200000 beep_enable: 0x200000
+fan5 : alarms: 0x400000 beep_enable: 0x400000
+tart1 : alarms: 0x010000 beep_enable: 0x040000 <== mismatch
+tart2 : alarms: 0x020000 beep_enable: 0x080000 <== mismatch
+tart3 : alarms: 0x040000 beep_enable: 0x100000 <== mismatch
+case_open : alarms: 0x001000 beep_enable: 0x001000
+user_enable : alarms: -------- beep_enable: 0x800000
+
+*** NOTE: It is the responsibility of user-space code to handle the fact
+that the beep enable and alarm bits are in different positions when using that
+feature of the chip.