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linux 2.6.16.38 w/ vs2.0.3-rc1
[linux-2.6.git]
/
arch
/
arm
/
mach-omap1
/
clock.c
diff --git
a/arch/arm/mach-omap1/clock.c
b/arch/arm/mach-omap1/clock.c
index
f1958e8
..
75110ba
100644
(file)
--- a/
arch/arm/mach-omap1/clock.c
+++ b/
arch/arm/mach-omap1/clock.c
@@
-1,4
+1,3
@@
-//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
/*
* linux/arch/arm/mach-omap1/clock.c
*
/*
* linux/arch/arm/mach-omap1/clock.c
*
@@
-21,7
+20,6
@@
#include <asm/io.h>
#include <asm/io.h>
-#include <asm/arch/cpu.h>
#include <asm/arch/usb.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
#include <asm/arch/usb.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
@@
-272,12
+270,8
@@
static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
/*
* In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM.
/*
* In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM.
- * (on 730, bit 13 must always be 1)
*/
*/
- if (cpu_is_omap730())
- omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
- else
- omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+ omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
@@
-351,7
+345,7
@@
static unsigned calc_ext_dsor(unsigned long rate)
*/
for (dsor = 2; dsor < 96; ++dsor) {
if ((dsor & 1) && dsor > 8)
*/
for (dsor = 2; dsor < 96; ++dsor) {
if ((dsor & 1) && dsor > 8)
- continue;
+ continue;
if (rate >= 96000000 / dsor)
break;
}
if (rate >= 96000000 / dsor)
break;
}
@@
-693,11
+687,6
@@
int __init omap1_clk_init(void)
clk_register(*clkp);
continue;
}
clk_register(*clkp);
continue;
}
-
- if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
- clk_register(*clkp);
- continue;
- }
}
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
}
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
@@
-754,7
+743,7
@@
int __init omap1_clk_init(void)
printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL);
printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL);
- omap_writew(
cpu_is_omap730() ? 0x3005 :
0x1005, ARM_CKCTL);
+ omap_writew(0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1);
}
ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1);
}
@@
-767,17
+756,13
@@
int __init omap1_clk_init(void)
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-#if
defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
+#if
def CONFIG_MACH_OMAP_PERSEUS2
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
- /* (on 730, bit 13 must not be cleared) */
- if (cpu_is_omap730())
- omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
- else
- omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+ omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
/* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1);
/* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1);
@@
-799,7
+784,7
@@
int __init omap1_clk_init(void)
clk_enable(&armxor_ck.clk);
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
clk_enable(&armxor_ck.clk);
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
- if (cpu_is_omap15
xx
())
+ if (cpu_is_omap15
10
())
clk_enable(&arm_gpio_ck);
return 0;
clk_enable(&arm_gpio_ck);
return 0;