-#define GP_TIMER_TIDR 0x00
-#define GP_TIMER_TISR 0x18
-#define GP_TIMER_TIER 0x1c
-#define GP_TIMER_TCLR 0x24
-#define GP_TIMER_TCRR 0x28
-#define GP_TIMER_TLDR 0x2c
-#define GP_TIMER_TSICR 0x40
-
-#define OS_TIMER_NR 1 /* GP timer 2 */
-
-static unsigned long timer_base[] = {
- IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
- IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
- IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
- IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
-};
-
-static inline unsigned int timer_read_reg(int nr, unsigned int reg)
-{
- return __raw_readl(timer_base[nr] + reg);
-}
-
-static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
-{
- __raw_writel(val, timer_base[nr] + reg);
-}
-
-/* Note that we always enable the clock prescale divider bit */
-static inline void omap2_gp_timer_start(int nr, unsigned long load_val)