- clk_h.rate = s3c2410_hclk;
- clk_p.rate = s3c2410_pclk;
- clk_f.rate = s3c2410_fclk;
-
- /* set the enabled clocks to a minimal (known) state */
- __raw_writel(S3C2410_CLKCON_PWMT | S3C2410_CLKCON_UART0 | S3C2410_CLKCON_UART1 | S3C2410_CLKCON_UART2 | S3C2410_CLKCON_GPIO | S3C2410_CLKCON_RTC, S3C2410_CLKCON);
+ clk_h.rate = s3c24xx_hclk;
+ clk_p.rate = s3c24xx_pclk;
+ clk_f.rate = s3c24xx_fclk;
+
+ /* it looks like just setting the register here is not good
+ * enough, and causes the odd hang at initial boot time, so
+ * do all of them indivdually.
+ *
+ * I think disabling the LCD clock if the LCD is active is
+ * very dangerous, and therefore the bootloader should be
+ * careful to not enable the LCD clock if it is not needed.
+ *
+ * and of course, this looks neater
+ */
+
+ s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
+ s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
+ s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
+ s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
+ s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
+ s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
+
+ /* assume uart clocks are correctly setup */