- writel(0, VA_VIC_BASE + VIC_INT_SELECT);
- writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
- writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
- writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
- writel(0, VA_VIC_BASE + VIC_ITCR);
- writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
-
- /*
- * Make sure we clear all existing interrupts
- */
- writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
- for (i = 0; i < 19; i++) {
- value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
- writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
- }
-
- for (i = 0; i < 16; i++) {
- value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
- writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
- }
-
- writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
-
- for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
- if (i != IRQ_VICSOURCE31) {
- set_irq_chip(i, &vic_chip);
- set_irq_handler(i, do_level_IRQ);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
- }
-
- set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
- vic_unmask_irq(IRQ_VICSOURCE31);