- mov r10, #0
- mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D cache
- mcr p15, 0, r10, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, r10, c7, c15, 0 @ clean+invalidate cache
- mcr p15, 0, r10, c7, c10, 4 @ drain write buffer
- mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
- mcr p15, 0, r10, c2, c0, 2 @ TTB control register
- mcr p15, 0, r4, c2, c0, 0 @ load TTB0
+ mov r0, #0
+ mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
+ mcr p15, 0, r0, c2, c0, 2 @ TTB control register