- *(unsigned short *)GRA= H8300_TIMER_COUNT_DATA;
- *(unsigned short *)TCNT=0;
- ctrl_outb(0x23,TCR);
- ctrl_outb(0x00,TIOR);
- request_timer_irq(26,timer_int,0,"timer",0);
- ctrl_outb(inb(TIER) | 0x01,TIER);
- ctrl_outb(inb(TSNC) & ~0x01,TSNC);
- ctrl_outb(inb(TMDR) & ~0x01,TMDR);
- ctrl_outb(inb(TSTR) | 0x01,TSTR);
+ *(unsigned short *)GRA= H8300_TIMER_FREQ / HZ; /* set interval */
+ *(unsigned short *)TCNT=0; /* clear counter */
+ ctrl_outb(0x80|CCLR_CMGRA|CLK_DIV8, TCR); /* set ITU0 clock */
+ ctrl_outb(0x88, TIOR); /* no output */
+ request_irq(26, timer_int, 0, "timer", 0);
+ ctrl_outb(0xf9, TIER); /* compare match GRA interrupt */
+ ctrl_outb(ctrl_inb(TSNC) & ~0x01, TSNC); /* ITU0 async */
+ ctrl_outb(ctrl_inb(TMDR) & ~0x01, TMDR); /* ITU0 normal mode */
+ ctrl_outb(ctrl_inb(TSTR) | 0x01, TSTR); /* ITU0 Start */